Semiconductor die and manufacturing method thereof
By setting hexagonal pads in the surrounding area of the semiconductor grains and maintaining rectangular pads in the central area, the problems of stress and heat damage in the surrounding area are solved, and the leakage current performance of the transistor and the reliability of the semiconductor grains are improved.
Patent Information
- Application Number
- CN202410393023.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-10-25
- Filing Date
- 2024-04-02
- Publication Date
- 2025-04-29
AI Technical Summary
The surrounding areas of semiconductor grains are susceptible to stress and heat damage during the process, resulting in cracking or failure of the joint pads, reducing the reliability of semiconductor grains.
A semiconductor grain is designed, with the pads in the surrounding area arranged as hexagonal, while the pads in the central area remain rectangular. This structure improves the problems of stress concentration and thermal accumulation, and prevents the pads from rupturing or failure.
Compared with rectangular pads, hexagonal pads have a larger channel density and current density, which reduces the on-resistance per unit area, improves the leakage current of the transistor, and improves the reliability of semiconductor grains.
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Figure CN119907311A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a semiconductor die and a method for manufacturing the same. Background Art
[0002] Generally, in a silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET), the gate pad, source pad, and drain pad of the transistor are configured in a rectangular shape.
[0003] However, the peripheral areas of semiconductor dies are more susceptible to stress and thermal damage during processing than the central areas. For example, transistor pads located at the corners and edges of semiconductor dies may be subjected to stress fracture or cracking during wafer segmentation. In addition, these pads are more susceptible to heat accumulation and damage during packaging processing and reliability testing. This may reduce the reliability of semiconductor dies and is a major challenge in the thermal design of semiconductor devices.
[0004] Therefore, how to propose a semiconductor crystal grain and a manufacturing method thereof that can solve the above problems is one of the problems that the industry is eager to invest research and development resources to solve. Summary of the invention
[0005] In view of this, an object of the present disclosure is to provide a semiconductor device and a manufacturing method thereof that can solve the above-mentioned problems.
[0006] To achieve the above-mentioned object, according to some embodiments of the present disclosure, a semiconductor die includes a first transistor and a second transistor. The first transistor is located in a peripheral region of the semiconductor die. The first transistor includes a first pad. In a top view, the first pad has a hexagonal first outer edge. The second transistor is located in a central region of the semiconductor die. The second transistor includes a second pad. In a top view, the second pad has a rectangular second outer edge. The peripheral region surrounds the central region and the first transistors jointly surround the second transistor.
[0007] According to other embodiments of the present disclosure, a method for manufacturing a semiconductor grain includes providing a substrate. The substrate includes a peripheral region and a central region. The peripheral region surrounds the central region. The method also includes forming a first transistor in the peripheral region. The first transistors each have a first pad. In a top view, the first pad has a hexagonal first outer edge. The method also includes forming a second transistor in the central region. The second transistor has a second pad. In a top view, the second pad has a rectangular second outer edge. The first transistors collectively surround the second transistor.
[0008] In summary, in some embodiments of the semiconductor crystal grains and their manufacturing methods disclosed herein, the pads in the peripheral area are set to be hexagonal while the pads in the central area are maintained in a rectangular shape, which can improve the stress concentration and heat accumulation problems in the peripheral area and prevent the pads in the peripheral area from breaking or failing. In addition, the hexagonal pads have a greater channel density and current density than the rectangular pads, which helps to reduce the on-resistance per unit area, thereby improving the leakage current of the transistor. Compared with the common semiconductor crystal grains and their manufacturing methods, the reliability of the device can be improved.
[0009] These and other aspects of the present disclosure will become apparent from the following description of preferred embodiments in conjunction with the accompanying drawings, but changes and modifications may be made therein without departing from the spirit and scope of the novel concepts of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
[0010] The accompanying drawings illustrate one or more embodiments of the present disclosure and together with the written description are used to explain the principles of the present disclosure. In all drawings, the same reference numerals are used as much as possible to refer to similar or identical elements of the embodiments, wherein:
[0011] Figure 1 FIG. 4 is a schematic top view of a wafer according to some embodiments of the present disclosure.
[0012] Figure 2 is a schematic top view of a semiconductor die according to some embodiments of the present disclosure.
[0013] Figure 3 According to some embodiments of the present disclosure, the semiconductor die is arranged along Figure 2 The line segment 3 in FIG. 1 is a schematic cross-sectional view of the surrounding area.
[0014] Figure 4 is a schematic top view of a semiconductor die according to some embodiments of the present disclosure.
[0015] Figure 5 is a schematic top view of a semiconductor die according to some embodiments of the present disclosure.
[0016] Figure 6 Schematic top view of a semiconductor die according to some other embodiments of the present disclosure.
[0017] Figure 7 FIG. 4 is a schematic top view of a semiconductor die according to yet other embodiments of the present disclosure. DETAILED DESCRIPTION
[0018] The following will disclose the embodiments of the present disclosure with the accompanying drawings. For the purpose of clear description, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present disclosure. In other words, in some embodiments of the present disclosure, these practical details are not necessary. In addition, in order to simplify the drawings, some conventional structures and elements will be depicted in a simple schematic manner in the drawings.
[0019] Please refer to Figure 1 and Figure 2 . Figure 1 FIG. 4 is a schematic top view of a wafer W according to some embodiments of the present disclosure. Figure 2 FIG. 1 is a schematic top view of a semiconductor die 100 according to some embodiments of the present disclosure. Figure 1 As shown in FIG. 1 , a wafer W includes a plurality of semiconductor grains 100. Figure 2 As shown in FIG. 1 , the semiconductor die 100 has a peripheral region PA and a central region CA. The peripheral region PA surrounds the central region CA. Figure 2 As shown in FIG. 1 , the peripheral region PA has an outermost edge E0 (or the outermost edge of the substrate 101 of the semiconductor die 100 ). In some embodiments, the outermost edge E0 is a rectangle.
[0020] In some embodiments, the semiconductor die 100 includes a plurality of first transistors (indicated by the first pads 110 included therein in the figure) and a second transistor (indicated by the second pad 120 included therein in the figure). Figure 2 As shown in FIG. 1 , the first transistors are substantially evenly arranged in the peripheral area PA. The second transistors are arranged in the central area CA. Since the peripheral area PA surrounds the central area CA, the first transistors arranged in the peripheral area PA jointly surround the second transistors arranged in the central area CA.
[0021] Generally speaking, during the process, the first transistors in the peripheral area PA are more susceptible to stress and heat damage. Therefore, in some embodiments of the present disclosure, a structure that helps to evenly distribute stress and heat is proposed for the transistors located in the peripheral area PA.
[0022] Specifically, each first transistor includes at least one first pad 110. Figure 2 As shown in the top view of FIG. 1 , the first pad 110 has a hexagonal first outer edge E1. In some embodiments, the first pad 110 may be a source or a gate of a first transistor. In some embodiments, two first pads 110 may be a source and a gate of the same first transistor, respectively. In some embodiments, adjacent first pads 110 are separated from each other.
[0023] The second transistor includes a second pad 120. Figure 2 As shown in the top view of the second embodiment, the second pad 120 has a rectangular second outer edge E2. In some embodiments, the second pad 120 can be a source or a gate of the second transistor. In some embodiments, the second pad 120 is separated from the adjacent first transistor.
[0024] Compared with the rectangular outer edge, the hexagonal outer edge has more straight edges and the angle between the two straight edges is larger, so it can improve the heat dissipation efficiency. In addition, the channel density and current density of the hexagonal pad are greater than those of the rectangular pad, so the on-resistance (R) per unit area of the hexagonal pad is on ) is smaller, which helps to improve the leakage current of the transistor.
[0025] like Figure 2 As shown in , there is at least a portion of the first transistor between the periphery of the second transistor and the outermost edge E0 of the semiconductor crystal grain 100 to disperse the heat accumulation around the semiconductor crystal grain 100. Specifically, as Figure 2 As shown in , the second outer edge E2 of the second pad 120 has a first straight side E21, a second straight side E22, a third straight side E23 and a fourth straight side E24. A first pad 110 of a first transistor is provided between the first straight side E21 and the outermost edge E0. Similarly, a first pad 110 of a first transistor is provided between the second straight side E22 and the outermost edge E0, between the third straight side E23 and the outermost edge E0, and between the fourth straight side E24 and the outermost edge E0. In this way, the heat accumulated in the peripheral area PA is dispersed through the hexagonal pads, and will not be conducted to the corners or edges of the rectangular pads for accumulation.
[0026] Please refer to Figure 3 , which is a semiconductor die 100 according to some embodiments of the present disclosure along Figure 2 The line segment 3 in FIG. 3 is a schematic cross-sectional view of the peripheral area PA. For the sake of clarity, Figure 3 The substrate 101 of the semiconductor die 100 is omitted.
[0027] like Figure 3As shown in , the semiconductor die 100 further includes a drain pad 130 and a device layer 140. The device layer 140 includes a first transistor T1 and a first transistor T2. The first transistor T1 and the first transistor T2 include a source, a gate, and a drain (drain) respectively. The source and the gate of the first transistor T1 are electrically connected to the two first pads 110 upwards respectively. The drain of the first transistor T1 is electrically connected to the drain pad 130 downwards. Similarly, the source or gate of the first transistor T2 is electrically connected to another first pad 110 upwards, and the drain is electrically connected to the drain pad 130 downwards.
[0028] Please also refer to Figure 2 and Figure 3 The method of manufacturing the semiconductor die 100 will be described in the following paragraphs. Figure 2 and Figure 3 Narrative.
[0029] The method first includes providing a substrate 101. Figure 2 As shown in FIG. 1 , the substrate 101 includes a peripheral area PA and a central area CA. The peripheral area PA surrounds the central area CA.
[0030] The method further includes forming a plurality of first transistors in the peripheral area PA. Figure 2 As shown in , each first transistor has a first pad 110. In a top view, the first outer edge E1 of the first pad 110 is a hexagon. These first pads 110 can be used as the source or gate of the first transistor. In some embodiments, as Figure 3 As shown in , the first pad 110 is disposed on the upper surface of the device layer 140 .
[0031] Next, the method includes coupling the first pads 110 to a gate voltage or a source voltage according to the electrical connection relationship of the first pads 110 .
[0032] The method further includes forming a second transistor in the central area CA. Figure 2 As shown in , the second transistor has a second pad 120. The first transistors surround the second transistor. The first pads 110 surround the second pad 120. In a top view, the second outer edge E2 of the second pad 120 is rectangular. Similarly, these second pads 120 can be used as the source or gate of the second transistor and can be disposed on the upper surface of the device layer 140.
[0033] Next, the method includes coupling the second pads 120 to a gate voltage or a source voltage according to the electrical connection relationship of the second pads 120 .
[0034] The method may further include forming a drain pad 130 on the lower surface of the device layer 140, such as Figure 3 In some embodiments, the drain pad 130 is entirely formed on the lower surface of the device layer 140. The method may further include coupling the drain pad 130 to a drain voltage.
[0035] Please refer to Figure 4 , which is a schematic top view of a semiconductor die 100' according to some embodiments of the present disclosure. The difference between the semiconductor die 100' and the semiconductor die 100 is that the semiconductor die 100' includes a plurality of second transistors in the central area CA. Figure 4 As shown in FIG. 1 , the semiconductor die 100 ′ includes four second pads 120 . The first pads 110 surround the four second pads 120 .
[0036] It should be noted that, similar to the semiconductor die 100 , there is at least one first pad 110 between the periphery of each second pad 120 and the outermost edge E0 of the semiconductor die 100 ′, so that the heat at the periphery is evenly distributed.
[0037] Please refer to Figure 5 , which is a schematic top view of a semiconductor die 100" according to some embodiments of the present disclosure. One of the differences between the semiconductor die 100" and the semiconductor die 100' is that the first pads (such as the first pad 110-1) of the semiconductor die 100" are staggered to increase the arrangement density.
[0038] In order to achieve a denser arrangement, in some embodiments, the first pad may partially extend between two second pads. Figure 5 As shown in FIG. 1 , the first pad 110 - 1 extends between the second pad 120 - 1 and the second pad 120 - 2 .
[0039] Accordingly, in some embodiments, the method of manufacturing the semiconductor die 100" may further include forming a plurality of second transistors in the central region, such that the first pad 110-1 of one of the first transistors extends between the second pad 120-1 of one of the second transistors and the second pad 120-2 of another second transistor, so as to achieve a higher arrangement density.
[0040] Another difference between the semiconductor die 100" and the semiconductor die 100' is that the semiconductor die 100" further includes a third transistor in the peripheral region. In some embodiments, the third transistor is located between the first transistor and the second transistor. In some embodiments, the third transistor is located between the first transistor and the outermost edge E0. The third transistor and the first transistor surround the second transistor together.
[0041] For example, the third transistor may include a third pad 110-2. Figure 5As shown in the top view of FIG. 1 , the third pad 110-2 is surrounded by a plurality of first pads and a plurality of second pads. In the top view, the third pad 110-2 has a third outer edge E3 of a trapezoid. The lower bottom side of the trapezoid of the third outer edge E3 is close to the second pad. Similar to the first pad, the third pad 110-2 can be a source or a gate of the third transistor.
[0042] For example, the third transistor may include a third pad 110-3. Figure 5 As shown in , the third pad 110-3 is located between the first pad and the outermost edge E0. In a top view, the third pad 110-3 has a trapezoidal third outer edge E3. The lower bottom side of the trapezoid of the third outer edge E3 is close to or overlaps with the outermost edge E0. Similarly, the third pad 110-3 can be used as a source or gate of the third transistor.
[0043] Accordingly, in some embodiments, the method of manufacturing a semiconductor grain 100" may include forming a third transistor in a peripheral region and located between a plurality of first transistors and a plurality of second transistors. In some embodiments, the method of manufacturing a semiconductor grain 100" may include forming a third transistor in a peripheral region and located between a plurality of first transistors and an outermost edge E0. In addition, the method of manufacturing a semiconductor grain 100" also includes coupling a third pad to a gate voltage or a source voltage.
[0044] Please refer to Figure 6 , which is a schematic top view of a semiconductor die 200 according to some other embodiments of the present disclosure. A difference between the semiconductor die 200 and the semiconductor die 100 is that Figure 6 As shown in , the first pad 210 of the semiconductor die 200 has a rectangular fourth outer edge E4, and the second pad 220 of the semiconductor die 200 has a rectangular fifth outer edge E5. Further, the fourth outer edge E4 is substantially square, and the fifth outer edge E5 is a long strip. In some embodiments, any side length of the fourth outer edge E4 is greater than any side length of the fifth outer edge E5.
[0045] In addition, another difference between the semiconductor die 200 and the semiconductor die 100 is that Figure 6 As shown in , the minimum distance between the first pad 210 and the second pad 220 of the semiconductor die 200 is greater than the minimum distance between the first pad 110 and the second pad 120 of the semiconductor die 100. By adjusting the characteristic length and distribution density of the pads in the central area and the peripheral area, the distribution of the current density can be controlled, thereby improving the uniformity of the heat distribution and the stress distribution.
[0046] Please refer to Figure 7, which is a schematic top view of a semiconductor die according to yet other embodiments of the present disclosure. In these embodiments, the features of the semiconductor die 100 and the semiconductor die 200 can be combined, a hexagonal pad is provided in the peripheral area PA, and a rectangular pad is provided in the central area CA, such as a first pad 210 and a second pad 220 that are the same as the semiconductor die 200, and the first pad 210 is made to surround the second pad 220 in the central area CA, so as to further optimize the heat distribution in the central area CA.
[0047] From the above detailed description of the specific embodiments of the present disclosure, it can be clearly seen that in some embodiments of the semiconductor grains and their manufacturing methods, while the pads in the central area are maintained in a rectangular shape, the pads in the peripheral area are set to be hexagonal, which can improve the stress concentration and heat accumulation problems in the peripheral area and prevent the pads located in the peripheral area from cracking or failing. In addition, the hexagonal pads have a greater channel density and current density than the rectangular pads, which helps to reduce the on-resistance per unit area, thereby improving the leakage current of the transistor. Compared with common semiconductor grains and their manufacturing methods, the reliability of the device can be improved.
[0048] The foregoing description is provided only to illustrate and describe exemplary embodiments of the present disclosure and is not intended to be exhaustive or to limit the precise forms of the invention disclosed in the present disclosure. The above teachings may be modified or varied.
[0049] The embodiments selected and described are intended to explain the content of the present disclosure and their practical applications so as to inspire other persons skilled in the art to utilize the present disclosure and various embodiments, and to make various modifications to meet the specific intended use. Alternative embodiments will be apparent to those skilled in the art without departing from the spirit and scope of the present disclosure. Therefore, the scope of the present disclosure is determined according to the appended claims, rather than being limited by the foregoing specification and the exemplary embodiments described therein.
[0050]
Explanation of symbols
[0051] 3: Line segment
[0052] 100,100',100",200: semiconductor grains
[0053] 101: Base material
[0054] 110,110-1,210: First pad
[0055] 110-2,110-3: The third pad
[0056] 120,120-1,120-2,220: Second pad
[0057] 130: Drain pad
[0058] 140: Component layer
[0059] CA: Central Area
[0060] E0: Outermost edge
[0061] E1: First outer edge
[0062] E2: Second outer edge
[0063] E21: First straight edge
[0064] E22: Second straight edge
[0065] E23: Third straight edge
[0066] E24: Fourth straight edge
[0067] E3: The Third Outer Edge
[0068] E4: The Fourth Outer Edge
[0069] E5: The Fifth Outer Edge
[0070] PA: Surrounding area
[0071] T1, T2: first transistor
[0072] W: Wafer.
Claims
1. A semiconductor crystal grain, characterized in that: Include: a plurality of first transistors located in the peripheral region of the semiconductor die and respectively comprising a first pad, wherein the first pad has a hexagonal first outer edge in a top view; and The second transistor is located in the central region of the semiconductor die and includes a second pad, wherein the second pad has a rectangular second outer edge in a top view, The peripheral area surrounds the central area and the plurality of first transistors collectively surround the second transistor.
2. The semiconductor crystal grain according to claim 1, characterized in that: The semiconductor grain has an outermost edge, and the second outer edge of the second pad has a first straight edge, a second straight edge, a third straight edge and a fourth straight edge, wherein at least a portion of a first of the multiple first transistors is located between the first straight edge and the outermost edge, at least a portion of a second of the multiple first transistors is located between the second straight edge and the outermost edge, at least a portion of a third of the multiple first transistors is located between the third straight edge and the outermost edge, and at least a portion of a fourth of the multiple first transistors is located between the fourth straight edge and the outermost edge.
3. The semiconductor crystal grain according to claim 1, characterized in that: Another second transistor is also included in the central region, wherein the first pad of one of the plurality of first transistors extends between the second pad of the second transistor and the second pad of the another second transistor.
4. The semiconductor crystal grain according to claim 1, characterized in that: The first pad is a source or a gate, and the second pad is a source or a gate.
5. The semiconductor crystal grain according to claim 1, characterized in that: The invention also includes a third transistor in the peripheral region and a third pad, wherein the third pad has a trapezoidal third outer edge in a top view, and the third transistor is located between the second transistor and one of the plurality of first transistors.
6. The semiconductor crystal grain according to claim 1, characterized in that: It also includes a third transistor in the peripheral region and a third pad, wherein in a top view, the third pad has a trapezoidal third outer edge and the third transistor is located between the outermost edge of the semiconductor die and one of the plurality of first transistors.
7. A method for manufacturing a semiconductor crystal grain, characterized in that: Include: Providing a substrate, the substrate comprising a peripheral region and a central region, wherein the peripheral region surrounds the central region; forming a plurality of first transistors in the peripheral region, wherein the plurality of first transistors respectively have a first pad and in a plan view, the first pad has a hexagonal first outer edge; and forming a second transistor in the central region, wherein the second transistor has a second pad and the second pad has a rectangular second outer edge in a top view, The plurality of first transistors collectively surround the second transistor.
8. The method according to claim 7, characterized in that The method also includes forming another second transistor in the central region, wherein the first pad of one of the plurality of first transistors extends between the second pad of the second transistor and the second pad of the another second transistor.
9. The method according to claim 7, characterized in that: The method further includes forming a third transistor in the peripheral region, wherein the third transistor includes a third pad, and in a top view, the third pad has a trapezoidal third outer edge and the third transistor is located between the second transistor and one of the plurality of first transistors.
10. The method according to claim 7, characterized in that It also includes forming a third transistor in the peripheral area, wherein the third transistor includes a third pad, and in a top view, the third pad has a trapezoidal third outer edge and the third transistor is located between the outermost edge of the substrate and one of the plurality of first transistors.