Method for reducing generation of defects in polycrystalline silicon etching process
By combining F ion implantation and specific etching processes on the polysilicon layer, the problem of random tapered defects during polysilicon etching in CMOS image sensors is solved, and the yield stability is improved.
Patent Information
- Application Number
- CN202311388012.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-24
- Publication Date
- 2025-04-29
AI Technical Summary
During the polysilicon etching process of CMOS image sensors, there are a large number of random conical defects, which affect the stability of yield.
The first photoresist layer that reacts with F ions is removed by implanting at least F ions on the polysilicon layer, and the first photoresist layer that has been reacted with F ions is removed by N2H2 dry method and O2/N2H2 dry method, and then residues on the surface of the polysilicon layer are removed by wet etching to reduce the occurrence of defects in subsequent etching.
It effectively reduces the occurrence of defects during polysilicon etching and improves the yield stability of CMOS image sensor.
Smart Images
Figure CN119907324A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of integrated circuits, and in particular to a method for reducing defect generation in a polysilicon etching process. Background Art
[0002] In CMOS image sensor products, polysilicon (Poly) is used as the gate electrode. When the doping concentration of N-type ions (for example, phosphorus (P) and fluorine (F)) is limited, a voltage drop will be formed, and an electric field will exist. As a result, electrons at the silicon oxide (SiO2) interface are easily attracted to one side of the gate electrode by the electric field, resulting in a depletion layer at the interface.
[0003] The main function of the NPO (NMOS Poly pre-dope) process is to allow the doped N-type ions of the NMOS polysilicon to reach the interface between the polysilicon and the gate oxide layer after the polysilicon is deposited, thereby preventing the occurrence of polysilicon depletion. The purpose of the F ion injection in the NPO process is to improve the random telegraph signal (RTS) noise.
[0004] In order to make polysilicon etch a better morphology, the polysilicon etching (Poly Etch) process usually uses a hard mask (HM) as an etching barrier layer. PEOX (Plasma Enhanced Oxide) is used as HM1, which usually has a low deposition rate and high density to prevent ions from precipitating in polysilicon. Low Temperature Oxide (LTO) is used as HM2 to reduce the impact on gate damage.
[0005] In the formation process of CMOS image sensors, a large number of random cone defects (Random Cone Defect) are found in the polysilicon etching process. CMOS image sensors are sensitive to some special cone defects (Special Cone Defect). Some cone defects will cause loss of yield, seriously affecting the stability of the yield of CMOS image sensors. Summary of the invention
[0006] Based on the above problems, an embodiment of the present invention provides a method for reducing defects in the polysilicon etching process, which at least includes: providing a substrate; forming a first dielectric layer and a polysilicon layer on the substrate; forming a patterned first photoresist layer on the polysilicon layer; implanting at least F ions into the polysilicon layer; removing a portion of the first photoresist layer after reacting with the F ions by N2H2 dry etching, and then removing the remaining portion of the first photoresist layer after reacting with the F ions by O2 and N2H2 dry etching; removing residues on the surface of the polysilicon layer by wet etching, thereby reducing defects in the subsequent polysilicon etching process.
[0007] In some embodiments, the process parameters for removing a portion of the first photoresist layer after reaction with F ions by N2H2 dry etching include: gas pressure range: 500~2000mT; RF power range: 1500~3000w, RF time range: 10~90s; N2H2 gas flow range: 2000~6000sccm.
[0008] In some embodiments, the process parameters for removing the remaining portion of the first photoresist layer after reacting with F ions by O2 and N2H2 dry etching include: the process parameters for the first time through O2 and N2H2 dry etching are: gas pressure range: 500~2000mT; RF power range: 1500~3000w, RF time range: 10~90s; O2 / N2H2 gas flow ratio: 1 / 9; the process parameters for the second time through O2 and N2H2 dry etching are: gas pressure range: 500~2000mT; RF power range: 1500~3000w, RF time range: 10~90s; O2 / N2H2 gas flow ratio: 9 / 1.
[0009] In some embodiments, the N2H2 dry etching removes 5% to 15% of the first photoresist layer after the reaction with the F ions.
[0010] In some embodiments, the thickness of the patterned first photoresist layer is greater than 3100 Å.
[0011] In some embodiments, the ion implantation containing at least fluorine ions into the polysilicon layer comprises: implanting P ions into the polysilicon layer; and implanting F ions into the polysilicon layer.
[0012] In some embodiments, the method further includes: forming a hard mask layer on the polysilicon layer; forming a patterned second photoresist layer on the hard mask layer; and etching away a portion of the hard mask layer and a portion of the polysilicon layer to form a polysilicon gate.
[0013] In some embodiments, the method is applied to a CMOS image sensor.
[0014] The present invention also provides a method for forming a CMOS image sensor, which at least includes: providing a substrate; forming a first dielectric layer and a polysilicon layer on the substrate; forming a patterned first photoresist layer on the polysilicon layer; implanting ions containing at least F into the polysilicon layer; removing a portion of the first photoresist layer after reacting with the F ions by N2H2 dry etching, and then removing the remaining portion of the first photoresist layer after reacting with the F ions by O2 and N2H2 dry etching; removing residues on the surface of the polysilicon layer by wet etching, thereby reducing defects generated in the subsequent polysilicon etching process.
[0015] In some embodiments, the process parameters for removing a portion of the first photoresist layer after the reaction with F ions by N2H2 dry etching include: a gas pressure range of 500-2000 mT; a radio frequency power range of 1500-3000 w, a radio frequency time range of 10-90 s; a N2H2 gas flow range of 2000-6000 sccm; the process parameters for removing the remaining portion of the first photoresist layer after the reaction with F by O2 and N2H2 dry etching include: the first O2 The process parameters of the first pass of O2 and N2H2 dry etching are: gas pressure range: 500~2000mT; RF power range: 1500~3000w, RF time range: 10~90s; O2 / N2H2 gas flow ratio: 1 / 9; the process parameters of the second pass of O2 and N2H2 dry etching are: gas pressure range: 500~2000mT; RF power range: 1500~3000w, RF time range: 10~90s; O2 / N2H2 gas flow ratio: 9 / 1. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 The invention discloses a method for etching polysilicon to form a gate for an image sensor.
[0017] Figures 2 to 7 for Figure 1 A schematic diagram of the structure of the process of etching polysilicon to form a gate for an image sensor.
[0018] Figure 8 The invention discloses a new method for etching polysilicon to form a gate for an image sensor.
[0019] Figures 9 to 15 for Figure 8 A schematic diagram of the structure of the process of etching polysilicon to form a gate for an image sensor. DETAILED DESCRIPTION
[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some examples or embodiments of the present invention. For ordinary technicians in this field, the present invention can also be applied to other similar scenarios based on these drawings without creative work. Unless it is obvious from the language environment or otherwise explained, the same reference numerals in the figures represent the same structure or operation.
[0021] Figure 1 The present invention provides a method for etching polysilicon to form a gate for an image sensor, and the method comprises the following steps.
[0022] Step S11: providing a substrate.
[0023] For step S11, refer to Figure 2 , the substrate 101 may be a doped or undoped semiconductor material, such as silicon, germanium, silicon germanium, silicon germanium on insulator (SGOI) or a combination thereof. The substrate 101 may include a substrate of multiple epitaxial layers. The substrate 101 includes a pixel region and a logic region of the image sensor. The pixel region of the image sensor is used to receive an external optical signal and convert it into an electrical signal for imaging. The specific structure of the pixel region and the logic region of the image sensor is not described in detail here.
[0024] Step S12: forming a first dielectric layer and a polysilicon layer on the substrate.
[0025] For step S12, refer to Figure 2 , a first dielectric layer 102 and a polysilicon layer 103 may be formed on the substrate 101 by deposition. The first dielectric layer 102 is silicon oxide.
[0026] Step S13: forming a patterned first photoresist layer on the polysilicon layer.
[0027] For step S13, refer to Figure 2 The first photoresist layer 104 can be formed on the polysilicon layer 103 by spin coating. The first photoresist layer 104 is a photoresist. Through exposure and development, a patterned first photoresist layer 104 is formed.
[0028] Step S14: implanting at least F ions into the polysilicon layer.
[0029] For step S14, refer to Figure 3 , F ions 105 are implanted into the polysilicon layer 103. Part of the F ions 105 are implanted into the first photoresist layer 104, and react with the first photoresist layer to form reactants 106. Part of the F ions 105 are implanted into the polysilicon layer 103. Before the F ion implantation, a P ion implantation step is required.
[0030] Step S15: removing the first photoresist layer after reacting with F ions by O2 and N2H2 dry etching.
[0031] For step S15, refer to Figure 4 , the first photoresist layer (or reactant 106) after reacting with F ions is removed by O2 and N2H2 dry etching. In this step, the reactant 106 on the surface of the polysilicon layer 103 cannot be completely removed, and part of the reactant 106 will remain on the surface of the polysilicon layer 103. The reactant 106 has a strong hardness and is prone to forming defects in the subsequent etching process.
[0032] Step S16: removing residues on the surface of the polysilicon layer by wet etching.
[0033] In step S16 , the residue is removed by wet etching, but the reactant 106 is still difficult to remove.
[0034] Step S17: forming a hard mask layer on the polysilicon layer, and forming a patterned second photoresist layer on the hard mask layer.
[0035] For step S17, refer to Figure 5 A hard mask layer 107 is deposited on the polysilicon layer 103, and a patterned second photoresist layer 108 is formed on the hard mask layer 107. The hard mask layer 107 is made of silicon oxide, silicon nitride, silicon oxynitride, etc. The second photoresist layer 108 is photoresist.
[0036] Step S18: etching and removing a portion of the hard mask layer and a portion of the polysilicon layer to form a polysilicon gate.
[0037] For step S18, refer to Figure 6 and Figure 7 After etching away a portion of the hard mask layer 107, reactants 106 still exist on the surface of the polysilicon layer 103. Due to the presence of reactants 106, after etching away a portion of the polysilicon layer 103, unremoved polysilicon 103 exists on the surface of the substrate 101, thereby forming defects 109. The defects 109 reduce the yield of the image sensor chip.
[0038] In order to prevent defects 109 from being generated during the subsequent etching of polysilicon 103 due to the product 106 formed by the reaction of F ions with the first photoresist layer 104 , the present invention further provides a new polysilicon etching process.
[0039] Figure 8 The present invention provides a method for etching polysilicon to form a gate for an image sensor, and the method comprises the following steps.
[0040] Step S21: providing a substrate.
[0041] For step S21, refer to Fig. 9 , the substrate 201 may be a doped or undoped semiconductor material, such as silicon, germanium, silicon germanium, silicon germanium on insulator (SGOI) or a combination thereof. The substrate 201 may include a substrate of multiple epitaxial layers. The substrate 201 includes a pixel region and a logic region of the image sensor. The pixel region of the image sensor is used to receive an external optical signal and convert it into an electrical signal for imaging. The specific structure of the pixel region and the logic region of the image sensor is not described in detail here.
[0042] Step S22: forming a first dielectric layer and a polysilicon layer on the substrate.
[0043] For step S22, refer to Fig. 9 , a first dielectric layer 202 and a polysilicon layer 203 may be formed on the substrate 201 by deposition. The first dielectric layer 202 is silicon oxide.
[0044] Step S23: forming a patterned first photoresist layer on the polysilicon layer.
[0045] For step S23, refer to Fig. 9 , a first photoresist layer 204 can be formed on the polysilicon layer 103 by spin coating. The first photoresist layer 204 is a photoresist. Through exposure and development, a patterned first photoresist layer 204 is formed. The thickness of the patterned first photoresist layer 204 is greater than 3100 Å.
[0046] Step S24: implanting at least F ions into the polysilicon layer.
[0047] For step S24, refer to Fig.10 , F ions 205 are implanted into the polysilicon layer 203. Part of the F ions 205 are implanted into the first photoresist layer 204, and react with the first photoresist layer to form a reactant 206. Part of the F ions 205 are implanted into the polysilicon layer 203. Before the F ion implantation, a P ion implantation step is required.
[0048] Step S25: removing a portion of the first photoresist layer after the reaction with the F ions by N2H2 dry etching, and then removing the remaining portion of the first photoresist layer after the reaction with the F ions by O2 and N2H2 dry etching.
[0049] For step S25, refer to Fig.11, a portion of the first photoresist layer (or reactant 106) after reacting with F ions is removed by N2H2 dry etching. The process parameters include: gas pressure range: 500~2000mT; RF power range: 1500~3000w, RF time range: 10~90s; N2H2 gas flow range: 2000~6000sccm.
[0050] The N2H2 dry etching is used to remove 5% to 15% of the first photoresist layer after reacting with F ions.
[0051] refer to Fig.12 , the remaining part of the first photoresist layer after the reaction with the F ions (or the reactant 106) is removed by O2 and N2H2 dry etching. The process parameters of the first O2 and N2H2 dry etching are: gas pressure range: 500~2000mT; RF power range: 1500~3000w, RF time range: 10~90s; O2 / N2H2 gas flow ratio: 1 / 9; the process parameters of the second O2 and N2H2 dry etching are: gas pressure range: 500~2000mT; RF power range: 1500~3000w, RF time range: 10~90s; O2 / N2H2 gas flow ratio: 9 / 1.
[0052] Step S26: removing residues on the surface of the polysilicon layer by wet etching, thereby reducing defects generated in the subsequent polysilicon etching process.
[0053] Further, refer to Fig.13 A hard mask layer 207 is deposited on the polysilicon layer 203, and a patterned second photoresist layer 208 is formed on the hard mask layer 207. The hard mask layer 207 is made of silicon oxide, silicon nitride, silicon oxynitride, etc. The second photoresist layer 208 is photoresist.
[0054] Further, refer to Fig.14 : Part of the hard mask layer 207 and part of the polysilicon layer 203 are removed by etching to form a polysilicon gate.
[0055] Further, refer to Fig.15 , ion implantation is performed on the substrate 201 to form a source 208 and a drain 209 of the transistor.
[0056] For step S18, refer to Figure 6 and Figure 7After etching away a portion of the hard mask layer 107, reactants 106 still exist on the surface of the polysilicon layer 103. Due to the presence of reactants 106, after etching away a portion of the polysilicon layer 103, unremoved polysilicon 103 exists on the surface of the substrate 101, thereby forming defects 109. The defects 109 reduce the yield of the image sensor chip.
[0057] Figure 8 The embodiment described removes a portion of the first photoresist layer after reacting with F ions by N2H2 dry etching, and then removes the remaining portion of the first photoresist layer after reacting with F ions by O2 and N2H2 dry etching. This can significantly reduce defects caused by subsequent polysilicon etching due to the products of the reaction between F ions and the first photoresist layer, thereby improving the yield of the image sensor.
[0058] The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is only for example and does not constitute a limitation of the present invention. Although it is not explicitly stated here, those skilled in the art may make various modifications, improvements and corrections to the present invention. Such modifications, improvements and corrections are suggested in the present invention, so such modifications, improvements and corrections still belong to the spirit and scope of the exemplary embodiments of the present invention. It should be understood that the embodiments described in the present invention are only used to illustrate the principles of the embodiments of the present invention. Other variations may also fall within the scope of the present invention. Therefore, as an example and not a limitation, the alternative configurations of the embodiments of the present invention may be considered to be consistent with the teachings of the present invention. Accordingly, the embodiments of the present invention are not limited to the embodiments explicitly introduced and described in the present invention.
Claims
1. A method for reducing defects in polysilicon etching, characterized in that: At least: providing a substrate; forming a first dielectric layer and a polysilicon layer on the substrate; forming a patterned first photoresist layer on the polysilicon layer; implanting at least F ions into the polysilicon layer; removing a portion of the first photoresist layer after reacting with the F ions by N2H2 dry etching, and then removing the remaining portion of the first photoresist layer after reacting with the F ions by O2 and N2H2 dry etching; Residues on the surface of the polysilicon layer are removed by wet etching, thereby reducing defects generated in the subsequent polysilicon etching process.
2. The method according to claim 1, characterized in that The process parameters for removing a portion of the first photoresist layer after reacting with F ions by N2H2 dry etching include: Air pressure range: 500~2000mT; The RF power range is: 1500~3000w, and the RF time range is: 10~90s; The N2H2 gas flow range is: 2000~6000sccm.
3. The method according to claim 1, characterized in that The process parameters for removing the remaining portion of the first photoresist layer after the reaction with F ions by O2 and N2H2 dry etching include: The process parameters for the first pass of O2 and N2H2 dry etching are: Air pressure range: 500~2000mT; The RF power range is: 1500~3000w, and the RF time range is: 10~90s; The O2 / N2H2 gas flow ratio is: 1 / 9; The process parameters for the second pass of O2 and N2H2 dry etching are: Air pressure range: 500~2000mT; The RF power range is: 1500~3000w, and the RF time range is: 10~90s; The O2 / N2H2 gas flow ratio is: 9 / 1.
4. The method according to claim 1, characterized in that The N2H2 dry etching is used to remove 5% to 15% of the first photoresist layer after reacting with F ions.
5. The method according to claim 1, characterized in that The thickness of the patterned first photoresist layer is greater than 3100 Å.
6. The method according to claim 1, characterized in that The step of implanting ions containing at least fluorine ions into the polysilicon layer comprises: Performing P ion implantation on the polysilicon layer; F ions are implanted into the polysilicon layer.
7. The method according to claim 1, characterized in that Further including: forming a hard mask layer on the polysilicon layer; forming a patterned second photoresist layer on the hard mask layer; A portion of the hard mask layer and a portion of the polysilicon layer are removed by etching to form a polysilicon gate.
8. The method according to claim 1, characterized in that The method is applied to a CMOS image sensor.
9. A method for forming a CMOS image sensor, characterized in that: At least: providing a substrate; forming a first dielectric layer and a polysilicon layer on the substrate; forming a patterned first photoresist layer on the polysilicon layer; Implanting ions containing at least F into the polysilicon layer; removing a portion of the first photoresist layer after reacting with the F ions by N2H2 dry etching, and then removing the remaining portion of the first photoresist layer after reacting with the F ions by O2 and N2H2 dry etching; Residues on the surface of the polysilicon layer are removed by wet etching, thereby reducing defects generated in the subsequent polysilicon etching process.
10. The method according to claim 9, characterized in that The process parameters for removing a portion of the first photoresist layer after reacting with F ions by N2H2 dry etching include: Air pressure range: 500~2000mT; The RF power range is: 1500~3000w, and the RF time range is: 10~90s; N2H2 gas flow range: 2000~6000sccm; The process parameters for removing the remaining portion of the first photoresist layer after the reaction with F by O2 and N2H2 dry etching include: The process parameters for the first pass of O2 and N2H2 dry etching are: Air pressure range: 500~2000mT; The RF power range is: 1500~3000w, and the RF time range is: 10~90s; The O2 / N2H2 gas flow ratio is: 1 / 9; The process parameters for the second pass of O2 and N2H2 dry etching are: Air pressure range: 500~2000mT; The RF power range is: 1500~3000w, and the RF time range is: 10~90s; The O2 / N2H2 gas flow ratio is: 9 / 1.