Preparation method of solar cell, solar cell and photovoltaic module

Abstract

The invention relates to a preparation method of a solar cell, the solar cell and a photovoltaic module. The solar cell comprises a first polarity region and a second polarity region; the preparation method comprises the steps of providing a semiconductor substrate; the semiconductor substrate is provided with a first surface and a second surface which are oppositely arranged; sequentially forming an intrinsic amorphous semiconductor layer and a first doped semiconductor layer on the first surface; the intrinsic amorphous semiconductor layer and the first doped semiconductor layer are located in the first polarity region and the second polarity region; performing first patterning processing on the first doped semiconductor layer to remove at least part of the first doped semiconductor layer in the second polarity region and expose at least part of the intrinsic amorphous semiconductor layer in the second polarity region; oxidizing at least part of the intrinsic amorphous semiconductor layer in the second polar region to form a first oxide layer; and the first oxide layer is removed through chemical etching. Therefore, according to the preparation method of the solar cell, the solar cell and the photovoltaic module provided by the invention, the conversion efficiency of the solar cell can be improved.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and in particular to a method for preparing a solar cell, a solar cell and a photovoltaic module. Background Art

[0002] Solar cells, also known as photovoltaic cells, are semiconductor devices that convert sunlight directly into electrical energy. As they are green and environmentally friendly products that do not cause environmental pollution, and solar energy is a renewable resource, solar cells are a new type of battery with broad development prospects.

[0003] In the related art, a back contact heterojunction solar cell (HBC) is a cell in which a metal electrode is disposed on the backlight side of the cell, so that the light-facing side of the cell is not blocked by the metal electrode, thereby increasing the light absorption area and thus improving the photoelectric conversion efficiency. However, the conversion efficiency of the above HBC cell still needs to be improved. Summary of the invention

[0004] Based on this, it is necessary to provide a method for preparing a solar cell, a solar cell and a photovoltaic module, which can improve the conversion efficiency of the solar cell.

[0005] In a first aspect, an embodiment of the present application provides a method for preparing a solar cell, wherein the solar cell comprises a first polarity region and a second polarity region with different polarities;

[0006] The preparation method comprises:

[0007] Providing a semiconductor substrate; the semiconductor substrate has a first surface and a second surface arranged opposite to each other;

[0008] An intrinsic amorphous semiconductor layer and a first doped semiconductor layer are sequentially formed on the first surface; the intrinsic amorphous semiconductor layer and the first doped semiconductor layer are both located in the first polarity region and the second polarity region;

[0009] Performing a first patterning process on the first doped semiconductor layer to remove at least a portion of the first doped semiconductor layer located in the second polarity region and expose at least a portion of the intrinsic amorphous semiconductor layer located in the second polarity region;

[0010] Oxidizing at least a portion of the intrinsic amorphous semiconductor layer located in the second polarity region to form a first oxide layer;

[0011] The first oxide layer is removed by chemical etching.

[0012] The method for preparing a solar cell provided in an embodiment of the present application exposes an intrinsic amorphous semiconductor layer through a first patterning treatment, then oxidizes the exposed intrinsic amorphous semiconductor layer to form a first oxide layer, and removes the first oxide layer through chemical etching, thereby achieving residue-free etching of the intrinsic amorphous semiconductor layer and the first doped semiconductor layer, and causing no damage to the second passivation layer and the second doped semiconductor layer, thereby ensuring perfect contact between the second conductive layer and the second doped semiconductor layer without reducing the passivation effect of the solar cell.

[0013] In one embodiment, the first polarity region and the second polarity region are disposed adjacent to each other, the second polarity region includes a first sub-region and a second sub-region, and the second sub-region is located between the first sub-region and the first polarity region;

[0014] Performing a first patterning process on the first doped semiconductor layer, including: removing at least a portion of the first doped semiconductor layer located in the first sub-region to expose at least a portion of the intrinsic amorphous semiconductor layer located in the first sub-region;

[0015] Oxidation treatment of at least a portion of the intrinsic amorphous semiconductor layer located in the second polarity region includes: oxidation treatment of the intrinsic amorphous semiconductor layer located in the first sub-region.

[0016] In one embodiment, the oxidation treatment of the intrinsic amorphous semiconductor layer in the first sub-region includes: crystallizing the intrinsic amorphous semiconductor layer in the first sub-region, and oxidizing the crystallized intrinsic amorphous semiconductor layer to form a first oxide layer.

[0017] In one embodiment, performing a first patterning process on the first doped semiconductor layer includes:

[0018] A portion of the first doped semiconductor layer located in the first sub-region is removed, and another portion of the first doped semiconductor layer located in the first sub-region is retained.

[0019] In one embodiment, the material of the first doped semiconductor layer includes a doped microcrystalline semiconductor;

[0020] The intrinsic amorphous semiconductor layer located in the first sub-region is oxidized, comprising: oxidizing the intrinsic amorphous semiconductor layer and the first doped semiconductor layer located in the first sub-region to form a first oxide layer and a second oxide layer respectively;

[0021] Chemically etching and removing the first oxide layer includes: chemically etching and removing the first oxide layer and the second oxide layer.

[0022] In one embodiment, the material of the first doped semiconductor layer includes a doped amorphous semiconductor;

[0023] Oxidation treatment of the intrinsic amorphous semiconductor layer located in the first sub-region includes: crystallizing the intrinsic amorphous semiconductor layer and the first doped semiconductor layer located in the first sub-region, and oxidizing the crystallized intrinsic amorphous semiconductor layer and the first doped semiconductor layer to form a first oxide layer and a second oxide layer, respectively;

[0024] Chemically etching and removing the first oxide layer includes: chemically etching and removing the first oxide layer and the second oxide layer.

[0025] In one embodiment, performing a first patterning process on the first doped semiconductor layer includes: removing the entire first doped semiconductor layer located in the first sub-region.

[0026] In one embodiment, performing a first patterning process on the first doped semiconductor layer includes: removing at least a portion of the first doped semiconductor layer located in the first sub-region, and thinning at least a portion of the intrinsic amorphous semiconductor layer located in the first sub-region.

[0027] In one embodiment, the thickness of the thinned intrinsic amorphous semiconductor layer is less than or equal to 7 nm.

[0028] In one embodiment, the oxidation treatment environment includes oxygen;

[0029] The oxidation treatment uses a laser heating process.

[0030] In one embodiment, the laser used in the laser heating process includes a first picosecond laser;

[0031] The first picosecond laser includes a picosecond green laser or a picosecond violet laser; and / or,

[0032] The energy density range of the first picosecond laser is 0.1J / cm 2 -2J / cm 2 and / or,

[0033] The scanning speed of the first picosecond laser is in the range of 10m / s-800m / s; and / or,

[0034] The frequency range of the first picosecond laser is 100KHZ-1000KHZ; and / or,

[0035] The overlap rate of the light spot of the first picosecond laser is 0; and / or,

[0036] The energy distribution of the light spot of the first picosecond laser is Gaussian distribution; and / or,

[0037] The oxygen concentration in the oxidation treatment environment ranges from 10% to 30%.

[0038] In one embodiment, the first patterning process uses a laser etching process;

[0039] The laser used in the laser etching process includes a second picosecond laser; and / or,

[0040] The second picosecond laser includes a picosecond green laser or a picosecond violet laser;

[0041] The energy density range of the second picosecond laser is 0.1J / cm 2 -2J / cm 2 and / or,

[0042] The scanning speed of the second picosecond laser is in the range of 10m / s-800m / s; and / or,

[0043] The frequency range of the second picosecond laser is 100KHZ-1000KHZ; and / or,

[0044] The overlap rate of the light spot of the second picosecond laser is 0; and / or,

[0045] The energy distribution of the spot of the second picosecond laser is Gaussian distribution.

[0046] In one embodiment, chemically etching to remove the first oxide layer includes:

[0047] Using a hydrofluoric acid solution to etch and remove the first oxide layer;

[0048] Wherein, the volume concentration range of hydrofluoric acid is 1%-50%; and / or, the time range of chemical etching is 40s-300s.

[0049] In one embodiment, a material of at least one of the first oxide layer and the second oxide layer includes silicon oxide.

[0050] In one embodiment, before sequentially forming an intrinsic amorphous semiconductor layer and a first doped semiconductor layer on the first surface, the method includes:

[0051] A second passivation layer and a second doped semiconductor layer are formed on the first surface; the second passivation layer and the second doped semiconductor layer are both located in the second polarity region, and the second passivation layer is located between the second doped semiconductor layer and the semiconductor substrate.

[0052] In a second aspect, an embodiment of the present application provides a solar cell, the solar cell comprising a first polarity region and a second polarity region with different polarities; the solar cell comprises:

[0053] A semiconductor substrate having a first surface and a second surface arranged opposite to each other;

[0054] The intrinsic amorphous semiconductor layer and the first doped semiconductor layer are stacked and arranged on the first surface in a direction away from the semiconductor substrate, and are both located in the first polarity region;

[0055] The second passivation layer and the second doped semiconductor layer are stacked on the first surface in a direction away from the semiconductor substrate and are located in the second polarity region;

[0056] A second conductive layer is disposed on a side of the second doped semiconductor layer away from the semiconductor substrate and is located in the second polarity region;

[0057] The contact resistance between the second doped semiconductor layer and the second conductive layer is less than or equal to 0.05 Ωcm 2 , and / or, the composite current density in the second passivation layer and the second doped semiconductor layer is less than or equal to 1.5 fA / cm 2 .

[0058] The solar cell provided in the embodiment of the present application has a contact resistance between the second doped semiconductor layer and the second conductive layer that is less than or equal to 0.05 Ωcm 2 , and / or, the composite current density in the second passivation layer and the second doped semiconductor layer is less than or equal to 1.5 fA / cm 2 , making the conversion efficiency of solar cells higher.

[0059] In one embodiment, the first polarity region and the second polarity region are disposed adjacent to each other, the second polarity region includes a first sub-region and a second sub-region, and the second sub-region is located between the first sub-region and the first polarity region;

[0060] Part of the intrinsic amorphous semiconductor layer and part of the first doped semiconductor layer are also located in the second sub-region, and the intrinsic amorphous semiconductor layer located in the second sub-region is located on a side of the second doped semiconductor layer away from the semiconductor substrate.

[0061] In one embodiment, the solar cell includes a first conductive layer, where the first conductive layer is located on a side of the first doped semiconductor layer facing away from the semiconductor substrate.

[0062] In one embodiment, the solar cell comprises a first electrode, the first electrode is located on a side of the first conductive layer facing away from the semiconductor substrate; and / or,

[0063] The solar cell comprises a second electrode, which is located on a side of the second conductive layer facing away from the semiconductor substrate.

[0064] In one embodiment, the material of the intrinsic amorphous semiconductor layer includes intrinsic amorphous silicon; and / or,

[0065] The material of the first doped semiconductor layer includes doped microcrystalline silicon or doped amorphous silicon; and / or,

[0066] The resistance of the solar cell is less than or equal to 0.4Ωcm 2 .

[0067] In a third aspect, an embodiment of the present application provides a photovoltaic assembly, comprising the solar cell in the second aspect.

[0068] The photovoltaic module provided in the embodiment of the present application includes a solar cell, wherein the contact resistance between the second doped semiconductor layer and the second conductive layer is less than or equal to 0.05 Ωcm 2 , and / or, the composite current density in the second passivation layer and the second doped semiconductor layer is less than or equal to 1.5 fA / cm 2 , making the conversion efficiency of solar cells higher. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] Figure 1a A top view of a solar cell provided in an embodiment of the present application.

[0070] Figure 1b Another top view of the solar cell provided in an embodiment of the present application.

[0071] Figure 1c for Figure 1b Cross-sectional view along DD direction.

[0072] Figure 2 A schematic diagram of the structure after providing a semiconductor substrate is provided in an embodiment of the present application.

[0073] Figure 3 A schematic diagram of the structure after forming an intrinsic amorphous semiconductor layer and a first doped semiconductor layer provided in an embodiment of the present application.

[0074] Figure 4 This is a schematic diagram of the structure after the first patterning process provided in an embodiment of the present application.

[0075] Figure 5 Another structural schematic diagram after the first patterning process provided in an embodiment of the present application.

[0076] Figure 6 Another structural schematic diagram after the first patterning process provided in an embodiment of the present application.

[0077] Figure 7 Another structural schematic diagram after the first patterning process provided in an embodiment of the present application.

[0078] Figure 8 Another structural schematic diagram after the first patterning process provided in an embodiment of the present application.

[0079] Fig. 9 A schematic diagram of the process of preparing a solar cell provided in an embodiment of the present application.

[0080] Description of reference numerals:

[0081] 100, solar cell; 100a, first polarity region; 100b, second polarity region; 101b, first sub-region; 102b, second sub-region; 110, semiconductor substrate; 111, first surface; 112, second surface; 121, first doped semiconductor layer; 122, second doped semiconductor layer; 131, intrinsic amorphous semiconductor layer; 132, second passivation layer; 133, third passivation layer; 141, first conductive layer; 142, second conductive layer; 151, first electrode; 152, second electrode; 160, anti-reflection layer. DETAILED DESCRIPTION

[0082] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.

[0083] In addition, if the terms "first" or "second" appear, these terms are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, if the term "plurality" appears, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0084] It should be noted that, if an element is referred to as being “disposed on” another element, it may be directly on the other element or there may be an element centered therebetween.

[0085] In the related art, the HBC battery has an N-type region and a P-type region. The HBC battery includes a semiconductor substrate, the semiconductor substrate has a first surface and a second surface arranged opposite to each other, a tunneling oxide layer and a polycrystalline silicon layer are sequentially arranged on the first surface of the N-type region, and an intrinsic amorphous silicon layer and a microcrystalline silicon layer are sequentially arranged on the first surface of the P-type region.

[0086] In the process of preparing the HBC battery, a tunneling oxide layer and a polycrystalline silicon layer may be first formed on the first surface of the N-type region, and then an intrinsic amorphous silicon layer and a microcrystalline silicon layer may be sequentially formed on the first surface, wherein the intrinsic amorphous silicon layer and the microcrystalline silicon layer are both located in the N-type region and the P-type region. Then, laser etching (e.g., laser ablation etching) is used to remove at least a portion of the intrinsic amorphous silicon layer and the microcrystalline silicon layer in the N-type region, and at least the intrinsic amorphous silicon layer and the microcrystalline silicon layer located in the P-type region are retained.

[0087] However, on the one hand, if the energy of the laser used for laser etching is too large, during the process of laser etching the intrinsic amorphous silicon layer and the microcrystalline silicon layer, the laser easily penetrates the intrinsic amorphous silicon layer and the microcrystalline silicon layer to cause light leakage, making it easy for the laser to damage the tunneling oxide layer and the polycrystalline silicon layer below, resulting in excessive surface roughness of the damaged film layer, reducing the passivation effect of the HBC battery, and thus adversely affecting the conversion efficiency of the HBC battery. On the other hand, if the energy of the laser used for laser etching is too small, it will cause the intrinsic amorphous silicon layer and the microcrystalline silicon layer to be difficult to etch cleanly and leave residues, which will in turn increase the contact resistance between the transparent conductive layer formed on the polycrystalline silicon layer and the polycrystalline silicon layer, and the subsequent series connection of the HBC battery will change, and affect the fill factor of the solar cell.

[0088] To solve the above problems, the embodiments of the present application provide a method for preparing a solar cell 100 , a solar cell 100 , and a photovoltaic module, which can improve the conversion efficiency of the solar cell 100 .

[0089] The following will describe the method for preparing the solar cell 100 , the solar cell 100 , and the photovoltaic module provided in the embodiments of the present application in conjunction with the accompanying drawings.

[0090] An embodiment of the present application provides a method for preparing a solar cell 100 . The method for preparing a solar cell 100 is used to prepare the solar cell 100 .

[0091] See also Figure 1a-1c , the solar cell 100 includes a first polarity region 100a and a second polarity region 100b having different polarities.

[0092] In some embodiments, see Figure 1a , the first polarity region 100a and the second polarity region 100b may be arranged at intervals.

[0093] In some other embodiments, see Figure 1b The first polarity region 100a and the second polarity region 100b are adjacently arranged, and the second polarity region 100b includes a first sub-region 101b and a second sub-region 102b, and the second sub-region 102b is located between the first polarity region 100a and the first sub-region 101b. The embodiment of the present application is described by taking the first polarity region 100a and the second polarity region 100b as an example of being adjacently arranged.

[0094] See also Figure 1a and Figure 1b , the first polarity region 100a and the second polarity region 100b may both be in an interdigitated shape.

[0095] See also Fig. 9 , the method for preparing the solar cell 100 may include:

[0096] S100: providing a semiconductor substrate; the semiconductor substrate has a first surface and a second surface that are oppositely disposed.

[0097] See also Figure 2 The semiconductor substrate 110 may have a first surface 111 and a second surface 112 that are oppositely disposed along a thickness direction of the semiconductor substrate 110. The semiconductor substrate 110 may provide support for a film layer to be formed subsequently.

[0098] Exemplarily, at least one of the first surface 111 and the second surface 112 of the semiconductor substrate 110 may be textured so that at least one of the first surface 111 and the second surface 112 forms a texture structure.

[0099] For example, the velvet structure can be prepared by wet chemical etching, for example, an alkaline solution can be used for velvet preparation, such as a NaOH solution, or chemical etching, laser etching, mechanical method, plasma etching, etc. can be used to prepare the velvet structure.

[0100] For example, before texturing the semiconductor substrate 110 , at least one of the first surface 111 and the second surface 112 may be polished.

[0101] For example, the second passivation layer 132 may be formed by a deposition process.

[0102] Exemplarily, the deposition process may include atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or reactive plasma deposition (RPD). Other structural layers in the embodiments of the present disclosure may also be formed by deposition, which will not be described in detail.

[0103] S200: forming an intrinsic amorphous semiconductor layer and a first doped semiconductor layer in sequence on the first surface; the intrinsic amorphous semiconductor layer and the first doped semiconductor layer are both located in the first polarity region and the second polarity region.

[0104] In some embodiments, see Figure 3 After providing the semiconductor substrate 110, the method may include sequentially forming an intrinsic amorphous semiconductor layer 131 and a first doped semiconductor layer 121 on the first surface 111, wherein the intrinsic amorphous semiconductor layer 131 and the first doped semiconductor layer 121 are both located in the first polarity region 100a and the second polarity region 100b.

[0105] S300: performing a first patterning process on the first doped semiconductor layer to remove at least a portion of the first doped semiconductor layer located in the second polarity region and expose at least a portion of the intrinsic amorphous semiconductor layer located in the second polarity region.

[0106] See also Figure 4-Figure 7 After the intrinsic amorphous semiconductor layer 131 and the first doped semiconductor layer 121 are sequentially formed on the first surface 111, the method may include performing a first patterning process on the first doped semiconductor layer 121 to remove at least a portion of the first doped semiconductor layer 121 located in the second polarity region 100b, and exposing at least a portion of the intrinsic amorphous semiconductor layer 131 located in the second polarity region 100b. In this way, during the first patterning process, the exposed at least a portion of the intrinsic amorphous semiconductor layer 131 is retained, and the retained at least a portion of the intrinsic amorphous semiconductor layer 131 can prevent the first patterning process from causing damage to the second passivation layer 132 and the second doped semiconductor layer 122 thereunder, thereby facilitating the improvement of the conversion efficiency of the solar cell 100.

[0107] In some embodiments, performing the first patterning process on the first doped semiconductor layer 121 may include removing at least a portion of the first doped semiconductor layer 121 located in the first sub-region 101b, exposing at least a portion of the intrinsic amorphous semiconductor layer 131 located in the first sub-region 101b. In this way, during the first patterning process, the exposed at least a portion of the intrinsic amorphous semiconductor layer 131 is retained, and the retained at least a portion of the intrinsic amorphous semiconductor layer 131 located in the first sub-region 101b can prevent the first patterning process from causing damage to the second passivation layer 132 and the second doped semiconductor layer 122 thereunder, thereby facilitating improving the conversion efficiency of the solar cell 100.

[0108] Exemplarily, the first patterning process for the first doped semiconductor layer 121 may be performed by wet etching, dry etching, laser etching, etc. The patterning process for other structural layers in the embodiment of the present application is similar and will not be described in detail.

[0109] The embodiment of the present application is described by taking the laser etching process as an example of the first patterning process. By exposing the at least part of the intrinsic amorphous semiconductor layer 131 located in the first sub-region 101b during the first patterning process, the exposed at least part of the intrinsic amorphous semiconductor layer 131 is retained, and the retained at least part of the intrinsic amorphous semiconductor layer 131 located in the first sub-region 101b can avoid the laser etching process from damaging the second passivation layer 132 and the second doped semiconductor layer 122, thereby facilitating the improvement of the conversion efficiency of the solar cell 100.

[0110] Exemplarily, the laser used in the laser etching process includes a second picosecond laser. The picosecond laser can accurately act on the first sub-region 101b, and the etching time is short and the efficiency is high. In addition, the energy of the picosecond laser is lower than that of laser ablation etching, which is beneficial to prevent the laser etching from causing over-etching of the intrinsic amorphous semiconductor layer 131, thereby helping the retained intrinsic amorphous semiconductor layer 131 to form a complete protection effect on the second passivation layer 132 and the second doped semiconductor layer 122 thereunder, which is beneficial to improving the conversion efficiency of the solar cell 100.

[0111] Exemplarily, the second picosecond laser includes a picosecond green laser (for example, the wavelength may be 532 nm) or a picosecond violet laser (for example, the wavelength may be 352 nm).

[0112] Exemplarily, the energy density of the second picosecond laser is in the range of 0.1 J / cm 2 -2J / cm 2 , thereby preventing the energy density of the second picosecond laser from being too low and causing low etching efficiency, and also preventing the energy density of the second picosecond laser from being too high and causing over-etching of the intrinsic amorphous semiconductor layer 131. For example, the energy density of the second picosecond laser is 0.1 J / cm 2 , 0.2J / cm 2 , 0.5J / cm 2 , 1J / cm 2 , 1.5J / cm 2 , 2J / cm 2 or between 0.1J / cm 2 -2J / cm 2 Any number in between.

[0113] Exemplarily, the scanning speed of the second picosecond laser ranges from 10m / s to 800m / s, thereby preventing the second picosecond laser from having a scanning speed that is too slow and resulting in low etching efficiency, and also preventing the second picosecond laser from having a scanning speed that is too fast and resulting in high costs. For example, the scanning speed of the second picosecond laser can be 10m / s, 50m / s, 100m / s, 200m / s, 300m / s, 500m / s, 600m / s, 800m / s, or any number between 10m / s and 800m / s.

[0114] Exemplarily, the frequency range of the second picosecond laser is 100KHZ-1000KHZ, so as to avoid the second picosecond laser frequency being too low and resulting in low etching efficiency, and to avoid the second picosecond laser frequency being too high and resulting in high cost. For example, the frequency of the second picosecond laser can be 100KHZ, 200KHZ, 300KHZ, 400KHZ, 600KHZ, 800KHZ, 1000KHZ or any number between 100KHZ-1000KHZ.

[0115] Exemplarily, the overlap rate of the spot of the second picosecond laser is 0, which can avoid excessive energy in the spot overlapping area and cause over-engraving of the intrinsic amorphous semiconductor layer 131, thereby facilitating the retained intrinsic amorphous semiconductor layer 131 to form a complete protection effect for the second passivation layer 132 and the second doped semiconductor layer 122 thereunder.

[0116] Exemplarily, the energy distribution of the light spot of the second picosecond laser is Gaussian distribution.

[0117] In some embodiments, see Figure 5 , performing a first patterning process on the first doped semiconductor layer 121 may include removing a portion of the first doped semiconductor layer 121 located in the first sub-region 101b, and retaining another portion of the first doped semiconductor layer 121 located in the first sub-region 101b. In this way, by removing a portion of the first doped semiconductor layer 121 located in the first sub-region 101b, a portion of the intrinsic amorphous semiconductor layer 131 located in the first sub-region 101b is exposed, thereby facilitating subsequent oxidation of the exposed portion of the intrinsic amorphous semiconductor layer 131. In addition, retaining another portion of the first doped semiconductor layer 121 located in the first sub-region 101b is beneficial to reducing the time of laser etching, thereby facilitating preventing the laser etching from causing over-etching of the intrinsic amorphous semiconductor layer 131.

[0118] In some other embodiments, see Figure 4 , performing a first patterning process on the first doped semiconductor layer 121 may include removing the entire first doped semiconductor layer 121 located in the first sub-region 101b to expose the entire intrinsic amorphous semiconductor layer 131 located in the first sub-region 101b, thereby facilitating the oxidation rate of the intrinsic amorphous semiconductor layer 131 in the first sub-region 101b and improving the preparation efficiency of the solar cell 100.

[0119] In some other embodiments, see Figure 6 and Figure 7The process of performing the first patterning treatment on the first doped semiconductor layer 121 also includes thinning at least a portion of the intrinsic amorphous semiconductor layer 131 located in the first sub-region 101b. In this way, in the first sub-region 101b, the thickness of the thinned intrinsic amorphous semiconductor layer 131 is relatively thin, which is conducive to the speed of quickly and completely oxidizing the thinned intrinsic amorphous semiconductor layer 131.

[0120] Exemplarily, the thickness of the thinned intrinsic amorphous semiconductor layer 131 is less than or equal to 7 nm, so that the thickness of the thinned intrinsic amorphous semiconductor layer 131 is small, which is conducive to the rapid and complete oxidation of the thinned intrinsic amorphous semiconductor layer 131. For example, the thickness of the thinned intrinsic amorphous semiconductor layer 131 can be 1 nm, 3 nm, 5 nm, 7 nm, or any value less than 7 nm.

[0121] In some other embodiments, participating Figure 4 and Figure 5 In the process of performing the first patterning treatment on the first doped semiconductor layer 121, the intrinsic amorphous semiconductor layer 131 located in the first sub-region 101b is not thinned, so that the thickness of the retained intrinsic amorphous semiconductor layer 131 is relatively large. In the first patterning process, it is beneficial to improve the protective effect of the intrinsic amorphous semiconductor layer 131 on the second passivation layer 132 and the second doped semiconductor layer 122 thereunder, thereby helping to improve the conversion efficiency of the solar cell 100.

[0122] S400: performing oxidation treatment on at least a portion of the intrinsic amorphous semiconductor layer located in the second polarity region to form a first oxide layer.

[0123] In some embodiments, after the first doped semiconductor layer 121 is subjected to the first patterning process, the process includes oxidizing at least a portion of the intrinsic amorphous semiconductor layer 131 located in the second polarity region 100b to form a first oxide layer. The oxidation process of at least a portion of the intrinsic amorphous semiconductor layer 131 located in the second polarity region 100b may include oxidizing the intrinsic amorphous semiconductor layer 131 in the first sub-region 101b so that the intrinsic amorphous semiconductor layer 131 forms a first oxide layer. After at least a portion of the intrinsic amorphous semiconductor layer 131 located in the first sub-region 101b is exposed, it is convenient to oxidize the intrinsic amorphous semiconductor layer 131 located in the first sub-region 101b. The first oxide layer is easier to be removed by a chemical etching process than the intrinsic amorphous semiconductor layer 131, so that the first oxide layer can be completely removed without using a laser etching technology, thereby preventing the second passivation layer 132 and the second doped semiconductor layer 122 from being damaged by excessive energy when removing the first oxide layer by laser etching, thereby facilitating the improvement of the conversion efficiency of the solar cell 100.

[0124] In some embodiments, the oxidation treatment of the intrinsic amorphous semiconductor layer 131 of the first sub-region 101b may specifically include crystallizing the intrinsic amorphous semiconductor layer 131 of the first sub-region 101b, and oxidizing the crystallized intrinsic amorphous semiconductor layer 131 to form a first oxide layer. Since the intrinsic amorphous semiconductor layer 131 before crystallization is in an amorphous state and is not easily oxidized, the intrinsic amorphous semiconductor layer 131 after crystallization may be in a microcrystalline state and is more easily oxidized, therefore, by crystallizing the intrinsic amorphous semiconductor layer 131, the oxidation of the intrinsic amorphous semiconductor layer 131 may be more easily achieved.

[0125] In some embodiments, in an implementation method of using a first patterning treatment to thin the intrinsic amorphous semiconductor layer 131 located in the first sub-region 101b, oxidation treatment of the intrinsic amorphous semiconductor layer 131 in the first sub-region 101b may include oxidation treatment of the thinned intrinsic amorphous semiconductor layer 131. Since the thickness of the thinned intrinsic amorphous semiconductor layer 131 is relatively thin, it is beneficial to quickly and completely oxidize the thinned intrinsic amorphous semiconductor layer 131, thereby improving the oxidation treatment efficiency.

[0126] Exemplarily, the oxidation treatment may adopt a laser heating process, and the laser can act precisely on the first sub-region 101b without acting on other regions, and the laser heating time is short and the efficiency is high. When the first sub-region 101b is treated by the laser heating process, the intrinsic amorphous semiconductor layer 131 of the first sub-region 101b can be crystallized, and oxygen is introduced into the oxidation treatment environment (that is, the oxidation treatment environment includes oxygen) to facilitate oxidation of the crystallized intrinsic amorphous semiconductor layer 131.

[0127] For example, the oxygen concentration in the oxidation treatment environment ranges from 10% to 30%, thereby avoiding low oxidation efficiency due to too low oxygen concentration in the oxidation treatment environment, and also avoiding high costs due to too high oxygen concentration. For example, the oxygen concentration in the oxidation treatment environment can be 10%, 15%, 20%, 25%, 30%, or any value between 10% and 30%.

[0128] Exemplarily, the laser used in the laser heating process includes a first picosecond laser. The picosecond laser has low energy, which is beneficial for preventing the local temperature of the solar cell 100 from overheating.

[0129] Exemplarily, the first picosecond laser includes a picosecond green laser (for example, the wavelength may be 532 nm) or a picosecond violet laser (for example, the wavelength may be 352 nm).

[0130] For example, the energy density of the first picosecond laser is in the range of 0.1 J / cm 2 -2J / cm 2, so as to avoid the low heating efficiency caused by the low energy density of the first picosecond laser, and also avoid the local temperature being too high due to the high energy density of the first picosecond laser. For example, the energy density of the first picosecond laser is 0.1 J / cm 2 , 0.5J / cm 2 , 1J / cm 2 , 1.5J / cm 2 , 2J / cm 2 or between 0.1J / cm 2 -2J / cm 2 Any number in between.

[0131] Exemplarily, the scanning speed of the first picosecond laser ranges from 10m / s to 800m / s, thereby preventing the first picosecond laser from having a scanning speed that is too slow and resulting in low heating efficiency, and also preventing the first picosecond laser from having a scanning speed that is too fast and resulting in high costs. For example, the scanning speed of the first picosecond laser can be 10m / s, 50m / s, 100m / s, 200m / s, 300m / s, 500m / s, 600m / s, 800m / s, or any number between 10m / s and 800m / s.

[0132] Exemplarily, the frequency range of the first picosecond laser is 100KHZ-1000KHZ, so as to avoid the first picosecond laser frequency being too low and resulting in low heating efficiency, and to avoid the first picosecond laser frequency being too high and resulting in high cost. For example, the frequency of the first picosecond laser can be 100KHZ, 200KHZ, 300KHZ, 400KHZ, 600KHZ, 800KHZ, 1000KHZ or any number between 100KHZ-1000KHZ.

[0133] Exemplarily, the overlap rate of the light spots of the first picosecond laser is 0, which can avoid excessive energy in the light spot overlap area and cause excessive local temperature.

[0134] Exemplarily, the energy distribution of the light spot of the first picosecond laser is Gaussian distribution.

[0135] In an embodiment in which a first patterning process is used to remove a portion of the first doped semiconductor layer 121 located in the first sub-region 101b, and another portion of the first doped semiconductor layer 121 located in the first sub-region 101b is retained, the material of the first doped semiconductor layer 121 may include a doped microcrystalline semiconductor, and the process of oxidizing the intrinsic amorphous semiconductor layer 131 of the first sub-region 101b also includes: oxidizing the retained first doped semiconductor layer 121 to form a second oxide layer, which is easier to be removed by chemical etching than the doped microcrystalline semiconductor, and the second oxide layer can be completely removed without using laser etching technology, thereby preventing the second passivation layer 132 and the second doped semiconductor layer 122 from being damaged due to excessive energy when removing the second oxide layer by laser etching, which is beneficial to improving the conversion efficiency of the solar cell 100.

[0136] In the embodiment where the first patterning process is used to remove a portion of the first doped semiconductor layer 121 located in the first sub-region 101b and another portion of the first doped semiconductor layer 121 located in the first sub-region 101b is retained, the material of the first doped semiconductor layer 121 may include a doped amorphous semiconductor, and the process of oxidizing the intrinsic amorphous semiconductor layer 131 of the first sub-region 101b may further include: crystallizing the first doped semiconductor layer 121, and oxidizing the crystallized first doped semiconductor layer 121 to form a second oxide layer. Since the first doped semiconductor layer 121 before crystallization is in an amorphous state and is not easily oxidized, the first doped semiconductor layer 121 after crystallization may be in a microcrystalline state and is more easily oxidized, therefore, by crystallizing the retained first doped semiconductor layer 121, it is possible to facilitate the oxidation of the retained first doped semiconductor layer 121.

[0137] S500: chemically etching to remove the first oxide layer.

[0138] See also Figure 8 After the intrinsic amorphous semiconductor layer 131 of the first sub-region 101b is oxidized, the first oxide layer may be removed by chemical etching to expose the second doped semiconductor layer 122 located in the first sub-region 101b, so that the second conductive layer 142 formed subsequently contacts the second doped semiconductor layer 122. The chemical etching can completely remove the first oxide layer, and can also avoid the second passivation layer 132 and the second doped semiconductor layer 122 being easily damaged by excessive laser energy when the first oxide layer is laser-etched, thereby facilitating the conversion efficiency of the solar cell 100.

[0139] In an embodiment in which a second oxide layer is formed, the process of chemically etching to remove the first oxide layer also includes chemically etching to remove the second oxide layer, so that the first oxide layer and the second oxide layer can be removed at the same time, thereby simplifying the process of removing the first oxide layer and the second oxide layer and reducing the preparation cost of the solar cell 100.

[0140] It should be noted that, on the one hand, since chemical etching is used to remove the first oxide layer, chemical etching can completely remove the first oxide layer, thereby avoiding the residual intrinsic amorphous semiconductor layer 131 and the first doped semiconductor layer 121 in the first sub-region 101b, so as to avoid the residual causing the contact resistance between the second doped semiconductor layer 122 and the second conductive layer 142 to increase, and achieve perfect contact between the second doped semiconductor layer 122 and the second conductive layer 142, so that the contact resistance between the second doped semiconductor layer 122 and the second conductive layer 142 is less than or equal to 0.05Ωcm 2 On the other hand, chemical etching is used to remove the first oxide layer, which can also avoid excessive laser energy when laser etching the first oxide layer, which can easily damage the second passivation layer 132 and the second doped semiconductor layer 122 thereunder, thereby avoiding adverse effects on the back passivation effect of the solar cell 100, so that the composite current density in the second passivation layer 132 and the second doped semiconductor layer 122 is less than or equal to 1.5 fA / cm 2 , so that the conversion efficiency of the solar cell is relatively high. In summary, the embodiment of the present application exposes the intrinsic amorphous semiconductor layer 131 by laser etching, and then forms a first oxide layer by laser oxidation treatment of the exposed intrinsic amorphous semiconductor layer 131, and removes the first oxide layer by hydrofluoric acid, thereby achieving residue-free etching of the intrinsic amorphous semiconductor layer 131 and the first doped semiconductor layer 121, and without damaging the second passivation layer 132 and the second doped semiconductor layer 122, thereby ensuring that the second conductive layer 142 and the second doped semiconductor layer 122 are in perfect contact without reducing the passivation effect of the solar cell 100.

[0141] Exemplarily, chemically etching to remove the first oxide layer may include using hydrofluoric acid bath etching or chain etching to remove the first oxide layer.

[0142] For example, the contact resistance between the second doped semiconductor layer 122 and the second conductive layer 142 may be 0.01 Ωcm 2 , 0.02Ωcm 2 , 0.03Ωcm 2 , 0.05Ωcm 2 Or less than 0.05Ωcm 2 The contact resistance can be obtained through battery IV (current voltage) curve and characteristic parameter test analysis.

[0143] For example, the combined current density in the second passivation layer 132 and the second doped semiconductor layer 122 may be 1 fA / cm 2 , 1.1fA / cm 2 , 1.2fA / cm 2 , 1.3fA / cm 2 , 1.5fA / cm 2 Or less than 1.5fA / cm 2 Any value of .

[0144] For example, the resistance of the solar cell 100 is less than or equal to 0.4 Ωcm 2 , the resistance of the solar cell 100 is small, which is beneficial to reduce the energy loss and heat generation of the solar cell 100 during operation, thereby reducing the temperature and loss of the solar cell 100 and extending the life of the solar cell 100. For example, the resistance of the solar cell 100 is 0.10Ωcm 2 , 0.20Ωcm 2 、0.35Ωcm 2 , 0.40Ωcm 2 Or less than 0.40Ωcm 2 Any value of .

[0145] In some embodiments, see Figure 1c After chemically etching and removing the first oxide layer, the first conductive layer 141 and the second conductive layer 142 may be formed. The first conductive layer 141 is disposed on the side of the first doped semiconductor layer 121 away from the semiconductor substrate 110, and the first conductive layer 141 is located in the first polarity region 100a. The second conductive layer 142 is disposed on the side of the second doped semiconductor layer 122 away from the semiconductor substrate 110, and the second conductive layer 142 may be located in the first sub-region 101b. The first conductive layer 141 and the second conductive layer 142 are spaced apart, so as to prevent the first conductive layer 141 and the second conductive layer 142 from short-circuiting.

[0146] By way of example, the second conductive layer 142 may extend to the second sub-region 102 b .

[0147] In some embodiments, see Figure 1cAfter forming the first conductive layer 141 and the second conductive layer 142, the first electrode 151 and the second electrode 152 may be formed. The first electrode 151 is located on the side of the first conductive layer 141 away from the semiconductor substrate 110, and the first electrode 151 may be located in the first polarity region 100a. The second electrode 152 is located on the side of the second conductive layer 142 away from the semiconductor substrate 110, and the second electrode 152 may be located in the first sub-region 101b. The first electrode 151 and the second electrode 152 are arranged at intervals, so that the first electrode 151 and the second electrode 152 can be prevented from being short-circuited.

[0148] In some embodiments, chemically etching to remove the first oxide layer may include etching to remove the first oxide layer using a hydrofluoric acid solution.

[0149] Exemplarily, the volume concentration of hydrofluoric acid ranges from 1% to 50%, so as to avoid the first oxide layer being difficult to remove due to the volume concentration of hydrofluoric acid being too low, and to avoid the other film layers being easily damaged due to the volume concentration of hydrofluoric acid being too high. For example, the volume concentration of hydrofluoric acid can be 1%, 5%, 10%, 20%, 30%, 40%, 50%, or any value between 1% and 50%.

[0150] Exemplarily, the chemical etching time ranges from 40s to 300s, thereby preventing the chemical etching time from being too short, which makes it difficult to completely remove the first oxide layer and causes the first oxide layer to remain, and also preventing the chemical etching time from being too long, which causes low etching efficiency. For example, the chemical etching time can be 40s, 80s, 120s, 150s, 200s, 250s, 300s, or any value between 40s and 300s.

[0151] Exemplarily, the temperature of chemical etching may be room temperature.

[0152] Exemplarily, a material of at least one of the first oxide layer and the second oxide layer includes silicon oxide.

[0153] Exemplarily, the material of the intrinsic amorphous semiconductor layer 131 includes intrinsic amorphous silicon.

[0154] Exemplarily, the material of the first doped semiconductor layer 121 includes doped microcrystalline silicon or doped amorphous silicon.

[0155] In some embodiments, see Figure 3After providing the semiconductor substrate 110, the method includes forming a second passivation layer 132 and a second doped semiconductor layer 122 on the first surface 111. The second passivation layer 132 and the second doped semiconductor layer 122 are both located in the second polarity region 100b, and the second passivation layer 132 is located between the second doped semiconductor layer 122 and the semiconductor substrate 110. The second passivation layer 132 is in contact with the first surface 111 located in the second polarity region 100b.

[0156] It should be noted that, in the embodiment where the first polarity region 100a and the second polarity region 100b are alternately arranged, the first patterning treatment of the first doped semiconductor layer 121 may include: removing at least a portion of the first doped semiconductor layer 121 located in the second polarity region 100b, or removing the entire first doped semiconductor layer 121 located in the second polarity region 100b. The oxidation treatment of at least a portion of the intrinsic amorphous semiconductor layer 131 located in the second polarity region 100b may include crystallizing and oxidizing the entire intrinsic amorphous semiconductor layer 131 located in the second polarity region 100b.

[0157] Exemplarily, the preparation process of the solar cell 100 may be: firstly, the semiconductor substrate 110 is double-sided polished, and the second passivation layer 132 and the second doped semiconductor layer 122 are deposited by CVD, the second passivation layer 132 and the second doped semiconductor layer 122 are located in the first polarity region 100a and the second polarity region 100b, and a 70nm silicon nitride mask layer is deposited by CVD (temperature 400°C), and the second passivation layer 132 and the second doped semiconductor layer 122 of the first polarity region 100a are laser etched, and the semiconductor substrate 110 of the first polarity region 100a is wet-textured, and then, the silicon nitride mask layer is removed by wet etching, and then, the intrinsic amorphous semiconductor layer 131 and the first doped semiconductor layer 121 are deposited by CVD, and the total thickness of the intrinsic amorphous semiconductor layer 131 and the first doped semiconductor layer 121 is 37nm. Then, at least a portion of the first doped semiconductor layer 121 is removed by laser etching to expose at least a portion of the intrinsic amorphous semiconductor layer 131. The process parameters for laser etching to remove the first doped semiconductor layer 121 are as follows: the laser for laser etching is a picosecond laser with a wavelength of 532 nm and a laser energy density of 0.2 J / cm 2 , the scanning speed is 500m / s, the frequency is 200KHZ, the spot is a single spot, the spot width is 120μm, and the energy distribution of the spot is Gaussian distribution. Then, laser heating and oxygen are used to oxidize the exposed at least part of the intrinsic amorphous semiconductor layer 131. The process parameters of laser heating are: the laser for laser heating is a picosecond laser with a wavelength of 532nm and a laser energy density of 0.05J / cm 2, scanning speed 500m / s, frequency 200KHZ, single spot, spot width 120μm, energy distribution of spot Gaussian distribution, oxygen concentration 20%. Then, HF chain etching was used to remove the first oxide layer, where HF concentration was 20%, temperature was room temperature, and etching time was 120s.

[0158] The solar cell 100 provided in the embodiment of the present application is described below.

[0159] See also Figure 1a and Figure 1c , the solar cell 100 may have a first direction A, a second direction B and a third direction C, and the first direction A, the second direction B and the third direction C are all different. The first direction A, the second direction B and the third direction C may be perpendicular to each other. For example, the third direction C may be the thickness direction of the solar cell 100, and the first direction A and the second direction B may be any two different directions perpendicular to the thickness direction of the solar cell 100. The first direction A may be the length direction of the solar cell 100, and the second direction B may be the width direction of the solar cell 100. The length, width and thickness in the embodiments of the present application are merely for the convenience of description and do not imply any limitation on the size. For example, the width may be greater than, equal to or less than the length. The direction of the solar cell 100 may be consistent with the direction of the film layer such as the semiconductor substrate 110.

[0160] See also Figure 1c , the solar cell 100 includes a first polarity region 100a and a second polarity region 100b. The first polarity region 100a and the second polarity region 100b are arranged adjacent to each other, and the second polarity region 100b includes a first sub-region 101b and a second sub-region 102b, and the second sub-region 102b can be between the first sub-region 101b and the first polarity region 100a. Alternatively, the first polarity region 100a and the second polarity region 100b are arranged at intervals. The embodiment of the present application is described by taking the first polarity region 100a and the second polarity region 100b as an example of being arranged adjacent to each other.

[0161] See also Figure 1c The solar cell 100 includes a semiconductor substrate 110, which can provide support for the film layers to be formed subsequently. The semiconductor substrate 110 can be used to receive incident light and generate photogenerated carriers.

[0162] For example, see Figure 1cThe semiconductor substrate 110 may have a first surface 111 and a second surface 112 that are arranged opposite to each other along the thickness direction (i.e., the third direction C) of the semiconductor substrate 110, and at least one of the first surface 111 and the second surface 112 may be used to receive sunlight. The embodiment of the present application is described by taking the second surface 112 being used to receive sunlight as an example, that is, the second surface 112 is close to the light-facing surface of the solar cell 100, and the first surface 111 is close to the backlight surface of the solar cell 100.

[0163] For example, the semiconductor substrate 110 may be a silicon substrate, and the material of the silicon substrate may include at least one of single crystal silicon and polycrystalline silicon. The present application embodiment is described by taking single crystal silicon as an example.

[0164] Exemplarily, the doping type of the semiconductor substrate 110 may be N-type doping, which may be achieved by doping N-type ions, and the N-type ions may include at least one of phosphorus, arsenic, and antimony. Alternatively, the doping type of the semiconductor substrate 110 may be P-type doping, which may be achieved by doping P-type ions, and the P-type ions may include at least one of aluminum and boron. The embodiment of the present application is described by taking the doping type of the semiconductor substrate 110 as N-type doping as an example.

[0165] In some embodiments, at least one of the first surface 111 and the second surface 112 may have a velvet structure. The velvet structure may be a pyramid velvet, an etched pit velvet, etc. The velvet structure has a low reflectivity to incident light, and thus has a high absorption rate of incident light, so that the photoelectric conversion efficiency of the solar cell 100 is high. In other embodiments, at least one of the first surface 111 and the second surface 112 may not have a velvet structure.

[0166] See also Figure 1c The solar cell 100 includes an intrinsic amorphous semiconductor layer 131 (i.e., a first passivation layer) and a first doped semiconductor layer 121. The intrinsic amorphous semiconductor layer 131 and the first doped semiconductor layer 121 are both disposed on the first surface 111. The intrinsic amorphous semiconductor layer 131 and the first doped semiconductor layer 121 are located in the first polarity region 100a. The intrinsic amorphous semiconductor layer 131 is disposed between the first doped semiconductor layer 121 and the semiconductor substrate 110. The intrinsic amorphous semiconductor layer 131 can improve the photoelectric conversion efficiency by reducing the surface recombination rate, thereby improving the open circuit voltage and conversion efficiency of the solar cell 100. The intrinsic amorphous semiconductor layer 131 is in contact with the first surface 111 located in the first polarity region 100a. The first doped semiconductor layer 121 has a relatively low resistance, which can effectively reduce the current loss and increase the conductivity.

[0167] See also Figure 1cPart of the intrinsic amorphous semiconductor layer 131 and part of the first doped semiconductor layer 121 may also be located in the second sub-region 102 b , and the intrinsic amorphous semiconductor layer 131 located in the second sub-region 102 b is located on a side of the second doped semiconductor layer 122 away from the semiconductor substrate 110 .

[0168] Exemplarily, the material of the intrinsic amorphous semiconductor layer 131 includes intrinsic amorphous silicon.

[0169] Exemplarily, the material of the first doped semiconductor layer 121 includes doped microcrystalline silicon or doped amorphous silicon.

[0170] See also Figure 1c , the solar cell 100 includes a second passivation layer 132 and a second doped semiconductor layer 122 stacked in a direction away from the semiconductor substrate 110; the second passivation layer 132 and the second doped semiconductor layer 122 are both located in the second polarity region 100b. In the second sub-region 102b, the second passivation layer 132 and the second doped semiconductor layer 122 are both located between the semiconductor substrate 110 and the intrinsic amorphous semiconductor layer 131, that is, in the second sub-region 102b, the intrinsic amorphous semiconductor layer 131 is located on the side of the second doped semiconductor layer 122 away from the semiconductor substrate 110. The second passivation layer 132 can improve the photoelectric conversion efficiency by reducing the surface recombination rate, and improve the open circuit voltage and conversion efficiency of the solar cell 100. The second doped semiconductor layer 122 has a lower resistance, which can effectively reduce the current loss and increase the conductivity. Among them, the second passivation layer 132 is in contact with the first surface 111 located in the second polarity region 100b.

[0171] Exemplarily, the doping type of the second doped semiconductor layer 122 is opposite to the doping type of the first doped semiconductor layer 121. The doping type of one of the first doped semiconductor layer 121 and the second doped semiconductor layer 122 may be N-type doping, and the doping type of the other may be P-type doping.

[0172] Exemplarily, the second passivation layer 132 may include tunnel oxide or intrinsic amorphous silicon.

[0173] Exemplarily, the material of the second doped semiconductor layer 122 includes doped polycrystalline silicon, doped amorphous silicon, or doped microcrystalline silicon.

[0174] For example, the second passivation layer 132 may include a tunneling oxide, and the second doped semiconductor layer 122 may include doped polysilicon.

[0175] For another example, the second passivation layer 132 may include intrinsic amorphous silicon, and the second doped semiconductor layer 122 may include a doped amorphous silicon layer or doped microcrystalline silicon.

[0176] In some embodiments, see Figure 1cThe solar cell 100 includes a first conductive layer 141, which can collect the current generated by the cell and transmit it to the first electrode 151. In addition, the first conductive layer 141 can also have an anti-reflection effect. The first conductive layer 141 is disposed on the side of the first doped semiconductor layer 121 away from the semiconductor substrate 110, and the first conductive layer 141 is located in the first polarity region 100a.

[0177] Exemplarily, the first conductive layer 141 may be located only in the first polarity region 100a, and not extend to the second sub-region 102b, so that the distance between the first conductive layer 141 and the second conductive layer 142 is relatively far, which is conducive to preventing the first conductive layer 141 and the second conductive layer 142 from short-circuiting. In other examples, the first conductive layer 141 may extend from the first polarity region 100a to the second sub-region 102b, so that the area of ​​the first conductive layer 141 is relatively large, which is conducive to improving the transmission of carriers by the first conductive layer 141.

[0178] In some embodiments, the solar cell 100 includes a second conductive layer 142, which can collect the current generated by the battery and transmit it to the second electrode 152. In addition, the second conductive layer 142 can also have an anti-reflection effect. The second conductive layer 142 is arranged on the side of a portion of the second doped semiconductor layer 122 and a portion of the first doped semiconductor layer 121 away from the semiconductor substrate 110, and the second conductive layer 142 is located in the second polarity region 100b. In this way, by extending the second conductive layer 142 from the first sub-region 101b to the second sub-region 102b, the second conductive layer 142 can be arranged in a larger area, and the second doped semiconductor layer 122 can be well covered, which is conducive to improving the conduction of carriers by the second conductive layer 142. Among them, the first conductive layer 141 and the second conductive layer 142 are arranged at intervals, so as to prevent the first conductive layer 141 and the second conductive layer 142 from short-circuiting.

[0179] Exemplarily, the material of at least one of the first conductive layer 141 and the second conductive layer 142 may include at least one of indium tin oxide (ITO), aluminum zinc oxide (AZO), gallium aluminum zinc oxide (GAZO), tin oxide (SnO2), antimony tin oxide (ATO), fluorine tin oxide (FTO), cerium indium oxide (ICO), and aluminum indium oxide (IWO).

[0180] The first electrode 151 and the second electrode 152 provided in the embodiment of the present application are described below.

[0181] In some embodiments, see Figure 1cThe solar cell 100 includes a first electrode 151, which is located on a side of the first conductive layer 141 away from the semiconductor substrate 110. The first electrode 151 can collect and transmit carriers, thereby realizing solar energy conversion. The first electrode 151 can be located in the first polarity region 100a.

[0182] In some embodiments, see Figure 1c The solar cell 100 includes a second electrode 152, which is located on the side of the second conductive layer 142 away from the semiconductor substrate 110. The second electrode 152 can collect and transmit carriers, thereby realizing the conversion of solar energy into electrical energy. The second electrode 152 can be located in the first sub-region 101b. The first electrode 151 and the second electrode 152 can be arranged at intervals.

[0183] Exemplarily, the material of at least one of the first electrode 151 and the second electrode 152 includes a conductive metal such as silver, copper, or tin.

[0184] In some embodiments, see Figure 1c The solar cell 100 includes a third passivation layer 133 , and the third passivation layer 133 is located on the second surface 112 .

[0185] Exemplarily, the third passivation layer 133 includes one or more of intrinsic amorphous silicon, a composite layer of intrinsic amorphous silicon and doped microcrystalline silicon or doped amorphous silicon, a composite layer of tunneling oxide and doped polysilicon, silicon oxide, aluminum oxide, silicon nitride, and silicon oxynitride.

[0186] In some embodiments, see Figure 1c The solar cell 100 includes an anti-reflection layer 160 . The anti-reflection layer 160 is located on a side of the third passivation layer 133 facing away from the semiconductor substrate 110 .

[0187] Exemplarily, the anti-reflection layer 160 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, magnesium fluoride, and transparent conductive oxide.

[0188] It should be noted that, in the embodiment where the first polarity region 100a and the second polarity region 100b can be spaced apart, the first doped semiconductor layer 121 and the intrinsic amorphous semiconductor layer 131 are located in the first polarity region 100a and spaced apart from the second polarity region 100b. The first conductive layer 141 is located in the first polarity region 100a and spaced apart from the second polarity region 100b. The first electrode 151 is located in the first polarity region 100a and spaced apart from the second polarity region 100b.

[0189] The photovoltaic module provided in the embodiments of the present application is described below.

[0190] The embodiment of the present application further provides a photovoltaic module, which may include a solar cell 100. There may be at least one solar cell 100 in the photovoltaic module. The embodiment of the present application takes the photovoltaic module as an example in which there are multiple solar cells 100, and the multiple solar cells 100 together constitute a battery string layer.

[0191] In some embodiments, the photovoltaic module may include a first encapsulation member and a second encapsulation member located on both sides of the battery string layer, and the first encapsulation member and the second encapsulation member encapsulate the battery string layer to protect the battery string layer. The first encapsulation member and the second encapsulation member may include an encapsulation adhesive layer and a cover plate, the encapsulation adhesive layer is located on the side of the cover plate facing the battery string layer, the cover plate can protect the battery string layer, and the encapsulation adhesive layer can be used to connect the cover plate and the battery string layer.

[0192] Exemplarily, the solar cell 100 may include a heterojunction solar cell (HJT for short), a back contact cell (BC for short), a tunnel oxide passivating contact cell (TOPCON for short), a heterojunction back contact cell (HBC for short), or a hybrid full passivation back contact cell (HBC for short). The present application embodiment is described by taking a heterojunction back contact cell as an example.

[0193] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0194] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application.

Claims

1. A method for preparing a solar cell, characterized in that: The solar cell comprises a first polarity region and a second polarity region having different polarities; The preparation method comprises: Providing a semiconductor substrate; the semiconductor substrate has a first surface and a second surface arranged opposite to each other; An intrinsic amorphous semiconductor layer and a first doped semiconductor layer are sequentially formed on the first surface; the intrinsic amorphous semiconductor layer and the first doped semiconductor layer are both located in the first polarity region and the second polarity region; Performing a first patterning process on the first doped semiconductor layer to remove at least a portion of the first doped semiconductor layer located in the second polarity region and expose at least a portion of the intrinsic amorphous semiconductor layer located in the second polarity region; Oxidizing at least a portion of the intrinsic amorphous semiconductor layer located in the second polarity region to form a first oxide layer; The first oxide layer is removed by chemical etching.

2. The method for preparing a solar cell according to claim 1, characterized in that: The first polarity region and the second polarity region are arranged adjacent to each other, the second polarity region includes a first sub-region and a second sub-region, and the second sub-region is located between the first sub-region and the first polarity region; The performing a first patterning process on the first doped semiconductor layer comprises: removing at least a portion of the first doped semiconductor layer located in the first sub-region to expose at least a portion of the intrinsic amorphous semiconductor layer located in the first sub-region; The oxidation treatment of at least a portion of the intrinsic amorphous semiconductor layer located in the second polarity region comprises: The intrinsic amorphous semiconductor layer located in the first sub-region is oxidized.

3. The method for preparing a solar cell according to claim 2, characterized in that: The oxidation treatment of the intrinsic amorphous semiconductor layer located in the first sub-region includes: The intrinsic amorphous semiconductor layer located in the first sub-region is crystallized, and the crystallized intrinsic amorphous semiconductor layer is oxidized to form the first oxide layer.

4. The method for preparing a solar cell according to claim 3, characterized in that: The performing a first patterning process on the first doped semiconductor layer comprises: A portion of the first doped semiconductor layer located in the first sub-region is removed, and another portion of the first doped semiconductor layer located in the first sub-region is retained.

5. The method for preparing a solar cell according to claim 4, characterized in that: The material of the first doped semiconductor layer includes a doped microcrystalline semiconductor; The oxidation treatment of the intrinsic amorphous semiconductor layer located in the first sub-region comprises: Oxidizing the intrinsic amorphous semiconductor layer and the first doped semiconductor layer located in the first sub-region to form the first oxide layer and the second oxide layer respectively; The chemical etching to remove the first oxide layer comprises: The first oxide layer and the second oxide layer are removed by chemical etching.

6. The method for preparing a solar cell according to claim 4, characterized in that: The material of the first doped semiconductor layer includes a doped amorphous semiconductor; The oxidation treatment of the intrinsic amorphous semiconductor layer located in the first sub-region comprises: crystallize the intrinsic amorphous semiconductor layer and the first doped semiconductor layer located in the first sub-region, and oxidize the crystallized intrinsic amorphous semiconductor layer and the first doped semiconductor layer to form the first oxide layer and the second oxide layer, respectively; The chemical etching to remove the first oxide layer comprises: The first oxide layer and the second oxide layer are removed by chemical etching.

7. The method for preparing a solar cell according to claim 2, characterized in that: The performing a first patterning process on the first doped semiconductor layer comprises: All of the first doped semiconductor layer located in the first sub-region is removed.

8. The method for preparing a solar cell according to any one of claims 2 to 7, characterized in that: The performing a first patterning process on the first doped semiconductor layer comprises: At least a portion of the first doped semiconductor layer located in the first sub-region is removed, and at least a portion of the intrinsic amorphous semiconductor layer located in the first sub-region is thinned.

9. The method for preparing a solar cell according to claim 8, characterized in that: The thickness of the thinned intrinsic amorphous semiconductor layer is less than or equal to 7 nm.

10. The method for preparing a solar cell according to any one of claims 1 to 7, characterized in that: The oxidation treatment environment includes oxygen; The oxidation treatment adopts a laser heating process.

11. The method for preparing a solar cell according to claim 10, characterized in that: The laser used in the laser heating process includes a first picosecond laser; The first picosecond laser includes a picosecond green laser or a picosecond violet laser; and / or, The energy density range of the first picosecond laser is 0.1 J / cm 2 -2J / cm 2 and / or, The scanning speed of the first picosecond laser is in the range of 10m / s-800m / s; and / or, The frequency range of the first picosecond laser is 100KHZ-1000KHZ; and / or, The overlap rate of the light spots of the first picosecond laser is 0; and / or, The energy distribution of the light spot of the first picosecond laser is Gaussian distribution; and / or, The oxygen concentration in the oxidation treatment environment ranges from 10% to 30%.

12. The method for preparing a solar cell according to any one of claims 1 to 7, characterized in that: The first patterning process adopts a laser etching process; The laser used in the laser etching process includes a second picosecond laser; and / or, The second picosecond laser includes a picosecond green laser or a picosecond violet laser; The energy density range of the second picosecond laser is 0.1 J / cm 2 -2J / cm 2 and / or, The scanning speed of the second picosecond laser is in the range of 10m / s-800m / s; and / or, The frequency range of the second picosecond laser is 100KHZ-1000KHZ; and / or, The overlap rate of the light spots of the second picosecond laser is 0; and / or, The energy distribution of the light spot of the second picosecond laser is Gaussian distribution.

13. The method for preparing a solar cell according to any one of claims 1 to 7, characterized in that: The chemical etching to remove the first oxide layer comprises: Using a hydrofluoric acid solution to etch and remove the first oxide layer; Wherein, the volume concentration range of the hydrofluoric acid is 1%-50%; and / or, the time range of the chemical etching is 40s-300s.

14. The method for preparing a solar cell according to claim 5 or 6, characterized in that: A material of at least one of the first oxide layer and the second oxide layer includes silicon oxide.

15. The method for preparing a solar cell according to any one of claims 1 to 7, characterized in that: Before sequentially forming an intrinsic amorphous semiconductor layer and a first doped semiconductor layer on the first surface, the method comprises: A second passivation layer and a second doped semiconductor layer are formed on the first surface; the second passivation layer and the second doped semiconductor layer are both located in the second polarity region, and the second passivation layer is located between the second doped semiconductor layer and the semiconductor substrate.

16. A solar cell, characterized in that: The solar cell comprises a first polarity region and a second polarity region having different polarities; The solar cell comprises: A semiconductor substrate having a first surface and a second surface arranged opposite to each other; An intrinsic amorphous semiconductor layer and a first doped semiconductor layer are stacked and arranged on the first surface in a direction away from the semiconductor substrate, and are both located in the first polarity region; A second passivation layer and a second doped semiconductor layer are stacked on a first surface in a direction away from the semiconductor substrate and are located in the second polarity region; A second conductive layer is provided on a side of the second doped semiconductor layer away from the semiconductor substrate and is located in the second polarity region; Wherein, the contact resistance between the second doped semiconductor layer and the second conductive layer is less than or equal to 0.05Ωcm 2 , and / or, the combined current density in the second passivation layer and the second doped semiconductor layer is less than or equal to 1.5 fA / cm 2 .

17. The solar cell according to claim 16, characterized in that: The first polarity region and the second polarity region are arranged adjacent to each other, the second polarity region includes a first sub-region and a second sub-region, and the second sub-region is located between the first sub-region and the first polarity region; Part of the intrinsic amorphous semiconductor layer and part of the first doped semiconductor layer are also located in the second sub-region, and the intrinsic amorphous semiconductor layer located in the second sub-region is located on a side of the second doped semiconductor layer away from the semiconductor substrate.

18. The solar cell according to claim 16, characterized in that: The solar cell includes a first conductive layer, where the first conductive layer is located on a side of the first doped semiconductor layer facing away from the semiconductor substrate.

19. The solar cell according to claim 18, characterized in that The solar cell comprises a first electrode, wherein the first electrode is located on a side of the first conductive layer away from the semiconductor substrate; and / or The solar cell includes a second electrode, and the second electrode is located on a side of the second conductive layer away from the semiconductor substrate.

20. The solar cell according to any one of claims 16 to 19, characterized in that: The material of the intrinsic amorphous semiconductor layer includes intrinsic amorphous silicon; and / or, The material of the first doped semiconductor layer includes doped microcrystalline silicon or doped amorphous silicon; and / or, The resistance of the solar cell is less than or equal to 0.4Ωcm 2 .

21. A photovoltaic module, characterized in that: A solar cell comprising the solar cell described in any one of claims 16 to 20.

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