A solar cell, a method for manufacturing the same, and a battery assembly

Abstract

This application discloses a solar cell comprising a silicon substrate, with a first region and a second region adjacent to each other along a first direction on one side surface of the silicon substrate. In the first region, a first doped layer and a first electrode are sequentially stacked on the silicon substrate. The first doped layer extends into the second region. The first doped layer in the first region has a crystalline region. The projection of the crystalline region onto the silicon substrate at least partially overlaps with the projection of the first electrode onto the silicon substrate. In the second region, at least a portion of the first doped layer is an amorphous region. This solar cell can reduce contact resistance while avoiding leakage.

Description

[0001] This application claims priority to Chinese Patent Application No. 202410092536.4, filed on January 23, 2024, entitled “A Solar Cell and its Preparation Method and Battery Components”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the photovoltaic field, specifically to a solar cell, its preparation method, and a cell assembly. Background Technology

[0003] Solar cells employing crystalline silicon-amorphous silicon heterojunction structures include front-back contact crystalline silicon-amorphous silicon heterojunction cells (SHJ) and interdigitated back contact crystalline silicon-amorphous silicon heterojunction cells (SHJ-IBC). However, the contact resistance of crystalline silicon-amorphous silicon structures is higher than that of tunneling silicon oxide passivated contact structures (TOPCon) and high-temperature diffused homojunctions. Therefore, reducing contact resistance is currently a key research focus for crystalline silicon-amorphous silicon heterojunctions. To improve the contact resistance of the n-terminal (c-Si / ia-Si:H / na-Si:H / TCO) and p-terminal (c-Si / ia-Si:H / pa-Si:H / TCO), existing technologies replace the phosphorus-doped amorphous (na-Si:H) and boron-doped amorphous (pa-Si:H) films with phosphorus or boron-doped microcrystalline / nanocrystalline films (n-nc-Si:H, p-nc-Si:H), thereby increasing the effective doping concentration of the phosphorus-doped film (hereinafter referred to as n-Si) and the boron-doped film (hereinafter referred to as p-Si). However, the process of forming microcrystalline or nanocrystalline silicon thin films requires a large amount of hydrogen and has a slow deposition rate, resulting in increased costs. In addition, due to the low sheet resistance and strong lateral conductivity of the microcrystalline n and p films, severe leakage occurs at the interface between the n and p regions of the SHJ-IBC battery. Summary of the Invention

[0004] To address the aforementioned problems, this application provides a solar cell that can reduce contact resistance while preventing leakage.

[0005] This application provides a solar cell, including a silicon substrate, wherein one side surface of the silicon substrate includes a first region and a second region adjacent to each other along a first direction; wherein,

[0006] In the first region, a first doped layer and a first electrode are sequentially stacked on the silicon substrate; the first doped layer extends into the second region;

[0007] The first doped layer in the first region has a crystallized region; the projection of the crystallized region onto the silicon substrate at least partially overlaps with the projection of the first electrode onto the silicon substrate.

[0008] In the second region, at least a portion of the first doped layer is an amorphous region.

[0009] Furthermore, a third region is also included on one side surface of the silicon substrate, and along the first direction, the third region is located on the side of the second region opposite to the first region;

[0010] In the third region, a second doped layer and a second electrode are sequentially stacked on the silicon substrate; the second doped layer extends into the second region, and within the second region, the second doped layer is located on the side of the first doped layer closer to the silicon substrate; the conductivity of the first doped layer and the second doped layer are opposite.

[0011] Furthermore, the second doped layer comprises doped polycrystalline silicon.

[0012] Furthermore, the second doped layer in the third region has a crystallization region; the projection of the crystallization region onto the silicon substrate at least partially overlaps with the projection of the second electrode onto the silicon substrate.

[0013] In the second region, at least a portion of the second doped layer is an amorphous region.

[0014] Furthermore, within the first region, the first doped layer includes a first crystallized region and a first amorphous region A;

[0015] The portion of the first crystallization region at least on the side furthest from the silicon substrate has crystals.

[0016] Furthermore, a third region is also included on one side surface of the silicon substrate. Along the first direction, the third region is located on the side of the second region opposite to the first region. On the third region, a second doped layer and a second electrode are sequentially stacked on the silicon substrate. The conductivity of the first doped layer and the second doped layer are opposite.

[0017] In the second region, the first doped layer is stacked on the side of the second doped layer away from the silicon substrate;

[0018] The first amorphized region A includes side portions located at both ends of the first region along the first direction, and the side portions are stacked on the side of the second doped layer near the first region.

[0019] Furthermore, along the first direction, the first amorphized region A includes a middle portion located between the side portion and the first crystallized region, one end of the middle portion being connected to one of the side portions, and the other end of the middle portion being connected to the first crystallized region.

[0020] Furthermore, the sum of the lengths of the middle portion and the adjacent side portion stacked on the silicon substrate is L≥5μm.

[0021] Furthermore, within the first region, along the thickness direction from the side surface furthest from the silicon substrate to the side closest to the silicon substrate, the crystallinity of the crystallization region of the first doped layer gradually decreases; or

[0022] Within the first region, the crystallization rate of the crystallization region of the first doped layer is equal along the thickness direction from the side surface away from the silicon substrate to the side surface closer to the silicon substrate.

[0023] Further, the first doped layer in the amorphized region is an amorphous silicon layer, and the first doped layer in the crystalline region includes nanocrystalline silicon and / or microcrystalline silicon; and / or

[0024] The crystallinity of the first doped layer in the crystallization region is 0.01-100%; and / or

[0025] The first doped layer in the crystallized region is distributed in a continuous or discrete manner; and / or

[0026] The first doped layer in the crystallized region is formed by laser irradiation.

[0027] Furthermore, it also includes a first passivation layer located between the silicon substrate and the first doped layer; and / or, it also includes a first conductive layer disposed between the first doped layer and the first electrode; and / or, it also includes a second passivation layer located between the silicon substrate and the second doped layer; and / or, it also includes a second conductive layer disposed between the second doped layer and the second electrode.

[0028] A method for fabricating a solar cell, comprising the following steps:

[0029] A silicon substrate is provided, wherein one side surface of the silicon substrate includes a first region and a second region adjacent to each other along a first direction;

[0030] A first doped layer is formed in the first region and the second region of the silicon substrate;

[0031] At least a portion of the first doped layer in the first region is subjected to crystallization treatment, such that at least a portion of the first doped layer in the first region forms a crystallized region;

[0032] A first electrode is formed in the first region such that the projection of the crystallized region onto the silicon substrate at least partially overlaps with the projection of the first electrode onto the silicon substrate.

[0033] Furthermore, a third region is also included on one side surface of the silicon substrate, and along the first direction, the third region is located on the side of the second region opposite to the first region;

[0034] The method for preparing the solar cell further includes the following steps:

[0035] A second doped layer is formed in a third region and a second region of the silicon substrate; in the second region, the second doped layer is located on the side of the first doped layer closer to the silicon substrate; the conductivity of the first doped layer and the second doped layer are opposite.

[0036] A second electrode is formed in the third region.

[0037] Furthermore, the second doped layer is a polycrystalline silicon doped layer.

[0038] Furthermore, the method for preparing the solar cell further includes the following steps:

[0039] At least a portion of the second doped layer in the third region is subjected to crystallization treatment, such that at least a portion of the second doped layer in the third region forms a crystallized region;

[0040] The projection of the crystallized region in the third region onto the silicon substrate at least partially overlaps with the projection of the second electrode onto the silicon substrate.

[0041] Furthermore, after crystallizing at least a portion of the first doped layer in the first region, and before forming the first electrode in the first region, a first conductive layer is also formed in the first region.

[0042] Furthermore, the first doped layer in the first region is subjected to crystallization treatment, which is to irradiate the first doped layer in the first region with a laser.

[0043] Furthermore, the solar cell prepared is the aforementioned solar cell.

[0044] This application also provides a battery assembly including the aforementioned solar cell.

[0045] The solar cell provided in this application features a first doped layer with a crystalline region in the first region. This crystalline region exhibits good conductivity, which is beneficial for carrier collection. Furthermore, in the second region, at least a portion of the first doped layer is amorphous. Amorphous regions have lower carrier mobility and sheet resistance than crystalline regions, which significantly reduces leakage current. This is because photogenerated carriers migrate and diffuse laterally (perpendicular to the thickness direction of the doped layer) and longitudinally (parallel to the thickness direction of the doped layer) within the doped layers of different doping types. Attached Figure Description

[0046] The accompanying drawings are provided to better understand this application and do not constitute an undue limitation thereof. Wherein:

[0047] Figure 1 This is one of the structural schematic diagrams of the solar cell provided in this application.

[0048] Figure 2 This is a partial structural schematic diagram of the solar cell provided in this application.

[0049] Figure 3 This is a partial structural schematic diagram of the solar cell provided in this application.

[0050] Figure 4 This is a partial structural schematic diagram of the solar cell provided in this application.

[0051] Figure 5 This is a partial structural schematic diagram of the solar cell provided in this application.

[0052] Figure 6 This is a partial structural schematic diagram of the solar cell provided in this application.

[0053] Figure 7 This is a partial structural schematic diagram of the solar cell provided in this application.

[0054] Figure 8 This is a partial structural schematic diagram of the solar cell provided in this application.

[0055] Figure 9 This is a partial structural schematic diagram of the solar cell provided in this application.

[0056] Figure 10 This is a partial structural schematic diagram of the solar cell provided in this application.

[0057] Figure 11 This is one of the structural schematic diagrams of the solar cell provided in this application.

[0058] Figure 12 This is one of the structural schematic diagrams of the solar cell provided in this application.

[0059] Figure 13 The image shows the Raman spectrum of the first amorphized region A in Example 1 and Comparative Example 1 of this application.

[0060] Figure 14 This is a transmission electron microscope image of the solar cell prepared in Example 1 of this application after laser crystallization.

[0061] Figure 15 Parallel resistance diagram of the normalized battery structure provided in this application.

[0062] Figure 16The series resistance diagram of the normalized battery structure provided in this application.

[0063] Figure 17 This is one of the structural schematic diagrams of the solar cell provided in this application.

[0064] Figure 18 This is one of the structural schematic diagrams of the solar cell provided in this application.

[0065] Explanation of reference numerals in the attached figures

[0066] 1-First electrode, 2-Second electrode, 3-Silicon substrate, 4-Second passivation layer, 5-Second crystallization region, 6-Second conductive layer, 7-Second doped layer, 8-Insulating layer, 9-Laser absorption layer, 10-First doped layer, 11-First conductive layer, 12-First crystallization region, 13-Light incident surface passivation layer, 14-Antireflection layer, 15-First passivation layer, 16-First amorphous region A, 17-Second amorphous region B, 18-First amorphous region B. Detailed Implementation

[0067] The following description provides exemplary embodiments of this application, including various details to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this application. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0068] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, in the description of this application, the stacked layers are not necessarily in direct contact, and therefore should not be construed as a limitation of this application.

[0069] This application provides a solar cell including a silicon substrate 3, with a first region and a second region adjacent to each other along a first direction on one side surface of the silicon substrate 3. A first doped layer 10 and a first electrode 1 are sequentially stacked on the silicon substrate 3 in the first region; the first doped layer 10 extends into the second region; the first doped layer 10 in the first region has a crystallized region, and the projection of the crystallized region onto the silicon substrate 3 at least partially overlaps with the projection of the first electrode 1 onto the silicon substrate 3.

[0070] The solar cell provided in this application features a first doped layer 10 in the first region that exhibits crystalline regions due to the lateral (perpendicular to the thickness direction of the doped layer) and longitudinal (parallel to the thickness direction of the doped layer) migration and diffusion of photogenerated carriers within doped layers of different doping types. Crystalline regions possess good conductivity, which is beneficial for carrier collection. Furthermore, in the second region, at least a portion of the first doped layer 10 is amorphous. Amorphous regions have lower carrier mobility and lower sheet resistance than crystalline regions, significantly reducing leakage current.

[0071] The specific structure of the above-mentioned solar cell will be described in detail below through several embodiments. Example 1:

[0072] The silicon substrate 3 includes a first region, a second region, and a third region adjacent to each other along a first direction on one side surface. In the third region, a second doped layer 7 and a second electrode 2 are sequentially stacked on the silicon substrate 3. The first doped layer 10 and the second doped layer 7 extend into the second region. The second doped layer 7 in the third region has a crystallized region. The projection of the crystallized region in the third region onto the silicon substrate 3 at least partially overlaps with the projection of the second electrode 2 onto the silicon substrate 3. In the second region, at least a portion of the second doped layer 7 is an amorphous region. The first doped layer 10 and the second doped layer 7 have opposite conductivity.

[0073] The solar cell provided in this application addresses the issue that photogenerated carriers undergo both lateral (perpendicular to the thickness direction of the doped layer) and longitudinal (parallel to the thickness direction of the doped layer) migration and diffusion in doped layers of different doping types. By isolating the first doped layer 10 in the first region and the second doped layer 7 in the third region with a high-resistivity second region, lateral carrier migration can be reduced, thus decreasing leakage current. Furthermore, at least one of the first doped layer 10 in the first region and the second doped layer 7 in the third region has a crystalline region, which exhibits good conductivity, facilitating carrier collection. Additionally, in the second region, at least a portion of both the first doped layer 10 and the second doped layer 7 is amorphous. Amorphous regions have lower carrier mobility and lower sheet resistance than crystalline regions, significantly reducing leakage current.

[0074] In Embodiment 1, the second doped layer 7 in the amorphous region is an amorphous silicon layer, and the second doped layer 7 in the crystalline region includes nanocrystalline silicon and / or microcrystalline silicon. In this embodiment, when the solar cell further includes a second passivation layer 4, the second passivation layer 4 is located on the side of the second doped layer 7 closest to the silicon substrate 3. The second passivation layer 4 can be one or more of intrinsic amorphous silicon, intrinsic microcrystalline silicon, and intrinsic nanocrystalline silicon.

[0075] In some embodiments, the first doped layer 10 in the first region and the second doped layer 7 in the third region are isolated by a second passivation layer 4 in the second region, a second doped layer 7 that is at least partially amorphous, an insulating layer 8, a first passivation layer 15, and a first doped layer 10 that is at least partially amorphous. Moreover, both the first doped layer 10 in the first region and the second doped layer 7 in the third region have crystalline regions. Therefore, the solar cell not only avoids the risk of leakage at the junction between the first region and the third region, but also reduces the contact resistance between the first region and the third region, thereby improving the performance of the solar cell.

[0076] In some embodiments, within the first region, the first doped layer 10 includes a first crystallized region 12 and a first amorphous region A 16;

[0077] The portion of the first crystallization region 12 that is at least away from the silicon substrate 3 has crystals.

[0078] In some implementations, such as Figure 1 As shown, in the first region, the first doped layer 10 includes a first crystalline region 12 and a first amorphous region A 16; the first amorphous region A 16 includes side portions located at both ends of the first region, and the side portions are stacked on the second doped layer 7 and the side of the insulating layer near the first region. The first amorphous region A 16 also includes an intermediate portion located between the side portions and the first crystalline region, one end of the intermediate portion is connected to one side portion, and the other end of the intermediate portion is connected to the first crystalline region 12. When the first amorphous region A 16 includes two intermediate portions, the first crystalline region 12 is disposed between the two intermediate portions. That is, the first amorphous region A extends along the horizontal surface of the first conductive layer 11 away from the first electrode 1 towards the direction near the second region, passes through the side of the first conductive layer 11 near the second region, and is connected to the first amorphous region B in the second region. Because in the prior art, the first doped layer 10 and the second doped layer 7 are separated by a passivation layer at the junction of the second region (GAP region) and the first region. The passivation layer at the junction is relatively thin, making it easy for the first doped layer 10 and the second doped layer 7 to overlap, leading to leakage. In the second region of this application, at least a portion of the first doped layer 10 and the second doped layer 7 are amorphous regions. The amorphous portion can increase the sheet resistance of the first doped layer 10 and the second doped layer 7 at the overlap, increasing the parallel resistance of the battery. Furthermore, by only partially crystallizing the first doped layer 10 and / or the second doped layer 7, the conductivity of the doped layer at the crystallized area is improved. The uncrystallized area can further reduce the risk of leakage at the overlap of the first doped layer 10 and the second doped layer 7.

[0079] Furthermore, the sum of the lengths L of the middle portion and the adjacent side portions stacked on the silicon substrate 3 is ≥ 5 μm. For example, L can be 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 11 μm, 12 μm, 13 μm, 14 μm, 15 μm, 16 μm, 17 μm, 18 μm, 19 μm, 20 μm, etc. If L is too small, the risk of leakage will increase; if L is larger, the risk of leakage will be smaller, but at the same time, the area of ​​the crystallization region will be smaller, and the degree to which crystallization reduces the series resistance of the battery will be smaller.

[0080] In some implementations, such as Figure 17 As shown, the first doped layer 10 includes a first crystallized region 12 and a first amorphous region A 16; the first amorphous region A 16 includes side portions located at both ends of the first region, and the side portions are stacked on the second doped layer 7 and the side portion of the insulating layer near the first region. The two side portions are respectively connected to the two ends of the first crystallized region 12 at one end near the silicon substrate 3.

[0081] In some embodiments, the first doped layer 10 in the first region only includes the first amorphous region A 16, that is, the first doped layer 10 in the entire first region is the first amorphous region A 16.

[0082] In some embodiments, in the first region, the first doped layer 10 only includes the first crystallization region 12, that is, the first doped layer 10 in the entire first region is the first crystallization region 12.

[0083] In this application, within the third region, the second doped layer 7 includes a second crystallized region 5 and / or a second amorphous region A, wherein at least a portion of the second crystallized region 5 on the side away from the silicon substrate 3 has crystals.

[0084] In some embodiments, within the third region, the second doped layer 7 includes a second crystallized region 5 and a second amorphized region A.

[0085] In some implementations, the second doped layer 7 in the third region includes only the second crystallization region 5.

[0086] In some implementations, the second doped layer 7 in the third region includes only the second amorphous region A.

[0087] In some implementations, in the first region, the first doped layer 10 includes only the first amorphous region, and in the third region, the second doped layer 7 includes only the second crystalline region 5.

[0088] In some embodiments, in the first region, the first doped layer 10 includes only the first amorphous region, and in the third region, the second doped layer 7 includes the second crystalline region 5 and the second amorphous region.

[0089] In some embodiments, in the first region, the first doped layer 10 includes a first crystallized region 12 and a first amorphous region, and in the third region, the second doped layer 7 includes only a second amorphous region.

[0090] In some embodiments, in the first region, the first doped layer 10 includes a first crystallized region 12 and a first amorphous region, and in the third region, the second doped layer 7 includes only the second crystallized region 5.

[0091] In some embodiments, in the first region, the first doped layer 10 includes a first crystallized region 12 and a first amorphous region, and in the third region, the second doped layer 7 includes a second crystallized region 5 and a second amorphous region.

[0092] In some embodiments, within the first region, the crystallization rate of the crystallization region of the first doped layer gradually decreases along the thickness direction from the side surface away from the silicon substrate 3 to the side closer to the silicon substrate 3; that is, within the first crystallization region 12, the crystallization rate of the first crystallization region 12 gradually decreases in the direction from the first conductive layer 11 to the silicon substrate 3.

[0093] In some embodiments, within the first region, the crystallization rate of the crystallization region of the first doped layer is equal along the thickness direction from the side surface away from the silicon substrate 3 to the side surface near the silicon substrate 3; that is, in some embodiments, within the first crystallization region 12, the crystallization rate of the first crystallization region 12 is the same in the direction from the first conductive layer 11 to the silicon substrate 3.

[0094] In some embodiments, within the second crystallization region 5, the crystallization rate gradually decreases along the thickness direction from the side surface away from the silicon substrate 3 to the side closer to the silicon substrate 3; that is, the crystallization rate of the second crystallization region 5 gradually decreases in the direction from the second conductive layer 6 to the second passivation layer 4.

[0095] In some embodiments, within the second crystallization region 5, the crystallization rate is equal along the thickness direction from the side surface away from the silicon substrate 3 to the side surface near the silicon substrate 3; that is, the crystallization rate of the second crystallization region 5 is the same in the direction from the second conductive layer 6 to the second passivation layer 4.

[0096] In this application, within the second region, the first doped layer 10 is at least on the side closest to the first region as a first amorphous region B 18. The length of the first amorphous region B 18 is ≥50μm, for example, it can be 50μm, 55μm, 60μm, 65μm, 70μm, etc.

[0097] The second doped layer 7 has at least one side closest to the first region as a second amorphous region B 17. The length of the second amorphous region B 17 is ≥50μm, for example, it can be 50μm, 55μm, 60μm, 65μm, 70μm, etc.

[0098] In some embodiments, within the second region, the first doped layer 10 includes only the first amorphous region B 18. The length of the first amorphous region B 18 is ≥50μm, for example, it can be 50μm, 55μm, 60μm, 65μm, 70μm, etc. The first doped layer 10 within the second region is not crystallized, which can further reduce the risk of leakage current.

[0099] In some embodiments, within the second region, the first doped layer 10 includes a first amorphous region B 18 and a first crystalline region B, with the first amorphous region B 18 being close to the first region and the first crystalline region B being close to the third region.

[0100] In some embodiments, within the second region, the second doped layer 7 comprises only the second amorphous region B 17. The length of the second amorphous region B 17 is ≥50 μm, for example, it can be 50 μm, 55 μm, 60 μm, 65 μm, 70 μm, etc. The first doped layer 10 within the second region is entirely amorphous, which can further reduce the risk of leakage current.

[0101] In some implementations, the length of the first amorphous region B 18 in the second region is ≥50μm. When the length of the first amorphous region B 18 is too short, the isolation effect of the second region on the first region is poor. When the length of the first amorphous region B 18 is too long, the conductive area will become smaller, affecting the battery efficiency.

[0102] The length of the second amorphous region B17 is ≥50μm. When the length of the second amorphous region B17 is too short, the isolation effect of the second region on the third region is poor. When the length of the second amorphous region B17 is too long, the conductive area will become smaller, affecting the battery efficiency.

[0103] In some embodiments, the length of the first amorphous region B18 can be 50 μm-200 μm. The length of the second amorphous region B17 can be 50 μm-200 μm.

[0104] In some embodiments, within the second region, the second doped layer 7 includes a second amorphous region B 17 and a second crystallized region B, with the second amorphous region B 17 located near the first region and the second crystallized region B located near the third region.

[0105] In this application, the projection of the first electrode 1 onto the silicon substrate 3 is less than or equal to the projection of the first crystallized region 12 onto the silicon substrate 3. The projection of the second electrode 2 onto the silicon substrate 3 is less than or equal to the projection of the second crystallized region 5 onto the silicon substrate 3.

[0106] In this application, the projection of the first crystallization region 12 onto the silicon substrate 3 at least partially overlaps with the projection of the first electrode 1 onto the silicon substrate 3.

[0107] In some embodiments, the projection of the first electrode 1 onto the silicon substrate 3 overlaps with the projection of the first crystallized region 12 onto the silicon substrate 3.

[0108] In some embodiments, the projection of the first electrode 1 onto the silicon substrate 3 completely coincides with the projection of the first crystallized region 12 onto the silicon substrate 3.

[0109] In some embodiments, the projection of the first electrode 1 onto the silicon substrate 3 coincides with the projection of the first crystallization region 12 onto the silicon substrate 3, and the area of ​​the projection of the first electrode 1 onto the silicon substrate 3 is smaller than the area of ​​the projection of the first crystallization region 12 onto the silicon substrate 3.

[0110] In some embodiments, the projection of the first electrode 1 onto the silicon substrate 3 coincides with the projection of the first crystallization region 12 onto the silicon substrate 3, and the area of ​​the projection of the first electrode 1 onto the silicon substrate 3 is smaller than the area of ​​the projection of the first crystallization region 12 onto the silicon substrate 3.

[0111] In this application, the projection of the second crystallization region 5 onto the silicon substrate 3 at least partially overlaps with the projection of the second electrode 2 onto the silicon substrate 3.

[0112] In some embodiments, the projection of the second electrode 2 onto the silicon substrate 3 overlaps with the projection of the second crystallization region 5 onto the silicon substrate 3.

[0113] In some embodiments, the projection of the second electrode 2 onto the silicon substrate 3 completely coincides with the projection of the second crystallization region 5 onto the silicon substrate 3.

[0114] In some embodiments, the projection of the second electrode 2 onto the silicon substrate 3 coincides with the projection of the second crystallization region 5 onto the silicon substrate 3, and the area of ​​the projection of the second electrode 2 onto the silicon substrate 3 is smaller than the area of ​​the projection of the second crystallization region 5 onto the silicon substrate 3.

[0115] In some embodiments, the projection of the second electrode 2 onto the silicon substrate 3 coincides with the projection of the second crystallization region 5 onto the silicon substrate 3, and the area of ​​the projection of the second electrode 2 onto the silicon substrate 3 is smaller than the area of ​​the projection of the second crystallization region 5 onto the silicon substrate 3.

[0116] In some embodiments, the concentration of doped elements in the first crystallized region 12 is greater than the concentration of doped elements in the first amorphous region A 16.

[0117] In some embodiments, the concentration of doped elements in the second crystallization region 5 is greater than the concentration of doped elements in the second amorphous region A.

[0118] In this application, the first crystallization region 12 is a first microcrystalline doped layer, a first polycrystalline doped layer, or a first nanocrystalline doped layer.

[0119] The second crystallization region 5 is a second microcrystalline doped layer, a second polycrystalline doped layer, or a second nanocrystalline doped layer.

[0120] Both the first amorphized region A 16 and the first amorphized region B 18 are selected from one of the first amorphous silicon doped layer, the first amorphous silicon carbide (SiCx) doped layer, or the first amorphous silicon oxide (SiOx) doped layer.

[0121] The second amorphization region A and the second amorphization region B 17 are both selected from one of the second amorphous silicon doped layer, the second amorphous silicon carbide (SiCx) doped layer, or the second amorphous silicon oxide (SiOx) doped layer.

[0122] The first crystallization region 12 is selected from one of the first crystalline silicon doped layer, the first crystalline silicon carbide (SiCx) doped layer, or the first crystalline silicon oxide (SiOx) doped layer.

[0123] The second crystallization region 5 is selected from one of the following: a second crystalline silicon doped layer, a second crystalline silicon carbide (SiCx) doped layer, or a second crystalline silicon oxide (SiOx) doped layer.

[0124] The thickness of both the first amorphized region A 16 and the first amorphized region B 18 is 5nm-200nm, for example, it can be 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 180nm, 190nm or 200nm.

[0125] The thickness of both the second amorphized region A and the second amorphized region B 17 is 5nm-200nm, for example, it can be 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 180nm, 190nm or 200nm.

[0126] The thickness of the first crystallization region 12 is 5nm-200nm, for example, it can be 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 180nm, 190nm or 200nm.

[0127] The thickness of the second crystallization region 5 is 5nm-200nm, for example, it can be 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 180nm, 190nm or 200nm.

[0128] In this application, in the first region, the crystallization rate of the first doped layer in the crystallization region is 0.01%-100%, for example, it can be 3%, 5%, 10%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, 80%, 90%, etc.

[0129] In the third region, the crystallization rate of the second doped layer in the crystallization region is 0.01-100%, for example, it can be 3%, 5%, 10%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, 80%, 90%, etc.

[0130] Crystallinity can be measured using Raman spectroscopy. Amorphous silicon / silicon carbide / silicon oxide, microcrystalline silicon / silicon carbide / silicon oxide, and crystalline silicon / silicon carbide / silicon oxide have different wavenumbers; for example, amorphous silicon is approximately 480 / cm², microcrystalline silicon is approximately 510 / cm², and crystalline silicon is 520.7 / cm². The amount of each component affects the Raman spectral intensity of the corresponding peak, and the crystallinity is obtained by integration. Crystallinity is a parameter characterizing the degree of crystallization. Increased crystallinity leads to increased carrier mobility, increased effective doping concentration, and improved conductivity of the doped layer. Microcrystalline silicon has a short-range ordered atomic structure, while amorphous silicon is amorphous; therefore, the crystallization region and grain size can be observed using transmission electron microscopy.

[0131] The grain size of the first crystallization region 12 is in the nanometer range, not exceeding 100 nm, for example, it can be 100 nm, 90 nm, 80 nm, 70 nm, 60 nm, 50 nm, 40 nm or 30 nm.

[0132] The grain size of the second crystallization region 5 is in the nanometer range, not exceeding 100 nm, for example, it can be 100 nm, 90 nm, 80 nm, 70 nm, 60 nm, 50 nm, 40 nm or 30 nm.

[0133] Grain size can be observed using a transmission electron microscope.

[0134] In this application, the first crystallization region 12 is distributed in a continuous or discrete manner within the first region.

[0135] Within the third region, the second crystallization region 5 is distributed in a continuous or discrete manner.

[0136] In some implementations, such as Figure 1 Within the first region, the first crystallization region 12 is distributed in a continuous pattern. Within the third region, the second crystallization region 5 is distributed in a continuous pattern.

[0137] In this application, as Figure 1 and Figure 11 As shown, in the first region, the surface where the side is located is at an angle α to the surface where the first crystallization region 12 is located. The value of α ranges from 0 to 180°, but does not include 0° and 180°.

[0138] Specifically, α can be 10°, 20°, 30°, 40°, 50°, 60°, 70°, 80°, 90°, 100°, 110°, 120°, 130°, 140°, 150°, 160°, 170°, etc.

[0139] In this application, as Figure 12 As shown, in the first region, the side can be arc-shaped, and the tangent of the arc surface where the side is located is at an angle α to the surface where the first crystallization region 12 is located. The value of α ranges from 0 to 180°, but does not include 0° and 180°.

[0140] Specifically, α can be 10°, 20°, 30°, 40°, 50°, 60°, 70°, 80°, 90°, 100°, 110°, 120°, 130°, 140°, 150°, 160°, 170°, etc.

[0141] In this application, both the first crystallization region 12 and the second crystallization region 5 are formed by laser irradiation. That is, both the first crystallization region 12 and the second crystallization region 5 are formed by laser irradiation of the amorphous film layer, and part of the amorphous film layer is transformed into crystals under the action of the laser.

[0142] In this application, the selective action of laser light can be used to avoid crystallizing the amorphous n / p film at the edge of the amorphous n-film and amorphous p-film, thus maintaining its high resistivity and limiting the lateral leakage current. At the same time, the crystallization of the first crystallization region 12 and the second crystallization region 5 can increase the effective doping concentration and reduce the contact resistance, thereby helping to reduce the resistance loss of the battery.

[0143] The wavelength of a laser affects its absorption depth in amorphous films and its longitudinal range of action within the film. The longer the wavelength of the laser, the deeper the absorption depth, and the easier it is for amorphous films to transform into crystalline films in the longitudinal or thickness direction. In practical applications, the wavelength of the laser can be determined according to actual needs.

[0144] The greater the laser power, the greater the energy generated by the laser, and the easier it is for amorphous materials to be transformed into crystals.

[0145] Laser power, laser spot overlap rate, laser pulse width, and the number of laser irradiations affect the energy received per unit area, thus influencing the crystallization range, crystallization rate, and the degree of passivation damage to the silicon wafer surface beneath the film. Higher laser energy facilitates the transformation of amorphous materials into crystals, but also increases the degree of passivation damage to the silicon wafer surface. Therefore, in practical applications, the laser parameters should be designed according to specific conditions.

[0146] In this application, the single-spot energy density of a functional laser can be used to characterize the laser energy, and those skilled in the art can control the laser energy by adjusting the above parameters.

[0147] In the method of this application, for example, a single-spot energy density of the laser can be used, such as a single-spot energy density of the laser > 60 mJ / cm². 2 For example, it can be 61 mJ / cm. 2 65mJ / cm 2 70mJ / cm 2 75mJ / cm 2 80mJ / cm 2 85mJ / cm 2 90mJ / cm 2 100mJ / cm 2 110mJ / cm 2 120mJ / cm 2 130mJ / cm 2 140mJ / cm 2 150mJ / cm 2 160mJ / cm 2 170mJ / cm 2 180mJ / cm 2 190mJ / cm2 200mJ / cm 2 wait. Example 2:

[0148] A third region is also included on one side surface of the silicon substrate 3. Along the first direction, the third region is located on the side of the second region away from the first region. That is, one side surface of the silicon substrate 3 includes a first region, a second region, and a third region that are sequentially adjacent along the first direction.

[0149] In the third region, a second doped layer 7 and a second electrode 2 are sequentially stacked on the silicon substrate 3;

[0150] The second doped layer 7 extends into the second region; and within the second region, the second doped layer 7 is located on the side of the first doped layer 10 close to the silicon substrate 3; the first doped layer 10 and the second doped layer 7 have opposite conductivity, so as to collect and export electrons and holes respectively, which is conducive to the formation of photocurrent.

[0151] In some embodiments, the second doped layer 7 comprises doped polycrystalline silicon. Doped polycrystalline silicon has a high current transport capability, so when the second doped semiconductor layer is a doped polycrystalline silicon layer, it can further reduce the carrier recombination rate, which is beneficial to improving the photoelectric conversion efficiency of the hybrid solar cell.

[0152] like Figure 18 As shown, the solar cell also includes a second passivation layer 4, which is located on the side of the second doped layer 7 closest to the silicon substrate 3. That is, the second passivation layer 4 is located between the second doped layer 7 and the silicon substrate 3. For example, if the second doped layer 7 is doped polycrystalline silicon, the second passivation layer 4 can be a tunneling oxide layer. Thus, the second doped layer 7 and the second passivation layer 4 form a tunneling oxide passivation contact. The tunneling oxide passivation technology can form a tunneling film between the second electrode 2 and the silicon substrate 3, isolating the second electrode 2 from the silicon substrate 3, reducing contact recombination losses, and ensuring that electrons tunneling through the film do not affect current transfer. Simultaneously, passivation can bend the surface bandgap, reducing surface recombination losses on the silicon wafer, and effectively improving the front passivation and metal contact problems.

[0153] In some embodiments, the first doped layer 10 of the amorphous region can be an amorphous silicon layer, and the first doped layer 10 of the crystalline region includes nanocrystalline silicon and / or microcrystalline silicon. For example... Figure 18 As shown, the solar cell also includes a first passivation layer, which is located between the silicon substrate 3 and the first doped layer 10. That is, the first passivation layer is located on the side of the first doped layer 10 closer to the silicon substrate 3. The first passivation layer can be one or more of intrinsic amorphous silicon, intrinsic microcrystalline silicon and intrinsic nanocrystalline silicon.

[0154] In some embodiments, within the first region, the first doped layer 10 includes a first crystallized region 12 and a first amorphous region A 16;

[0155] The portion of the first crystallization region 12 that is at least away from the silicon substrate 3 has crystals.

[0156] like Figure 1 As shown, within the first region, the first doped layer 10 includes a first crystalline region 12 and a first amorphous region A16. The first amorphous region A16 includes side portions located at both ends of the first region, which are stacked on the side of the second doped layer 7 near the first region. The first amorphous region A16 also includes a middle portion located between the side portions and the first crystalline region, with one end of the middle portion connected to one of the side portions and the other end connected to the first crystalline region 12. The passivation layer at the interface is relatively thin, making it easy for the first doped layer 10 and the second doped layer 7 to overlap, leading to leakage. By including the side portion within the amorphous region, the overlap of the first doped layer 10 and the second doped layer 7 can be avoided, preventing leakage.

[0157] like Figure 18 As shown, the sum of the lengths L of the middle portion and the adjacent side portion stacked on the silicon substrate 3 is ≥ 5μm. For example, L can be 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, 11μm, 12μm, 13μm, 14μm, 15μm, 16μm, 17μm, 18μm, 19μm, 20μm, etc. If L is too small, the risk of leakage will increase; if L is larger, the risk of leakage will be smaller, but at the same time, the area of ​​the crystallization region will be smaller, and the degree to which crystallization reduces the series resistance of the battery will be smaller.

[0158] In this second embodiment, the characteristics of the first doped layer 10 and the first electrode, as well as the characteristics of the silicon substrate, can be referred to in the first embodiment, and will not be repeated here.

[0159] The following content applies to Examples 1 to 2 and other examples.

[0160] In some embodiments, such as Figure 18 As shown, the solar cell further includes a first conductive layer 11, which is located between the first doped layer and the first electrode 1. Additionally, the solar cell may also include a second conductive layer 6, which is located between the second doped layer and the second electrode 2. The conductive layer has high conductivity, which can promptly remove collected charge carriers and reduce the carrier recombination rate.

[0161] In some embodiments, in the first region, a first passivation layer 15 is further disposed between the silicon substrate 3 and the first doped layer 10, and a first conductive layer 11 is further disposed between the first doped layer 10 and the first electrode 1; that is, in the first region, the first passivation layer 15, the first doped layer 10, the first conductive layer 11 and the first electrode 1 are sequentially stacked on the silicon substrate 3.

[0162] In the third region, a second passivation layer 4 is disposed between the silicon substrate 3 and the second doped layer 7, and a second conductive layer 6 is disposed between the second doped layer 7 and the second electrode 2; that is, in the third region, the second passivation layer 4, the second doped layer 7, the second conductive layer 6 and the second electrode 2 are sequentially stacked on the silicon substrate 3.

[0163] The first passivation layer 15 and the second passivation layer 4 extend into the second region, such that the second passivation layer 4, the second doped layer 7, the first passivation layer 15, and the first doped layer 10 are sequentially stacked on the silicon substrate 3 in the second region. In some embodiments, an insulating layer 8 is disposed between the first passivation layer 15 and the second doped layer 7 in the second region; that is, the second passivation layer 4, the second doped layer 7, the insulating layer 8, the first passivation layer 15, and the first doped layer 10 are sequentially stacked on the silicon substrate 3 in the second region.

[0164] The silicon substrate 3 includes a light-facing surface and a back-light-facing surface, which are distributed opposite to each other. The back-light-facing surface of the silicon substrate 3 includes a first region and a second region that are adjacent along a first direction. Here, "adjacent" means that the first region and the second region are connected sequentially but do not overlap. The relative position and relative size of the first region are not specifically defined.

[0165] In some embodiments, the silicon substrate 3, the first passivation layer 15, the first doped layer 10, the second passivation layer 4, and the second doped layer 7 all have a textured structure.

[0166] In some embodiments, the silicon substrate 3, the first passivation layer 15, the first doped layer 10, the second passivation layer 4, and the second doped layer 7 all have smooth surfaces.

[0167] In some implementations, the silicon substrate 3, the first passivation layer 15, and the first doped layer 10 in the first region have a textured surface.

[0168] In some embodiments, the silicon substrate 3, the first passivation layer 15, and the first doped layer 10 in the first region are smooth surfaces.

[0169] In the case where a third region is also included on one side surface of the silicon substrate, each functional layer in the third region has a smooth surface, or each functional layer in the third region has a textured structure.

[0170] Specifically, a light-incident passivation layer 13 and an anti-reflection layer 14 are sequentially stacked on the side of the silicon substrate 3 facing away from the first passivation layer 15 and the second passivation layer 4. That is, a light-incident passivation layer 13 and an anti-reflection layer 14 are sequentially stacked on the light-facing side of the silicon substrate 3.

[0171] The silicon substrate 3 can be either a p-type doped silicon substrate 3 or an n-type doped silicon substrate 3.

[0172] The light-incident passivation layer 13 is intrinsic hydrogenated amorphous silicon with a thickness of 1-20 nm, for example, it can be 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm or 20 nm.

[0173] The antireflection layer 14 is a composite antireflection structure composed of silicon nitride, silicon oxide, magnesium fluoride, etc., or silicon nitride, silicon oxide, and magnesium fluoride, with a thickness not exceeding 200 nm. For example, it can be 200 nm, 190 nm, 180 nm, 170 nm, 160 nm, 150 nm, 140 nm, 130 nm, 120 nm, 110 nm, 100 nm, 90 nm, 80 nm, 70 nm, 60 nm, 50 nm, 40 nm, 30 nm, etc.

[0174] The insulating layer 8 is a silicon nitride layer, i.e., a SiNx layer, where x represents different silicon-nitrogen ratios. Different SiNx layers are generally represented by different refractive indices, ranging from 1.9 to 2.7. Its thickness is 30-200 nm, for example, it can be 200 nm, 190 nm, 180 nm, 170 nm, 160 nm, 150 nm, 140 nm, 130 nm, 120 nm, 110 nm, 100 nm, 90 nm, 80 nm, 70 nm, 60 nm, 50 nm, 40 nm, 30 nm, etc.

[0175] The first passivation layer 15 can be intrinsic hydrogenated amorphous silicon with a thickness of 1 nm to 20 nm, for example, it can be 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm or 20 nm.

[0176] The second passivation layer 4 can be intrinsic hydrogenated amorphous silicon or a tunneling oxide layer, with a thickness of 1 nm to 20 nm, for example, it can be 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm or 20 nm.

[0177] The first passivation layer 15 and the second passivation layer 4 are different layers, for example, they can have different hydrogen content, thickness and processes.

[0178] The first conductive layer 11 is a TCO layer with a thickness of 5 nm to 200 nm, for example, it can be 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, or 200 nm.

[0179] The second conductive layer 6 is a TCO layer with a thickness of 5 nm to 200 nm, for example, it can be 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, or 200 nm.

[0180] The first electrode 1 is made of silver, aluminum, copper, or an alloy thereof.

[0181] The second electrode 2 is made of silver, aluminum, copper, or their alloys.

[0182] In some embodiments, the thickness of the first doped layer is phosphorus or boron. For example, the thickness of the first doped layer is phosphorus, and the element doped in the second doped layer is boron; or, the element doped in the first doped layer is boron, and the element doped in the second doped layer is phosphorus.

[0183] In some embodiments, the thickness of the first doped layer is 5nm-200nm, for example, it can be 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 180nm, 190nm or 200nm.

[0184] The thickness of the second doped layer is 5nm-200nm, for example, it can be 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, 100nm, 110nm, 120nm, 130nm, 140nm, 150nm, 160nm, 170nm, 180nm, 190nm or 200nm.

[0185] This application also provides a solar cell, including a silicon substrate 3 and a first doped layer disposed on one side surface of the silicon substrate. The first doped layer includes a first portion and a second portion, wherein the first portion and the second portion are adjacent to each other along a second direction. That is, along the second direction, both sides of the first portion are adjacent to the second portion, or one side of the first portion is adjacent to the second portion. The second direction is parallel to the surface of the silicon substrate 3, and the second direction can be parallel to the arrangement direction of the first region, the second region, and the third region. The crystallinity of the first portion is greater than that of the second portion. The first doped layer can include at least one of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon, that is, the first doped layer can be an amorphous silicon layer, a nanocrystalline silicon layer, or a microcrystalline silicon layer. Alternatively, the first doped layer can also be any combination of two or three of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon. The crystallinity of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon can be improved after laser crystallization.

[0186] With the above technical solution, a crystalline structure is formed in the first portion of the first doped layer, resulting in a portion that is both crystalline and non-crystalline. The first portion is not entirely crystalline; it is mostly amorphous, with only a portion forming a crystalline structure, such as nanocrystals. The second portion of the first doped layer, adjacent to the first portion along the second direction, remains uncrystallized, retaining its original amorphous structure. (It should be noted that when the first doped layer includes nanocrystalline silicon or microcrystalline silicon, the degree of crystallinity or crystallineity of the nanocrystalline silicon or microcrystalline silicon in the second portion remains unchanged.) This results in the overall crystallinity of the first portion of the first doped layer being greater than that of the second portion. It is understandable that, all other things being equal, the lower the crystallinity of the semiconductor layer, the smaller the grains within it, potentially exhibiting the disordered nature of amorphous silicon. Smaller grains in the semiconductor layer result in more interfaces between the grains, leading to higher resistance at the grain interfaces. Therefore, the crystalline structure in the first part of the first doped layer reduces the contact resistance, thereby reducing the contact resistance between the first part and the conductive material (transparent conductive layer or electrode), which in turn helps to reduce the transport loss of charge carriers collected in the first doped layer to the conductive material. Simultaneously, the degree of crystallinity in the second part of the first doped layer is less than that in the first part, ensuring the passivation effect of the second part adjacent to the first part along the second direction, reducing recombination at the edge of the first doped layer. That is, for back-contact solar cells, the second part of the first doped layer is closer to the second semiconductor, and the lower degree of crystallinity in the second part ensures the passivation effect of the second part, preventing leakage between the second part and the second doped layer 7. As can be seen, by setting reasonable crystalline and amorphous regions on the first doped layer, the higher degree of crystallinity in the first part optimizes the overall cell efficiency of the solar cell, improving cell efficiency, while the lower degree of crystallinity in the second part ensures the passivation effect of the second part, preventing leakage.

[0187] This application also provides a method for preparing a solar cell, comprising the following steps:

[0188] Step 1: Provide a silicon substrate 3, one side surface of the silicon substrate 3 including a first region and a second region adjacent along a first direction;

[0189] Step 2: Form a first doped layer in the first and second regions of the silicon substrate 3; the first doped layer 10 is a first amorphous doped layer;

[0190] Step 3: Crystallize at least a portion of the first doped layer 10 in the first region, so that at least a portion of the first doped layer 10 in the first region has a crystallized region;

[0191] Step 4: Form a first electrode 1 in the first region such that the projection of the crystallized region on the silicon substrate 3 at least partially overlaps with the projection of the first electrode 1 on the silicon substrate 3.

[0192] In some embodiments, a third region is further included on one side surface of the silicon substrate 3, and along a first direction, the third region is located on the side of the second region opposite to the first region.

[0193] The fabrication method of solar cells also includes the following steps:

[0194] A second doped layer 7 is formed in a third region and a second region of the silicon substrate 3; in the second region, the second doped layer 7 is located on the side of the first doped layer closer to the silicon substrate 3; the conductivity of the first doped layer and the second doped layer 7 are opposite.

[0195] A second electrode 2 is formed in the third region.

[0196] It is understood that in the above preparation method, after providing the silicon substrate 3 and before forming the first doped layer in the first and second regions of the silicon substrate 3, the method further includes forming a second doped layer 7 in the third and second regions of the silicon substrate 3; in the second region, the second doped layer 7 is located on the side of the first doped layer close to the silicon substrate 3.

[0197] The formation of the second electrode 2 in the third region can be carried out simultaneously with the formation of the first electrode 1 in the first region. Alternatively, the first electrode 1 can be formed first and then the second electrode 2 can be formed, or the second electrode 2 can be formed first and then the first electrode 1 can be formed.

[0198] For example, the method for preparing the above-mentioned solar cell includes the following steps:

[0199] Step 1: Provide a silicon substrate 3, one side surface of which includes a first region, a second region and a third region that are sequentially adjacent;

[0200] Step 2: Form a second doped layer 7 in the first region, the second region, and the third region of the silicon substrate 3;

[0201] Step 3: Remove the second doped layer 7 in the first region to expose the silicon substrate 3;

[0202] Step 4: A first doped layer 10 is formed on the silicon substrate 3 in the first region, the second region, and the third region; the first doped layer 10 is a first amorphous doped layer;

[0203] Step 5: Perform crystallization treatment on the first doped layer 10 in the first region, so that the first doped layer 10 in the first region has a crystallization region;

[0204] Step 6: Form a first electrode 1 and a second electrode 2 in the first region and the third region respectively, such that the projection of the crystallized region on the silicon substrate 3 at least partially overlaps with the projection of the first electrode 1 on the silicon substrate 3.

[0205] In some embodiments, the second doped layer 7 is a polycrystalline silicon doped layer. Doped polycrystalline silicon has a high current transport capability, so when the second doped semiconductor layer is a doped polycrystalline silicon layer, the carrier recombination rate can be further reduced, which is beneficial to improving the photoelectric conversion efficiency of the hybrid solar cell.

[0206] In some embodiments, the method for preparing a solar cell further includes the step of:

[0207] At least a portion of the second doped layer 7 in the third region is crystallized, such that at least a portion of the second doped layer 7 in the third region forms a crystallized region;

[0208] The projection of the crystallized region in the third region onto the silicon substrate 3 at least partially overlaps with the projection of the second electrode 2 onto the silicon substrate 3.

[0209] It is understood that in the above preparation method, after providing the silicon substrate 3 and before forming the first doped layer in the first and second regions of the silicon substrate 3, the method further includes forming a second doped layer 7 in the third and second regions of the silicon substrate; in the second region, the second doped layer 7 is located on the side of the first doped layer close to the silicon substrate.

[0210] The crystallization treatment of at least a portion of the first doped layer in the first region and the crystallization treatment of at least a portion of the second doped layer 7 in the third region can be performed simultaneously or separately. The formation of the second electrode 2 in the third region and the formation of the first electrode 1 in the first region can be performed simultaneously or separately.

[0211] An exemplary method for fabricating a solar cell includes the following steps:

[0212] Step 1: Provide a silicon substrate 3, one side surface of which includes a first region, a second region and a third region that are sequentially adjacent;

[0213] Step 2: A second doped layer 7 is formed in the first region, the second region, and the third region of the silicon substrate 3; the second doped layer 7 is a second amorphous doped layer;

[0214] Step 3: Remove the second doped layer 7 in the first region to expose the silicon substrate 3;

[0215] Step 4: A first doped layer 10 is formed on the silicon substrate 3 in the first region, the second region, and the third region; the first doped layer 10 is a first amorphous doped layer;

[0216] Step 5: Remove the first doped layer 10 in the third region to expose the second doped layer 7;

[0217] Step 6: Perform crystallization treatment on the first doped layer 10 in the first region and / or the second doped layer 7 in the third region, so that at least one of the first doped layer 10 in the first region and the second doped layer 7 in the third region has a crystallization region;

[0218] Step 7: Form a first electrode 1 and a second electrode 2 in the first region and the third region respectively, such that the projection of the crystallized region on the silicon substrate 3 at least partially overlaps with the projection of the first electrode 1 on the silicon substrate 3, and / or the projection of the crystallized region on the silicon substrate 3 at least partially overlaps with the projection of the second electrode 2 on the silicon substrate 3.

[0219] The first doped layer 10 has opposite conductivity to the second doped layer 7.

[0220] In some embodiments, after crystallizing at least a portion of the first doped layer 10 in the first region, and before forming the first electrode 1 in the first region, a first conductive layer 11 is further formed in the first region. The first electrode 1 is directly formed on the side of the first conductive layer 11 facing away from the silicon substrate 3. When the third region also includes a second conductive layer 6, the first conductive layer 11 and the second conductive layer 6 can be formed in the same step. For example, before forming the first electrode 1 in the first region and before forming the second electrode in the third region, a conductive layer is formed on one side surface of the silicon substrate; the portion of the conductive layer corresponding to the first region is the first conductive layer 11, and the portion of the conductive layer corresponding to the second region is the second conductive layer 6. The conductive layer has an opening extending through its thickness to separate the first conductive layer 11 and the second conductive layer 6. The first conductive layer 11 is located between the first doped layer and the first electrode 1, and the second conductive layer 6 is located between the second doped layer 7 and the second electrode. Thus, the first conductive layer 11 and the second conductive layer 6 can be processed and formed in the same step, improving processing efficiency.

[0221] In step one, the silicon substrate 3 can be p-type doped or n-type doped.

[0222] In some embodiments, the front side of the silicon substrate 3 is textured, and the back side is flat.

[0223] In some embodiments, both the front and back sides of the silicon substrate 3 are textured.

[0224] In some embodiments, the back side of the silicon substrate 3 is textured, and the front side is flat.

[0225] In some embodiments, both the front and back sides of the silicon substrate 3 are planar.

[0226] In some embodiments, the back side of the silicon substrate 3 has a textured surface.

[0227] When the silicon substrate 3 has a textured structure, the actual contact area between the silicon substrate 3 and the amorphous film layer, the amorphous film layer and the TCO film layer, and the TCO film layer and the metal electrode grid line can be increased, thereby reducing the series resistance of the battery.

[0228] In step two, as Figure 2 A second passivation layer 4, a second doped layer 7, and an insulating layer 8 are sequentially formed on the back surface of the silicon substrate 3, and a laser absorption layer 9 is formed on the entire surface of the insulating layer 8.

[0229] The formation methods of the second passivation layer 4, the second doped layer 7, the insulating layer 8, and the laser absorption layer 9 are not further limited. For example, the second passivation layer 4 can be prepared by plasma-enhanced CVD (PECVD) or hot-filament CVD (cat-CVD), and the second doped layer 7 can be prepared by PECVD. The insulating layer 8 and the laser absorption layer 9 can be prepared by PECVD.

[0230] In step three, such as Figures 3-5 As shown, after sequentially removing the laser absorption layer 9, insulating layer 8, second doped layer 7, and second passivation layer 4 in the first region to expose the silicon substrate 3, the laser absorption layer 9 in the second and third regions is also removed.

[0231] The method for removing the laser absorption layer 9, insulating layer 8, second doped layer 7, and second passivation layer 4 is not further limited. For example, the removal methods for the laser absorption layer 9, insulating layer 8, second doped layer 7, and second passivation layer 4 can be as follows:

[0232] Step 3.1: Use laser ablation to remove the laser absorption layer 9 in the first region, thereby exposing the insulating layer 8 underneath.

[0233] Step 3.2: Using a wet process, the exposed insulating layer 8 is removed using an acidic solution, thereby exposing the underlying second doped layer 7. The acidic solution is not further limited; for example, it can be a hydrofluoric acid solution.

[0234] Step 3.3: Use an alkaline solution to remove the exposed second doped layer 7 and the second passivation layer 4 below it, thereby exposing the silicon substrate 3 in the first region and removing the laser absorption layer 9 in the second and third regions. The alkaline solution is not further limited and can be, for example, potassium hydroxide, sodium hydroxide, etc.

[0235] The function of the laser absorption layer 9 is to protect the insulating layer 8 and the second doped layer 7 in the second and third regions from damage during the implementation of steps 3.1-3.2.

[0236] Step 3.4: Texturing is performed on the silicon substrate 3 in the first region.

[0237] In some implementations, step 3.4 may be omitted.

[0238] In step four, as Figure 6 As shown, a first passivation layer 15 and a first doped layer 10 are sequentially formed on the silicon substrate 3 in the first region, and on the insulating layer 8 in the second and third regions. The formation method of the first passivation layer 15 and the first doped layer 10 is not further limited. For example, the first passivation layer 15 is formed by PECVD, and the first doped layer 10 is prepared by PECVD.

[0239] In step five, as Figures 7-9 As shown, the first doped layer 10, the first passivation layer 15, and the insulating layer 8 are removed sequentially within the third region. The method of removing the first doped layer 10, the first passivation layer 15, and the insulating layer 8 is not further limited. For example, the method of removing the first doped layer 10, the first passivation layer 15, and the insulating layer 8 is as follows:

[0240] Step 5.1: Use a laser to remove the first doped layer 10 in the third region, thereby exposing the insulating layer 8 underneath.

[0241] Step 5.2: A wet process is used to remove the exposed insulating layer 8 using an acidic solution, thereby exposing the underlying second doped layer 7. The acidic solution is not specifically limited; for example, it can be a hydrofluoric acid solution.

[0242] Step 5.3 may also be included before step six, such as... Figure 10 As shown, a light-incident passivation layer 13 and an anti-reflection layer 14 are sequentially formed on the light-facing surface of the silicon substrate 3. The formation method of the light-incident passivation layer 13 and the anti-reflection layer 14 is not specifically limited. For example, the light-incident passivation layer 13 is prepared by PECVD, and the anti-reflection layer 14 is prepared by PECVD.

[0243] In step six, a laser is used to irradiate the first doped layer in the first region and / or the second doped layer in the third region, such that at least one of the first doped layer in the first region and the second doped layer in the third region forms a crystallized region, thereby increasing the effective doping concentration of the doped elements in the first crystallized region 12 and / or the second crystallized region 5.

[0244] In some implementations, such as Figure 10As shown, the first region and the third region are irradiated with a laser. Under the action of the laser, the first doped layer in the first region undergoes a crystallization process, so that the first doped layer 10 in the first region includes the first amorphous region A 16 and the first crystallized region 12. The second doped layer in the third region undergoes a crystallization process, so that the second doped layer 7 in the third region is the second crystallized region 5.

[0245] In some implementations, a laser is used to irradiate the third region, and under the action of the laser, the second doped layer portion in the third region undergoes crystal transformation.

[0246] In some embodiments, when the first doped layer in the first region has a textured surface, only the raised portions of the textured surface in the laser irradiation region undergo crystal transformation, while the recessed portions do not undergo crystal transformation.

[0247] In some implementations, when the first doped layer in the first region has a smooth surface, the first doped layer in the laser irradiation region undergoes complete crystal transformation.

[0248] In some implementations, when the second doped layer in the third region has a textured surface, only the raised portions of the textured surface in the laser irradiation region undergo crystal transformation, while the recessed portions do not.

[0249] In some implementations, when the second doped layer in the third region has a smooth surface, the second doped layer in the laser irradiation region undergoes complete crystal transformation.

[0250] The wavelength of a laser affects its absorption depth in amorphous films and its longitudinal range of action within the film. The longer the wavelength of the laser, the deeper the absorption depth, and the easier it is for amorphous films to transform into crystalline films in the longitudinal or thickness direction. In practical applications, the wavelength of the laser can be determined according to actual needs.

[0251] The greater the laser power, the greater the energy generated by the laser, and the easier it is for amorphous materials to be transformed into crystals.

[0252] Laser power, laser spot overlap rate, laser pulse width, and the number of laser irradiations affect the energy received per unit area, thus influencing the crystallization range, crystallization rate, and the degree of passivation damage to the silicon wafer surface beneath the film. Higher laser energy facilitates the transformation of amorphous materials into crystals, but also increases the degree of passivation damage to the silicon wafer surface. Therefore, in practical applications, the laser parameters should be designed according to specific conditions.

[0253] In step seven, a first electrode 1 and a second electrode 2 are formed on the product obtained in step six, specifically including the following steps:

[0254] Step 7.1: Deposit a complete conductive layer on the first region, the second region, and the third region.

[0255] Step 7.2: Remove the conductive layer on the second region, for example, by using laser or photolithography to remove the conductive layer on the second region, so that there is a conductive layer only in the first region and the third region. The conductive layer in the first region is the first conductive layer 11, and the conductive layer in the third region is the second conductive layer 6.

[0256] The first conductive layer 11 is located on the side of the first doped layer 10 that is away from the first passivation layer 15.

[0257] The second conductive layer 6 is on the side of the second doped layer 7 that is away from the second passivation layer 4.

[0258] Step 7.3: Form the first electrode 1 and the second electrode 2 on the first conductive layer 11 and the second conductive layer 6, respectively.

[0259] The formation methods of the first conductive layer 11, the first electrode 1, the second conductive layer 6, and the second electrode 2 are not specifically limited. For example, the first conductive layer 11 and the second conductive layer 6 can be formed simultaneously, both through PVD (Physical Vapor Deposition) or RPD (Reactive Plasma Deposition), etc. Both the first conductive layer 11 and the second conductive layer 6 can be ITO (Indium Tin Oxide), IWO (Indium Tungsten Oxide), AZO (Aluminum Doped Zinc Oxide), etc. The first electrode 1 and the second electrode 2 are obtained by electroplating or screen printing.

[0260] The preparation method of this application produces a solar cell as described above. For each part of the solar cell, please refer to the foregoing description.

[0261] This application also provides a battery assembly including the aforementioned solar cell. Example

[0262] Unless otherwise specified, the experimental methods used in the following examples are conventional methods.

[0263] Unless otherwise specified, all materials and reagents used in the following examples are commercially available.

[0264] Example 1.1

[0265] The solar cell of this embodiment is prepared by a method comprising the following steps:

[0266] Step 1: Polish and clean the silicon wafer, and perform texturing on the light-receiving surface.

[0267] Step 2: On the back of the battery, a 5 nm intrinsic hydrogenated amorphous silicon passivation layer, a 30 nm amorphous n layer, a 100 nm SiNx layer (refractive index 2.5), and a 30 nm laser absorption layer are deposited sequentially using PECVD.

[0268] Step 3: Use a laser to remove the laser absorption layer in the first region, thereby forming a laser opening and exposing the SiNx layer.

[0269] Step 4: Perform a wet process, using 10% hydrofluoric acid to remove the SiNx layer inside the laser opening to expose the amorphous n layer, and using 10% potassium hydroxide to remove the exposed amorphous n layer, the intrinsic hydrogenated amorphous silicon passivation layer below it, and the laser absorption layer in the second and third regions, thereby exposing the silicon wafer in the first region and the silicon nitride layer in the second and third regions.

[0270] Step 5: Using PECVD technology, a 5 nm intrinsic hydrogenated amorphous silicon passivation layer and a 30 nm amorphous p layer are sequentially deposited on the silicon wafer in the first region, the second region, and the third region on the back of the battery.

[0271] Step 6: Use a laser (the single-spot energy density of the laser is 200 mJ / cm²). 2 The amorphous p-layer and intrinsic hydrogenated amorphous silicon passivation layer in the third region are removed to form an opening, thereby exposing the SiNx layer in the third region.

[0272] Step 7: Perform wet treatment, using 10% hydrofluoric acid to remove the SiNx layer in the third region.

[0273] Step 8: Deposit an intrinsic hydrogenated amorphous silicon passivation layer and a SiNx antireflection film on the light-incident surface using PECVD, with a refractive index of 2 and a thickness of 70 nm.

[0274] Step 9: Perform laser crystallization treatment. Use a laser to crystallize the middle region of the amorphous p layer in the first region into a nanocrystalline p region. That is, the first nanocrystalline silicon p-doped region and the first amorphous silicon p-doped region exist simultaneously in the first region. The first amorphous silicon p-doped region surrounds the first nanocrystalline silicon p-doped region. The part of the amorphous n layer and the electrode layer in the third region is crystallized into a nanocrystalline n region.

[0275] Step 10: Sequentially deposit a TCO layer and an Ag electrode (first electrode) on the nanocrystalline p layer; sequentially deposit a TCO layer and an Ag electrode (second electrode) on the nanocrystalline n layer.

[0276] The Raman spectrum of the second doped layer in the third region of this embodiment is shown below. Figure 13 Its transmission electron microscope image is shown below. Figure 14 .

[0277] The difference between Example 2 and Example 1 lies in step 9. In this example, laser processing is performed only on the central region of the amorphous p-layer within the first region, resulting in crystal transformation only occurring in the central region of the amorphous p-layer within the first region. The normalized parallel resistance of the solar cell in this example is shown below. Figure 15 The normalized series resistance of the solar cell in this embodiment is shown in [reference needed]. Figure 16 .

[0278] The difference between Example 3 and Example 1 lies in step 9. In this example, only the amorphous n-layer in the third region is laser-treated, so that only the amorphous n-layer in the third region undergoes crystal transformation. The normalized parallel resistance of the solar cell in this example is shown below. Figure 15 The normalized series resistance of the solar cell in this embodiment is shown in [reference needed]. Figure 16 .

[0279] The difference between Comparative Example 1 and Example 1 is that Comparative Example 1 omits the laser processing step 9; all other parameters are the same as in Example 1. The Raman spectrum of the first doped layer in the first region of the solar cell of this comparative example is shown below. Figure 13 The normalized parallel resistance of the solar cells in this comparative example is shown in [reference needed]. Figure 15 The normalized series resistance of the solar cells in this comparative example is shown in [reference needed]. Figure 16 .

[0280] The difference between Comparative Example 2 and Example 1 is that the amorphous p-layer in the first region was not laser-treated, meaning that the amorphous p-layer in the first region did not undergo any crystal transformation, and the second amorphous silicon doped layer in the second region was replaced with a second nanocrystalline silicon doped layer. The normalized parallel resistance of the solar cell in this example is shown in [reference needed]. Figure 15 .

[0281] For Examples 2-3, Comparative Examples 1 and 2 above, the normalized parallel resistance of the obtained solar cells was tested using an FCT650 instrument under standard test conditions. The results are as follows: Figure 15 For Examples 2-3 and Comparative Example 1 above, the normalized series resistance of the obtained solar cells was tested using an FCT650 testing machine under standard test conditions, see [link to test results]. Figure 16 As shown.

[0282] Summary: From Figure 13 and Figure 14 As can be seen, in this embodiment, under the action of a laser, the amorphous silicon in the first doped layer near the first conductive layer is transformed into crystalline silicon. The characteristic peak of the amorphous silicon film is at 480 cm⁻¹. -1 Nearby, the characteristic peak of the crystalline silicon film is at 510 cm⁻¹. -1Nearby. Compared to the film without laser treatment, the laser-treated film shows better performance at 510 cm⁻¹. -1 The appearance of a peak indicates that amorphous silicon has crystallized after laser treatment.

[0283] Depend on Figure 15 It can be seen that the parallel resistance of the battery in Comparative Example 2 is reduced by 3-4 orders of magnitude compared with the parallel resistance of the batteries in Examples 2 and 3. The parallel resistance of the batteries in Examples 2 and 3 is only slightly different from that in Comparative Example 1. A higher parallel resistance indicates less leakage. Therefore, the solar cell structure of this application can avoid the serious leakage problem that occurs in a full-surface crystalline film structure.

[0284] Depend on Figure 16 As can be seen, compared with Comparative Example 1, the series resistance of the solar cell in this application is significantly reduced. The reduction in contact resistance will lead to an increase in fill factor, thereby improving cell efficiency.

[0285] Although the embodiments of this application have been described above in conjunction with the accompanying drawings, this application is not limited to the specific embodiments and application fields described above. The specific embodiments described above are merely illustrative and instructive, not restrictive. Those skilled in the art can make many other forms based on the guidance of this specification and without departing from the scope of protection of the claims of this application, and these are all within the scope of protection of this application.

Claims

1. A solar cell, comprising a silicon substrate, wherein one side surface of the silicon substrate includes a first region and a second region adjacent to each other along a first direction; wherein, In the first region, a first doped layer and a first electrode are sequentially stacked on the silicon substrate; the first doped layer extends into the second region; The first doped layer in the first region has a crystallized region; the projection of the crystallized region onto the silicon substrate at least partially overlaps with the projection of the first electrode onto the silicon substrate. In the second region, at least a portion of the first doped layer is an amorphous region.

2. The solar cell according to claim 1, wherein, The silicon substrate also includes a third region on one side surface, which is located on the side of the second region opposite to the first region along the first direction; In the third region, a second doped layer and a second electrode are sequentially stacked on the silicon substrate; the second doped layer extends into the second region, and within the second region, the second doped layer is located on the side of the first doped layer closer to the silicon substrate; the conductivity of the first doped layer and the second doped layer are opposite.

3. The solar cell according to claim 2, wherein, The second doped layer comprises doped polycrystalline silicon.

4. The solar cell according to claim 2, wherein, The second doped layer in the third region has a crystallized region; the projection of the crystallized region onto the silicon substrate at least partially overlaps with the projection of the second electrode onto the silicon substrate. In the second region, at least a portion of the second doped layer is an amorphous region.

5. The solar cell according to claim 1, wherein, Within the first region, the first doped layer includes a first crystallized region and a first amorphous region A; The portion of the first crystallization region at least on the side furthest from the silicon substrate has crystals.

6. The solar cell according to claim 5, wherein, The silicon substrate also includes a third region on one side surface, which is located on the side of the second region away from the first region along the first direction; on the third region, a second doped layer and a second electrode are sequentially stacked on the silicon substrate; the first doped layer and the second doped layer have opposite conductivity. In the second region, the first doped layer is stacked on the side of the second doped layer away from the silicon substrate; The first amorphized region A includes side portions located at both ends of the first region along the first direction, and the side portions are stacked on the side of the second doped layer near the first region.

7. The solar cell according to claim 6, wherein, Along the first direction, the first amorphized region A includes a middle portion located between a side portion and a first crystallized region, one end of the middle portion being connected to one of the side portions, and the other end of the middle portion being connected to the first crystallized region.

8. The solar cell according to claim 7, wherein, The sum of the lengths of the middle portion and the adjacent side portion stacked on the silicon substrate is L≥5μm.

9. The solar cell according to any one of claims 1-8, wherein, Within the first region, along the thickness direction from the side surface furthest from the silicon substrate to the side closest to the silicon substrate, the crystallization rate of the crystallization region of the first doped layer gradually decreases; or Within the first region, the crystallization rate of the crystallization region of the first doped layer is equal along the thickness direction from the side surface away from the silicon substrate to the side surface closer to the silicon substrate.

10. The solar cell according to any one of claims 1-8, wherein, The first doped layer in the amorphous region is an amorphous silicon layer, and the first doped layer in the crystallized region includes nanocrystalline silicon and / or microcrystalline silicon; and / or The crystallinity of the first doped layer in the crystallization region is 0.01-100%; and / or The first doped layer in the crystallized region is distributed in a continuous or discrete manner; and / or The first doped layer in the crystallized region is formed by laser irradiation.

11. The solar cell according to any one of claims 2-4 or 6-8, wherein, It also includes a first passivation layer located between the silicon substrate and the first doped layer; and / or, it also includes a first conductive layer located between the first doped layer and the first electrode; and / or, it also includes a second passivation layer located between the silicon substrate and the second doped layer; and / or, it also includes a second conductive layer located between the second doped layer and the second electrode.

12. A method for preparing a solar cell, wherein, Includes the following steps: A silicon substrate is provided, wherein one side surface of the silicon substrate includes a first region and a second region adjacent to each other along a first direction; A first doped layer is formed in the first region and the second region of the silicon substrate; At least a portion of the first doped layer in the first region is subjected to crystallization treatment, such that at least a portion of the first doped layer in the first region forms a crystallized region; A first electrode is formed in the first region such that the projection of the crystallized region onto the silicon substrate at least partially overlaps with the projection of the first electrode onto the silicon substrate; In the second region, at least a portion of the first doped layer is an amorphous region.

13. The preparation method according to claim 12, wherein, The silicon substrate also includes a third region on one side surface, which is located on the side of the second region opposite to the first region along the first direction; The method for preparing the solar cell further includes the following steps: A second doped layer is formed in a third region and a second region of the silicon substrate; in the second region, the second doped layer is located on the side of the first doped layer closer to the silicon substrate; the conductivity of the first doped layer and the second doped layer are opposite. A second electrode is formed in the third region.

14. The preparation method according to claim 13, wherein, The second doped layer is a polycrystalline silicon doped layer.

15. The preparation method according to claim 13, wherein, The method for preparing the solar cell further includes the following steps: At least a portion of the second doped layer in the third region is subjected to crystallization treatment, such that at least a portion of the second doped layer in the third region forms a crystallized region; The projection of the crystallized region in the third region onto the silicon substrate at least partially overlaps with the projection of the second electrode onto the silicon substrate.

16. The preparation method according to any one of claims 12-15, wherein, After crystallizing at least a portion of the first doped layer in the first region, and before forming the first electrode in the first region, the method further includes forming a first conductive layer in the first region.

17. The preparation method according to any one of claims 12-15, wherein, The first doped layer in the first region is crystallized by irradiating the first doped layer in the first region with a laser.

18. A battery assembly, wherein, The solar cell includes any one of claims 1-11.

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