Passivation layer for LED chip, preparation method of passivation layer and LED chip
By using PECVD to deposit the silicon oxide layer on the LED chip and irradiate ultraviolet light, the problem of poor density of the passivation layer is solved, and the reliability and environmental resistance of the LED chip are significantly improved.
Patent Information
- Application Number
- CN202510075580.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-17
- Publication Date
- 2025-04-29
AI Technical Summary
The passivation layer of existing LED chips has poor density and is prone to corrosion in high temperature and high humidity environments, resulting in the failure of LED chips.
The silicon oxide layer is deposited by PECVD, and the Si-H bond is interrupted by ultraviolet light irradiation to improve the density of the passivation layer.
The density of the passivation layer and the reliability of the LED chip are improved, and the tolerance to high temperature and high humidity environments is enhanced.
Smart Images
Figure CN119907370A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor optoelectronic devices, and in particular to a passivation layer for an LED chip, a preparation method thereof, and an LED chip. Background Art
[0002] LED chips are composed of epitaxial layers and chip layers. The epitaxial layer generally includes a substrate, an N-type semiconductor, a quantum well, and a P-type semiconductor. The chip layer consists of a current blocking layer, a transparent conductive layer, an electrode, and a passivation layer from bottom to top. The passivation layer is generally a SiO2 layer, which is deposited by PECVD. However, during the PECVD growth of the SiO2 layer, a large amount of H will enter the SiO2 layer, forming Si-H bonds. The Si-H bonds not only make the passivation layer less dense, but also are unstable and easily break to form H free radicals, which in turn generate H + In a high temperature and high humidity environment, it will corrode the transparent conductive layer, epitaxial layer, etc., causing the LED chip to fail. Summary of the Invention
[0003] The technical problem to be solved by the present invention is to provide a method for preparing a passivation layer for an LED chip, wherein the passivation layer prepared by the method has high density and can effectively improve the reliability of the LED chip.
[0004] Another technical problem to be solved by the present invention is to provide a passivation layer for an LED chip, which has high density and can improve the reliability of the LED chip.
[0005] Another technical problem to be solved by the present invention is to provide an LED chip with high reliability.
[0006] In order to solve the above technical problems, the present invention provides a method for preparing a passivation layer for an LED chip, which comprises:
[0007] Depositing a silicon oxide layer in PECVD using the first gas and SiH4 as silicon source gases and N2O as oxygen source gas;
[0008] irradiating the silicon oxide layer with ultraviolet light;
[0009] The first gas is any one of N2, Ar, and He, or a mixture of at least two of them.
[0010] As an improvement of the above technical solution, in the silicon source gas, the volume ratio of SiH4 to the first gas is 1:2.5 to 1:5; the volume ratio of the silicon source gas to the oxygen source gas is 1:1.5 to 1:3;
[0011] The first gas is any one of N2 and Ar; or the first gas is a mixed gas of N2 and He; or the first gas is a mixed gas of Ar and He.
[0012] As an improvement of the above technical solution, the first gas is a mixed gas of N2 and He, and the volume ratio of N2 to He is 5:1 to 8:1; or
[0013] The first gas is a mixed gas of Ar and He, and the volume ratio of Ar to He is 5:1 to 8:1.
[0014] As an improvement of the above technical solution, the first gas is a mixed gas of Ar and He, and the volume ratio of Ar to He is 5.5:1 to 6.5:1.
[0015] As an improvement of the above technical solution, in the step of depositing the silicon oxide layer in PECVD using the first gas and SiH4 as silicon source gas and N2O as oxygen source gas, the RF power is 80-100W, the chamber pressure is 80-120Pa, and the temperature is 200-250°C.
[0016] As an improvement to the above technical solution, in the step of irradiating the silicon oxide layer with ultraviolet light, the ultraviolet light irradiation time, the thickness of the passivation layer, the wavelength of the ultraviolet light, and the energy density of the ultraviolet light meet the following relationship:
[0017]
[0018] Where t is the duration of UV light exposure, in seconds; H is the thickness of the passivation layer, in nm; W is the wavelength of UV light, in nm; J is the energy density of UV light, in J / cm 2 .
[0019] As an improvement of the above technical solution, the wavelength of the ultraviolet light is 250-350 nm, and the energy density is 250-800 J / cm 2 .
[0020] As an improvement of the above technical solution, in the step of irradiating the silicon oxide layer with ultraviolet light, the silicon oxide layer is irradiated with ultraviolet light under dry conditions.
[0021] Correspondingly, the present invention also discloses a passivation layer for an LED chip, which is prepared by the above-mentioned method for preparing a passivation layer for an LED chip.
[0022] Correspondingly, the present invention also discloses an LED chip, which includes the above-mentioned passivation layer.
[0023] The implementation of the present invention has the following beneficial effects:
[0024] In a method for preparing a passivation layer for an LED chip in one embodiment of the present invention, a silicon oxide layer is first deposited in PECVD using a specific reaction gas, and then ultraviolet light is used to irradiate the silicon oxide layer, so that the Si-H bonds inside the silicon oxide layer are broken and released, thereby improving the density of the passivation layer and improving the reliability of the LED chip based on the passivation layer. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Figure 1 is a flow chart of a method for preparing a passivation layer for an LED chip in one embodiment of the present invention;
[0026] Figure 2 Schematic diagram of the structure of an LED chip in one embodiment of the present invention. DETAILED DESCRIPTION
[0027] In order to make the purpose, technical solutions and advantages of the present application more clear, the present application is further described in detail below with reference to the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application. In addition, it should be understood that the specific embodiments described herein are merely used to explain the present application and are not intended to limit the present application.
[0028] In the description of this application, it should be understood that the terms "length", "width", "up", "down", "left", "right", "horizontal", "top", "bottom", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on this application.
[0029] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the described features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.
[0030] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections, electrical connections, or mutual communication; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.
[0031] In this application, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Moreover, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.
[0032] The disclosure below provides many different embodiments or examples for realizing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numbers and / or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those skilled in the art will appreciate the application of other processes and / or the use scenarios of other materials.
[0033] The traditional SiO2 passivation layer has a large number of Si-H bonds, resulting in poor density and poor reliability. To solve this problem, see Figure 1 An embodiment of the present invention discloses a method for preparing a passivation layer for an LED chip, which specifically includes the following steps:
[0034] S1: Depositing a silicon oxide layer in PECVD using the first gas and SiH4 as silicon source gases and N2O as oxygen source gas;
[0035] S2: irradiating the silicon oxide layer with ultraviolet light;
[0036] Based on the above preparation method, the Si-H bonds inside the silicon oxide layer can be broken and released by ultraviolet light irradiation, thereby improving the density of the passivation layer and improving the reliability of the LED chip based on the passivation layer.
[0037] Specifically, the first gas is any one of N2, Ar, and He, or a mixture of at least two of them. One of the first gases can act as a diluent gas to prevent the reaction from being too intense, thereby optimizing the uniformity of the silicon oxide layer; the other two can act as a plasma stabilizer to optimize the stress of the silicon oxide layer. In addition, N2 can partially react and enter the silicon oxide layer, thereby improving the passivation performance. Ar can be ionized during the reaction to form Ar plasma, which can effectively break Si-H bonds and reduce the number of Si-H bonds in the silicon oxide layer. Moreover, Ar does not participate in the reaction, which helps to form a high-purity silicon oxide layer. He can generate He plasma during the reaction. Although it does not participate in the reaction, it can bombard the already formed silicon oxide layer, thereby improving the density of the silicon oxide layer, and because He atoms are small, they will not damage the silicon oxide layer. Therefore, based on the above-mentioned first gas, the density of the silicon oxide layer can be improved and the generation of Si-H bonds can be reduced.
[0038] Preferably, in some embodiments, the first gas is any one of N2 and Ar. When based on the above first gas, the deposition rate is high.
[0039] Preferably, in some embodiments, the first gas is a mixture of N2 and He, with a volume ratio of N2 to He ranging from 5:1 to 8:1, illustratively 5.5:1, 6:1, 6.5:1, 7:1, or 7.5:1, but not limited thereto. This first gas can reduce the formation of Si-H bonds, improving the density and reliability of the passivation layer.
[0040] Preferably, in some embodiments, the first gas is a mixture of Ar and He, with a volume ratio of Ar to He ranging from 5:1 to 8:1. Exemplary ratios include, but are not limited to, 5.5:1, 6:1, 6.5:1, 7:1, or 7.5:1. More preferably, the ratio is from 5.5:1 to 6.5:1. This first gas can reduce the formation of Si-H bonds, improving the density and reliability of the passivation layer.
[0041] Specifically, in step S1 , the radio frequency power is 80-100 W, the chamber pressure is 80-120 Pa, the temperature is 200-250° C., and the volume ratio of the silicon source gas to the oxygen source gas is 1:1.5-1:3.
[0042] Specifically, in step S2, the silicon oxide layer is irradiated with ultraviolet light under dry conditions, so that Si-H bonds are broken and H is released in the form of H2, thereby improving the density of the passivation layer.
[0043] Specifically, in step S2, the wavelength of the ultraviolet light used is 250-350 nm, and the energy density is 250-800 J / cm 2 , to better break the Si-H bond, but not limited to this.
[0044] Preferably, in some embodiments, in step S2, the duration of ultraviolet light irradiation, the thickness of the passivation layer, the wavelength of the ultraviolet light, and the energy density of the ultraviolet light satisfy the following relationship:
[0045]
[0046] Where t is the duration of UV light exposure, in seconds; H is the thickness of the passivation layer, in nm; W is the wavelength of UV light, in nm; J is the energy density of UV light, in J / cm 2 .
[0047] Accordingly, see Figure 2 The present invention also discloses an LED chip in an embodiment, comprising a substrate 1, an epitaxial layer 2, a transparent conductive layer 3, a passivation layer 4, a first electrode 5, and a second electrode 6. The epitaxial layer 2 is disposed on the substrate 1 and comprises a first semiconductor layer 21, an active layer 22, and a second semiconductor layer 23 sequentially stacked on the substrate 1; an exposed region 24 exposing the first semiconductor layer 21 is formed on the epitaxial layer 2; the transparent conductive layer 3 is stacked on the second semiconductor layer 23; the first electrode 5 is disposed on the first semiconductor layer 21 within the exposed region 24 and is electrically connected to the first semiconductor layer 21; and the second electrode 6 is disposed on the transparent conductive layer 3 and is electrically connected to the second semiconductor layer 23. The passivation layer 4 covers the entire LED chip and has through-holes formed at the first and second electrodes 5 and 6 for electrical connection.
[0048] Specifically, the substrate 1 may be a sapphire substrate, a silicon substrate, a silicon carbide substrate, a gallium oxide substrate, or a zinc oxide substrate, but is not limited thereto. Preferably, it is a sapphire substrate, and more preferably, it is a patterned sapphire substrate.
[0049] Specifically, different types of epitaxial layers 2 can be selected based on the different emission wavelengths of the LED chip. Specifically, the LED chip of the present invention can be a red, green, yellow, or violet LED chip. Based on the control of the emission wavelength, different types of first semiconductor layers 21, active layers 22, and second semiconductor layers 23 can be selected. For example, in one embodiment of the present invention, when the LED chip is a blue LED chip or a green LED chip, the first semiconductor layer 21 can be an N-type GaN layer, the active layer 22 can be an InGaN-GaN type multi-quantum well layer, and the second semiconductor layer 23 can be a P-type GaN layer. In another embodiment of the present invention, when the LED chip is a violet LED chip, the first semiconductor layer 21 can be an N-type AlGaN layer, the active layer 22 can be an AlGaN-AlGaN type multi-quantum well layer, and the second semiconductor layer 23 can be a P-type AlGaN layer, but the present invention is not limited thereto. Preferably, in this embodiment, the first semiconductor layer 21 is an N-type GaN layer, the active layer 22 is an InGaN-GaN type multi-quantum well layer, and the second semiconductor layer 23 may be a P-type GaN layer.
[0050] Specifically, the transparent conductive layer 3 is an ITO layer, an IZO layer, an AZO layer, an ATO layer or an FTO layer, but is not limited thereto. Preferably, it is an ITO layer. The thickness of the transparent conductive layer 3 is
[0051] Specifically, the first electrode 5 and the second electrode 6 are both metal single-layer or stacked-layer structures commonly found in the art. For example, they can be made of one or more of Cr, Al, Ti, Pt, Ni, Au, Cu, and Ag.
[0052] It should be noted that the above embodiments only describe LED chips with upright structures. The passivation layer of the present invention can also be applied to flip-chip LED chips and vertical LED chips commonly used in the art, but is not limited thereto.
[0053] The present invention will be further described below with specific embodiments:
[0054] Example 1
[0055] This embodiment provides a method for preparing a passivation layer for an LED chip, which includes the following steps:
[0056] (1) Depositing a silicon oxide layer in a PECVD process using a first gas and SiH4 as silicon source gases and N2O as oxygen source gas; wherein the first gas is N2 with a flow rate of 600 sccm, the flow rate of SiH4 is 200 sccm, the flow rate of N2O is 1880 sccm, the RF power is 90 W, the chamber pressure is 90 Pa, and the temperature is 230°C;
[0057] (2) irradiating the silicon oxide layer with ultraviolet light; wherein the ultraviolet light irradiation is carried out under absolutely dry conditions, the ultraviolet light wavelength is 300nm, and the energy density is 300J / cm 2 , the irradiation time is 180s; the thickness of the passivation layer is 60nm.
[0058] Example 2
[0059] This embodiment provides a method for preparing a passivation layer for an LED chip, which includes the following steps:
[0060] (1) Depositing a silicon oxide layer in a PECVD process using a first gas and SiH4 as silicon source gases and N2O as oxygen source gas; wherein the first gas is Ar with a flow rate of 600 sccm, the flow rate of SiH4 is 200 sccm, the flow rate of N2O is 1880 sccm, the RF power is 90 W, the chamber pressure is 90 Pa, and the temperature is 230°C;
[0061] (2) irradiating the silicon oxide layer with ultraviolet light; wherein the ultraviolet light irradiation is carried out under absolutely dry conditions, the ultraviolet light wavelength is 300nm, and the energy density is 300J / cm 2 , the irradiation time is 180s; the thickness of the passivation layer is 60nm.
[0062] Example 3
[0063] This embodiment provides a method for preparing a passivation layer for an LED chip, which includes the following steps:
[0064] (1) Depositing a silicon oxide layer in PECVD using a first gas and SiH4 as silicon source gases and N2O as oxygen source gas; wherein the first gas is a mixture of N2 and He, the N2 flow rate is 600 sccm, the He flow rate is 100 sccm, the SiH4 flow rate is 200 sccm, the N2O flow rate is 1880 sccm, the RF power is 90 W, the chamber pressure is 90 Pa, and the temperature is 230°C;
[0065] (2) irradiating the silicon oxide layer with ultraviolet light; wherein the ultraviolet light irradiation is carried out under absolutely dry conditions, the ultraviolet light wavelength is 300nm, and the energy density is 300J / cm 2 , the irradiation time is 180s; the thickness of the passivation layer is 60nm.
[0066] Example 4
[0067] This embodiment provides a method for preparing a passivation layer for an LED chip, which includes the following steps:
[0068] (1) Depositing a silicon oxide layer in PECVD using a first gas and SiH4 as silicon source gases and N2O as oxygen source gas; wherein the first gas is a mixed gas of Ar and He, with an Ar flow rate of 600 sccm, a He flow rate of 100 sccm, a SiH4 flow rate of 200 sccm, and a N2O flow rate of 1880 sccm, a radio frequency power of 90 W, a chamber pressure of 90 Pa, and a temperature of 230°C;
[0069] (2) irradiating the silicon oxide layer with ultraviolet light; wherein the ultraviolet light irradiation is carried out under absolutely dry conditions, the ultraviolet light wavelength is 300nm, and the energy density is 300J / cm 2 , the irradiation time is 180s; the thickness of the passivation layer is 60nm.
[0070] Example 5
[0071] This embodiment provides a method for preparing a passivation layer for an LED chip, which includes the following steps:
[0072] (1) Depositing a silicon oxide layer in PECVD using a first gas and SiH4 as silicon source gases and N2O as oxygen source gas; wherein the first gas is a mixed gas of Ar and He, with an Ar flow rate of 600 sccm, a He flow rate of 100 sccm, a SiH4 flow rate of 200 sccm, and a N2O flow rate of 1880 sccm, a radio frequency power of 90 W, a chamber pressure of 90 Pa, and a temperature of 230°C;
[0073] (2) irradiating the silicon oxide layer with ultraviolet light; wherein the ultraviolet light irradiation is carried out under absolutely dry conditions, the ultraviolet light wavelength is 250nm, and the energy density is 300J / cm 2 , the irradiation time is 150s; the thickness of the passivation layer is 60nm.
[0074] Comparative Example 1
[0075] This comparative example provides a method for preparing a passivation layer for an LED chip, which comprises the following steps:
[0076] A silicon oxide layer was deposited using a PECVD process using a first gas and SiH₄ as silicon source gases and N₂O as an oxygen source gas. The first gas was N₂ at a flow rate of 600 sccm, the SiH₄ flow rate was 200 sccm, and the N₂O flow rate was 1880 sccm. The RF power was 90 W, the chamber pressure was 90 Pa, and the temperature was 230°C. The resulting passivation layer had a thickness of 60 nm.
[0077] Comparative Example 2
[0078] This comparative example provides a method for preparing a passivation layer for an LED chip, which comprises the following steps:
[0079] A silicon oxide layer was deposited in a PECVD process using a first gas and SiH₄ as silicon source gases and N₂O as oxygen source gas. The first gas was a mixture of Ar and He with an Ar flow rate of 600 sccm, a He flow rate of 100 sccm, a SiH₄ flow rate of 200 sccm, and a N₂O flow rate of 1880 sccm. The RF power was 90 W, the chamber pressure was 90 Pa, and the temperature was 230°C. The resulting passivation layer had a thickness of 60 nm.
[0080] The passivation layers of Examples 1 to 5 and Comparative Examples 1 to 2 were applied to 10mil*24mil upright LED chips. The chips were then lit for 1000 hours at 85°C, 85% RH, and a current of 5mA. The leakage current was tested with a -10V voltage. A leakage current of 1μA or higher was considered a failure, while a leakage current of less than 1μA was considered effective. The statistical failure rates are shown in the following table:
[0081] Failure rate (%) Example 1 5.3 Example 2 3.4 Example 3 4.2 Example 4 2.1 Example 5 1.2 Comparative Example 1 18.5 Comparative Example 2 14.3
[0082] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
[0083] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and intent of the present application, and that the scope of the present application is defined by the claims and their equivalents.
Claims
1. A method for preparing a passivation layer for an LED chip, characterized in that: include: Depositing a silicon oxide layer in PECVD using the first gas and SiH4 as silicon source gas and N2O as oxygen source gas; irradiating the silicon oxide layer with ultraviolet light; The first gas is any one of N2, Ar, and He, or a mixture of at least two of them.
2. The method for preparing a passivation layer for an LED chip according to claim 1, characterized in that: In the silicon source gas, the volume ratio of SiH4 to the first gas is 1:2.5 to 1:5; the volume ratio of the silicon source gas to the oxygen source gas is 1:1.5 to 1:3; The first gas is any one of N2 and Ar; or the first gas is a mixed gas of N2 and He; or the first gas is a mixed gas of Ar and He.
3. The method for preparing a passivation layer for an LED chip according to claim 1, characterized in that: The first gas is a mixed gas of N2 and He, and the volume ratio of N2 to He is 5:1 to 8:1; or The first gas is a mixed gas of Ar and He, and the volume ratio of Ar to He is 5:1 to 8:
1.
4. The method for preparing a passivation layer for an LED chip according to claim 1, characterized in that: The first gas is a mixed gas of Ar and He, and the volume ratio of Ar to He is 5.5:1 to 6.5:
1.
5. The method for preparing a passivation layer for an LED chip according to any one of claims 1 to 4, characterized in that: In the step of depositing the silicon oxide layer in PECVD using the first gas and SiH4 as silicon source gases and N2O as oxygen source gas, the RF power is 80-100W, the chamber pressure is 80-120Pa, and the temperature is 200-250°C.
6. The method for preparing a passivation layer for an LED chip according to claim 1, characterized in that: In the step of irradiating the silicon oxide layer with ultraviolet light, the duration of ultraviolet light irradiation, the thickness of the passivation layer, the wavelength of the ultraviolet light, and the energy density of the ultraviolet light meet the following relationship: Where t is the duration of UV light exposure, in seconds; H is the thickness of the passivation layer, in nm; W is the wavelength of UV light, in nm; J is the energy density of UV light, in J / cm 2 .
7. The method for preparing a passivation layer for an LED chip according to claim 6, characterized in that: The wavelength of the ultraviolet light is 250-350nm, and the energy density is 250-800J / cm 2 .
8. The method for preparing a passivation layer for an LED chip according to claim 1, characterized in that: In the step of irradiating the silicon oxide layer with ultraviolet light, the silicon oxide layer is irradiated with ultraviolet light under dry conditions.
9. A passivation layer for an LED chip, characterized in that: The passivation layer is prepared by the method for preparing a passivation layer for an LED chip as claimed in any one of claims 1 to 8.
10. An LED chip, characterized in that: Comprising the passivation layer as claimed in claim 9.