Deep ultraviolet LED chip and preparation method thereof

Abstract

The invention belongs to the technical field of deep ultraviolet LED chips, and particularly relates to a deep ultraviolet LED chip and a preparation method thereof, and the deep ultraviolet LED chip comprises a sapphire substrate, an epitaxial layer, a deep etching region, an n etching region, an n first electrode, a p first electrode, an n second electrode, a p second electrode, a first passivation layer, a connection / reflection layer, a second passivation layer, a p thick gold layer, an n thick gold layer, and a heat conduction thick gold layer. An epitaxial layer grows on the surface of the sapphire substrate, deep etching areas are etched at the center and two ends of the epitaxial layer, two n etching areas are etched on the epitaxial layer, an n first electrode and an n second electrode respectively grow on the surfaces of the two n etching areas, and a p first electrode and a p second electrode respectively grow on the surface of the epitaxial layer. Through the arrangement of the connection / reflection layer structure, large-area light beam reflection, current expansion of the p electrode and the n electrode and the series connection effect of the p electrode and the n electrode of the adjacent units are achieved at the same time, and the light extraction efficiency and the device reliability are improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of deep ultraviolet LED chips, and in particular relates to a deep ultraviolet LED chip and a preparation method thereof. Background Art

[0002] In recent years, the market application of deep ultraviolet LEDs has shown a growth trend, and deep ultraviolet LED devices have appeared in the fields of home appliances, maternal and child products, industrial water treatment, medical treatment, curing, etc. With the diversification of the application market, the downstream application end has also had diversified solutions in product design and development, which has brought higher requirements on the performance and cost of upstream chips and packaging devices. For example, the addition of deep ultraviolet sterilization function to the design of terminal products requires a good match in circuit design, space, and cost in order to be more conveniently applied to the product. Some will use integrated lamp beads to achieve high-power products, but the increase in the number of integrations will also increase the space occupied, thereby limiting the use of the product. Secondly, the use of integrated solutions will also have problems with product stability.

[0003] The invention patent with publication number CN104916771A provides a substrate-changing upright GaN-based light-emitting diode and its preparation method. Although the use of a high thermal conductivity substrate can improve the heat dissipation performance, the combination technology with the GaN epitaxial layer still faces challenges. There is a lattice mismatch and thermal expansion coefficient difference between the high thermal conductivity substrate and the GaN epitaxial layer, which may lead to the generation of interface stress and cracks, thereby reducing the thermal conductivity of the device.

[0004] The invention patent application with publication number CN108054249A provides a method for preparing blue and ultraviolet LED chips. Although the sapphire substrate has advantages such as good chemical stability and high mechanical strength, its thermal conductivity is poor, which will cause the LED chip to generate high thermal resistance during operation, thereby affecting its heat dissipation effect. The low thermal conductivity of the sapphire substrate will increase the internal temperature of the chip, thereby affecting the light output efficiency and device life. Summary of the invention

[0005] In view of the technical problems that the above-mentioned existing deep ultraviolet LED chip products are limited in application in terminal solutions and have high costs, the present invention provides a deep ultraviolet LED chip and a preparation method thereof, which realizes the integration effect from the chip structure design, and prepares a multi-area reflective layer to improve the luminous efficiency of the entire device; designs an array structure on the welding layer to improve the welding stability; and sets a thermal conductive layer to improve the reliability of the device.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is: A deep ultraviolet LED chip comprises a sapphire substrate, an epitaxial layer, a deep etching region, an n etching region, an n first electrode, a p first electrode, an n second electrode, a p second electrode, a first passivation layer, a connection / reflection layer, a second passivation layer, a p thick gold layer, an n thick gold layer, and a heat-conducting thick gold layer. An epitaxial layer is grown on the surface of the sapphire substrate, and the center and both ends of the epitaxial layer are etched with deep etching regions. Two n etching regions are etched on the epitaxial layer, and the surfaces of the two n etching regions are respectively grown with an n first electrode and an n second electrode. A p first electrode and a p second electrode are respectively grown on the surface of the epitaxial layer, a first passivation layer is prepared on the surface of the epitaxial layer, a connection / reflection layer is prepared on the surfaces of the first passivation layer, the n first electrode and the p second electrode, the n second electrode is connected to the p first electrode through the connection / reflection layer, a second passivation layer is prepared on the surface of the connection / reflection layer, the n first electrode is connected to the n thick gold layer through the connection / reflection layer, the p second electrode is connected to the p thick gold layer through the connection / reflection layer, and the thermally conductive thick gold layer is prepared on the second passivation layer.

[0007] The epitaxial layer includes an AlN buffer layer, an n-type AlGaN layer, a quantum light-emitting layer, a p-type AlGaN layer, and a P-GaN layer. The AlN buffer layer is grown on a sapphire substrate, the n-type AlGaN layer is grown on the AlN buffer layer, the quantum light-emitting layer is grown on the n-type AlGaN layer, the p-type AlGaN layer is grown on the quantum light-emitting layer, and the P-GaN layer is grown on the p-type AlGaN layer.

[0008] The deep etching region is etched from the P-GaN layer to the sapphire substrate, and the n-etching region is etched from the P-GaN layer to the n-type AlGaN layer.

[0009] A p welding layer is prepared on the p-thick gold layer, an n welding layer is prepared on the n-thick gold layer, and a heat-conducting welding layer is prepared on the heat-conducting thick gold layer.

[0010] The p welding layer, n welding layer and thermal conductive welding layer all adopt Au / Sn alloy or Au / Sn superposition structure with a thickness of 2μm-5μm; the p welding layer, n welding layer and thermal conductive welding layer all have a whole array of graphic structures; the gaps between the p welding layer, n welding layer and thermal conductive welding layer form an exhaust channel.

[0011] A method for preparing a deep ultraviolet LED chip comprises the following steps: S1. growing an epitaxial layer on a sapphire substrate, wherein the epitaxial layer includes, from bottom to top, an AlN buffer layer, an n-type AlGaN layer, a quantum light emitting layer, a p-type AlGaN layer, and a P-GaN layer; S2, using photolithography and dry etching processes to prepare a deep etching area, and etching to the sapphire substrate; S3, using photolithography and dry etching processes to prepare an n-etching area, and etching to the n-type AlGaN layer; S4, preparing an n first electrode, a p first electrode, an n second electrode and a p second electrode respectively through photolithography, metal evaporation, metal stripping and rapid annealing processes, wherein the n first electrode and the n second electrode are respectively disposed on the n-type AlGaN layer and form an ohmic contact, and the p first electrode and the p second electrode are respectively disposed on the P-GaN layer and form an ohmic contact; S5, preparing a first passivation layer by plasma enhanced chemical vapor deposition process, and exposing the regions of the n first electrode and the p first electrode by photolithography and dry / wet process; S6, preparing a connection / reflection layer by using photolithography, metal evaporation, and metal stripping processes, wherein the connection / reflection layer is prepared on the n first electrode and the p second electrode respectively, and the connection / reflection layer is prepared between the n second electrode and the p first electrode; S7, using a plasma enhanced chemical vapor deposition process to prepare a second passivation layer, and using photolithography and a dry / wet process to expose the connection / reflection layer in the area above the n first electrode and the p first electrode, and the other areas are covered with the second passivation layer; S8, using photolithography, metal evaporation, and metal stripping processes to prepare a thick gold layer, the thick gold layer including a p-thick gold layer, an n-thick gold layer, and a thermally conductive thick gold layer, the n-thick gold layer is prepared on the connection / reflection layer on the n-first electrode, the p-thick gold layer is prepared on the connection / reflection layer on the p-second electrode, and the thermally conductive thick gold layer is prepared on the second passivation layer; S9, using photolithography, metal evaporation, and metal stripping to simultaneously prepare a p welding layer, an n welding layer, and a thermal conductive welding layer, wherein the p welding layer is prepared on the p thick gold layer, the n thick gold layer is prepared on the n welding layer, and the thermal conductive welding layer is prepared on the thermal conductive thick gold layer, and the gaps between the p welding layer, the n welding layer, and the thermal conductive welding layer form an exhaust channel; S10: Use the back-end substrate thinning and cutting process to form independent unit chips and complete the preparation of deep ultraviolet LED chips.

[0012] The preparation process parameters of the n first electrode and the p first electrode in S4 are as follows: the n first electrode adopts Ti / Al / Ti / Au system, the thickness is 15 / 150 / 15 / 100nm, the rapid annealing temperature is 800℃-900℃, N 2 atmosphere, the time is 60s-180s; the p first electrode adopts Ni / Au system, the thickness is 20 / 20nm, the rapid annealing temperature is 500℃-700℃, N 2 Atmosphere, time is 60s-180s.

[0013] The first passivation layer in S5 and the second passivation layer in S7 are both made of SiO 2 or Si3 N 4 Materials, thickness is 1μm-3μm.

[0014] The connection / reflection layer in S6 adopts Cr / Al, Rh or Pt / Ti / Au / Pt / Ti metal system with a total thickness of 0.8μm-2μm; the p-thick gold layer, n-thick gold layer and thermal conductive thick gold layer in S8 all adopt Ti / Pt / Au stacking structure with a total thickness of 0.5μm-2μm.

[0015] The p welding layer, n welding layer and thermal conductive welding layer in S9 are all made of Au / Sn alloy or Au / Sn superposition structure, with a total thickness of 2μm-5μm; the p welding layer, n welding layer and thermal conductive welding layer are all full-row graphic structures; the gaps between the p welding layer, n welding layer and thermal conductive welding layer form an exhaust channel.

[0016] Compared with the prior art, the present invention has the following beneficial effects: The connection / reflection layer structure of the present invention realizes large-area light beam reflection, current expansion of p-electrode and n-electrode, and the series connection of adjacent unit p-electrode and n-electrode at the same time, thereby improving light extraction efficiency and device reliability. In addition, the thermal conductive layer of the present invention is composed of a thermal conductive thick gold layer and a thermal conductive welding layer, which effectively increases the thermal conductive area of ​​the device and improves product reliability. The welding layer of the present invention adopts a full-array graphic design, which effectively solves the stress influence of traditional processes in welding and improves product reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the implementation methods of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for the implementation methods or the description of the prior art. Obviously, the drawings in the following description are only exemplary, and for ordinary technicians in this field, other implementation drawings can be derived from the provided drawings without creative work.

[0018] The structures, proportions, sizes, etc. illustrated in this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with the technology. They are not used to limit the conditions under which the present invention can be implemented, and therefore have no substantial technical significance. Any structural modification, change in proportion or adjustment of size shall still fall within the scope of the technical contents disclosed in the present invention without affecting the effects and purposes that can be achieved by the present invention.

[0019] Figure 1 It is a schematic diagram of the structure of the epitaxial layer of the present invention; Figure 2 It is a schematic diagram of the structure of the deep etching area of ​​the present invention; Figure 3It is a schematic structural diagram of the n etching area of ​​the present invention; Figure 4 is a schematic structural diagram of an n first electrode and a p first electrode of the present invention; Figure 5 is a schematic structural diagram of the first passivation layer of the present invention; Figure 6 It is a schematic diagram of the structure of the connection / reflection layer and the second passivation layer of the present invention; Figure 7 It is a structural schematic diagram of the welding layer of the present invention; Figure 8 It is a top view schematic diagram of a traditional welding layer structure and a welding layer structure of the present invention.

[0020] Wherein: 101 is a sapphire substrate, 102 is an AlN buffer layer, 103 is an n-type AlGaN layer, 104 is a quantum light emitting layer, 105 is a p-type AlGaN layer, 106 is a P-GaN layer, 201 is a deep etching region, 301 is an n etching region, 401 is an n first electrode, 402 is a p first electrode, 403 is an n second electrode, 404 is a p second electrode, 501 is a first passivation layer, 601 is a connection / reflection layer, 602 is a second passivation layer, 701 is a p thick gold layer, 702 is an n thick gold layer, 703 is a thermal conductive thick gold layer, 704 is a p welding layer, 705 is an n welding layer, 706 is a thermal conductive welding layer, and 801 is an exhaust channel. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. These descriptions are only to further illustrate the features and advantages of the present invention, rather than to limit the claims of the present invention. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0022] The specific implementation of the present invention is further described in detail below in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0023] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0024] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0025] A deep ultraviolet LED chip, such as Figure 2-7 As shown, it includes a sapphire substrate 101, an epitaxial layer, a deep etching region 201, an n etching region 301, an n first electrode 401, a p first electrode 402, an n second electrode 403, a p second electrode 404, a first passivation layer 501, a connection / reflection layer 601, a second passivation layer 602, a p thick gold layer 701, an n thick gold layer 702, and a thermally conductive thick gold layer 703. Figure 1As shown, the epitaxial layer includes an AlN buffer layer 102, an n-type AlGaN layer 103, a quantum light emitting layer 104, a p-type AlGaN layer 105, and a P-GaN layer 106. The AlN buffer layer 102 is grown on a sapphire substrate 101, the n-type AlGaN layer 103 is grown on the AlN buffer layer 102, the quantum light emitting layer 104 is grown on the n-type AlGaN layer 103, the p-type AlGaN layer 105 is grown on the quantum light emitting layer 104, and the P-GaN layer 106 is grown on the p-type AlGaN layer 105. The deep etched region 201 is etched from the P-GaN layer 106 to the sapphire substrate 101, and the n-etched region 301 is etched from the P-GaN layer 106 to the n-type AlGaN layer 103. There are two n-etched regions 301, and n-first electrodes 401 and n-second electrodes 403 are grown on the surfaces of the two n-etched regions 301, respectively. p-first electrodes 402 and p-second electrodes 404 are grown on the surfaces of the P-GaN layer 106, respectively. A first passivation layer 501 is prepared on the surface of the epitaxial layer, and a connection / reflection layer 601 is prepared on the surfaces of the first passivation layer 501, the n-first electrode 401, and the p-second electrode 404. The n-second electrode 403 is connected to the p-first electrode 402 through the connection / reflection layer 601. The second passivation layer 602 is prepared on the surface of the connection / reflection layer 601, the n-first electrode 401 is connected to the n-thick gold layer 702 through the connection / reflection layer 601, the p-second electrode 404 is connected to the p-thick gold layer 701 through the connection / reflection layer 601, and the thermally conductive thick gold layer 703 is prepared on the second passivation layer 602. A p soldering layer 704 is prepared on the p thick gold layer 701, an n soldering layer 705 is prepared on the n thick gold layer 702, and a heat conductive soldering layer 706 is prepared on the heat conductive thick gold layer 703. The p soldering layer 704, the n soldering layer 705 and the heat conductive soldering layer 706 are all full array graphic structures, and the full array graphic structure adopts a rectangular or circular array; the gaps between the p soldering layer 704, the n soldering layer 705 and the heat conductive soldering layer 706 form an exhaust channel 801.

[0026] The connection / reflection layer 601 has an overall thickness of >1μm. The bottom layer is a reflective metal layer, which covers multiple areas. The functions of this layer include: 1. Thickening the p first electrode 402 and the n first electrode 401 to improve the current expansion capacity of the p second electrode 404 and the n first electrode 401, reduce current crowding and unevenness, and thus improve the device life and reliability; 2. Connecting the adjacent p first electrode 402 and n second electrode 403 in series; 3. The light beam reflection effect, the reflection effect is mainly reflected in the part not blocked by the electrode and the side wall steps, reducing the loss of light, and effectively reflecting this part of the light source to the light output surface, thereby improving the light extraction efficiency.

[0027] The area not blocked by the electrodes is the area not covered by the p first electrode 402 and the n second electrode 403. After the light source is emitted from the quantum light emitting layer 104, a part of the photons will pass through the p-type AlGaN layer 105, the p-GaN layer 106 area not blocked by the p first electrode 402 and the first passivation layer 501 to propagate to the connection / reflection layer 601, and then be reflected by the connection / reflection layer 601 and then emitted through the area not blocked by the electrodes. In addition, a part of the light source cannot be emitted due to the total interface reflection factor inside the sapphire substrate 101 and the epitaxial material. A part of the photons of this part of the light source can also be reflected and emitted through the connection / reflection layer 601 through the same principle as above; The sidewall step area is the epitaxial layer sidewall that will be exposed after the etching process in the chip process step, including the sidewalls of the AlN buffer layer 102, the n-type AlGaN layer 103, the quantum light emitting layer 104, the p-type AlGaN layer 105, and the P-GaN layer 106. Usually, after etching in the chip preparation process, the sidewall will have a certain inclination angle, and the sidewall will be protected by the first passivation layer 501. A part of the light source will be emitted through the sidewall, propagated through the first passivation layer 501 to the connection / reflection layer 601, and then reflected and emitted.

[0028] The welding layer adopts an array structure design, the electrodes can be rectangular arrays or circular arrays, etc., the pattern spacing is about 0.5μm-2μm, forming an exhaust channel 801, effectively improving the stress effect of the welding process and improving the reliability of the device. Figure 8 As shown, the traditional process is a whole-surface welding layer. During the high-temperature reflow soldering process, the metal layer will melt and combine with the substrate electrode. This process will be accompanied by the release of some volatiles. If the discharge is not thorough, welding voids are likely to occur, and current congestion will occur when the power is turned on, affecting the life of the device. In addition, the release of volatiles during the welding process will produce airflow stress, coupled with the volume shrinkage stress that occurs during the cooling and solidification process, which can easily lead to chip dislocation and the inability to guarantee the welding area, thereby resulting in insufficient welding force of the device and the risk of the device falling off. In the present invention, the p welding layer 704, the n welding layer 705, and the thermal conductive welding layer 706 adopt an array pattern structure, and an exhaust channel 801 is set between adjacent array patterns. During the welding process, volatiles can be fully discharged, effectively improving the formation of void defects and the influence of airflow stress. Furthermore, as the metal layer melts, the array gap will also reduce the volume shrinkage stress caused during the cooling and solidification process, effectively avoiding the problem of device welding displacement.

[0029] The heat-conducting welding layer 706 is arranged in the non-functional area, and is welded to the packaging substrate like the welding layer during packaging, connecting the chip and the substrate, thereby increasing the heat-conducting area and improving the reliability of the device. Usually, the flip-chip structure chip is flipped mainly by the p welding layer 704 and the n welding layer 705 to export the heat generated by the device, but the p welding layer 704 and the n welding layer 705 are in a hollow state and cannot fully export the heat. The heat generated by the LED device usually affects the life of the device. The heat-conducting welding layer 706 prepared by the present invention can effectively increase the heat-conducting area and can export more heat than the conventional structure, thereby improving the life and reliability of the device.

[0030] A method for preparing a deep ultraviolet LED chip comprises the following steps: Step 1: Figure 1 As shown, an epitaxial layer is grown on a sapphire substrate 101 , and the epitaxial layer includes an AlN buffer layer 102 , an n-type AlGaN layer 103 , a quantum light emitting layer 104 , a p-type AlGaN layer 105 , and a P-GaN layer 106 from bottom to top.

[0031] Step 2: Figure 2 As shown, a photolithography and dry etching process is used to prepare a deep etching area 201, which is etched to the sapphire substrate 101.

[0032] Step 3: Figure 3 As shown, the n-etching region 301 is prepared by photolithography and dry etching processes, and the etching is performed to the n-type AlGaN layer 103 .

[0033] Step 4: Figure 4 As shown, an n first electrode 401, a p first electrode 402, an n second electrode 403 and a p second electrode 404 are prepared respectively by photolithography, metal evaporation, metal stripping and rapid annealing processes. The n first electrode 401 and the n second electrode 403 are respectively arranged on the n-type AlGaN layer 103 to form an ohmic contact. The p first electrode 402 and the p second electrode 404 are respectively arranged on the P-GaN layer 106 to form an ohmic contact.

[0034] The first electrode 401 is made of Ti / Al / Ti / Au system with a thickness of 15 / 150 / 15 / 100 nm and a rapid annealing temperature of 800°C-900°C. 2 Atmosphere, time is 60s-180s.

[0035] The first electrode 402 is made of Ni / Au system with a thickness of 20 / 20nm and a rapid annealing temperature of 500℃-700℃. 2 Atmosphere, time is 60s-180s.

[0036] Step 5: Figure 5As shown, a plasma enhanced chemical vapor deposition process is used to prepare the first passivation layer 501 , and photolithography and dry / wet processes are used to expose the regions of the n first electrode 401 and the p first electrode 402 .

[0037] Step 6: Figure 6 As shown, the connection / reflection layer 601 is prepared by photolithography, metal evaporation, and metal stripping processes, and the connection / reflection layer 601 is prepared on the n first electrode 401 and the p second electrode 404, respectively, and the connection / reflection layer 601 is prepared between the n second electrode 403 and the p first electrode 402. The connection / reflection layer 601 adopts Cr / Al, Rh or Pt / Ti / Au / Pt / Ti metal system, and the total thickness is 0.8μm-2μm.

[0038] Step 7: Use plasma enhanced chemical vapor deposition to prepare the second passivation layer 602, and use photolithography, dry / wet process to expose the connection / reflection layer 601 above the n first electrode 401 and the p first electrode 402, and cover the other areas with the second passivation layer 602. The first passivation layer 501 and the second passivation layer 602 are both made of SiO 2 or Si 3 N 4 Materials, thickness is 1μm-3μm.

[0039] Step 8: Figure 7 As shown, a thick gold layer is prepared by photolithography, metal evaporation, and metal stripping processes, and the thick gold layer includes a p-thick gold layer 701, an n-thick gold layer 702, and a thermally conductive thick gold layer 703. The n-thick gold layer 702 is prepared on the connection / reflection layer 601 on the n-first electrode 401, the p-thick gold layer 701 is prepared on the connection / reflection layer 601 on the p-second electrode 404, and the thermally conductive thick gold layer 703 is prepared on the second passivation layer 602. The p-thick gold layer 701, the n-thick gold layer 702, and the thermally conductive thick gold layer 703 all adopt a Ti / Pt / Au stacking structure, and the total thickness is 0.5μm-2μm.

[0040] Step 9: Photolithography, metal evaporation, and metal stripping are used to simultaneously prepare p welding layer 704, n welding layer 705, and thermal welding layer 706. The p welding layer 704 is prepared on the p thick gold layer 701, the n thick gold layer 702 is prepared on the n welding layer 705, and the thermal welding layer 706 is prepared on the thermal thick gold layer 703. The gaps between the p welding layer 704, the n welding layer 705, and the thermal welding layer 706 form an exhaust channel 801. The p welding layer 704, the n welding layer 705, and the thermal welding layer 706 all adopt Au / Sn alloy or Au / Sn superposition structure, with a total thickness of 2μm-5μm. The p welding layer 704, the n welding layer 705, and the thermal welding layer 706 are all full-array graphic structures, and the full-array graphic structure adopts a rectangular or circular array.

[0041] Step 10: Use the back-end substrate thinning and cutting process to form independent unit chips to complete the preparation of deep ultraviolet LED chips.

[0042] Only the preferred embodiments of the present invention are described in detail above, but the present invention is not limited to the above embodiments. Various changes can be made within the knowledge scope of ordinary technicians in this field without departing from the purpose of the present invention, and various changes should be included in the protection scope of the present invention.

Claims

1. A deep ultraviolet LED chip, characterized in that: The invention comprises a sapphire substrate (101), an epitaxial layer, a deep etching region (201), an n etching region (301), an n first electrode (401), a p first electrode (402), an n second electrode (403), a p second electrode (404), a first passivation layer (501), a connection / reflection layer (601), a second passivation layer (602), a p thick gold layer (701), an n thick gold layer (702), and a thermally conductive thick gold layer (703). The epitaxial layer is grown on the surface of the sapphire substrate (101), the center and two ends of the epitaxial layer are etched with deep etching regions (201), the epitaxial layer is etched with two n etching regions (301), the surfaces of the two n etching regions (301) are respectively grown with an n first electrode (401) and an n second electrode (403), and the surface of the epitaxial layer is respectively grown with A p first electrode (402) and a p second electrode (404) are formed, a first passivation layer (501) is prepared on the surface of the epitaxial layer, a connection / reflection layer (601) is prepared on the surfaces of the first passivation layer (501), the n first electrode (401) and the p second electrode (404), the n second electrode (403) is connected to the p first electrode (402) via the connection / reflection layer (601), a second passivation layer (602) is prepared on the surface of the connection / reflection layer (601), the n first electrode (401) is connected to an n thick gold layer (702) via the connection / reflection layer (601), the p second electrode (404) is connected to a p thick gold layer (701) via the connection / reflection layer (601), and the thermally conductive thick gold layer (703) is prepared on the second passivation layer (602).

2. A deep ultraviolet LED chip according to claim 1, characterized in that: The epitaxial layer comprises an AlN buffer layer (102), an n-type AlGaN layer (103), a quantum light-emitting layer (104), a p-type AlGaN layer (105), and a P-GaN layer (106); the AlN buffer layer (102) is grown on a sapphire substrate (101); the n-type AlGaN layer (103) is grown on the AlN buffer layer (102); the quantum light-emitting layer (104) is grown on the n-type AlGaN layer (103); the p-type AlGaN layer (105) is grown on the quantum light-emitting layer (104); and the P-GaN layer (106) is grown on the p-type AlGaN layer (105).

3. A deep ultraviolet LED chip according to claim 2, characterized in that: The deep etching region (201) is etched from the P-GaN layer (106) to the sapphire substrate (101), and the n-etching region (301) is etched from the P-GaN layer (106) to the n-type AlGaN layer (103).

4. The deep ultraviolet LED chip according to claim 1, characterized in that: A p welding layer (704) is prepared on the p thick gold layer (701), an n welding layer (705) is prepared on the n thick gold layer (702), and a heat conductive welding layer (706) is prepared on the heat conductive thick gold layer (703).

5. A deep ultraviolet LED chip according to claim 4, characterized in that: The p welding layer (704), n welding layer (705) and thermally conductive welding layer (706) all adopt Au / Sn alloy or Au / Sn superposition structure, and have a thickness of 2μm-5μm; the p welding layer (704), n welding layer (705) and thermally conductive welding layer (706) all have a whole array of graphic structures; and the gaps between the p welding layer (704), n welding layer (705) and thermally conductive welding layer (706) form an exhaust channel (801).

6. A method for preparing a deep ultraviolet LED chip according to any one of claims 1 to 5, characterized in that: The following steps are involved: S1. growing an epitaxial layer on a sapphire substrate (101), wherein the epitaxial layer comprises, from bottom to top, an AlN buffer layer (102), an n-type AlGaN layer (103), a quantum light-emitting layer (104), a p-type AlGaN layer (105), and a P-GaN layer (106); S2, using photolithography and dry etching processes to prepare a deep etching area (201), and etching to the sapphire substrate (101); S3, using photolithography and dry etching processes to prepare an n-etching region (301), and etching to the n-type AlGaN layer (103); S4. Through photolithography, metal evaporation, metal stripping, and rapid annealing processes, an n first electrode (401), a p first electrode (402), an n second electrode (403), and a p second electrode (404) are respectively prepared. The n first electrode (401) and the n second electrode (403) are respectively arranged on the n-type AlGaN layer (103) to form an ohmic contact. The p first electrode (402) and the p second electrode (404) are respectively arranged on the P-GaN layer (106) to form an ohmic contact. S5, using a plasma enhanced chemical vapor deposition process to prepare a first passivation layer (501), and exposing regions of the n first electrode (401) and the p first electrode (402) through photolithography and dry / wet processes; S6, preparing a connection / reflection layer (601) by photolithography, metal evaporation, and metal stripping processes, wherein the connection / reflection layer (601) is prepared on the n first electrode (401) and the p second electrode (404), respectively, and the connection / reflection layer (601) is prepared between the n second electrode (403) and the p first electrode (402); S7, using a plasma enhanced chemical vapor deposition process to prepare a second passivation layer (602), and using photolithography and dry / wet processes to expose the connection / reflection layer (601) in the area above the n first electrode (401) and the p first electrode (402), while covering the other areas with the second passivation layer (602); S8. Using photolithography, metal evaporation, and metal stripping processes, a thick gold layer is prepared. The thick gold layer includes a p-thick gold layer (701), an n-thick gold layer (702), and a thermally conductive thick gold layer (703). The n-thick gold layer (702) is prepared on the connection / reflection layer (601) on the n-first electrode (401), the p-thick gold layer (701) is prepared on the connection / reflection layer (601) on the p-second electrode (404), and the thermally conductive thick gold layer (703) is prepared on the second passivation layer (602); S9, using photolithography, metal evaporation, and metal stripping to simultaneously prepare a p welding layer (704), an n welding layer (705), and a thermally conductive welding layer (706), wherein the p welding layer (704) is prepared on the p thick gold layer (701), the n thick gold layer (702) is prepared on the n welding layer (705), and the thermally conductive welding layer (706) is prepared on the thermally conductive thick gold layer (703), and the gaps between the p welding layer (704), the n welding layer (705), and the thermally conductive welding layer (706) form an exhaust channel (801); S10: Use the back-end substrate thinning and cutting process to form independent unit chips and complete the preparation of deep ultraviolet LED chips.

7. The method for preparing a deep ultraviolet LED chip according to claim 6, characterized in that: The preparation process parameters of the n first electrode (401) and the p first electrode (402) in S4 are as follows: the n first electrode (401) adopts the Ti / Al / Ti / Au system, the thickness is 15 / 150 / 15 / 100 nm, the rapid annealing temperature is 800°C-900°C, the N2 atmosphere is used, and the time is 60s-180s; the p first electrode (402) adopts the Ni / Au system, the thickness is 20 / 20 nm, the rapid annealing temperature is 500°C-700°C, the N2 atmosphere is used, and the time is 60s-180s.

8. The method for preparing a deep ultraviolet LED chip according to claim 6, characterized in that: The first passivation layer (501) in S5 and the second passivation layer (602) in S7 are both made of SiO2 or Si3N4 material, and have a thickness of 1 μm-3 μm.

9. The method for preparing a deep ultraviolet LED chip according to claim 6, characterized in that: The connection / reflection layer (601) in S6 adopts a Cr / Al, Rh or Pt / Ti / Au / Pt / Ti metal system, with a total thickness of 0.8 μm-2 μm; the p-thick gold layer (701), the n-thick gold layer (702) and the thermal conductive thick gold layer (703) in S8 all adopt a Ti / Pt / Au stacking structure, with a total thickness of 0.5 μm-2 μm.

10. The method for preparing a deep ultraviolet LED chip according to claim 6, characterized in that: The p welding layer (704), n welding layer (705) and thermal conductive welding layer (706) in the S9 all adopt Au / Sn alloy or Au / Sn superposition structure, with a total thickness of 2μm-5μm; the p welding layer (704), n welding layer (705) and thermal conductive welding layer (706) are all in a row of graphic structures; and the gaps between the p welding layer (704), n welding layer (705) and thermal conductive welding layer (706) form an exhaust channel (801).

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