Display panel and display device

Abstract

The invention relates to a display panel and a display device. The display panel includes a substrate; the array layer is arranged on one side of the substrate and comprises a plurality of driving transistors; the first electrodes are arranged on the side, away from the substrate, of the array layer, each first capacitor comprises a first polar plate and a second polar plate which are oppositely arranged, the first polar plates are arranged on one side of the substrate, and the first polar plates are connected with the control ends of the corresponding driving transistors; the pixel limiting layer comprises a first pixel limiting part and a second pixel limiting part, the first pixel limiting part is arranged on the side, away from the substrate, of the corresponding first pole plate, the second pole plate is arranged on the side, away from the first pole plate, of the first pixel limiting part, and the second pixel limiting part covers the part of the corresponding first electrode; the dielectric constant of the second pixel limiting part is smaller than that of the first pixel limiting part. Therefore, according to the display panel and the display device provided by the invention, the display effect of the display panel can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) display technology is regarded as the most promising new flat panel display technology of the next generation. Compared with liquid crystal display technology, OLED display technology has the advantages of low energy consumption, low cost, self-luminescence, wide viewing angle and fast response speed. However, the current OLED display panel has the problem of poor display effect. Summary of the invention

[0003] Based on this, it is necessary to provide a display panel and a display device that can improve the display effect.

[0004] In a first aspect, an embodiment of the present application provides a display panel, which includes: a substrate; an array layer, which is arranged on one side of the substrate and includes a plurality of driving transistors; a plurality of first electrodes, which are arranged on a side of the array layer away from the substrate, and the first electrodes are connected to the first ends of the corresponding driving transistors; a plurality of first capacitors, the first capacitors including a first electrode plate and a second electrode plate which are arranged opposite to each other, the first electrode plate is arranged on one side of the substrate, and the first electrode plate is connected to the control end of the corresponding driving transistor; a pixel defining layer, which includes a first pixel defining portion and a second pixel defining portion, the first pixel defining portion is arranged on a side of the corresponding first electrode plate away from the substrate, the orthographic projection of the first pixel defining portion on the substrate overlaps with the orthographic projection of the corresponding first electrode plate on the substrate, the second electrode plate is arranged on a side of the first pixel defining portion away from the first electrode plate, and the second pixel defining portion covers a portion of the corresponding first electrode; wherein the dielectric constant of the second pixel defining portion is smaller than the dielectric constant of the first pixel defining portion.

[0005] In the display panel provided by the embodiment of the present application, the dielectric constant of the second pixel defining portion is smaller than the dielectric constant of the first pixel defining portion, that is, the dielectric constant of the first pixel defining portion is set to be larger, and the dielectric constant of the second pixel defining portion is set to be smaller. Since the dielectric constant of the first pixel defining portion is larger, using the first pixel defining portion as the capacitor medium of the first capacitor is conducive to increasing the capacitance value of the first capacitor, thereby improving the stability of the control terminal voltage of the driving transistor, so as to improve the display effect of the display panel.

[0006] In one embodiment, the pixel defining layer defines a plurality of pixel openings, and the display panel further comprises:

[0007] A plurality of light-emitting units, wherein the light-emitting units are arranged in corresponding pixel openings and are located on a side of the corresponding first electrode away from the array layer;

[0008] A plurality of second electrodes, wherein the second electrodes are arranged on a side of the corresponding light emitting unit away from the array layer;

[0009] Wherein, the second electrode plate is electrically connected to the second electrode;

[0010] Preferably, the second plate and the second electrode are configured with a first power supply voltage;

[0011] Preferably, the display panel further includes:

[0012] A partition structure is arranged on a side of the pixel defining layer away from the substrate, the partition structure defines a plurality of partition openings, and the partition openings are connected to corresponding pixel openings;

[0013] Wherein, at least part of the partition structure is reused as the second electrode plate;

[0014] Preferably, the second electrode overlaps the partition structure;

[0015] Preferably, the isolation structure is configured with a first power supply voltage.

[0016] In one embodiment, the number of the first pixel defining portion is one, and the number of the second pixel defining portion is multiple, wherein:

[0017] The orthographic projection of the first pixel defining portion on the substrate surrounds the orthographic projections of the plurality of second pixel defining portions on the substrate;

[0018] Preferably, the first pixel defining portion is connected to a plurality of second pixel defining portions;

[0019] Preferably, there is a gap between adjacent first electrodes, and the orthographic projection of the first pixel defining portion on the substrate covers the orthographic projection of the gap on the substrate.

[0020] In one embodiment, an orthographic projection of the first pixel defining portion on the substrate does not overlap with an orthographic projection of the first electrode on the substrate.

[0021] In one embodiment, the first electrode plate is disposed in the same layer as the first electrode and has a distance between the first electrode and the first electrode;

[0022] Preferably, the first electrode plate surrounds at least a portion of the outer circumference of the corresponding first electrode.

[0023] In one embodiment, the orthographic projection of the first electrode plate on the substrate is located within the orthographic projection of the first pixel defining portion on the substrate.

[0024] In one embodiment, the orthographic projection of the second pixel defining portion on the substrate does not overlap with the orthographic projection of the first electrode plate on the substrate.

[0025] In one embodiment, the array layer further comprises:

[0026] A plurality of second capacitors, wherein the second capacitors include a third plate and a fourth plate that are arranged opposite to each other, the control end of the driving transistor is multiplexed as the corresponding third plate, and the orthographic projection of the fourth plate on the substrate at least partially overlaps with the orthographic projection of the control end of the corresponding driving transistor on the substrate;

[0027] Preferably, the fourth plate is configured with a second power supply voltage;

[0028] Preferably, the second electrode plate is configured with a first power supply voltage, and a voltage value of the first power supply voltage is less than a voltage value of the second power supply voltage;

[0029] Preferably, the display panel further includes:

[0030] A plurality of via holes, two ends of the via holes are respectively connected to the corresponding first electrode plate and the control end of the corresponding driving transistor;

[0031] Preferably, the orthographic projection of the fourth electrode plate on the substrate surrounds at least a portion of the periphery of the corresponding via hole.

[0032] In one embodiment, the dielectric constant of the first pixel defining portion is greater than or equal to 5 F / m;

[0033] Preferably, the dielectric constant of the second pixel defining portion is less than 5 F / m;

[0034] Preferably, a difference between a dielectric constant of the first pixel defining portion and a dielectric constant of the second pixel defining portion is greater than or equal to 1 F / m.

[0035] In one embodiment, the material of at least one of the first pixel defining portion and the second pixel defining portion includes an inorganic insulating material;

[0036] Preferably, the material of the first pixel defining portion includes silicon nitride;

[0037] Preferably, the material of the second pixel defining portion includes silicon oxide.

[0038] In one embodiment, at least one of the first pixel defining portion and the second pixel defining portion has a thickness in a range of 200 nm to 1000 nm.

[0039] In a second aspect, an embodiment of the present application provides a display panel, which includes: a substrate; an array layer, which is arranged on one side of the substrate and includes a plurality of driving transistors; a plurality of first electrodes, which are arranged on a side of the array layer away from the substrate, and the first electrodes are connected to the first ends of the corresponding driving transistors; a plurality of first capacitors, wherein the first capacitors include a first electrode plate and a second electrode plate which are arranged opposite to each other, the first electrode plate is arranged on one side of the substrate, and the first electrode plate is connected to the control end of the corresponding driving transistor; a pixel defining layer, which defines a plurality of pixel openings and includes a first pixel defining portion and a second pixel defining portion, the first pixel defining portion is arranged on a side of the corresponding first electrode plate away from the substrate, the orthographic projection of the first pixel defining portion on the substrate overlaps with the orthographic projection of the corresponding first electrode plate on the substrate, the second electrode plate is arranged on a side of the first pixel defining portion away from the first electrode plate, and the second pixel defining portion covers a portion of the corresponding first electrode; a partition structure, which is arranged on a side of the pixel defining layer away from the substrate, the partition structure defines a plurality of partition openings, the partition openings are connected to the corresponding pixel openings, and at least part of the partition structure is reused as the second electrode plate; wherein the dielectric constant of the second pixel defining portion is smaller than the dielectric constant of the first pixel defining portion.

[0040] In the display panel provided by the embodiment of the present application, the dielectric constant of the second pixel defining portion is smaller than the dielectric constant of the first pixel defining portion, that is, the dielectric constant of the first pixel defining portion is set to be larger, and the dielectric constant of the second pixel defining portion is set to be smaller. Since the dielectric constant of the first pixel defining portion is larger, using the first pixel defining portion as the capacitor medium of the first capacitor is conducive to increasing the capacitance value of the first capacitor, thereby improving the stability of the control terminal voltage of the driving transistor, so as to improve the display effect of the display panel.

[0041] In one embodiment, a plurality of light-emitting units are provided in corresponding pixel openings and are located on a side of the corresponding first electrode away from the array layer;

[0042] A plurality of second electrodes, wherein the second electrodes are arranged on a side of the corresponding light emitting unit away from the array layer;

[0043] Wherein, the second electrode plate is electrically connected to the second electrode;

[0044] Preferably, the second plate and the second electrode are configured with a first power supply voltage;

[0045] Preferably, the second electrode overlaps the partition structure;

[0046] Preferably, the isolation structure is configured with a first power supply voltage.

[0047] In one embodiment, the number of the first pixel defining portion is one, and the number of the second pixel defining portion is multiple, wherein:

[0048] The orthographic projection of the first pixel defining portion on the substrate surrounds the orthographic projections of the plurality of second pixel defining portions on the substrate;

[0049] Preferably, the first pixel defining portion is connected to a plurality of second pixel defining portions;

[0050] Preferably, there is a gap between adjacent first electrodes, and the orthographic projection of the first pixel defining portion on the substrate covers the orthographic projection of the gap on the substrate.

[0051] In a third aspect, an embodiment of the present application provides a display device, comprising the display panel in the first aspect and the second aspect.

[0052] The display device provided by the embodiment of the present application includes a display panel, wherein the dielectric constant of the second pixel defining portion is smaller than the dielectric constant of the first pixel defining portion, that is, the dielectric constant of the first pixel defining portion is set to be larger, and the dielectric constant of the second pixel defining portion is set to be smaller. Since the dielectric constant of the first pixel defining portion is larger, using the first pixel defining portion as the capacitor medium of the first capacitor is conducive to increasing the capacitance value of the first capacitor, thereby improving the stability of the control terminal voltage of the driving transistor, so as to improve the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of the present application, the drawings required for use in the description of the embodiments or exemplary embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0054] Figure 1 A perspective top view of a first electrode, a first electrode plate, and a pixel defining layer provided in an embodiment of the present application.

[0055] Figure 2 A top view of the first electrode and the first electrode plate provided in an embodiment of the present application.

[0056] Figure 3 for Figure 1 Sectional view along AA direction.

[0057] Figure 4 for Figure 3 A partial enlarged schematic diagram of .

[0058] Figure 5 This is an equivalent circuit diagram of a driving transistor, a first capacitor, a second capacitor, and a light-emitting device provided in an embodiment of the present application.

[0059] Description of reference numerals:

[0060] 100, display panel; 101, array layer; 102, semiconductor layer; 110, substrate; 120, partition structure; 121, first isolation portion; 122, second isolation portion; 123, blocking portion; 124, partition opening; 130, light-emitting device; 131, first electrode; 132, second electrode; 133, light-emitting unit; 140, pixel defining layer; 141, first pixel defining portion; 142, second pixel defining portion; 143, pixel opening; 151, first plate; 152, second plate; 1 54, fourth electrode plate; 1711, first via hole; 1721, first connector; 1722, second connector; 181, first packaging layer; 182, second packaging layer; 183, third packaging layer; 190, insulating layer; 1911, first insulating layer; 1921, first planarization layer; M1, first metal layer; M2, second metal layer; M3, third metal layer; M4, fourth metal layer; DT, driving transistor; DT1, first end; DT2, second end; DT3, control end; DT4, active layer. DETAILED DESCRIPTION

[0061] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0062] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, they do not represent any order, quantity or importance, but are only used to distinguish different components. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present application, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element. "Including" or "comprising" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0063] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0064] Organic Light Emitting Diode (OLED) display technology is regarded as the most promising new flat panel display technology of the next generation. Compared with liquid crystal display technology, OLED display technology has the advantages of low energy consumption, low cost, self-luminescence, wide viewing angle and fast response speed.

[0065] In the relevant OLED display panels, the inventors have found through research that in display panels with high pixel density units (Pixels Per Inch, PPI), due to the limited area of ​​a single sub-pixel, it is difficult to increase the storage capacitor in the pixel circuit, which affects the stability of the gate voltage of the driving transistor in the pixel circuit. This will cause the display panel to have display anomalies such as flickering, bright spots on black screens, etc., resulting in the display panel having a poor display effect.

[0066] In view of at least one of the above problems, embodiments of the present application provide a display panel and a display device, which can improve the display effect of the display panel.

[0067] The following will be combined Figure 1-Figure 5 The display device provided in the embodiment of the present application is described.

[0068] The embodiment of the present application provides a display device, which includes a display panel 100. The display device can be an electronic paper, a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, a smart bracelet, a smart watch, a super personal computer, a navigator, a wireless device, a personal digital assistant (PDA), a handheld or portable computer, a GPS receiver / navigator, a camera, an MP4 video player, a camera, a game console, a clock, a calculator, a TV monitor, a computer monitor, a car display (e.g., an odometer display, etc.), a cockpit controller and / or display, a display of a camera view (e.g., a display of a rear-view camera in a vehicle), an electronic billboard or sign, a projector, and other mobile or fixed terminals.

[0069] Exemplarily, the display panel 100 may be an organic light-emitting diode (OLED) display panel, a micro organic light-emitting diode (Micro OLED) display panel, a light emitting diode (LED) display panel, a quantum dot light emitting diode (QLED) display panel, a mini light emitting diode (Mini LED) display panel, a micro light emitting diode (Micro LED) display panel, or a liquid crystal (LCD) display panel, etc. The embodiment of the present application is described by taking the OLED display panel 100 as an example.

[0070] The display panel 100 provided in the embodiment of the present application is described below.

[0071] See also Figure 1 The embodiment of the present application provides a display panel 100, and the display panel 100 may include a substrate 110. The substrate 110 may provide support for other film layers that are subsequently arranged.

[0072] In some embodiments, see Figure 1 and Figure 3 The display panel 100 may include a plurality of first electrodes 131 , and the first electrodes 131 are disposed on one side of the substrate 110 .

[0073] In some embodiments, see Figure 3 The display panel 100 may further include a pixel defining layer 140, which is disposed on a side of the substrate 110 close to the first electrode 131, and the pixel defining layer 140 defines a plurality of pixel openings 143. The pixel openings 143 are disposed corresponding to the first electrodes 131. A portion of the first electrode 131 may be located between the pixel openings 143 and the substrate 110, and the pixel openings 143 expose the portion of the first electrode 131. Another portion of the first electrode 131 may be located between the pixel defining layer 140 and the substrate 110.

[0074] For example, see Figure 1 and Figure 3The pixel defining layer 140 includes a first pixel defining portion 141 and a plurality of second pixel defining portions 142 , the second pixel defining portions 142 define a pixel opening 143 , the first pixel defining portion 141 is disposed at the periphery of each second pixel defining portion 142 , and the second pixel defining portion 142 covers a portion of the corresponding first electrode 131 .

[0075] In some embodiments, see Figure 3 , the display panel 100 may include a partition structure 120, which is disposed on a side of the pixel defining layer 140 away from the substrate 110. The partition structure 120 may define a plurality of partition openings 124, and the plurality of partition openings 124 may be arranged at intervals. The pixel opening 143 is correspondingly connected to the partition opening 124. The orthographic projection of the pixel opening 143 on the substrate 110 may be located within the orthographic projection of the partition opening 124 on the substrate 110. Among them, at least a portion of the partition structure 120 may be formed of a conductive material.

[0076] For example, see Figure 3 and Figure 4 , the orthographic projection of the first electrode 131 covered by the second pixel defining portion 142 on the substrate 110 and the orthographic projection of the partition structure 120 on the substrate 110 can overlap each other. The dielectric constant of the second pixel defining portion 142 is smaller than the dielectric constant of the first pixel defining portion 141, that is, the dielectric constant of the first pixel defining portion 141 is set to be larger, and the dielectric constant of the second pixel defining portion 142 is set to be smaller. In this way, the dielectric constant of the second pixel defining portion 142 is set to be smaller, so that the parasitic capacitance of the partition structure 120 and the first electrode 131 can be reduced, and the charge charged into the first electrode 131 under low brightness can be reduced, which is beneficial to the display uniformity of the display panel 100 under low brightness, thereby improving the display effect of the display panel 100.

[0077] For example, see Figure 3 and Figure 4 The orthographic projection of the first pixel defining portion 141 on the substrate 110 does not overlap with the orthographic projection of the first electrode 131 on the substrate 110, thereby avoiding the first pixel defining portion 141 from being disposed between the partition structure 120 and the first electrode 131, so as to alleviate the adverse effect of the first pixel defining portion 141 on the parasitic capacitance between the partition structure 120 and the first electrode 131.

[0078] See also Figure 4 The display panel 100 may include an array layer 101, and the array layer 101 is disposed between the first electrode 131 and the substrate 110. A plurality of pixel circuits may be disposed in the array layer 101, and the pixel circuits are electrically connected to the corresponding first electrodes 131.

[0079] For example, the pixel circuit may include a thin film transistor (TFT for short). Figure 4 and Figure 5 , the thin film transistor in the pixel circuit may include a driving transistor DT. The driving transistor DT is electrically connected to the first electrode 131 correspondingly. The first electrode 131 is electrically connected to the first end DT1 of the corresponding driving transistor DT. The second end DT2 of the driving transistor DT is configured with a second power supply voltage. For example, the second end DT2 of the driving transistor DT may be electrically connected to a second power supply line, and the second power supply line provides a second power supply voltage (e.g., ELVDD). Among them, one of the first end DT1 and the second end DT2 of the driving transistor DT is a source, and the other is a drain.

[0080] The first capacitor C1 provided in the embodiment of the present application is described below.

[0081] See also Figure 3 and Figure 5 , the display panel 100 may include a plurality of first capacitors C1, and the first capacitor C1 includes a first electrode plate 151 and a second electrode plate 152 that are arranged opposite to each other. The first electrode plate 151 is located on the side of the first pixel defining portion 141 facing the substrate 110, that is, the first pixel defining portion 141 is arranged on the side of the corresponding first electrode plate 151 away from the substrate 110. The orthographic projection of the first pixel defining portion 141 on the substrate 110 overlaps with the orthographic projection of the corresponding first electrode plate 151 on the substrate 110, and the second electrode plate 152 is arranged on the side of the first pixel defining portion 141 away from the first electrode plate 151. The first pixel defining portion 141 can electrically isolate the first electrode plate 151 and the second electrode plate 152. For example, the first electrode plate 151 is electrically connected to the driving transistor DT, and the first electrode plate 151 is electrically connected to the control terminal DT3 of the corresponding driving transistor DT. The dielectric constant of the second pixel defining portion 142 is smaller than the dielectric constant of the first pixel defining portion 141, that is, the dielectric constant of the first pixel defining portion 141 is set to be larger, and the dielectric constant of the second pixel defining portion 142 is set to be smaller. In this way, since the dielectric constant of the first pixel defining portion 141 is larger, the first pixel defining portion 141 is used as the capacitor medium of the first capacitor C1, which is beneficial to increase the capacitance value of the first capacitor C1, thereby improving the stability of the voltage of the control terminal DT3 of the driving transistor DT, so as to improve the display effect of the display panel 100.

[0082] In some embodiments, see Figure 3 and Figure 4At least part of the partition junction 120 is reused as the second electrode plate 152, and the existing partition structure 120 in the display panel 100 is reused as the second electrode plate 152 of the first capacitor C1. There is no need to additionally set the second electrode plate 152. The second electrode plate 152 of the first capacitor C1 can be formed without adding an additional film layer of the display panel 100 and a corresponding mask, which is beneficial to simplifying the preparation process of the display panel 100. In addition, using the first capacitor C1 as a storage capacitor is beneficial to increasing the capacitance value of the storage capacitor and avoiding the high PPI design restricting the capacitance value of the storage capacitor. By increasing the capacitance value of the storage capacitor, the stability of the voltage at the control terminal DT3 of the driving transistor DT is improved, thereby improving the display effect of the display panel 100 (for example, alleviating abnormal phenomena such as flickering, black screen bright spots, etc. in the display panel 100).

[0083] For example, part of the partition structure 120 is reused as the second electrode plate 152, and the part of the partition structure 120 reused as the second electrode plate 152 can be arranged opposite to the first electrode plate 151 along the thickness direction of the substrate 110. Another part of the partition structure 120 does not overlap with the first electrode plate 151 along the thickness direction of the substrate 110, and is not reused as the second electrode plate 152.

[0084] In some other examples, the second electrode plate 152 may also be other structures other than the partition structure 120. The present application is described by taking a part of the partition structure 120 reused as the second electrode plate 152 as an example.

[0085] For example, the first electrode plate 151 may be located in the array layer 101, so that the first electrode plate 151 may be more flexible in the thickness direction of the substrate 110. For example, the first electrode plate 151 may be located in the fourth metal layer M4.

[0086] For example, see Figure 1 The first electrode plate 151 can be located between the array layer 101 and the pixel defining layer 140, so that the distance between the first electrode plate 151 and the partition structure 120 is relatively close, that is, the distance between the two electrode plates of the first capacitor C1 along the thickness direction of the substrate 110 is relatively close, which is beneficial to increase the capacitance value of the first capacitor C1, so as to enhance the stability of the voltage at the control terminal DT3 of the driving transistor DT, thereby improving the display effect of the display panel 100.

[0087] For example, see Figure 1The first electrode 151 and the first electrode 131 are arranged in the same layer, and there may be a distance between the first electrode 151 and the first electrode 131 along the extension direction of the substrate 110, so that the first electrode 151 and the first electrode 131 can be prepared at the same time, which is beneficial to simplify the preparation process of the first electrode 151 and the first electrode 131. In addition, the distance between the first electrode 151 and the partition structure 120 along the thickness direction of the substrate 110 is also made closer, which is beneficial to increase the capacitance value of the first capacitor C1, so as to enhance the stability of the voltage at the control terminal DT3 of the driving transistor DT, thereby improving the display effect of the display panel 100. The principle has been explained and will not be repeated here.

[0088] For example, see Figure 3 , the first electrode plate 151 surrounds at least a portion of the outer circumference of the corresponding first electrode 131. For example, the first electrode plate 151 may be in a ring shape, which is beneficial to increasing the coverage of the first electrode plate 151 along the circumference of the first electrode 131, and is beneficial to increasing the area of ​​the first electrode plate 151, thereby facilitating increasing the capacitance value of the first capacitor C1, so as to enhance the stability of the voltage at the control terminal DT3 of the driving transistor DT, thereby improving the display effect of the display panel 100.

[0089] For example, see Figure 1 and Figure 2 The orthographic projection of the first electrode plate 151 on the substrate 110 is located within the orthographic projection of the first pixel defining portion 141 on the substrate 110, so that the first pixel defining portion 141 completely covers the first electrode plate 151, so that the capacitor medium of the first capacitor C1 is the first pixel defining portion 141, thereby better increasing the capacitance value of the first capacitor C1, better improving the stability of the voltage at the control terminal DT3 of the driving transistor DT, and thus better improving the display effect of the display panel 100.

[0090] For example, see Figure 1 and Figure 2 The orthographic projection of the second pixel defining portion 142 on the substrate 110 does not overlap with the orthographic projection of the first electrode plate 151 on the substrate 110, thereby avoiding the second pixel defining portion 142 from being arranged between the first electrode plate 151 and the second electrode plate 152, thereby alleviating the adverse effect of the second pixel defining portion 142 on the capacitance value of the first capacitor C1.

[0091] The pixel defining layer 140 provided in the embodiment of the present application is further described below.

[0092] For example, see Figure 1The number of the first pixel defining portion 141 is one, and the number of the second pixel defining portions 142 is multiple, and the orthographic projection of the first pixel defining portion 141 on the substrate 110 surrounds the orthographic projections of the multiple second pixel defining portions 142 on the substrate, thereby simplifying the structure of the first pixel defining portion 141 and helping to reduce the preparation cost of the pixel defining layer 140.

[0093] For example, see Figure 1 and Figure 3 The first pixel defining portion 141 is connected to the plurality of second pixel defining portions 142 , thereby improving the structural stability of the pixel defining layer 140 .

[0094] For example, see Figure 1 , there is a gap B between adjacent first electrodes 131, and the orthographic projection of the first pixel defining portion 141 on the substrate 110 covers the orthographic projection of the gap B on the substrate 110, so that the first pixel defining portion 141 and the first electrode 131 do not overlap along the thickness direction of the substrate 110, which is beneficial to reducing the adverse effect of the first pixel defining portion 141 on the parasitic capacitance between the first electrode 131 and the partition structure 120.

[0095] Exemplarily, the dielectric constant of the first pixel defining portion 141 is greater than or equal to 5F / m, which is beneficial to increase the capacitance value of the first capacitor C1, so as to improve the stability of the voltage of the control terminal DT3 of the driving transistor DT, thereby improving the display effect of the display panel 100. For example, the dielectric constant of the first pixel defining portion 141 can be 5F / m, 5.5F / m, 6F / m, 6.5F / m, 7F / m, 8F / m or any value greater than 5F / m.

[0096] Exemplarily, the dielectric constant of the second pixel defining portion 142 is less than 5F / m, which is beneficial to reducing the parasitic capacitance between the partition structure 120 and the first electrode 131, and can reduce the charge charged into the first electrode 131 at low brightness, which is beneficial to the display uniformity of the display panel 100 at low brightness, thereby improving the display effect of the display panel 100. For example, the dielectric constant of the second pixel defining portion 142 can be 1F / m, 1.5F / m, 2F / m, 2.5F / m, 3F / m, 4F / m, 4.5F / m or any value less than 5F / m.

[0097] Exemplarily, the difference between the dielectric constant of the first pixel defining portion 141 and the dielectric constant of the second pixel defining portion 142 is greater than or equal to 1F / m, so as to reduce the parasitic capacitance between the partition structure 120 and the first electrode 131 while increasing the capacitance value of the first capacitor C1. For example, the difference may be 1F / m, 1.5F / m, 2F / m, 2.5F / m, or any value greater than 1F / m.

[0098] Exemplarily, the material of at least one of the first pixel defining portion 141 and the second pixel defining portion 142 may include an inorganic insulating material. For example, the materials of the first pixel defining portion 141 and the second pixel defining portion 142 may both include an inorganic insulating material, thereby facilitating the reduction of the manufacturing cost of the first pixel defining portion 141 and the second pixel defining portion 142, facilitating the reduction of the film thickness of the first pixel defining portion 141 and the second pixel defining portion 142, and facilitating the thinning of the display panel 100.

[0099] Exemplarily, the material of the first pixel defining portion 141 includes silicon nitride (SiNy).

[0100] Exemplarily, the material of the second pixel defining portion 142 includes silicon oxide (SiOx).

[0101] Exemplarily, the thickness of the first pixel defining portion 141 ranges from 200nm to 1000nm, so that the thickness can be avoided from being too small, so that the first pixel defining portion 141 has a good covering effect on the first electrode 151. In addition, the thickness can be avoided from being too large, which is beneficial to the thinness of the display panel 100 and to increase the capacitance value of the first capacitor C1. For example, the thickness of the first pixel defining portion 141 can be 200nm, 400nm, 600nm, 800nm, 1000nm or any value between 200nm and 1000nm.

[0102] Exemplarily, the thickness of the second pixel defining portion 142 ranges from 200 nm to 1000 nm, so that the thickness can be avoided from being too small, so that the second pixel defining portion 142 has a good covering effect on part of the first electrode 131, which is beneficial to reducing the parasitic capacitance between the partition structure 120 and the first electrode 131. In addition, the thickness can be avoided from being too large, which is beneficial to the thinness of the display panel 100. For example, the thickness of the second pixel defining portion 142 can be 200 nm, 400 nm, 600 nm, 800 nm, 1000 nm, or any value between 200 nm and 1000 nm.

[0103] The second capacitor C2 provided in the embodiment of the present application is described below.

[0104] In some embodiments, see Figure 4 and Figure 5 The array layer 101 includes a plurality of second capacitors C2, the second capacitor C2 includes a third plate and a fourth plate 154 arranged opposite to each other, the control terminal DT3 of the driving transistor DT is multiplexed as the corresponding third plate, and the orthographic projection of the fourth plate 154 on the substrate 110 at least partially overlaps with the orthographic projection of the control terminal DT3 of the corresponding driving transistor DT on the substrate 110.

[0105] Exemplarily, the fourth electrode plate 154 is disposed on the side of the control terminal DT3 of the corresponding driving transistor DT facing the partition structure 120, and the first insulating layer 1911 is disposed between the control terminal DT3 of the driving transistor DT and the fourth electrode plate 154. The fourth electrode plate 154 and the control terminal DT3 of the driving transistor DT are jointly configured as two electrode plates of the second capacitor C2. In this configuration, the first capacitor C1 and the second capacitor C2 are jointly used as storage capacitors, and the total capacitance of the storage capacitor is the sum of the capacitance values ​​of the first capacitor C1 and the second capacitor C2. Even in a high PPI design, the capacitance value of the storage capacitor can be increased to further improve the stability of the voltage at the control terminal DT3 of the driving transistor DT, thereby further improving the display effect of the display panel 100.

[0106] Exemplarily, the fourth electrode plate 154 may be electrically connected to a second power line, and the second power line is used to input a second power voltage (eg, ELVDD) to the fourth electrode plate 154 .

[0107] Exemplarily, the display panel 100 further includes a plurality of vias, and the two ends of the vias are respectively connected to the corresponding first electrode plate 151 and the control terminal DT3 of the corresponding driving transistor DT. For example, the vias may include a first via 1711. The first insulating layer 1911 is provided with the first via 1711, and the first electrode plate 151 and the control terminal DT3 of the driving transistor DT are electrically connected at least through the first via 1711.

[0108] Exemplarily, the orthographic projection of the fourth electrode plate 154 on the substrate 110 surrounds at least a portion of the outer periphery of the corresponding first via hole 1711. For example, the fourth electrode plate 154 may be annular, which is beneficial to improving the coverage of the fourth electrode plate 154 and the area of ​​the fourth electrode plate 154, thereby facilitating increasing the capacitance value of the second capacitor C2, so as to enhance the stability of the voltage at the control terminal DT3 of the driving transistor DT, thereby improving the display effect of the display panel 100.

[0109] The partition structure 120 provided in the embodiment of the present application is further described below.

[0110] In some embodiments, the partition structure 120 may refer to an undercut structure that is larger on top and smaller on the bottom and can partition adjacent light-emitting units 133. The partition structure 120 may be a structure formed by a single film layer or a structure formed by stacking multiple film layers.

[0111] In some embodiments, see Figure 1The partition structure 120 may include a first isolation portion 121 and a blocking portion 123, wherein the first isolation portion 121 is located on the side of the blocking portion 123 facing the substrate 110, and the orthographic projection of the first isolation portion 121 on the substrate 110 is located within the orthographic projection of the blocking portion 123 on the substrate 110, thereby making the partition structure 120 form an undercut structure of "large on top and small on bottom", that is, the partition structure 120 has an "eaves", so that in the process of forming the light-emitting unit 133, the partition structure 120 can separate two adjacent light-emitting units 133.

[0112] For example, the cross-sectional shape of the partition structure 120 may be an inverted trapezoid, a T-shape, an I-shape, or the like, which is “large at the top and small at the bottom”.

[0113] In some embodiments, see Figure 1 , the partition structure 120 may include a second isolation portion 122, the second isolation portion 122 may be located on a side of the first isolation portion 121 away from the blocking portion 123, and the orthographic projection of the first isolation portion 121 on the substrate 110 may be located within the orthographic projection of the second isolation portion 122 on the substrate 110. In this way, in an embodiment in which the material of the partition structure 120 is a conductive material, the partition structure 120 can reduce the resistance of the partition structure 120 by providing the stacked first isolation portion 121, the second isolation portion 122 and the blocking portion 123. Since the resistance of the partition structure 120 is relatively small, when the first power supply voltage (for example, ELVSS) is carried by the partition structure 120, the in-plane ELVSS voltage drop can be ignored, ensuring that the in-plane ELVSS voltage distribution is uniform and is not easily affected by other voltages and suddenly changes, ensuring that the charge amount of the storage capacitor remains unchanged and that the voltage at the control terminal DT3 of the driving transistor DT is not affected by ELVSS fluctuations. At this time, the cross-sectional shape of the partition structure 120 formed by the first isolation portion 121 , the second isolation portion 122 and the blocking portion 123 may be an I-shape.

[0114] Exemplarily, at least one of the first isolation portion 121, the second isolation portion 122, and the barrier portion 123 may be made of a conductive material. The material of at least one of the first isolation portion 121, the second isolation portion 122, and the barrier portion 123 may include a metal such as titanium, silver, copper, aluminum, molybdenum, or an alloy, or a conductive oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), aluminum zinc oxide (AZO), zinc gallium oxide, titanium tantalum oxide, tin oxide, cadmium oxide, indium oxide, or any one or more thereof.

[0115] For example, the material of the barrier 123 may include at least one of titanium and molybdenum.

[0116] For example, the material of the first isolation portion 121 may include at least one of aluminum, copper, and silver.

[0117] For example, the material of the second isolation portion 122 may include at least one of titanium and molybdenum.

[0118] Exemplarily, the second electrode 132 overlaps the partition structure 120 . For example, the second electrode 132 overlaps at least one of the first isolation portion 121 and the second isolation portion 121 , so as to be electrically connected to the partition structure 120 .

[0119] In the embodiment where at least one of the first isolation portion 121, the second isolation portion 122 and the blocking portion 123 is made of a conductive material, the second electrode 132 of the light emitting device 130 may be electrically connected to the partition structure 120, and the partition structure 120 may be electrically connected to the second power line, and the first power voltage (for example, ELVSS) is input to the partition structure 120 through the second power line. In this way, it is convenient to electrically connect the second electrode 132 to the second power line through the partition structure 120, so as to input the first power voltage to the second electrode 132, thereby optimizing the wiring arrangement of the display panel 100.

[0120] In the embodiment where the material of the first isolation portion 121 is a conductive material, the second electrode 132 may be electrically connected to the first isolation portion 121. In this way, the second electrodes 132 located in each isolation opening 124 may be connected as a whole through the first isolation portion 121, so as to apply the first power supply voltage to the second electrodes 132, thereby optimizing the wiring arrangement of the display panel 100.

[0121] In the embodiment where the material of the second isolation portion 122 is a conductive material, the second electrode 132 of the light emitting device 130 may be electrically connected to the second isolation portion 122. In this way, the first power supply voltage may be applied to the second electrode 132 through the second isolation portion 122, thereby optimizing the wiring arrangement of the display panel 100.

[0122] In the embodiment where the materials of the first isolation part 121 and the second isolation part 122 are both conductive materials, the second electrode 132 of the light-emitting device 130 can be electrically connected to at least one of the first isolation part 121 and the second isolation part 122, and the first power supply voltage can be applied to the second electrode 132 through at least one of the first isolation part 121 and the second isolation part 122, so as to optimize the wiring arrangement of the display panel 100. For example, the second electrode 132 of the light-emitting device 130 is connected to both the first isolation part 121 and the second isolation part 122, so as to improve the connection stability between the second electrode 132 and the partition structure 120.

[0123] The structure of the partition structure 120 is described in patents PCT / CN2023 / 134518, 202310759370.2, 202310740412.8, 202310707209.0, 202311346196.5, and 202310909421.5 for reference.

[0124] The light emitting device 130 provided in the embodiment of the present application is described below.

[0125] In some embodiments, see Figure 1 A light-emitting unit 133 and a second electrode 132 are sequentially arranged on the side of the first electrode 131 facing away from the substrate 110. There can be multiple light-emitting units 133, which are arranged in the corresponding pixel opening 143 and located on the side of the corresponding first electrode 131 facing away from the array layer 101. There can be multiple second electrodes 132, which are arranged on the side of the corresponding light-emitting unit 133 facing away from the array layer 101. The correspondingly arranged first electrodes 131, light-emitting units 133 and second electrodes 132 together form a light-emitting device 130.

[0126] Exemplarily, the second electrode 152 is electrically connected to the second electrode 132, so that the first power supply voltage of the second electrode 132 can be reused as a fixed voltage that needs to be input to the second electrode 152, and there is no need to provide a fixed voltage to the second electrode 152 separately, which is conducive to reducing the number of signal terminals and signal lines for transmitting voltage signals in the display panel 100, thereby simplifying the structure of the display panel 100. At this time, the second electrode 152 and the second electrode 132 are both configured with the first power supply voltage.

[0127] For example, one of the first electrode 131 and the second electrode 132 may be an anode, and the other of the first electrode 131 and the second electrode 132 may be a cathode. The present embodiment is described by taking the first electrode 131 as an anode and the second electrode 132 as a cathode as an example.

[0128] Exemplarily, one of the first power line and the second power line is used to transmit a high voltage signal ( Figure 5 ELVDD in), and the other is used to transmit low voltage signals ( Figure 5 For example, the first power line is used to transmit a high voltage, that is, the second power line is a high voltage signal, and the second power line is used to transmit a low voltage, that is, the first power line is a low voltage signal. The voltage value of the first power line is less than the voltage value of the second power line.

[0129] Exemplarily, the light-emitting device 130 may further include one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron injection layer (EIL), an electron transport layer (ETL), a hole blocking layer (HBL) and an electron blocking layer (EBL).

[0130] Exemplarily, the plurality of light emitting devices 130 include, but are not limited to, red light emitting devices, green light emitting devices, and blue light emitting devices. In some other examples, the plurality of light emitting devices 130 may also include white light emitting devices. For example, the light emitting unit 133 of the red light emitting device is formed of a red light emitting material, the light emitting unit 133 of the green light emitting device is formed of a green light emitting material, and the light emitting unit 133 of the blue light emitting device is formed of a blue light emitting material.

[0131] The encapsulation layer provided in the embodiments of the present application is described below.

[0132] In some embodiments, see Figure 1 The display panel 100 includes a first encapsulation layer 181, which may include a plurality of encapsulation parts. The encapsulation parts are arranged corresponding to the light-emitting devices 130, and the encapsulation parts cover the side of the corresponding light-emitting devices 130 away from the substrate 110, and the encapsulation parts extend to the side wall of the partition structure 120 and the side of the partition structure 120 away from the substrate 110.

[0133] In some embodiments, see Figure 1 The display panel 100 may include a second encapsulation layer 182 , where the second encapsulation layer 182 is located on a side of the first encapsulation layer 181 facing away from the substrate 110 .

[0134] In some embodiments, the display panel 100 may include a third encapsulation layer 183 , where the third encapsulation layer 183 is located on a side of the second encapsulation layer 182 facing away from the substrate 110 .

[0135] For example, see Figure 1 The material of the second encapsulation layer 182 can be an organic material, which is helpful to relieve the stress of the film layer. For example, it can be prepared by coating, inkjet printing or other methods.

[0136] Exemplarily, at least one of the first encapsulation layer 181 and the third encapsulation layer 183 may be made of an inorganic material. The encapsulation layer of an inorganic material has a better barrier effect on water vapor and oxygen, thereby achieving a better encapsulation effect. For example, a deposition process may be used, such as atomic layer deposition (ALD), physical vapor deposition (PVD), or chemical vapor deposition (CVD).

[0137] The array layer 101 provided in the embodiment of the present application is further described below.

[0138] In some embodiments, see Figure 1 The array layer 101 may include a semiconductor layer 102, a first metal layer M1, a second metal layer M2, a third metal layer M3 and a fourth metal layer M4 which are sequentially stacked on a substrate 110, and an insulating layer 190 is disposed between each two adjacent layers of the semiconductor layer 102, the first metal layer M1, the second metal layer M2, the third metal layer M3 and the fourth metal layer M4.

[0139] For example, see Figure 1 The first planarization layer 1921 may be disposed on the side of the fourth metal layer M4 facing away from the substrate 110, and the first electrode 131 and the pixel defining layer 140 are both disposed on the side of the first planarization layer 1921 facing away from the substrate 110. The first planarization layer 1921 provides good planar support for subsequent film formation.

[0140] Exemplarily, the insulating layer 190 between the third metal layer M3 and the fourth metal layer M4 may be reused as the second planarization layer.

[0141] For example, see Figure 1 , the active layer DT4 of the driving transistor DT may be formed by the semiconductor layer 102, the control terminal DT3 of the driving transistor DT may be formed by the first metal layer M1, the fourth electrode 154 of the second capacitor C2 may be formed by the second metal layer M2, and the second terminal DT2 and the first terminal DT1 of the driving transistor DT may be formed by the third metal layer M3. The first electrode 151 may be connected to the control terminal DT3 of the driving transistor DT through a first connector 1721, and the first connector 1721 may be formed by the third metal layer M3 and the fourth metal layer M4. The first electrode 131 and the first terminal DT1 of the driving transistor DT may be connected through a second connector 1722, and the second connector 1722 may be formed by the fourth metal layer M4.

[0142] Exemplarily, the thin film transistor may include at least one of a metal oxide (MO) thin film transistor and a low temperature polysilicon (LTPS) thin film transistor, a high temperature polysilicon thin film transistor, and an amorphous silicon thin film transistor. For example, a low temperature polycrystalline oxide (LTPO) technology may be used, and LTPS thin film transistors and MO thin film transistors may be used as thin film transistors in a driving unit. LTPS thin film transistors may be used as driving thin film transistors, which have high mobility, can reduce driving voltage, and achieve high refresh rate and high resolution; MO thin film transistors may be used as switching thin film transistors, which have low leakage current, can enable the display panel 100 to maintain a good display effect at a low frame rate, and reduce the power consumption of the display panel 100. LTPO may combine the advantages of these two thin film transistors.

[0143] In the case of using “including”, “having”, and “comprising” described herein, another component may be added unless a clear limiting term such as “only”, “consisting of”, etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as being one in number.

[0144] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0145] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A display panel, characterized in that: The display panel comprises: substrate; An array layer, disposed on one side of the substrate, comprising a plurality of driving transistors; A plurality of first electrodes are arranged on a side of the array layer away from the substrate, and the first electrodes are connected to first ends of corresponding driving transistors; A plurality of first capacitors, wherein the first capacitors include a first electrode plate and a second electrode plate that are arranged opposite to each other, wherein the first electrode plate is arranged on one side of the substrate, and the first electrode plate is connected to a control terminal of the corresponding driving transistor; A pixel defining layer, comprising a first pixel defining portion and a second pixel defining portion, wherein the first pixel defining portion is disposed on a side of the corresponding first electrode plate away from the substrate, an orthographic projection of the first pixel defining portion on the substrate overlaps an orthographic projection of the corresponding first electrode plate on the substrate, and the second electrode plate is disposed on a side of the first pixel defining portion away from the first electrode plate, and the second pixel defining portion covers a portion of the corresponding first electrode; Wherein, the dielectric constant of the second pixel defining portion is smaller than the dielectric constant of the first pixel defining portion.

2. The display panel according to claim 1, characterized in that: The pixel defining layer defines a plurality of pixel openings, and the display panel further comprises: a plurality of light-emitting units, wherein the light-emitting units are disposed in corresponding pixel openings and located on a side of the corresponding first electrode away from the array layer; A plurality of second electrodes, wherein the second electrodes are arranged on a side of the corresponding light-emitting unit away from the array layer; Wherein, the second electrode plate is electrically connected to the second electrode; Preferably, the second plate and the second electrode are configured with a first power supply voltage; Preferably, the display panel further includes: A partition structure is disposed on a side of the pixel defining layer away from the substrate, the partition structure defines a plurality of partition openings, and the partition openings are connected to the corresponding pixel openings; Wherein, at least part of the partition structure is reused as the second electrode plate; Preferably, the second electrode overlaps the partition structure; Preferably, the isolation structure is configured with a first power supply voltage.

3. The display panel according to claim 1, characterized in that: The number of the first pixel defining portion is one, and the number of the second pixel defining portion is a plurality, wherein: The orthographic projection of the first pixel defining portion on the substrate surrounds the orthographic projections of a plurality of the second pixel defining portions on the substrate; Preferably, the first pixel defining portion is connected to a plurality of the second pixel defining portions; Preferably, there is a gap between adjacent first electrodes, and the orthographic projection of the first pixel defining portion on the substrate covers the orthographic projection of the gap on the substrate.

4. The display panel according to any one of claims 1 to 3, characterized in that: An orthographic projection of the first pixel defining portion on the substrate does not overlap with an orthographic projection of the first electrode on the substrate.

5. The display panel according to any one of claims 1 to 3, characterized in that: The first electrode plate is disposed in the same layer as the first electrode and has a distance between the first electrode and the first electrode; Preferably, the first electrode plate surrounds at least a portion of the outer circumference of the corresponding first electrode.

6. The display panel according to any one of claims 1 to 3, characterized in that: The orthographic projection of the first electrode plate on the substrate is located within the orthographic projection of the first pixel defining portion on the substrate.

7. The display panel according to any one of claims 1 to 3, characterized in that: An orthographic projection of the second pixel defining portion on the substrate does not overlap with an orthographic projection of the first electrode plate on the substrate.

8. The display panel according to any one of claims 1 to 3, characterized in that: The array layer further comprises: A plurality of second capacitors, wherein the second capacitors include a third plate and a fourth plate that are arranged opposite to each other, the control end of the driving transistor is multiplexed as the corresponding third plate, and the orthographic projection of the fourth plate on the substrate at least partially overlaps with the orthographic projection of the control end of the corresponding driving transistor on the substrate; Preferably, the fourth electrode plate is configured with a second power supply voltage; Preferably, the second electrode plate is configured with a first power supply voltage, and a voltage value of the first power supply voltage is smaller than a voltage value of the second power supply voltage; Preferably, the display panel further includes: A plurality of via holes, two ends of each via hole being respectively connected to a corresponding first electrode plate and a corresponding control end of the driving transistor; Preferably, the orthographic projection of the fourth electrode plate on the substrate surrounds at least a portion of the outer periphery of the corresponding via hole.

9. The display panel according to any one of claims 1 to 3, characterized in that: The dielectric constant of the first pixel defining portion is greater than or equal to 5F / m; Preferably, the dielectric constant of the second pixel defining portion is less than 5F / m; Preferably, a difference between a dielectric constant of the first pixel defining portion and a dielectric constant of the second pixel defining portion is greater than or equal to 1 F / m.

10. The display panel according to any one of claims 1 to 3, characterized in that: The material of at least one of the first pixel defining portion and the second pixel defining portion includes an inorganic insulating material; Preferably, the material of the first pixel defining portion includes silicon nitride; Preferably, the material of the second pixel defining portion includes silicon oxide.

11. The display panel according to any one of claims 1 to 3, characterized in that: A thickness of at least one of the first pixel defining portion and the second pixel defining portion is in a range of 200 nm to 1000 nm.

12. A display panel, characterized in that: The display panel comprises: substrate; An array layer, disposed on one side of the substrate, comprising a plurality of driving transistors; A plurality of first electrodes are arranged on a side of the array layer away from the substrate, and the first electrodes are connected to first ends of corresponding driving transistors; A plurality of first capacitors, wherein the first capacitors include a first electrode plate and a second electrode plate that are arranged opposite to each other, wherein the first electrode plate is arranged on one side of the substrate, and the first electrode plate is connected to a control terminal of the corresponding driving transistor; a pixel defining layer defining a plurality of pixel openings and comprising a first pixel defining portion and a second pixel defining portion, wherein the first pixel defining portion is disposed on a side of the corresponding first electrode plate away from the substrate, an orthographic projection of the first pixel defining portion on the substrate overlaps an orthographic projection of the corresponding first electrode plate on the substrate, and the second electrode plate is disposed on a side of the first pixel defining portion away from the first electrode plate, and the second pixel defining portion covers a portion of the corresponding first electrode; A partition structure is disposed on a side of the pixel defining layer away from the substrate, the partition structure defines a plurality of partition openings, the partition openings are connected to the corresponding pixel openings, and at least a portion of the partition structure is reused as the second electrode plate; Wherein, the dielectric constant of the second pixel defining portion is smaller than the dielectric constant of the first pixel defining portion.

13. The display panel according to claim 12, characterized in that: a plurality of light-emitting units, wherein the light-emitting units are disposed in corresponding pixel openings and located on a side of the corresponding first electrode away from the array layer; A plurality of second electrodes, wherein the second electrodes are arranged on a side of the corresponding light-emitting unit away from the array layer; Wherein, the second electrode plate is electrically connected to the second electrode; Preferably, the second plate and the second electrode are configured with a first power supply voltage; Preferably, the second electrode overlaps the partition structure; Preferably, the isolation structure is configured with a first power supply voltage.

14. The display panel according to claim 12, characterized in that: The number of the first pixel defining portion is one, and the number of the second pixel defining portion is a plurality, wherein: The orthographic projection of the first pixel defining portion on the substrate surrounds the orthographic projections of a plurality of the second pixel defining portions on the substrate; Preferably, the first pixel defining portion is connected to a plurality of the second pixel defining portions; Preferably, there is a gap between adjacent first electrodes, and the orthographic projection of the first pixel defining portion on the substrate covers the orthographic projection of the gap on the substrate.

15. A display device, characterized in that: A display panel comprising any one of claims 1 to 14.

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