Display panel, preparation method of display panel and electronic equipment

Abstract

The embodiment of the invention provides a display panel, a preparation method of the display panel and electronic equipment, and relates to the technical field of display, the display panel comprises a substrate, a conductive layer and a packaging layer, the conductive layer is located on one side of the substrate, the conductive layer comprises a power line, and at least part of the power line is located in a non-display area; the packaging layer is located on the side, away from the substrate, of the conductive layer, extends from the display area to the non-display area and covers at least part of the side face of the power source wire located in the non-display area. According to the display panel, the packaging layer is arranged to cover at least part of the side face of the power source wire located in the non-display area, packaging of the side face of the power source wire is not prone to losing efficacy, external water vapor is not prone to entering the display area through the side face of the power source wire, and therefore the display effect of the display panel is not prone to being affected.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular, to a display panel, a method for preparing a display panel, and an electronic device. Background Art

[0002] Organic Light Emitting Diode (OLED) and flat-panel display devices based on technologies such as Light Emitting Diode (LED) have been widely used in various consumer electronic products such as mobile phones, televisions, laptops, desktop computers, etc. due to their advantages such as high image quality, power saving, thin body and wide application range, becoming the mainstream in display panels.

[0003] However, there are still some problems with display panels that need to be solved urgently. Summary of the invention

[0004] In order to overcome the technical problems mentioned in the above technical background, an embodiment of the present application provides a display panel, wherein the display panel includes a display area and a non-display area surrounding at least a portion of the display area, and the display panel includes: substrate; A conductive layer, located on one side of the substrate, the conductive layer comprising power lines, at least part of which is located in the non-display area; The encapsulation layer is located on a side of the conductive layer away from the substrate, and the encapsulation layer extends from the display area to the non-display area and covers at least a portion of a side surface of the power supply wiring located in the non-display area.

[0005] In some possible implementations, the display panel further includes a planarization layer located on a side of the conductive layer away from the substrate, and the planarization layer is at least partially located in the display area; Preferably, the display panel further comprises a pixel defining layer located on a side of the planarization layer away from the substrate, the pixel defining layer is at least partially located in the non-display area, and the pixel defining layer located in the non-display area covers at least a portion of a side of the power wiring away from the substrate; Preferably, the encapsulation layer extends from a side of the power line through a side of the pixel defining layer to a side of the pixel defining layer located in the non-display area away from the substrate; Preferably, the encapsulation layer covers the side surface of the pixel defining layer located in the non-display area; Preferably, the encapsulation layer covers the side surface of the power wiring and the side surface of the pixel defining layer located in the non-display area; Preferably, the pixel defining layer extends from the display area to the non-display area; Preferably, the side surface of the pixel defining layer is at least partially flush with the side surface of the power wiring; Preferably, the material of the pixel defining layer includes an inorganic material.

[0006] In some possible implementations, the display panel further includes a planarization layer located on a side of the conductive layer away from the substrate, and the planarization layer is at least partially located in the display area; Preferably, the display panel further comprises a pixel defining layer located on a side of the planarization layer away from the substrate, and the pixel defining layer is at least partially located in the display area; Preferably, the encapsulation layer extends from a side of the power line to a side of the power line away from the substrate; Preferably, the material of the pixel defining layer is an organic material.

[0007] In some possible implementations, the power supply line includes a first power supply line and a second power supply line, and the encapsulation layer covers the side surfaces of the first power supply line and the second power supply line located in the non-display area; Preferably, the encapsulation layer fills at least a portion of the gap between the first power line and the second power line; Preferably, the first power line and the second power line are arranged on the same layer; Preferably, the first power line and the second power line transmit different power signals; Preferably, the first power supply line comprises a power supply voltage line; Preferably, the second power supply line comprises a common ground voltage line.

[0008] In some possible implementations, the display panel further includes an isolation structure on a side of the conductive layer away from the substrate, and the isolation structure encloses to form an isolation opening; Preferably, the display panel further comprises a pixel defining layer located on a side of the conductive layer away from the substrate, and the isolation structure is located on a side of the pixel defining layer away from the substrate; Preferably, the pixel defining layer is provided with a via hole located in the non-display area, and the isolation structure is electrically connected to the second power supply line through the via hole.

[0009] In some possible implementations, the display panel further includes a light emitting unit at least partially located in the isolation opening, the light emitting unit including a first electrode, a light emitting portion, and a second electrode sequentially stacked in a direction away from the substrate; Preferably, the pixel defining layer comprises a pixel opening exposing at least a portion of the first electrode, and an orthographic projection of the pixel opening on the substrate is located within an orthographic projection of the isolation opening on the substrate.

[0010] In some possible implementations, the display panel includes a first encapsulation layer located on a side of the light-emitting unit away from the substrate, the first encapsulation layer includes a plurality of encapsulation units arranged at intervals, and at least some of the encapsulation units extend from a side of the isolation structure toward the isolation opening to a side of the isolation structure away from the substrate; Preferably, the encapsulation unit is arranged at intervals on a side of the isolation structure away from the substrate; Preferably, there is a gap between the packaging unit located on a side of the isolation structure away from the substrate and a side of the isolation structure away from the substrate; Preferably, the orthographic projection of the encapsulation unit on the substrate covers the orthographic projection of the isolation opening on the substrate and covers a portion of the orthographic projection of the isolation structure on the substrate.

[0011] In some possible implementations, the display panel further includes a second encapsulation layer located on a side of the first encapsulation layer away from the substrate; Preferably, the display panel further comprises a third encapsulation layer located on a side of the second encapsulation layer away from the substrate; Preferably, the encapsulation layer includes the third encapsulation layer, or the encapsulation layer includes the first encapsulation layer and the third encapsulation layer; Preferably, the materials of the first encapsulation layer and the third encapsulation layer both include inorganic materials; Preferably, the material of the second encapsulation layer includes organic material.

[0012] In some possible implementations, the isolation structure includes a first isolation portion and a second isolation portion which are sequentially stacked in a direction away from the substrate, and an orthographic projection of a side of the first isolation portion away from the substrate on the substrate is located within an orthographic projection of the second isolation portion on the substrate; Preferably, the second electrode is electrically connected to the first isolation portion; and / or the isolation structure further comprises a third isolation portion located on a side of the first isolation portion facing the substrate, and the second electrode is electrically connected to the third isolation portion; Preferably, the material of the third isolation portion includes molybdenum metal; and / or the material of the first isolation portion includes aluminum metal; and / or the material of the second isolation portion includes titanium metal.

[0013] In some possible implementations, the present application further provides a method for preparing a display panel, wherein the display panel includes a display area and a non-display area surrounding at least a portion of the display area, and the method includes: providing a substrate; A conductive layer is formed on one side of the substrate, the conductive layer comprising a first power line, a second power line, and a connecting line connected between a side surface of the first power line and a side surface of the second power line, and at least a portion of the first power line, at least a portion of the second power line, and the connecting line are all located in the non-display area; removing the connecting wiring; An encapsulation layer is formed on a side of the conductive layer away from the substrate, wherein the encapsulation layer extends from the display area to the non-display area and covers at least a portion of side surfaces of the first power wiring and the second power wiring located in the non-display area.

[0014] In some possible implementations, before the step of removing the connecting wire, the method further includes: forming a planarization layer on a side of the conductive layer away from the substrate, wherein the planarization layer is located in the display area; A first electrode layer is formed on a side of the planarization layer away from the substrate, and the electrode layer is patterned to form a plurality of first electrodes that are spaced apart.

[0015] In some possible implementations, after the step of forming a first electrode layer on a side of the planarization layer away from the substrate and patterning the first electrode layer, the method further includes: forming a pixel defining material layer on a side of the first electrode layer away from the substrate, wherein the pixel defining material layer includes a via hole exposing at least a portion of the second power supply line; forming an isolation material layer on a side of the pixel defining material layer away from the substrate, and patterning the isolation material layer and the pixel defining material layer in sequence to form an isolation structure and a pixel defining layer respectively, wherein the isolation structure encloses an isolation opening, the pixel defining layer includes a pixel opening exposing at least a portion of the first electrode, the pixel opening is connected to the isolation opening, and the isolation structure is electrically connected to the second power supply line through the via hole; A light emitting unit is formed in the isolation opening, and a first encapsulation layer is formed in the display area on a side of the light emitting unit away from the substrate, wherein the first encapsulation layer includes an encapsulation unit, and at least a part of the encapsulation unit extends from a side of the isolation structure toward the isolation opening to a side of the isolation structure away from the substrate; forming a second encapsulation layer located in the display area on a side of the first encapsulation layer away from the substrate; The pixel definition layer between the first power line and the second power line is removed to expose the connection line.

[0016] In some possible implementations, after the step of forming a first electrode layer on a side of the planarization layer away from the substrate and patterning the first electrode layer, the method further includes: forming a pixel defining layer on a side of the first electrode layer away from the substrate, the pixel defining layer being located in the display area, and the pixel defining layer comprising a pixel opening exposing at least a portion of the first electrode; forming a light emitting unit in the pixel opening; forming a first encapsulation layer located in the display area on a side of the light emitting unit away from the substrate; A second encapsulation layer located in the display area is formed on a side of the first encapsulation layer away from the substrate.

[0017] In some possible implementations, the step of forming an encapsulation layer on a side of the conductive layer away from the substrate includes: forming a third encapsulation layer on a side of the second encapsulation layer away from the substrate, wherein the third encapsulation layer extends from the display area to the non-display area and covers the side surfaces of the first power line and the second power line located in the non-display area; Preferably, the step of removing the connecting wiring includes: The connecting traces are removed by dry etching.

[0018] In some possible implementations, the present application further provides an electronic device, which includes the display panel described in the present application, or includes a display panel prepared by the method for preparing the display panel described in the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 A schematic top view of a display panel in the related art provided by an embodiment of the present application; Figure 2 Provided for the embodiments of this application Figure 1 Schematic cross-sectional view at AA in the middle; Figure 3 This is one of the schematic top views of a display panel provided in an embodiment of the present application; Figure 4 Provided for the embodiments of this application Figure 3 One of the cross-sectional views at the middle BB; Figure 5 Provided for the embodiments of this application Figure 3 One of the cross-sectional views at CC in the middle; Figure 6 Provided for the embodiments of this application Figure 3 The second cross-sectional view of the middle BB; Figure 7a Provided for the embodiments of this application Figure 3 The second cross-sectional view at CC in the middle; Figure 7b Provided for the embodiments of this application Figure 3 The third cross-sectional view of the CC in the middle; Figure 8 Provided for the embodiments of this application Figure 3 The fourth cross-sectional view of the CC in the middle; Figure 9a Provided for the embodiments of this application Figure 3 Sectional view of CC in the middle No. 5; Figure 9b Provided for the embodiments of this application Figure 3 Sectional view of CC in the middle No. 6; Fig.10 A schematic diagram of a process for preparing a display panel provided in an embodiment of the present application; Fig.11 A second schematic top view of a display panel provided in an embodiment of the present application; Fig.12 Provided for the embodiments of this application Fig.11 The cross-sectional view of the first power supply line, the second power supply line and the connecting line formed on one side of the substrate at DD in the middle; Fig.13 Provided for the embodiments of this application Fig.11 The cross-sectional view of the planarization layer formed on the side of the conductive layer away from the substrate at EE in the middle; Fig.14 Provided for the embodiments of this application Fig.11 The cross-sectional view of forming the first electrode layer on the side of the planarization layer away from the substrate at EE in the middle; Fig.15 Provided for the embodiments of this application Fig.11 EE in the middle is one of the cross-sectional views of forming a pixel defining material layer on a side of the first electrode layer away from the substrate; Fig.16 Provided for the embodiments of this application Fig.11A schematic cross-sectional view of the first power supply line, the connecting line, and the second power supply line in the non-display area covered by the pixel definition layer at DD in the middle; Fig.17 Provided for the embodiments of this application Fig.11 A cross-sectional schematic diagram of forming an isolation material layer at a side of the pixel defining material layer away from the substrate at EE in the middle; Fig.18 Provided for the embodiments of this application Fig.11 A cross-sectional schematic diagram of the isolation material layer and the pixel definition material layer after patterning in sequence at EE in the middle; Fig.19 Provided for the embodiments of this application Fig.11 EE in the middle is one of the cross-sectional views of forming a second encapsulation layer located in the display area on the side of the first encapsulation layer away from the substrate; Fig. 20 Provided for the embodiments of this application Fig.11 The cross-section diagram at DD in the middle is a schematic diagram of a section after removing the pixel definition layer between the first power supply line and the second power supply line; Fig.21 Provided for the embodiments of this application Fig.11 EE in the middle is the second cross-sectional view of forming a pixel defining layer on the side of the first electrode layer away from the substrate; Fig. 22 Provided for the embodiments of this application Fig.11 The cross-sectional view of the light-emitting unit formed in the pixel opening at EE in the middle; Fig.23a Provided for the embodiments of this application Fig.11 The EE in the middle is a second cross-sectional view of forming a second encapsulation layer located in the display area on the side of the first encapsulation layer away from the substrate; Figure 23b Provided for the embodiments of this application Fig.11 EE in the middle is the third cross-sectional view of forming a second encapsulation layer located in the display area on the side of the first encapsulation layer away from the substrate; Fig.24 Provided for the embodiments of this application Fig.11 One of the cross-sectional intentions of removing the connection trace between the first power trace and the second power trace at DD in the middle; Fig.25 Provided for the embodiments of this application Fig.11 The second cross-sectional intention is to remove the connecting wire between the first power wire and the second power wire at DD in the middle.

[0021] Figure numerals: 1. power supply line; 101. first power supply line; 102. second power supply line; 2. substrate; 3. packaging layer; 4. pixel defining layer; 41. pixel opening; 42. via; 5. first electrode; 6. light-emitting portion; 7. second electrode; 8. isolation structure; 81. first isolation portion; 82. second isolation portion; 83. third isolation portion; 9. first packaging layer; 91. packaging unit; 10. isolation opening; 11. planarization layer; 12. light-emitting unit; 13. second packaging layer; 14. third packaging layer; 15. connection line; 16. pixel defining material layer; 17. isolation material layer. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0023] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0024] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0025] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "vertical", "horizontal", "inner", "outer", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, or the positions or positional relationships in which the invention product is usually placed when in use, which are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0026] It should be noted that, in the absence of conflict, different features in the embodiments of the present application may be combined with each other.

[0027] Improving the density of light-emitting units in a display panel (i.e., pixel density) is an important way to improve the display effect. However, the display panels currently made using the fine metal evaporation mask (FMM) technology cannot further increase the density of light-emitting units due to technical limitations. The inventors have found through long-term research that in order to solve the technical problem that the density of light-emitting units cannot be further increased, an isolation structure is set in some display panels. When the light-emitting functional layer and the second electrode are evaporated in the entire layer, the light-emitting functional layer and the second electrode can be disconnected at the isolation structure. Through multiple evaporation and multiple etching processes (i.e., light-emitting unit patterning), light-emitting units of different colors can be formed in different isolation openings.

[0028] Among them, patents CN118251982A, 202410864269.8, PCT / CN2024 / 098407, PCT / CN2024 / 102783, PCT / CN2024 / 098217, PCT / CN2024 / 099419, and PCT / CN2024 / 099072 record relevant technical solutions for isolation structures, and their contents are incorporated into this application by reference for reference.

[0029] See also Figure 1 and Figure 2 The display panel in the related art includes a display area AA and a non-display area AB surrounding at least a portion of the display area AA. The display panel includes a substrate 2, a power line 1 located on one side of the substrate 2, and an encapsulation layer 3 located on a side of the power line 1 away from the substrate 2.

[0030] In the process of preparing the display panel, for example, when forming a planarization layer on the side of the film layer where the power supply line 1 is located away from the substrate 2, the developer of the planarization layer will side-etch the side of the power supply line 1. For another example, when forming a first electrode layer on the side of the planarization layer away from the substrate 2 and patterning the first electrode layer, the etching solution of the first electrode layer will side-etch the side of the power supply line 1. In this way, the side of the power supply line 1 will be etched to a large extent. When forming the encapsulation layer 3, the encapsulation layer 3 is prone to encapsulation failure on the side of the power supply line 1, and the external water vapor is easy to enter the display area AA through the position where the encapsulation of the power supply line 1 fails, thereby affecting the display effect of the display panel and even causing the display panel to fail.

[0031] In order to solve the above-mentioned technical problems, the inventor innovatively designed the following technical solutions, and the specific implementation solutions of the present application will be described in detail below in conjunction with the accompanying drawings. It should be noted that the defects existing in the solutions in the above-mentioned prior art are the results obtained by the inventor after practice and careful research. Therefore, the discovery process of the above-mentioned technical problems and the solutions proposed in this embodiment below for the above-mentioned problems should all be the contributions made by the inventor to the present application in the process of invention and creation, and should not be understood as the technical content known to those skilled in the art.

[0032] See also Figure 3-Figure 5 This embodiment provides a display panel, which includes a display area AA and a non-display area AB surrounding at least a portion of the display area AA. The display panel includes a substrate 2, a conductive layer and an encapsulation layer 3.

[0033] The conductive layer is located on one side of the substrate 2, and the conductive layer includes a power line 1, and at least part of the power line 1 is located in the non-display area AB; the encapsulation layer 3 is located on the side of the conductive layer away from the substrate 2, and the encapsulation layer 3 extends from the display area AA to the non-display area AB and covers at least part of the side of the power line 1 located in the non-display area AB.

[0034] The power line 1 can provide a power signal for the first electrode 5 and the second electrode 7 of the display panel to make the light-emitting unit 12 of the display panel emit light. In this embodiment, since the encapsulation layer 3 covers the side of the power line 1, that is, the encapsulation layer 3 fits the side of the power line 1, the encapsulation layer 3 can encapsulate the side of the power line 1 more effectively, and it is not easy for external water vapor to enter the display area AA of the display panel from the side of the power line 1, thereby not easily causing the display panel to fail.

[0035] Based on the above design, this embodiment sets the encapsulation layer 3 to cover at least part of the side of the power line 1 located in the non-display area AB, so that the encapsulation on the side of the power line 1 is not easy to fail, and external water vapor is not easy to enter the display area AA through the side of the power line 1, thereby not easily affecting the display effect of the display panel.

[0036] For some possible implementations, see Figure 5 As shown in FIG. 7 , the display panel further includes a light emitting unit 12 , which includes a first electrode 5 , a light emitting portion 6 , and a second electrode 7 which are sequentially stacked in a direction away from the substrate 2 , wherein the first electrode 5 may be an anode and the second electrode 7 may be a cathode.

[0037] For some possible implementations, see again Figure 3 and Figure 4The power supply line 1 includes a first power supply line 101 and a second power supply line 102 , and the encapsulation layer 3 covers the side surfaces of the first power supply line 101 and the second power supply line 102 located in the non-display area AB.

[0038] The encapsulation layer 3 completely covers the positions on the sides of the first power line 101 and the second power line 102 where water vapor can easily penetrate, thereby further improving the encapsulation effect of the encapsulation layer 3 on the sides of the first power line 101 and the second power line 102, making it more difficult for water vapor to enter the display area AA through the sides of the first power line 101 and the second power line 102.

[0039] Preferably, the packaging layer 3 fills at least a portion of the gap between the first power line 101 and the second power line 102 , so that the packaging layer 3 has a better packaging effect on the side surfaces of the first power line 101 and the second power line 102 .

[0040] Preferably, the first power line 101 and the second power line 102 are arranged on the same layer. For example, the first power line 101 and the second power line 102 are both located on the fourth conductive layer or the fifth conductive layer of the display panel. In this way, the first power line 101 and the second power line 102 can be simultaneously formed through the same conductive layer.

[0041] Preferably, the power signals transmitted by the first power line 101 and the second power line 102 are different. The first power line 101 includes a power voltage line, and the second power line 102 includes a common ground voltage line. The first power line 101 can be electrically connected to the first electrode 5 to transmit a positive voltage to the light-emitting unit 12, and the second power line 102 can be electrically connected to the second electrode 7 to transmit a negative voltage to the light-emitting unit 12.

[0042] In one embodiment, see Figure 3 , Figure 5 and Figure 6 In some possible embodiments, the display panel further includes a planarization layer 11 located on a side of the conductive layer away from the substrate 2 and a pixel defining layer 4 located on a side of the planarization layer 11 away from the substrate 2, the planarization layer 11 is at least partially located in the display area AA, the pixel defining layer 4 is at least partially located in the non-display area AB, the pixel defining layer 4 located in the non-display area AB covers the side of the power line 1 away from the substrate 2, the encapsulation layer 3 extends from the side of the power line 1 through the side of the pixel defining layer 4 to the side of the pixel defining layer 4 located in the non-display area AB away from the substrate 2, and the encapsulation layer 3 covers the side of the pixel defining layer 4 located in the non-display area AB.

[0043] In this embodiment, the pixel defining layer 4 includes an inorganic material, the pixel defining layer 4 extends to the side of the power line 1 in the non-display area AB away from the substrate 2, and the encapsulation layer 3 extends from the side of the power line 1 through the side of the pixel defining layer 4 to the side of the pixel defining layer 4 in the non-display area AB away from the substrate 2. The encapsulation layer 3 can cover the side of the power line 1 and the side of the pixel defining layer 4 in the non-display area AB for more effective encapsulation.

[0044] Preferably, the pixel defining layer 4 extends from the display area AA to the non-display area AB, and the side of the pixel defining layer 4 is at least partially flush with the side of the power line 1. In this way, the encapsulation layer 3 can be more closely attached to the side of the power line 1 and the pixel defining layer 4.

[0045] In this embodiment, please refer again to Figure 5 The display panel also includes an isolation structure 8 on the side of the conductive layer away from the substrate 2, the isolation structure 8 encloses an isolation opening 10, at least part of the light-emitting unit 12 is located in the isolation opening 10, the isolation structure 8 is located on the side of the pixel defining layer 4 away from the substrate 2, the pixel defining layer 4 includes a pixel opening 41 exposing at least part of the first electrode 5, and the orthographic projection of the pixel opening 41 on the substrate 2 is located within the orthographic projection of the isolation opening 10 on the substrate 2.

[0046] The setting of the isolation structure 8 in this embodiment enables the display panel to form film layers of light-emitting units 12 of different colors in different isolation openings 10 without the need for a fine metal mask. When forming a light-emitting functional layer, the light-emitting functional layer will be separated by the isolation structure 8 to form a plurality of light-emitting portions 6 arranged at intervals. When forming a second electrode layer, the second electrode layer will be separated by the isolation structure 8 to form a plurality of second electrodes 7 arranged at intervals. The isolation structure 8 includes a conductive material. The second electrode 7 is electrically connected to the isolation structure 8. One first electrode 5, one light-emitting portion 6 and one second electrode 7 form one light-emitting unit 12.

[0047] In this way, different light-emitting units 12 can be made independent of each other, thereby improving the crosstalk between adjacent light-emitting units 12 and improving the display effect of the display panel. At the same time, due to the presence of the isolation structure 8, the light-emitting functional layer and the second electrode layer in the light-emitting unit 12 of each color in the display panel can be first prepared on the entire surface and then patterned, thereby eliminating the need for a fine metal mask, thereby saving the manufacturing cost of the display panel.

[0048] Preferably, see again Figure 5 A via 42 is provided on the pixel defining layer 4 and is located in the non-display area AB. The isolation structure 8 is electrically connected to the second power line 102 through the via 42. In this way, it is easier to electrically connect the second power line 102 to the isolation structure 8, thereby making it easier for the power signal of the second power line 102 to be transmitted to the second electrode 7 through the isolation structure 8.

[0049] Preferably, see again Figure 5 The display panel includes a first encapsulation layer 3 located on a side of the light-emitting unit 12 away from the substrate 2, the first encapsulation layer 3 includes a plurality of encapsulation units 91 arranged at intervals, at least some of the encapsulation units 91 extend from the side of the isolation structure 8 toward the isolation opening 10 to the side of the isolation structure 8 away from the substrate 2, the encapsulation units 91 are arranged at intervals on the side of the isolation structure 8 away from the substrate 2, there is a gap between the encapsulation units 91 located on the side of the isolation structure 8 away from the substrate 2 and the side of the isolation structure 8 away from the substrate 2, the orthographic projection of the encapsulation unit 91 on the substrate 2 covers the orthographic projection of the isolation opening 10 on the substrate 2 and covers part of the orthographic projection of the isolation structure 8 on the substrate 2.

[0050] During the patterning process of the light-emitting unit 12 , the first encapsulation layer 3 is disconnected at the isolation structure 8 to form an encapsulation unit 91 . The encapsulation unit 91 can completely and independently encapsulate the corresponding light-emitting unit 12 , thereby improving the display characteristics of the display panel.

[0051] In other embodiments, please refer again to Figure 3 , Figure 4 and Figure 7a-Figure 7b At least part of the planarization layer 11 and at least part of the pixel defining layer 4 of the display panel are both located in the display area AA, and the encapsulation layer 3 extends from the side of the power line 1 to the side of the power line 1 away from the substrate 2.

[0052] In this embodiment, different light-emitting units 12 share the second electrode 7, and the pixel defining layer 4 includes organic materials. Therefore, the pixel defining layer 4 does not extend to the side of the power line 1 in the non-display area AB. The encapsulation layer 3 extends from the side of the power line 1 to the side of the power line 1 away from the substrate 2. The encapsulation layer 3 can cover the side of the power line 1, thereby reducing the risk of water vapor invading the display area AA from the side of the power line 1.

[0053] Please see again Figure 7a and Figure 7b In this embodiment, the first encapsulation layer 9 continuously covers the second electrode 7 , and the first encapsulation layer 9 continuously covers different light-emitting units 12 .

[0054] Please see again Figure 7a The first encapsulation layer 3 may extend from the display area AA to the non-display area AB and cover the side surfaces of the first power wiring 101 and the second power wiring 102 located in the non-display area AB.

[0055] Please see again Figure 7b , the first encapsulation layer 3 does not extend from the display area AA to the non-display area AB.

[0056] For some possible implementations, see Figure 8 and Figure 9a to Figure 9b The display panel also includes a second encapsulation layer 13 located on the side of the first encapsulation layer 9 away from the substrate 2 and a third encapsulation layer 14 located on the side of the second encapsulation layer 13 away from the substrate 2. The materials of the first encapsulation layer 9 and the third encapsulation layer 14 both include inorganic materials, and the material of the second encapsulation layer 13 includes organic materials.

[0057] For example, the first encapsulation layer 9 and the third encapsulation layer 14 may be formed by chemical vapor deposition (CVD), and the second encapsulation layer 13 may be formed by inkjet printing (IJP). The second encapsulation layer 13 and the third encapsulation layer 14 may provide a better encapsulation effect on the light-emitting unit 12, thereby further improving the encapsulation quality of the display panel.

[0058] In one embodiment, see again Figure 6 and Figure 8 The encapsulation layer 3 includes a third encapsulation layer 14. When the third encapsulation layer 14 is formed, the third encapsulation layer 14 is extended to the non-display area AB to cover the side of the first power line 101 and the second power line 102. In this way, there is no need to separately prepare the encapsulation layer 3 located in the non-display area AB to cover the first power line 101 and the second power line 102, thereby reducing the cost of forming the encapsulation layer 3.

[0059] In another embodiment, please refer again to Figure 4 and Figure 9a-9b The encapsulation layer 3 includes a first encapsulation layer 9 and a third encapsulation layer 14 .

[0060] For details, please refer again to Figure 4 and Figure 9a The encapsulation layer 3 includes a first encapsulation layer 9. When the first encapsulation layer 9 is formed, the first encapsulation layer 9 is extended to the non-display area AB to cover the side of the first power line 101 and the second power line 102. In this way, there is no need to separately prepare the encapsulation layer 3 located in the non-display area AB to cover the first power line 101 and the second power line 102, thereby reducing the cost of forming the encapsulation layer 3.

[0061] Please see again Figure 4 and Figure 9b The encapsulation layer 3 includes a third encapsulation layer 14. When the third encapsulation layer 14 is formed, the third encapsulation layer 14 is extended to the non-display area AB to cover the side of the first power line 101 and the second power line 102. In this way, there is no need to separately prepare the encapsulation layer 3 located in the non-display area AB to cover the first power line 101 and the second power line 102, thereby reducing the cost of forming the encapsulation layer 3.

[0062] Please see again Figure 4 and Figure 9b The encapsulation layer 3 includes a first encapsulation layer 9 and a third encapsulation layer 14. When the first encapsulation layer 9 and the third encapsulation layer 14 are formed, the first encapsulation layer 9 and the third encapsulation layer 14 are extended to the non-display area AB to cover the side of the first power line 101 and the second power line 102. In this way, there is no need to separately prepare the encapsulation layer 3 located in the non-display area AB to cover the first power line 101 and the second power line 102, thereby reducing the cost of forming the encapsulation layer 3.

[0063] For some possible implementations, see again Figure 5 The isolation structure 8 includes a first isolation portion 81 and a second isolation portion 82 which are stacked in sequence in a direction away from the substrate 2 , and the orthographic projection of the side of the first isolation portion 81 away from the substrate 2 on the substrate 2 is located within the orthographic projection of the second isolation portion 82 on the substrate 2 .

[0064] Since the second isolation portion 82 is located on the side of the first isolation portion 81 away from the substrate, and the lateral width of the second isolation portion 82 is greater than the lateral width of the first isolation portion 81, the second isolation portion 82 disconnects the light-emitting functional layer and the second electrode layer at the isolation structure 8. In this way, the isolation structure 8 formed by the first isolation portion 81 and the second isolation portion 82 can make it easier to independently package each light-emitting unit 12, thereby improving the packaging yield of the display panel.

[0065] Preferably, the second electrode 7 is electrically connected to the first isolation portion 81; the first isolation portion 81 includes a conductive material, and the second electrode 7 corresponding to the light-emitting unit 12 extends from the pixel opening 41 to contact the side wall of the first isolation portion 81 to achieve electrical connection between the second electrode 7 corresponding to the light-emitting unit 12 and the first isolation portion 81.

[0066] Please see again Figure 8 The isolation structure 8 further includes a third isolation portion 83 located on a side of the first isolation portion 81 facing the substrate, and the second electrode 7 of the light-emitting unit 12 is electrically connected to the third isolation portion 83 .

[0067] The third isolation part 83 includes a conductive material, and the second electrode 7 corresponding to the light-emitting unit 12 extends from the pixel opening 41 to contact the side wall of the third isolation part 83, so as to realize the electrical connection between the second electrode 7 corresponding to the light-emitting unit 12 and the third isolation part 83. Specifically, the material of the third isolation part 83 includes molybdenum metal; and / or, the material of the first isolation part 81 includes aluminum metal; and / or, the material of the second isolation part 82 includes titanium metal. In this way, when the isolation structure 8 separates the second electrode layer into the second electrode 7, the second electrode 7 is more easily electrically connected to the first isolation part 81 and / or the third isolation part 83.

[0068] It should be noted that the second electrode 7 corresponding to the light-emitting unit 12 only needs to be electrically connected to the isolation structure 8 , and the contact position between the second electrode 7 and the isolation structure 8 is not specifically limited.

[0069] For some possible implementations, see Fig.10 and Fig.11 The present application also provides a method for preparing a display panel, the display panel comprising a display area AA and a non-display area AB surrounding at least a portion of the display area AA, the method comprising: S10: providing a substrate 2.

[0070] S11: A conductive layer is formed on one side of the substrate 2, the conductive layer including a first power line 101, a second power line 102, and a connecting line 15 connected between a side surface of the first power line 101 and a side surface of the second power line 102, at least a portion of the first power line 101, at least a portion of the second power line 102, and the connecting line 15 are located in the non-display area AB.

[0071] See also Fig.11 and Fig.12 A conductive layer is formed on one side of the substrate 2, and the conductive layer is the fourth conductive layer or the fifth conductive layer of the display panel. The connecting line 15 can connect the side surfaces of the first power line 101 and the second power line 102, thereby protecting the side surfaces of the first power line 101 and the second power line 102.

[0072] See also Fig.13 A planarization layer 11 is formed on a side of the conductive layer away from the substrate 2 , and the planarization layer 11 is located in the display area AA.

[0073] The planarization layer 11 does not extend to the first power line 101 and the second power line 102 in the non-display area AB. Since the connecting line 15 is connected to the sides of the first power line 101 and the second power line 102, the developer used to form the planarization layer 11 will not engrave the sides of the first power line 101 and the second power line 102.

[0074] See also Fig.14 A first electrode layer is formed on a side of the planarization layer 11 away from the substrate 2 , and the first electrode layer is patterned to form a plurality of first electrodes 5 that are spaced apart.

[0075] Since the connecting line 15 is connected to the side of the first power line 101 and the second power line 102, when the first electrode layer is patterned into a plurality of first electrodes 5 arranged at intervals, the etching solution for etching the first electrode layer will not perform side etching on the side of the first power line 101 and the second power line 102.

[0076] In some embodiments, see Fig.15 A pixel defining material layer 16 is formed on a side of the first electrode layer away from the substrate 2 , and the pixel defining material layer 16 includes a via 42 exposing at least a portion of the second power trace 102 .

[0077] See also Fig.16 The pixel defining layer 4 extends from the display area AA to the non-display area AB and covers the first power line 101 , the connecting line 15 and the second power line 102 in the non-display area AB.

[0078] See also Fig.17 and Fig.18 An isolation material layer 17 is formed on the side of the pixel defining material layer 16 away from the substrate 2, and the isolation material layer 17 and the pixel defining material layer 16 are patterned in turn to form an isolation structure 8 and a pixel defining layer 4, respectively. The isolation structure 8 encloses an isolation opening 10, and the pixel defining layer 4 includes a pixel opening 41 that exposes at least a portion of the first electrode 5. The pixel opening 41 is connected to the isolation opening 10, and the isolation structure 8 is electrically connected to the second power line 102 through a via 42.

[0079] Please see again Figure 5 A light-emitting unit 12 is formed in the isolation opening 10, and a first encapsulation layer 9 is formed in the display area AA on the side of the light-emitting unit 12 away from the substrate 2. The first encapsulation layer 9 includes an encapsulation unit 91, and at least part of the encapsulation unit 91 extends from the isolation structure 8 toward the side of the isolation opening 10 to the side of the isolation structure 8 away from the substrate 2.

[0080] See also Fig.19 A second encapsulation layer 13 is formed on a side of the first encapsulation layer 3 away from the substrate 2 and located in the display area AA, and the second encapsulation layer 13 does not extend to the power supply line 1 in the non-display area AB.

[0081] See also Fig. 20 , the pixel definition layer 4 between the first power line 101 and the second power line 102 is removed to expose the connection line 15 .

[0082] Before forming the third encapsulation layer 14 , a portion of the pixel definition layer 4 is removed to expose the connection wiring 15 , so as to facilitate the subsequent removal of the connection wiring 15 .

[0083] In other embodiments, see Fig.21 A pixel defining layer 4 is formed on a side of the first electrode layer away from the substrate 2 . The pixel defining layer 4 is located in the display area AA. The pixel defining layer 4 includes a pixel opening 41 that exposes at least a portion of the first electrode 5 .

[0084] See also Fig. 22 , a light emitting unit 12 is formed in the pixel opening 41 .

[0085] Please see again Figure 7a and Figure 7b , a first encapsulation layer 3 is formed on a side of the light emitting unit 12 away from the substrate 2 and located in the display area AA.

[0086] Please see again Figure 7a The first encapsulation layer 3 may extend from the display area AA to the non-display area AB and cover the side surfaces of the first power wiring 101 and the second power wiring 102 located in the non-display area AB.

[0087] Please see again Figure 7b , the first encapsulation layer 3 does not extend from the display area AA to the non-display area AB.

[0088] See also Fig.23a and Figure 23b A second encapsulation layer 13 is formed on a side of the first encapsulation layer 3 away from the substrate 2 and located in the display area AA, and the second encapsulation layer 13 does not extend to the power supply line 1 in the non-display area AB.

[0089] S12: Remove connecting trace 15.

[0090] See also Fig.24 and Fig.25 , the connection line 15 connected between the first power line 101 and the second power line 102 is removed. Specifically, the connection line 15 is removed by dry etching, so that it is not easy to etch the side surfaces of the first power line 101 and the second power line 102.

[0091] S13: forming an encapsulation layer 3 on a side of the conductive layer away from the substrate 2, wherein the encapsulation layer 3 extends from the display area AA to the non-display area AB and covers at least part of the side surfaces of the first power line 101 and the second power line 102 in the non-display area AB.

[0092] Please see again Figure 8 , Figure 9a-9b A third encapsulation layer 14 is formed on a side of the second encapsulation layer 13 away from the substrate 2 , and the third encapsulation layer 14 extends from the display area AA to the non-display area AB and covers the sides of the first power line 101 and the second power line 102 located in the non-display area AB.

[0093] When forming the third encapsulation layer 14, the third encapsulation layer 14 is extended to the non-display area AB to cover the side of the first power line 101 and the second power line 102. In this way, there is no need to separately prepare the encapsulation layer 3 located in the non-display area AB to cover the first power line 101 and the second power line 102, thereby reducing the cost of forming the encapsulation layer 3.

[0094] Since the connecting wire 15 connected between the first power wire 101 and the second power wire 102 is removed by dry etching before the third packaging layer 14 is formed, the side surfaces of the first power wire 101 and the second power wire 102 are not easily etched during the process of forming the display panel, and the third packaging layer 14 can more easily cover the side surfaces of the first power wire 101 and the second power wire 102. The third packaging layer 14 can more effectively package the side surfaces of the first power wire 101 and the second power wire 102, and external water vapor is not easy to enter the display area AA of the display panel from the side surfaces of the first power wire 101 and the second power wire 102, thereby not easily causing the display panel to fail.

[0095] In some possible implementations, the present application further provides an electronic device, the electronic device including the display panel in the present application, or including the display panel prepared by the method for preparing the display panel in the present application. The electronic device may include a device with image processing capabilities, such as a server, a personal computer, a laptop computer, etc. Since the electronic device includes the display panel in the present application, the packaging effect of the electronic device at the power supply line 1 is better, it is not easy to fail, and the display quality is better.

[0096] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0097] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A display panel, characterized in that: The display panel includes a display area and a non-display area surrounding at least a portion of the display area, and the display panel includes: substrate; A conductive layer, located on one side of the substrate, the conductive layer comprising power lines, at least part of which is located in the non-display area; The encapsulation layer is located on a side of the conductive layer away from the substrate, and the encapsulation layer extends from the display area to the non-display area and covers at least a portion of a side surface of the power supply wiring located in the non-display area.

2. The display panel according to claim 1, characterized in that: The display panel further comprises a planarization layer located on a side of the conductive layer away from the substrate, wherein at least a portion of the planarization layer is located in the display area; Preferably, the display panel further comprises a pixel defining layer located on a side of the planarization layer away from the substrate, the pixel defining layer is at least partially located in the non-display area, and the pixel defining layer located in the non-display area covers at least a portion of a side of the power wiring away from the substrate; Preferably, the encapsulation layer extends from a side of the power line through a side of the pixel defining layer to a side of the pixel defining layer located in the non-display area away from the substrate; Preferably, the encapsulation layer covers the side surface of the pixel defining layer located in the non-display area; Preferably, the encapsulation layer covers the side surface of the power wiring and the side surface of the pixel defining layer located in the non-display area; Preferably, the side surface of the pixel defining layer is at least partially flush with the side surface of the power wiring; Preferably, the pixel defining layer extends from the display area to the non-display area; Preferably, the material of the pixel defining layer includes an inorganic material.

3. The display panel according to claim 1, characterized in that: The display panel further comprises a planarization layer located on a side of the conductive layer away from the substrate, wherein at least a portion of the planarization layer is located in the display area; Preferably, the display panel further comprises a pixel defining layer located on a side of the planarization layer away from the substrate, and the pixel defining layer is at least partially located in the display area; Preferably, the encapsulation layer extends from a side of the power line to a side of the power line away from the substrate; Preferably, the material of the pixel defining layer is an organic material.

4. The display panel according to claim 1, characterized in that: The power supply line includes a first power supply line and a second power supply line, and the encapsulation layer covers the side surfaces of the first power supply line and the second power supply line located in the non-display area; Preferably, the encapsulation layer fills at least a portion of the gap between the first power line and the second power line; Preferably, the first power line and the second power line are arranged on the same layer; Preferably, the first power line and the second power line transmit different power signals; Preferably, the first power supply line comprises a power supply voltage line; Preferably, the second power supply line comprises a common ground voltage line.

5. The display panel according to claim 4, characterized in that: The display panel further comprises an isolation structure on one side of the conductive layer away from the substrate, wherein the isolation structure encloses and forms an isolation opening; Preferably, the display panel further comprises a pixel defining layer located on a side of the conductive layer away from the substrate, and the isolation structure is located on a side of the pixel defining layer away from the substrate; Preferably, the pixel defining layer is provided with a via hole located in the non-display area, and the isolation structure is electrically connected to the second power supply line through the via hole.

6. The display panel according to claim 5, characterized in that: The display panel further includes a light emitting unit at least partially located in the isolation opening, the light emitting unit including a first electrode, a light emitting portion, and a second electrode sequentially stacked in a direction away from the substrate; Preferably, the pixel defining layer comprises a pixel opening exposing at least a portion of the first electrode, and an orthographic projection of the pixel opening on the substrate is located within an orthographic projection of the isolation opening on the substrate.

7. The display panel according to claim 6, characterized in that: The display panel comprises a first encapsulation layer located on a side of the light emitting unit away from the substrate, the first encapsulation layer comprises a plurality of encapsulation units arranged at intervals, at least some of the encapsulation units extend from a side of the isolation structure toward the isolation opening to a side of the isolation structure away from the substrate; Preferably, the encapsulation unit is arranged at intervals on a side of the isolation structure away from the substrate; Preferably, there is a gap between the packaging unit located on a side of the isolation structure away from the substrate and a side of the isolation structure away from the substrate; Preferably, the orthographic projection of the encapsulation unit on the substrate covers the orthographic projection of the isolation opening on the substrate and covers a portion of the orthographic projection of the isolation structure on the substrate.

8. The display panel according to claim 7, characterized in that: The display panel further comprises a second encapsulation layer located on a side of the first encapsulation layer away from the substrate; Preferably, the display panel further comprises a third encapsulation layer located on a side of the second encapsulation layer away from the substrate; Preferably, the encapsulation layer includes the third encapsulation layer, or the encapsulation layer includes the first encapsulation layer and the third encapsulation layer; Preferably, the materials of the first encapsulation layer and the third encapsulation layer both include inorganic materials; Preferably, the material of the second encapsulation layer includes organic material.

9. The display panel according to claim 6, characterized in that: The isolation structure comprises a first isolation portion and a second isolation portion which are sequentially stacked in a direction away from the substrate, wherein an orthographic projection of a side of the first isolation portion away from the substrate on the substrate is located within an orthographic projection of the second isolation portion on the substrate; Preferably, the second electrode is electrically connected to the first isolation portion; and / or the isolation structure further comprises a third isolation portion located on a side of the first isolation portion facing the substrate, and the second electrode is electrically connected to the third isolation portion; Preferably, the material of the third isolation portion includes molybdenum metal; and / or the material of the first isolation portion includes aluminum metal; and / or the material of the second isolation portion includes titanium metal.

10. A method for preparing a display panel, characterized in that: The display panel includes a display area and a non-display area surrounding at least a portion of the display area, and the method includes: providing a substrate; A conductive layer is formed on one side of the substrate, the conductive layer comprising a first power line, a second power line, and a connecting line connected between a side surface of the first power line and a side surface of the second power line, and at least a portion of the first power line, at least a portion of the second power line, and the connecting line are all located in the non-display area; removing the connecting wiring; An encapsulation layer is formed on a side of the conductive layer away from the substrate, wherein the encapsulation layer extends from the display area to the non-display area and covers at least a portion of side surfaces of the first power wiring and the second power wiring located in the non-display area.

11. The method for preparing a display panel according to claim 10, characterized in that: Before the step of removing the connecting wiring, the method further includes: forming a planarization layer on a side of the conductive layer away from the substrate, wherein the planarization layer is located in the display area; A first electrode layer is formed on a side of the planarization layer away from the substrate, and the electrode layer is patterned to form a plurality of first electrodes that are spaced apart.

12. The method for preparing a display panel according to claim 11, characterized in that: After the step of forming a first electrode layer on a side of the planarization layer away from the substrate and patterning the first electrode layer, the method further includes: forming a pixel defining material layer on a side of the first electrode layer away from the substrate, wherein the pixel defining material layer includes a via hole exposing at least a portion of the second power supply line; forming an isolation material layer on a side of the pixel defining material layer away from the substrate, and patterning the isolation material layer and the pixel defining material layer in sequence to form an isolation structure and a pixel defining layer respectively, wherein the isolation structure encloses an isolation opening, the pixel defining layer includes a pixel opening exposing at least a portion of the first electrode, the pixel opening is connected to the isolation opening, and the isolation structure is electrically connected to the second power supply line through the via hole; A light emitting unit is formed in the isolation opening, and a first encapsulation layer is formed in the display area on a side of the light emitting unit away from the substrate, wherein the first encapsulation layer includes an encapsulation unit, and at least a part of the encapsulation unit extends from a side of the isolation structure toward the isolation opening to a side of the isolation structure away from the substrate; forming a second encapsulation layer located in the display area on a side of the first encapsulation layer away from the substrate; The pixel definition layer between the first power line and the second power line is removed to expose the connection line.

13. The method for preparing a display panel according to claim 11, characterized in that: After the step of forming a first electrode layer on a side of the planarization layer away from the substrate and patterning the first electrode layer, the method further includes: forming a pixel defining layer on a side of the first electrode layer away from the substrate, the pixel defining layer being located in the display area, and the pixel defining layer comprising a pixel opening exposing at least a portion of the first electrode; forming a light emitting unit in the pixel opening; forming a first encapsulation layer located in the display area on a side of the light emitting unit away from the substrate; A second encapsulation layer located in the display area is formed on a side of the first encapsulation layer away from the substrate.

14. The method for preparing a display panel according to claim 12 or 13, characterized in that: The step of forming a packaging layer on a side of the conductive layer away from the substrate comprises: forming a third encapsulation layer on a side of the second encapsulation layer away from the substrate, wherein the third encapsulation layer extends from the display area to the non-display area and covers the side surfaces of the first power line and the second power line located in the non-display area; Preferably, the step of removing the connecting wiring includes: The connecting traces are removed by dry etching.

15. An electronic device, characterized in that: The electronic device comprises the display panel according to any one of claims 1 to 9, or comprises a display panel prepared by the method for preparing a display panel according to any one of claims 10 to 14.

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