Display panel, preparation method of display panel and electronic equipment

Abstract

The embodiment of the invention provides a display panel, a preparation method of the display panel and electronic equipment, and relates to the technical field of display, the display panel comprises a display area, the display panel comprises a substrate, an array layer, a light-emitting unit and an isolation structure, the array layer is located on one side of the substrate, the array layer comprises a gate driving unit, and the isolation structure is located on one side of the substrate. At least part of the gate driving units are located in the display area; the isolation structure is located on the side, away from the substrate, of the array layer, and an isolation opening is defined by the isolation structure; the light-emitting units are located in the isolation openings, and orthographic projections of part of the light-emitting units on the substrate are overlapped with orthographic projections of the gate driving units on the substrate. According to the display panel, at least part of the gate driving units are arranged in the display area, so that the frame width of the display panel can be reduced, and the narrow-frame or frameless display panel can be formed.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular, to a display panel, a method for preparing a display panel, and an electronic device. Background Art

[0002] Organic Light Emitting Diode (OLED) and flat-panel display devices based on technologies such as Light Emitting Diode (LED) have the advantages of high image quality, power saving, thin body and wide application range, and are widely used in various consumer electronic products such as mobile phones, televisions, laptops, desktop computers, etc., becoming the mainstream in display panels. In the preparation process of traditional display panels, the graphicization of luminous pixels is usually achieved through a fine metal mask (FMM). FMM technology is mature and has rich experience in mass production. However, FMM technology also has problems such as limited accuracy, high development cost, and long development cycle. The non-fine metal mask technology eliminates the limitations of traditional OLED processes on display screen size, resolution and other screen performance, and has the advantages of high performance, full-domain size, and agile delivery. Patents CN118251982A, CN116648095A, CN117062489A, CN118742138A, CN118678783A, CN118660598A, CN118675450A, CN118824188A, and CN118781966A record relevant contents of the non-fine metal mask technology for reference.

[0003] However, there are still some problems with display panels that need to be solved urgently. Summary of the invention

[0004] In order to overcome the technical problems mentioned in the above technical background, an embodiment of the present application provides a display panel, wherein the display panel includes a display area, and the display panel includes:

[0005] substrate;

[0006] An array layer, located at one side of the substrate, the array layer comprising a gate driving unit, at least part of the gate driving unit is located in the display area;

[0007] An isolation structure, located at a side of the array layer away from the substrate, the isolation structure encloses an isolation opening;

[0008] The light-emitting unit is located in the isolation opening, and the orthographic projection of a part of the light-emitting unit on the substrate overlaps with the orthographic projection of the gate driving unit on the substrate.

[0009] In some possible implementations, the gate driving unit includes a plurality of shift registers, and the plurality of shift registers are arranged along a first direction;

[0010] The orthographic projection of the display area on the substrate includes a first edge and a second edge that are oppositely arranged, the first edge and the second edge extend along a second direction, the first edge and the second edge are arranged along the first direction, the gate driving unit extends from the first edge to the second edge, and the first direction and the second direction intersect; the orthographic projection of the display area on the substrate also includes a third edge and a fourth edge that are oppositely arranged, the third edge and the fourth edge extend along the first direction, and the third edge and the fourth edge are arranged along the second direction;

[0011] Preferably, the orthographic projection of the gate driving unit on the substrate is located at a middle position between the third edge and the fourth edge;

[0012] Preferably, the first direction is perpendicular to the second direction.

[0013] In some possible implementations, the array layer includes a plurality of pixel circuits, the light-emitting unit includes a first electrode, a light-emitting portion, and a second electrode sequentially stacked in a direction away from the substrate, and the pixel circuit is electrically connected to the first electrode; the orthographic projection of the gate driving unit on the substrate is located outside the orthographic projection of the pixel circuit on the substrate;

[0014] Preferably, the orthographic projections of the plurality of pixel circuits on the substrate are located on both sides of the orthographic projection of the gate driving unit on the substrate.

[0015] In some possible implementations, the array layer includes a plurality of pixel circuits, a portion of the display area located between the gate driving unit and the third edge includes a first region and a second region, the second region is located between the first region and the third edge, and a ratio of a density of pixel circuits located in the first region to a density of pixel circuits located in the second region is greater than or equal to 1; and / or

[0016] The portion of the display area located between the gate driving unit and the fourth edge includes a third area and a fourth area, the fourth area is located between the third area and the fourth edge, and a ratio of a density of pixel circuits located in the third area to a density of pixel circuits located in the fourth area is greater than or equal to 1;

[0017] Preferably, the third edge is connected to both the first edge and the second edge;

[0018] Preferably, the fourth edge is connected to both the first edge and the second edge.

[0019] In some possible implementations, the array layer further includes a first insulating layer, a first conductive layer, and a second insulating layer which are sequentially stacked and located on a side of the pixel circuit away from the substrate, the first electrode is located on a side of the second insulating layer away from the substrate, the first conductive layer includes a plurality of first conductive traces which are spaced apart, and the pixel circuit and the corresponding first electrode are electrically connected via the first conductive traces;

[0020] Preferably, the first insulating layer is provided with a first via hole penetrating the first insulating layer, the second insulating layer is provided with a second via hole penetrating the second insulating layer, the first conductive trace is electrically connected to the pixel circuit through the first via hole, and the first electrode is electrically connected to the first conductive trace through the second via hole.

[0021] In some possible implementations, the array layer further includes a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, and a third insulating layer which are stacked in sequence and located on a side of the pixel circuit away from the substrate, the first electrode is located on a side of the third insulating layer away from the substrate, the second conductive layer includes a plurality of second conductive traces arranged at intervals, and the pixel circuit and the corresponding first electrode are electrically connected via one of the second conductive traces;

[0022] Preferably, the material of the second conductive trace comprises indium tin oxide.

[0023] In some possible embodiments, the array layer also includes a semiconductor layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer which are stacked in sequence along a direction away from the substrate and located on one side of the substrate, and the first conductive layer is located on a side of the fifth conductive layer away from the substrate.

[0024] In some possible implementations, the display panel further includes a power line, the power line extends to the display area, the power line is located between the gate driving unit and the isolation structure, the orthographic projection of the power line on the substrate overlaps with the orthographic projection of the gate driving unit on the substrate, and the power line is electrically connected to the isolation structure;

[0025] Preferably, the portion of the power supply line extending to the display area is in a strip shape and extends along the first direction;

[0026] Preferably, the orthographic projection of the portion of the power supply line extending to the display area on the substrate is located at a middle position between the third edge and the fourth edge.

[0027] In some possible implementations, the display panel further includes a third insulating layer and a pixel defining layer which are sequentially stacked between the power wiring and the isolation structure, the third insulating layer is provided with a fourth via hole penetrating the third insulating layer, the fourth via hole exposes a portion of the power wiring, the pixel defining layer is provided with a fifth via hole penetrating the pixel defining layer and a pixel opening, the isolation structure is electrically connected to the power wiring through the fifth via hole and the fourth via hole in sequence, and the pixel opening is connected to the isolation opening;

[0028] Preferably, the array layer comprises a plurality of conductive layers stacked in sequence along a side away from the substrate, and the power supply line is located in a conductive layer of the plurality of conductive layers that is closest to the isolation structure;

[0029] Preferably, a center of an orthographic projection of the fifth via hole on the substrate coincides with a center of an orthographic projection of the fourth via hole on the substrate.

[0030] In some possible implementations, the display panel further includes a first encapsulation layer located on a side of the light-emitting unit away from the substrate, the first encapsulation layer including a plurality of encapsulation units arranged at intervals, and at least a portion of the encapsulation unit extends from a side of the isolation structure toward the isolation opening to a side of the isolation structure away from the substrate;

[0031] Preferably, the encapsulation unit is arranged at intervals on a side of the isolation structure away from the substrate;

[0032] Preferably, there is a gap between the packaging unit located on a side of the isolation structure away from the substrate and a side of the isolation structure away from the substrate;

[0033] Preferably, the display panel further comprises a second encapsulation layer located on a side of the first encapsulation layer away from the substrate and a third encapsulation layer located on a side of the second encapsulation layer away from the substrate;

[0034] Preferably, the materials of the first encapsulation layer and the third encapsulation layer both include inorganic materials;

[0035] Preferably, the material of the second encapsulation layer includes organic material.

[0036] In some possible implementations, the isolation structure includes a first isolation portion and a second isolation portion which are sequentially stacked in a direction away from the substrate, and an orthographic projection of a side of the first isolation portion away from the substrate on the substrate is located within an orthographic projection of the second isolation portion on the substrate;

[0037] Preferably, the second electrode of the light-emitting unit is electrically connected to the first isolation portion; and / or the isolation structure further comprises a third isolation portion located on a side of the first isolation portion facing the substrate, and the second electrode of the light-emitting unit is electrically connected to the third isolation portion;

[0038] Preferably, the material of the third isolation portion includes molybdenum; and / or the material of the first isolation portion includes aluminum; and / or the material of the second isolation portion includes titanium.

[0039] In some possible implementations, the present application further provides a display panel, the display panel including a display area, the display panel including:

[0040] substrate;

[0041] An array layer, located at one side of the substrate, the array layer comprising a gate driving unit, at least part of the gate driving unit is located in the display area;

[0042] The light-emitting unit, a part of which has an orthographic projection on the substrate overlapped with an orthographic projection of the gate driving unit on the substrate.

[0043] In some possible implementations, the array layer includes a plurality of pixel circuits, the light-emitting unit includes a first electrode, a light-emitting portion, and a second electrode sequentially stacked in a direction away from the substrate, and the pixel circuit is electrically connected to the first electrode; the orthographic projection of the gate driving unit on the substrate is located outside the orthographic projection of the pixel circuit on the substrate;

[0044] Preferably, the orthographic projections of the plurality of pixel circuits on the substrate are located on both sides of the orthographic projection of the gate driving unit on the substrate.

[0045] In some possible implementations, the gate driving unit includes a plurality of shift registers, and the plurality of shift registers are arranged along a first direction;

[0046] The orthographic projection of the display area on the substrate includes a first edge and a second edge that are oppositely arranged, the first edge and the second edge extend along a second direction, the first edge and the second edge are arranged along the first direction, the gate driving unit extends from the first edge to the second edge, and the first direction and the second direction intersect; the orthographic projection of the display area on the substrate also includes a third edge and a fourth edge that are oppositely arranged, the third edge and the fourth edge extend along the first direction, and the third edge and the fourth edge are arranged along the second direction;

[0047] Preferably, the portion of the display area located between the gate driving unit and the third edge includes a first area and a second area, the second area is located between the first area and the third edge, and a ratio of a density of pixel circuits located in the first area to a density of pixel circuits located in the second area is greater than or equal to 1; and / or

[0048] The portion of the display area located between the gate driving unit and the fourth edge includes a third area and a fourth area, the fourth area is located between the third area and the fourth edge, and a ratio of a density of pixel circuits located in the third area to a density of pixel circuits located in the fourth area is greater than or equal to 1;

[0049] Preferably, an orthographic projection of the gate driving unit on the substrate is located at a middle position between the third edge and the fourth edge.

[0050] In some possible implementations, the present application further provides an electronic device, which includes the display panel described in the present application.

[0051] Compared with the prior art, this application has the following beneficial effects:

[0052] The present application provides a display panel, a method for manufacturing a display panel, and an electronic device. By disposing at least part of a gate driving unit in a display area, the border width of the display panel can be reduced, thereby facilitating the formation of a display panel with a narrow border or no border. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0054] Figure 1 This is one of the top view schematic diagrams of the display panel provided in the embodiment of the present application;

[0055] Figure 2 Provided in the embodiments of this application Figure 1 Schematic cross-sectional view at AA in the middle;

[0056] Figure 3 A second schematic top view of a display panel provided in an embodiment of the present application;

[0057] Figure 4 A third schematic top view of a display panel provided in an embodiment of the present application;

[0058] Figure 5 Provided in the embodiments of this application Figure 4 One of the cross-sectional views at the middle BB;

[0059] Figure 6 Provided in the embodiments of this application Figure 4 The second cross-sectional view of the middle BB;

[0060] Figure 7 Provided in the embodiments of this application Figure 4 The third cross-sectional view of the middle BB;

[0061] Figure 8 Provided in the embodiments of this application Figure 4 The fourth cross-sectional view of the middle BB;

[0062] Fig. 9 A fourth schematic top view of a display panel provided in an embodiment of the present application;

[0063] Fig.10 Provided in the embodiments of this application Fig. 9 One of the cross-sectional views at CC in the middle;

[0064] Fig.11 Provided in the embodiments of this application Figure 4 The fifth cross-sectional view of the middle BB;

[0065] Fig.12 Provided in the embodiments of this application Fig. 9 The second cross-sectional view at CC in the middle;

[0066] Fig.13a Provided in the embodiments of this application Fig. 9 The third cross-sectional view of the CC in the middle;

[0067] Fig.13b Provided in the embodiments of this application Figure 4 The fifth cross-sectional view of the middle BB;

[0068] Fig.14 A schematic diagram of a process for preparing a display panel provided in an embodiment of the present application;

[0069] Fig.15 A cross-sectional view showing a pixel circuit and a gate driving unit formed on one side of a substrate provided in an embodiment of the present application;

[0070] Fig.16 A cross-sectional view of forming a first insulating layer on a side of a pixel circuit and a gate driving unit away from a substrate provided in an embodiment of the present application;

[0071] Fig.17A cross-sectional schematic diagram of forming a first conductive layer on a side of the first insulating layer away from the substrate provided in an embodiment of the present application;

[0072] Fig.18 A cross-sectional schematic diagram of forming a second insulating layer on a side of the first conductive layer away from the substrate provided in an embodiment of the present application;

[0073] Fig.19 A cross-sectional view of forming a second conductive layer on a side of the second insulating layer away from the substrate provided in an embodiment of the present application;

[0074] Fig. 20 A cross-sectional view of forming a third insulating layer on a side of the second conductive layer away from the substrate provided in an embodiment of the present application;

[0075] Fig.21 A cross-sectional view of forming a first electrode layer on a side of a third insulating layer away from a substrate provided in an embodiment of the present application;

[0076] Fig. 22 A cross-sectional view of forming a pixel defining material layer on a side of the first electrode layer away from the substrate provided in an embodiment of the present application;

[0077] Fig.23 The cross-sectional intention of forming an isolation material layer on a side of the pixel defining material layer away from the substrate provided in the embodiment of the present application;

[0078] Fig.24 The cross-sectional view after the isolation material layer and the pixel defining material are patterned in sequence is provided in the embodiment of the present application.

[0079] Figure numerals: 1, substrate; 2, array layer; 3, gate drive unit; 4, light-emitting unit; 5, isolation structure; 51, first isolation portion; 52, second isolation portion; 53, third isolation portion; 6, isolation opening; 7, first insulating layer; 71, first via hole; 8, second insulating layer; 81, second via hole; 9, pixel defining layer; 91, pixel opening; 92, fifth via hole; 10, pixel circuit; 11, first conductive trace; 12, first electrode; 13, light-emitting part; 14, second electrode; 15, scanning line; 16, first edge; 17, second edge; 18, third edge; 19, fourth edge; 20, second conductive trace; 21, third insulating layer; 211, third via; 212, fourth via; 22, semiconductor layer; 23, drain; 24, source; 25, power trace; 26, packaging unit; 27, second packaging layer; 28, third packaging layer; 29, pixel defining material layer; 30, isolation material layer. DETAILED DESCRIPTION

[0080] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0081] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0082] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0083] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "vertical", "horizontal", "inner", "outer", etc. indicate positions or positional relationships based on the drawings, or are the positions or positional relationships in which the invented product is usually placed when in use. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0084] It should be noted that, in the absence of conflict, different features in the embodiments of the present application may be combined with each other.

[0085] Improving the density of light-emitting units in a display panel (i.e., pixel density) is an important way to improve display effects. However, the display panels currently made using fine metal mask (FMM) technology are unable to further increase the density of light-emitting units due to technical limitations. The inventors have found through long-term research that in order to solve the technical problem that the density of light-emitting units cannot be further increased, an isolation structure is provided in some display panels. When the light-emitting functional layer and the second electrode are evaporated in the entire layer, the light-emitting functional layer and the second electrode can be disconnected at the isolation structure. Through multiple evaporation and multiple etching processes (i.e., light-emitting unit patterning), light-emitting units of different colors can be formed in different isolation openings.

[0086] The display panel in the related art includes a display area and a non-display area. The display panel includes a gate drive unit (Gate drive in Panel, GIP) and a light-emitting unit. The light-emitting unit is located in the display area, and the gate drive unit is located in the non-display area. Specifically, the gate drive unit is located at the frame position of the display panel, and the gate drive unit is electrically connected to the gate line of the light-emitting unit to provide a scanning signal to the light-emitting unit.

[0087] However, the gate driving unit is relatively large in size and occupies a relatively large space of the frame, so it is not easy to reduce the frame width of the display panel, which is not conducive to forming a display panel with a narrow frame or no frame.

[0088] In order to solve the above-mentioned technical problems, the inventor innovatively designed the following technical solutions, and the specific implementation solutions of the present application will be described in detail below in conjunction with the accompanying drawings. It should be noted that the defects existing in the solutions in the above-mentioned prior art are the results obtained by the inventor after practice and careful research. Therefore, the discovery process of the above-mentioned technical problems and the solutions proposed in this embodiment below for the above-mentioned problems should all be the contributions made by the inventor to the present application in the process of invention and creation, and should not be understood as the technical content known to those skilled in the art.

[0089] See also Figure 1-Figure 2 This embodiment provides a display panel, which includes a display area AA. The display panel includes a substrate 1, an array layer 2, an isolation structure 5 and a light-emitting unit 4.

[0090] The array layer 2 is located on one side of the substrate 1 . The array layer 2 includes a gate driving unit 3 . At least a portion of the gate driving unit 3 is located in the display area AA.

[0091] The isolation structure 5 is located at a side of the array layer 2 away from the substrate 1 , and the isolation structure 5 encloses an isolation opening 6 .

[0092] At least part of the light emitting unit 4 is located in the isolation opening 6 , and the orthographic projection of part of the light emitting unit 4 on the substrate 1 overlaps with the orthographic projection of the gate driving unit 3 on the substrate 1 .

[0093] In the present embodiment, the gate driving unit 3 is disposed in the array layer 2, and the gate driving unit 3 is disposed in the display area AA of the display panel. Thus, the gate driving unit 3 does not need to be disposed at the border position of the display panel, and will not occupy the space at the border of the display panel, thereby reducing the border size of the display panel, which is more conducive to forming a display panel with a narrow border or no border.

[0094] Since the orthographic projection of part of the light emitting unit 4 on the substrate 1 overlaps with the orthographic projection of the gate driving unit 3 on the substrate 1, the part of the gate driving unit 3 away from the substrate 1 can be displayed normally, thereby not affecting the display effect of the display panel.

[0095] Based on the above design, this embodiment arranges at least part of the gate driving unit 3 in the display area AA, so as to reduce the border width of the display panel, thereby facilitating the formation of a display panel with a narrow border or no border.

[0096] For some possible implementations, see Figure 3 , the gate driving unit 3 extends along the first direction Y, the orthographic projection of the display area AA on the substrate 1 includes a first edge 16 and a second edge 17 that are oppositely arranged, the first edge 16 and the second edge 17 extend along the second direction X, the first edge 16 and the second edge 17 are arranged along the first direction Y, the gate driving unit 3 extends from the first edge 16 to the second edge 17, the orthographic projection of the display area AA on the substrate 1 also includes a third edge 18 and a fourth edge 19 that are oppositely arranged, the third edge 18 and the fourth edge 19 extend along the first direction Y, the third edge 18 and the fourth edge 19 are arranged along the second direction X, and the first direction Y and the second direction X intersect.

[0097] Optionally, the array layer 2 further includes a scan line 15 , and the first direction Y includes an extension direction of the scan line 15 in the display area AA.

[0098] Optionally, the gate driving unit 3 includes a plurality of shift registers, which are arranged along the first direction Y, and the shift registers are electrically connected to the gate via the scanning line 15 .

[0099] Optionally, the first direction Y is perpendicular to the second direction X.

[0100] In this way, the gate driving unit 3 can better provide scanning signals to the light emitting units 4 in different rows through the scanning lines 15 .

[0101] Preferably, the orthographic projection of the gate driving unit 3 on the substrate 1 is located in the middle of the third edge 18 and the fourth edge 19. In this way, the gate driving unit 3 can further and better provide scanning signals for the light emitting units 4 of different rows through the scanning lines 15.

[0102] For some possible implementations, see Figure 4 and Figure 5 The array layer 2 includes a plurality of pixel circuits 10, the light-emitting unit 4 includes a first electrode 12, a light-emitting portion 13, and a second electrode 14 which are sequentially stacked in a direction away from the substrate 1, the pixel circuit 10 is electrically connected to the first electrode 12, and the orthographic projection of the gate driving unit 3 on the substrate 1 is located outside the orthographic projection of the pixel circuit 10 on the substrate 1.

[0103] Preferably, the orthographic projections of the plurality of pixel circuits 10 on the substrate 1 are located on both sides of the orthographic projection of the gate driving unit 3 on the substrate 1. In this way, it is easier to arrange the pixel circuits 10 whose orthographic projections are located in the gate driving unit 3, which is more conducive to the normal display of the display panel.

[0104] For some possible implementations, see again Figure 3 , the portion of the display area AA located between the gate driving unit 3 and the third edge 18 includes a first area AA1 and a second area AA2, the second area AA2 is located between the first area AA1 and the third edge 18, and the ratio of the density of the pixel circuits 10 located in the first area AA1 to the density of the pixel circuits 10 located in the second area AA2 is greater than or equal to 1; and / or, the portion of the display area AA located between the gate driving unit 3 and the fourth edge 19 includes a third area AA3 and a fourth area AA4, the fourth area AA4 is located between the third area AA3 and the fourth edge 19, and the ratio of the density of the pixel circuits 10 located in the third area AA3 to the density of the pixel circuits 10 located in the fourth area AA4 is greater than or equal to 1.

[0105] Optionally, the third edge 18 is connected to both the first edge 16 and the second edge 17 , and the fourth edge 19 is connected to both the first edge 16 and the second edge 17 .

[0106] In some embodiments, please refer again to Figure 3 The ratio of the density of the pixel circuits 10 located in the first area AA1 to the density of the pixel circuits 10 located in the second area AA2 is equal to 1, and the ratio of the density of the pixel circuits 10 located in the third area AA3 to the density of the pixel circuits 10 located in the fourth area AA4 is equal to 1.

[0107] The gate driving unit 3 will occupy part of the space of the pixel circuit 10 of the light emitting unit 4. In this embodiment, the pixel circuit 10 of the light emitting unit 4 is moved in sequence from the gate driving unit 3 to the third edge 18 and from the gate driving unit 3 to the fourth edge 19. The moved pixel circuit 10 is still located in the display area AA. In this way, the space occupied by the gate driving unit 3 can be compensated, and the pixel densities located in the first area AA1, the second area AA2, the third area AA3 and the fourth area AA4 are the same.

[0108] In other embodiments, please refer again to Figure 4 The ratio of the density of the pixel circuits 10 located in the first area AA1 to the density of the pixel circuits 10 located in the second area AA2 is greater than 1, and the ratio of the density of the pixel circuits 10 located in the third area AA3 to the density of the pixel circuits 10 located in the fourth area AA4 is greater than 1.

[0109] The gate driving unit 3 will occupy part of the space of the pixel circuit 10 of the light emitting unit 4. In this embodiment, the density of the pixel circuit 10 located in the first area AA1 is greater than the density of the pixel circuit 10 located in the second area AA2, and the density of the pixel circuit 10 located in the third area AA3 is greater than the density of the pixel circuit 10 located in the fourth area AA4, that is, the space occupied by the pixel circuits 10 located in the first area AA1 and the third area AA3 is compressed. For example, six pixel circuits 10 are arranged on the space occupied by five pixel circuits 10 in the related art, while the density of the pixel circuits 10 located in the second area AA2 and the fourth area AA4 remains unchanged, that is, the same as the related art, so that the space occupied by the gate driving unit 3 can be compensated.

[0110] Two methods of electrically connecting the pixel circuit 10 to the first electrode 12 are described below.

[0111] In some embodiments, see Figure 4 and Figure 5 The array layer 2 includes a first insulating layer 7, a first conductive layer, and a second insulating layer 8 which are stacked in sequence on a side of the pixel circuit 10 away from the substrate 1. The first electrode 12 is located on a side of the second insulating layer 8 away from the substrate 1. The first conductive layer includes a plurality of first conductive traces 11 which are spaced apart. The pixel circuit 10 and the corresponding first electrode 12 are electrically connected via the first conductive traces 11.

[0112] Optionally, a first via 71 penetrating the first insulating layer 7 is provided on the first insulating layer 7, a second via 81 penetrating the second insulating layer 8 is provided on the second insulating layer 8, the first conductive trace 11 is electrically connected to the pixel circuit 10 through the first via 71, and the first electrode 12 is electrically connected to the first conductive trace 11 through the second via 81.

[0113] In this embodiment, the pixel circuit 10 is electrically connected to the first electrode 12 via a first conductive trace 11 .

[0114] In other embodiments, see Figure 4 and Figure 6 The array layer 2 includes a first insulating layer 7, a first conductive layer, a second insulating layer 8, a second conductive layer and a third insulating layer 21 which are stacked in sequence and located on a side of the pixel circuit 10 away from the substrate 1. The first electrode 12 is located on a side of the third insulating layer 21 away from the substrate 1. The second conductive layer includes a plurality of second conductive traces 20 which are arranged at intervals. The pixel circuit 10 and the corresponding first electrode 12 are electrically connected through the second conductive traces 20.

[0115] Optionally, the first insulating layer 7 is provided with a first via 71 passing through the first insulating layer 7, the second insulating layer 8 is provided with a second via 81 passing through the second insulating layer 8, the third insulating layer 21 is provided with a third via 211 passing through the third insulating layer 21, the first conductive layer includes a plurality of first conductive traces 11 arranged at intervals, the first conductive trace 11 is electrically connected to the pixel circuit 10 through the first via 71, the second conductive trace 20 is electrically connected to the first conductive trace 11 through the second via 81, and the first electrode 12 is electrically connected to the second conductive trace 20 through the third via 211.

[0116] In this embodiment, the pixel circuit 10 is electrically connected to the first electrode 12 via the first conductive trace 11 and the second conductive trace 20 , wherein the material of the second conductive trace 20 includes indium tin oxide (ITO).

[0117] For some possible implementations, see Figure 4 , Figure 7 and Figure 8 The array layer 2 also includes a semiconductor layer 22, a third conductive layer, a fourth conductive layer and a fifth conductive layer, which are stacked in sequence along a direction away from the substrate 1 and located on one side of the substrate 1. The first conductive layer is located on a side of the fifth conductive layer away from the substrate 1.

[0118] Preferably, the third conductive layer includes a gate, the fifth conductive layer includes a source 24 and a drain 23, both the source 24 and the drain 23 are electrically connected to the semiconductor layer 22, the pixel circuit 10 includes a transistor, the transistor includes a source 24, a drain 23 and a gate, and the first conductive trace 11 is electrically connected to the drain 23 through a first via 71.

[0119] The semiconductor layer 22 includes a source region, a drain region and a channel region, the third conductive layer includes a gate and a first capacitor plate, the fourth conductive layer includes a second capacitor plate, the first capacitor plate and the second capacitor plate form a capacitor, the fifth conductive layer includes a drain 23 and a source 24, the drain 23 is electrically connected to the drain region, the source 24 is electrically connected to the source region, and the gate, the source 24 and the drain 23 form a transistor. In this way, the signal of the transistor can be transmitted to the first electrode 12 through the first conductive trace 11, or the signal of the transistor can be transmitted to the first electrode 12 through the first conductive trace 11 and the second conductive trace 20 to light up the corresponding light-emitting unit 4.

[0120] For some possible implementations, see Fig. 9 and Fig.10The display panel also includes a power line 25, which extends to the display area AA. The power line 25 is located between the gate driving unit 3 and the isolation structure 5. The orthographic projection of the power line 25 on the substrate 1 overlaps with the orthographic projection of the gate driving unit 3 on the substrate 1, and the power line 25 is electrically connected to the isolation structure 5.

[0121] The power line 25 in the related art is located at the border of the display panel. In this embodiment, the power line 25 is extended to the display area AA and electrically connected to the isolation structure 5 of the display area AA. In this way, the distance of the electrical connection between the power line 25 and the isolation structure 5 can be reduced, thereby reducing the power supply voltage drop provided to the second electrode 14, and further improving the display effect of the light-emitting unit 4.

[0122] Preferably, the portion of the power trace 25 extending to the display area AA is in a strip shape and extends along the first direction.

[0123] Optionally, the orthographic projection of the portion of the power supply line 25 extending to the display area AA on the substrate 1 is located at a middle position between the third edge 18 and the fourth edge 19 .

[0124] The power line 25 extends from the first edge 16 to the second edge 17, and the orthographic projection of the power line 25 on the substrate 1 at least partially overlaps with the orthographic projection of the gate driving unit 3 on the substrate 1. In this way, the electrical connection distance between the power line 25 and the isolation structure 5 can be further reduced.

[0125] Preferably, the orthographic projection of the power supply wiring 25 on the substrate 1 is located within the orthographic projection of the gate driving unit 3 on the substrate 1 .

[0126] In this way, on the one hand, the space utilization of the display panel can be improved, and on the other hand, the power line 25 is not likely to affect the light transmittance of the display panel.

[0127] Optionally, the material of the power line 25 includes indium tin oxide, which is a light-transmitting material. In this way, the light shielding amount of the power line 25 can be further reduced, and the light transmittance of the display panel can be improved.

[0128] In some possible embodiments, the third insulating layer 21 is provided with a fourth via 212 passing through the third insulating layer 21, the fourth via 212 exposes a portion of the power line 25, the pixel defining layer 9 is provided with a fifth via 92 passing through the pixel defining layer 9, and the isolation structure 5 is electrically connected to the power line 25 through the fifth via 92 and the fourth via 212 in sequence.

[0129] The center of the orthographic projection of the fifth via 92 on the substrate 1 coincides with the center of the orthographic projection of the fourth via 212 on the substrate 1, and the fifth via 92 and the fourth via 212 are interconnected. When the isolation structure 5 is formed, the material of the isolation structure 5 will electrically contact the power line 25 along the fifth via 92 and the fourth via 212 in sequence, thereby making it easier to electrically connect the power line 25 and the isolation structure 5 in the display area AA.

[0130] Preferably, the array layer 2 includes a plurality of conductive layers stacked in sequence along a side away from the substrate 1 , and the power supply trace 25 is located in a conductive layer of the plurality of conductive layers that is closest to the isolation structure 5 .

[0131] In this embodiment, the power supply line 25 is located in the second conductive layer, and is located in the same conductive layer as the second conductive line 20 . This makes it easier to electrically connect the power supply line 25 to the isolation structure 5 .

[0132] For some possible implementations, see Figure 11-Figure 12 The display panel also includes a first encapsulation layer located on the side of the light-emitting unit 4 away from the substrate 1, the first encapsulation layer includes a plurality of encapsulation units 26 arranged at intervals, at least part of the encapsulation units 26 extend from the side of the isolation structure 5 toward the isolation opening 6 to the side of the isolation structure 5 away from the substrate 1, and the encapsulation units 26 are arranged at intervals on the side of the isolation structure 5 away from the substrate 1.

[0133] Optionally, a gap exists between the packaging unit 26 located on the side of the isolation structure 5 away from the substrate 1 and the side of the isolation structure 5 away from the substrate 1 .

[0134] During the patterning process of the light-emitting unit 4 , the first packaging material layer is disconnected at the isolation structure 5 to form the packaging unit 26 . The packaging unit 26 can completely and independently package the corresponding light-emitting unit 4 , thereby improving the display characteristics of the display panel.

[0135] Preferably, see Fig.13a The display panel further includes a second encapsulation layer 27 located on a side of the first encapsulation layer away from the substrate 1 and a third encapsulation layer 28 located on a side of the second encapsulation layer 27 away from the substrate 1. The materials of the first encapsulation layer and the third encapsulation layer 28 both include inorganic materials, and the material of the second encapsulation layer 27 includes organic materials.

[0136] For example, the first encapsulation layer and the third encapsulation layer 28 can be formed by chemical vapor deposition (CVD), and the second encapsulation layer 27 can be formed by inkjet printing (IJP). The second encapsulation layer 27 and the third encapsulation layer 28 can provide a better encapsulation effect on the light-emitting unit 4, thereby further improving the encapsulation quality of the display panel.

[0137] For some possible implementations, see again Fig.12 The isolation structure 5 includes a first isolation portion 51 and a second isolation portion 52 which are stacked in sequence in a direction away from the substrate 1 , and the orthographic projection of the side of the first isolation portion 51 away from the substrate 1 on the substrate 1 is located within the orthographic projection of the second isolation portion 52 on the substrate 1 .

[0138] Since the second isolating portion 52 is located on the side of the first isolating portion 51 away from the substrate, and the lateral width of the second isolating portion 52 is greater than the lateral width of the first isolating portion 51 in a plane parallel to the substrate, the second isolating portion 52 disconnects the light-emitting material layer and the second electrode 14 material layer at the isolating structure 5. In this way, the isolating structure 5 formed by the first isolating portion 51 and the second isolating portion 52 can make it easier to independently package each light-emitting unit 4, thereby improving the packaging yield of the display panel.

[0139] Preferably, the second electrode 14 of the light-emitting unit 4 is electrically connected to the first isolation portion 51; the first isolation portion 51 includes a conductive material, and the second electrode 14 corresponding to the light-emitting unit 4 extends to contact the side wall of the first isolation portion 51 to achieve electrical connection between the second electrode 14 corresponding to the light-emitting unit 4 and the first isolation portion 51.

[0140] Please see again Fig.13a The isolation structure 5 further includes a third isolation portion 53 located on a side of the first isolation portion 51 facing the substrate 1 , and the second electrode 14 of the light emitting unit 4 is electrically connected to the third isolation portion 53 .

[0141] The third isolation portion 53 includes a conductive material, and the second electrode 14 corresponding to the light emitting unit 4 extends to contact the side wall of the third isolation portion 53 to achieve electrical connection between the second electrode 14 corresponding to the light emitting unit 4 and the third isolation portion 53 .

[0142] Specifically, the material of the third isolation portion 53 includes molybdenum; and / or the material of the first isolation portion 51 includes aluminum; and / or the material of the second isolation portion 52 includes titanium. In this way, when the isolation structure 5 separates the second electrode 14 material layer into the second electrode 14, the second electrode 14 is more easily electrically connected to the first isolation portion 51 and / or the third isolation portion 53.

[0143] The orthographic projection of the light emitting portion 13 on the substrate is outside the orthographic projection of the third isolation portion 53 and / or the first isolation portion 51. In this way, the light emitting portion 13 does not overlap the isolation structure 5, thereby effectively improving the crosstalk problem between the light emitting units 4.

[0144] For some possible implementations, see Figure 4 and Fig.13bThe present application also provides a display panel, the display panel includes a display area AA, and the display panel includes a substrate 1, an array layer 2 and a light-emitting unit 4.

[0145] The array layer 2 is located on one side of the substrate 1 . The array layer 2 includes a gate driving unit 3 . At least a portion of the gate driving unit 3 is located in the display area AA.

[0146] The orthographic projection of a portion of the light emitting unit 4 on the substrate 1 overlaps with the orthographic projection of the gate driving unit 3 on the substrate 1 .

[0147] In the present embodiment, the gate driving unit 3 is disposed in the array layer 2, and the gate driving unit 3 is disposed in the display area AA of the display panel. Thus, the gate driving unit 3 does not need to be disposed at the border position of the display panel, and will not occupy the space at the border of the display panel, thereby reducing the border size of the display panel, which is more conducive to forming a display panel with a narrow border or no border.

[0148] Since the orthographic projection of part of the light emitting unit 4 on the substrate 1 overlaps with the orthographic projection of the gate driving unit 3 on the substrate 1, the part of the gate driving unit 3 away from the substrate 1 can be displayed normally, thereby not affecting the display effect of the display panel.

[0149] The remaining solutions of the display panel in this embodiment are the same as the remaining solutions of the display panel in the above embodiment, and will not be described again here.

[0150] For some possible implementations, see Fig.14 The present application also provides a method for preparing a display panel, the display panel including a display area AA, the method comprising:

[0151] S10: providing a substrate 1.

[0152] S11: forming an array layer 2 on one side of the substrate 1, wherein the array layer 2 includes a gate driving unit 3, and at least a portion of the gate driving unit 3 is located in the display area AA.

[0153] See also Fig.15 , a pixel circuit 10 and a gate driving unit 3 are formed on one side of the substrate 1.

[0154] See also Fig.16 A first insulating layer 7 is formed on a side of the pixel circuit 10 and the gate driving unit 3 away from the substrate 1 , and a first via hole 71 penetrating the first insulating layer 7 is formed on the first insulating layer 7 .

[0155] See also Fig.17 A first conductive layer is formed on a side of the first insulating layer 7 away from the substrate 1 , the first conductive layer includes a plurality of first conductive traces 11 arranged at intervals, and the first conductive traces 11 are electrically connected to the pixel circuit 10 through a first via 71 .

[0156] See also Fig.18 A second insulating layer 8 is formed on a side of the first conductive layer away from the substrate 1 , and a second via hole 81 penetrating through the second insulating layer 8 is formed on the second insulating layer 8 .

[0157] See also Fig.19 A second conductive layer is formed on a side of the second insulating layer 8 away from the substrate 1 , the second conductive layer includes a power supply line 25 and a plurality of second conductive lines 20 arranged at intervals, and the second conductive lines 20 are electrically connected to the first conductive lines 11 through second vias 81 .

[0158] See also Fig. 20 A third insulating layer 21 is formed on a side of the second conductive layer away from the substrate 1 , and a third via hole 211 and a fourth via hole 212 penetrating the third insulating layer 21 are formed on the third insulating layer 21 , wherein the fourth via hole 212 exposes a portion of the power line 25 .

[0159] S12 : forming an isolation structure 5 on a side of the array layer 2 away from the substrate 1 , wherein the isolation structure 5 encloses an isolation opening 6 .

[0160] S13 : forming a light emitting unit 4 in the isolation opening 6 , wherein the orthographic projection of a portion of the light emitting unit 4 on the substrate 1 overlaps with the orthographic projection of the gate driving unit 3 on the substrate 1 .

[0161] In the display panel formed by the above method, the gate driving unit 3 is arranged on the array layer 2, and the gate driving unit 3 is arranged in the display area AA of the display panel. In this way, the gate driving unit 3 does not need to be arranged at the border position of the display panel, and the gate driving unit 3 does not occupy the space at the border of the display panel, thereby reducing the border size of the display panel, which is more conducive to forming a display panel with a narrow border or no border.

[0162] Since the orthographic projection of part of the light emitting unit 4 on the substrate 1 overlaps with the orthographic projection of the gate driving unit 3 on the substrate 1, the part of the gate driving unit 3 away from the substrate 1 can be displayed normally, thereby not affecting the display effect of the display panel.

[0163] In some possible implementations, the step of forming the isolation structure 5 on a side of the array layer 2 away from the substrate 1 includes:

[0164] See also Fig.21 A first electrode layer is formed on a side of the third insulating layer 21 away from the substrate 1 , and the first electrode layer includes a plurality of first electrodes 12 arranged at intervals, and the first electrodes 12 are electrically connected to the second conductive trace 20 through the third via 211 .

[0165] See also Figure 22-Figure 23A pixel defining material layer 29 and an isolation material layer 30 are sequentially formed on the side of the first electrode layer away from the substrate 1, and a fifth via hole 92 penetrating the pixel defining material layer 29 is formed on the pixel defining material layer 29, the fifth via hole 92 exposes a portion of the power line 25, and the isolation material layer 30 is electrically connected to the power line 25 through the fifth via hole 92 and the fourth via hole 212 in sequence.

[0166] See also Fig.24 The isolation material layer 30 and the pixel defining material 29 are patterned in sequence to form an isolation structure 5 and a pixel defining layer 9 respectively. The pixel defining layer 9 is provided with a pixel opening 91 , and the pixel opening 91 is connected to the isolation opening 6 .

[0167] In this way, when the second conductive layer is formed, the second conductive trace 20 and the power trace 25 can be formed. When the isolation material layer 30 is formed, the isolation material layer 30 can be electrically connected to the power trace 25 through the fifth via 92 and the fourth via 212. The power trace 25 extends to the display area AA and is electrically connected to the isolation structure 5 of the display area AA. The distance between the electrical connection between the power trace 25 and the isolation structure 5 can be reduced, thereby reducing the power supply voltage drop provided to the second electrode 14, and further improving the display effect of the light-emitting unit 4.

[0168] In some possible implementations, the present application further provides an electronic device, the electronic device comprising the display panel of the present application, or comprising a display panel prepared by the method for preparing a display panel of the present application. The electronic device may include a device with image processing capabilities, such as a server, a personal computer, a laptop computer, etc. Since the electronic device comprises the display panel of the present application, the display quality of the electronic device is better.

[0169] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0170] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A display panel, characterized in that: The display panel includes a display area, and the display panel includes: substrate; An array layer, located at one side of the substrate, the array layer comprising a gate driving unit, at least part of the gate driving unit is located in the display area; An isolation structure, located at a side of the array layer away from the substrate, the isolation structure encloses an isolation opening; The light-emitting unit is located in the isolation opening, and the orthographic projection of a part of the light-emitting unit on the substrate overlaps with the orthographic projection of the gate driving unit on the substrate.

2. The display panel according to claim 1, characterized in that: The gate driving unit includes a plurality of shift registers, and the plurality of shift registers are arranged along a first direction; The orthographic projection of the display area on the substrate includes a first edge and a second edge that are oppositely arranged, the first edge and the second edge extend along a second direction, the first edge and the second edge are arranged along the first direction, the gate driving unit extends from the first edge to the second edge, and the first direction and the second direction intersect; the orthographic projection of the display area on the substrate also includes a third edge and a fourth edge that are oppositely arranged, the third edge and the fourth edge extend along the first direction, and the third edge and the fourth edge are arranged along the second direction; Preferably, the orthographic projection of the gate driving unit on the substrate is located at a middle position between the third edge and the fourth edge; Preferably, the first direction is perpendicular to the second direction.

3. The display panel according to claim 1 or 2, characterized in that: The array layer includes a plurality of pixel circuits, the light-emitting unit includes a first electrode, a light-emitting portion, and a second electrode which are sequentially stacked in a direction away from the substrate, and the pixel circuit is electrically connected to the first electrode; the orthographic projection of the gate driving unit on the substrate is located outside the orthographic projection of the pixel circuit on the substrate; Preferably, the orthographic projections of the plurality of pixel circuits on the substrate are located on both sides of the orthographic projection of the gate driving unit on the substrate.

4. The display panel according to claim 2, characterized in that: The array layer includes a plurality of pixel circuits, a portion of the display area located between the gate driving unit and the third edge includes a first region and a second region, the second region is located between the first region and the third edge, and a ratio of a density of pixel circuits located in the first region to a density of pixel circuits located in the second region is greater than or equal to 1; and / or The portion of the display area located between the gate driving unit and the fourth edge includes a third area and a fourth area, the fourth area is located between the third area and the fourth edge, and a ratio of a density of pixel circuits located in the third area to a density of pixel circuits located in the fourth area is greater than or equal to 1; Preferably, the third edge is connected to both the first edge and the second edge; Preferably, the fourth edge is connected to both the first edge and the second edge.

5. The display panel according to claim 3, characterized in that: The array layer further comprises a first insulating layer, a first conductive layer, and a second insulating layer which are sequentially stacked and located at a side of the pixel circuit away from the substrate, the first electrode is located at a side of the second insulating layer away from the substrate, the first conductive layer comprises a plurality of first conductive traces which are spaced apart, and the pixel circuit and the corresponding first electrode are electrically connected via the first conductive traces; Preferably, the first insulating layer is provided with a first via hole penetrating the first insulating layer, the second insulating layer is provided with a second via hole penetrating the second insulating layer, the first conductive trace is electrically connected to the pixel circuit through the first via hole, and the first electrode is electrically connected to the first conductive trace through the second via hole.

6. The display panel according to claim 3, characterized in that: The array layer further comprises a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer and a third insulating layer which are sequentially stacked and located at a side of the pixel circuit away from the substrate, the first electrode is located at a side of the third insulating layer away from the substrate, the second conductive layer comprises a plurality of second conductive traces arranged at intervals, and the pixel circuit is electrically connected to the corresponding first electrode via one of the second conductive traces; Preferably, the material of the second conductive trace comprises indium tin oxide.

7. The display panel according to claim 5 or 6, characterized in that: The array layer also includes a semiconductor layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer which are stacked in sequence on one side of the substrate and away from the substrate, and the first conductive layer is located on a side of the fifth conductive layer away from the substrate.

8. The display panel according to claim 2, characterized in that: The display panel further includes a power line, the power line extending to the display area, the power line being located between the gate driving unit and the isolation structure, the orthographic projection of the power line on the substrate overlapping the orthographic projection of the gate driving unit on the substrate, and the power line being electrically connected to the isolation structure; Preferably, the portion of the power supply line extending to the display area is in a strip shape and extends along the first direction; Preferably, the orthographic projection of the portion of the power supply line extending to the display area on the substrate is located at a middle position between the third edge and the fourth edge.

9. The display panel according to claim 8, characterized in that: The display panel further includes a third insulating layer and a pixel defining layer which are sequentially stacked between the power wiring and the isolation structure, the third insulating layer is provided with a fourth via hole penetrating the third insulating layer, the fourth via hole exposes a portion of the power wiring, the pixel defining layer is provided with a fifth via hole penetrating the pixel defining layer and a pixel opening, the isolation structure is electrically connected to the power wiring through the fifth via hole and the fourth via hole in sequence, and the pixel opening is connected to the isolation opening; Preferably, the array layer comprises a plurality of conductive layers stacked in sequence along a side away from the substrate, and the power supply line is located in a conductive layer of the plurality of conductive layers that is closest to the isolation structure; Preferably, a center of an orthographic projection of the fifth via hole on the substrate coincides with a center of an orthographic projection of the fourth via hole on the substrate.

10. The display panel according to claim 1, characterized in that: The display panel further comprises a first encapsulation layer located on a side of the light emitting unit away from the substrate, the first encapsulation layer comprising a plurality of encapsulation units arranged at intervals, at least a portion of the encapsulation units extending from a side of the isolation structure toward the isolation opening to a side of the isolation structure away from the substrate; Preferably, the encapsulation unit is arranged at intervals on a side of the isolation structure away from the substrate; Preferably, there is a gap between the packaging unit located on a side of the isolation structure away from the substrate and a side of the isolation structure away from the substrate; Preferably, the display panel further comprises a second encapsulation layer located on a side of the first encapsulation layer away from the substrate and a third encapsulation layer located on a side of the second encapsulation layer away from the substrate; Preferably, the materials of the first encapsulation layer and the third encapsulation layer both include inorganic materials; Preferably, the material of the second encapsulation layer includes organic material.

11. The display panel according to claim 1, characterized in that: The isolation structure comprises a first isolation portion and a second isolation portion which are sequentially stacked in a direction away from the substrate, wherein an orthographic projection of a side of the first isolation portion away from the substrate on the substrate is located within an orthographic projection of the second isolation portion on the substrate; Preferably, the second electrode of the light-emitting unit is electrically connected to the first isolation portion; and / or the isolation structure further comprises a third isolation portion located on a side of the first isolation portion facing the substrate, and the second electrode of the light-emitting unit is electrically connected to the third isolation portion; Preferably, the material of the third isolation portion includes molybdenum; and / or the material of the first isolation portion includes aluminum; and / or the material of the second isolation portion includes titanium.

12. A display panel, characterized in that: The display panel includes a display area, and the display panel includes: substrate; An array layer, located at one side of the substrate, the array layer comprising a gate driving unit, at least part of the gate driving unit is located in the display area; The light-emitting unit, a part of which has an orthographic projection on the substrate overlapped with an orthographic projection of the gate driving unit on the substrate.

13. The display panel according to claim 12, characterized in that: The array layer includes a plurality of pixel circuits, the light-emitting unit includes a first electrode, a light-emitting portion, and a second electrode which are sequentially stacked in a direction away from the substrate, and the pixel circuit is electrically connected to the first electrode; the orthographic projection of the gate driving unit on the substrate is located outside the orthographic projection of the pixel circuit on the substrate; Preferably, the orthographic projections of the plurality of pixel circuits on the substrate are located on both sides of the orthographic projection of the gate driving unit on the substrate.

14. The display panel according to claim 13, characterized in that: The gate driving unit includes a plurality of shift registers, and the plurality of shift registers are arranged along a first direction; The orthographic projection of the display area on the substrate includes a first edge and a second edge that are oppositely arranged, the first edge and the second edge extend along a second direction, the first edge and the second edge are arranged along the first direction, the gate driving unit extends from the first edge to the second edge, and the first direction and the second direction intersect; the orthographic projection of the display area on the substrate also includes a third edge and a fourth edge that are oppositely arranged, the third edge and the fourth edge extend along the first direction, and the third edge and the fourth edge are arranged along the second direction; Preferably, the portion of the display area located between the gate driving unit and the third edge includes a first area and a second area, the second area is located between the first area and the third edge, and a ratio of a density of pixel circuits located in the first area to a density of pixel circuits located in the second area is greater than or equal to 1; and / or The portion of the display area located between the gate driving unit and the fourth edge includes a third area and a fourth area, the fourth area is located between the third area and the fourth edge, and a ratio of a density of pixel circuits located in the third area to a density of pixel circuits located in the fourth area is greater than or equal to 1; Preferably, an orthographic projection of the gate driving unit on the substrate is located at a middle position between the third edge and the fourth edge.

15. An electronic device, characterized in that: The electronic device comprises the display panel according to any one of claims 1 to 14.

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