Display panel mother board, preparation method of display panel mother board and test method of display panel mother board

Abstract

The embodiment of the invention provides a display panel mother board, a preparation method of the display panel mother board and a test method, and relates to the technical field of display, and the display panel mother board comprises a substrate and at least one test element group. The test element group comprises a test electrode and an isolation test structure arranged on the peripheral side of the test electrode, the isolation test structure comprises at least two isolation test parts arranged at intervals, orthographic projections of the at least two isolation test parts on the substrate are not overlapped, and the test electrode is electrically connected with at least one isolation test part. According to the invention, the isolation test structure comprises at least two isolation test parts which are arranged at intervals, and the isolation test parts are electrically connected through the test electrode, so that the lap joint electrode between the isolation test structure and the test electrode can be tested more accurately and directly. Therefore, the lap joint effect between the isolation structure of the display area and the cathode can be evaluated more accurately and directly, and the performance of the display panel mother board can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel motherboard, a preparation method of the display panel motherboard, and a testing method. Background Art

[0002] Organic Light Emitting Diode (OLED) and flat display panels based on technologies such as Light Emitting Diode (LED) are widely used in various consumer electronic products such as mobile phones, televisions, laptops, desktop computers, etc. due to their advantages such as high image quality, power saving, thin body and wide application range, becoming the mainstream in display devices.

[0003] However, there are still some problems that need to be solved in the process of manufacturing display devices. Summary of the invention

[0004] In order to overcome the technical problems mentioned in the above technical background, an embodiment of the present application provides a display panel motherboard, wherein the display panel motherboard includes a display area and a non-display area at least partially surrounding the display area, wherein the non-display area includes a test area, and the display panel motherboard includes:

[0005] substrate;

[0006] At least one test element group is located on one side of the substrate, the test element group includes a test electrode and an isolation test structure arranged around the test electrode, the isolation test structure includes at least two isolation test parts arranged at intervals from each other, and the orthographic projections of at least two isolation test parts on the substrate do not overlap with each other.

[0007] In some possible implementations, the test element group further includes at least two partition parts, the partition part is arranged between two adjacent isolation test parts, and the isolation test part and the partition part are arranged around the test electrode;

[0008] Preferably, the partition portion comprises an insulating material;

[0009] Preferably, at least two of the isolation test parts and at least two of the partition parts are continuously arranged to form an annular test opening, and the test electrode is arranged in the test opening.

[0010] In some possible implementations, the display panel motherboard further includes a conductive layer located on a side of the test element group close to the substrate, the conductive layer includes a plurality of test traces, any one of the test element groups is correspondingly provided with at least two of the test traces, and the isolation test parts are respectively electrically connected to one of the test traces;

[0011] Preferably, the display panel motherboard further comprises a first insulating layer located on a side of the conductive layer away from the substrate, and the test element group is located on a side of the first insulating layer away from the substrate;

[0012] Preferably, along a direction perpendicular to the substrate, a plurality of first test vias are provided on the first insulating layer, the first test vias expose at least a portion of the test traces, and the isolation test portion is electrically connected to the test traces through the first test vias;

[0013] Preferably, the first insulating layer comprises a first protruding portion extending in a direction away from the substrate, and at least a portion of the orthographic projection of the first protruding portion on the substrate is located between the orthographic projections of adjacent isolation test portions on the substrate;

[0014] Preferably, along a side away from the substrate, the first protrusion extends to a side of the test element group away from the substrate to form a partition portion between adjacent isolation test structures;

[0015] Preferably, the test trace electrically connected to the isolation test portion is electrically connected to at least two pins.

[0016] In some possible implementations, the display panel motherboard further includes a third insulating layer located on a side of the first insulating layer away from the substrate, and along a direction perpendicular to the substrate, a plurality of second test vias exposing at least a portion of the test traces are provided on the third insulating layer, and the isolation test portion is electrically connected to the test traces through the second test vias and the first test vias in sequence;

[0017] Preferably, the third insulating layer is further provided with a partition opening, and at least part of the first protrusion is provided in the partition opening;

[0018] Preferably, the orthographic projection of the second test via hole on the substrate covers the orthographic projection of the first test via hole on the substrate.

[0019] In some possible implementations, the display panel motherboard further includes a first insulating layer and a third insulating layer sequentially disposed along a side away from the substrate, and the test element group is located on a side of the third insulating layer away from the substrate;

[0020] Preferably, the first insulating layer includes a first protrusion extending in a direction away from the substrate, the third insulating layer includes a second protrusion located on a side of the first protrusion away from the substrate, the second protrusion extending to a side of the test element group away from the substrate along the side away from the substrate, and the first protrusion and the second protrusion form a partition located between adjacent isolation test structures;

[0021] Preferably, orthographic projections of at least part of the first protrusion and at least part of the second protrusion on the substrate are both located between orthographic projections of adjacent isolation test parts on the substrate;

[0022] Preferably, the display panel motherboard further comprises a second insulating layer located at a side of the second protrusion away from the substrate, the second insulating layer covers at least a portion of the isolation test portion, and an orthographic projection of the second protrusion on the substrate is located within the orthographic projection range of the second insulating layer on the substrate;

[0023] Preferably, the second protrusion contacts side surfaces of two adjacent isolation test portions.

[0024] In some possible implementations, the display panel motherboard further includes a first insulating layer and a third insulating layer sequentially disposed away from the substrate, and the test element group is located on a side of the third insulating layer away from the substrate;

[0025] Preferably, the third insulating layer comprises a second protrusion extending in a direction away from the substrate, and the second protrusion extends to a side of the test element group away from the substrate to form a partition portion located between adjacent isolation test structures;

[0026] Preferably, at least part of the orthographic projection of the second protruding portion on the substrate is located between the orthographic projections of adjacent isolated test portions on the substrate;

[0027] Preferably, the second protrusion contacts the side surfaces of two adjacent isolation test portions;

[0028] Preferably, the display panel motherboard further comprises a second insulating layer located on a side of the second protruding portion away from the substrate, and the second insulating layer covers at least a portion of the isolation test portion.

[0029] In some possible implementations, at least a portion of the third insulating layer extends to a side wall of the first test via hole;

[0030] Preferably, the third insulating layer covers the side wall of the first test via hole;

[0031] Preferably, the orthographic projection of the second test hole on the substrate is located within the orthographic projection of the first test hole on the substrate;

[0032] Preferably, the center of the orthographic projection of the first test via hole on the substrate coincides with the center of the orthographic projection of the second test via hole on the substrate;

[0033] Preferably, the third insulating layer extends to a display area of ​​the display panel motherboard, and the third insulating layer further includes a pixel opening located in the display area.

[0034] In some possible implementations, the method further includes a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer stacked in sequence in a direction away from the substrate, and the test trace is located in any one of the first conductive layer, the second conductive layer, the third conductive layer, or the fourth conductive layer;

[0035] Preferably, the test trace is located in the fourth conductive layer;

[0036] Preferably, a first planarization layer is provided between the third conductive layer and the fourth conductive layer, a second planarization layer is provided on a side of the fourth conductive layer away from the substrate, the first insulating layer includes the second planarization layer, and the first test via is arranged on the second planarization layer.

[0037] In some possible implementations, the test element group further includes a light emitting test portion located in the test opening, and the light emitting test portion is located on a side of the test electrode close to the substrate;

[0038] Preferably, the display panel motherboard comprises a display panel and a test area located around the display panel, the test element group is arranged in the test area, and the display panel motherboard further comprises an isolation structure located on the display panel, the isolation structure encloses to form an isolation opening;

[0039] Preferably, the isolation structure and the isolation test structure are arranged at the same layer;

[0040] Preferably, the shape of the orthographic projection of the test opening on the substrate is the same as the shape of the orthographic projection of the isolation opening on the substrate;

[0041] Preferably, an area of ​​an orthographic projection of the test opening on the substrate is N times an area of ​​an orthographic projection of the isolation opening on the substrate, wherein N is greater than or equal to 1.

[0042] In some possible implementations, the display panel motherboard further includes a light emitting unit at least partially located in the isolation opening;

[0043] Preferably, the light-emitting unit comprises a first electrode, a light-emitting portion, and a second electrode which are sequentially stacked in a direction away from the substrate, and the second electrode is electrically connected to a side of the isolation structure facing the isolation opening;

[0044] Preferably, the light emitting part and the light emitting testing part are arranged on the same layer;

[0045] Preferably, the second electrode is arranged in the same layer as the test electrode;

[0046] Preferably, the light-emitting unit includes a first light-emitting unit and a second light-emitting unit having different light-emitting colors, the test element group includes a first test component for testing the first light-emitting unit and a second test component for testing the second light-emitting unit, the light-emitting test part of the first test component is made of the same material as the light-emitting part of the first light-emitting unit, and the light-emitting test part of the second test component is made of the same material as the light-emitting part of the second light-emitting unit.

[0047] In some possible implementations, the display panel motherboard further includes a first encapsulation layer located on a side of the light-emitting unit away from the substrate, and the first encapsulation layer includes a plurality of encapsulation units arranged at intervals;

[0048] Preferably, at least part of the packaging unit extends from a side surface of the isolation structure to a side of the isolation structure away from the substrate, and the side surface of the isolation structure is a surface of the isolation structure facing the isolation opening;

[0049] Preferably, at least part of the encapsulation unit extends from a side surface of the isolation structure to a side of the isolation structure away from the substrate;

[0050] Preferably, adjacent packaging units are arranged at intervals on a side of the isolation structure away from the substrate;

[0051] Preferably, there is a gap between the packaging unit located on a side of the isolation structure away from the substrate and a side of the isolation structure away from the substrate;

[0052] Preferably, the isolation structure comprises a first isolation portion and a second isolation portion which are sequentially stacked in a direction away from the substrate, and an orthographic projection of a side of the first isolation portion away from the substrate on the substrate is located within an orthographic projection of the second isolation portion on the substrate;

[0053] Preferably, the second electrode of the light-emitting unit is electrically connected to the first isolation portion; and / or the isolation structure further comprises a third isolation portion located on a side of the first isolation portion facing the substrate, and the second electrode of the light-emitting unit is electrically connected to the third isolation portion;

[0054] Preferably, the material of the third isolation portion includes molybdenum metal; and / or the material of the first isolation portion includes aluminum metal; and / or the material of the second isolation portion includes titanium metal.

[0055] In some possible implementations, the isolation test structure includes a first test portion and a second test portion stacked in sequence in a direction away from the substrate, an orthographic projection of a side of the first test portion away from the substrate on the substrate is located within an orthographic projection of the second test portion on the substrate, and the test electrode extends to be electrically connected to the first test portion;

[0056] Preferably, the isolation test structure includes a first isolation test part and a second isolation test part that are spaced apart from each other, and the test element group also includes a first partition part and a second partition part located between the first isolation test part and the second isolation test part, the first isolation test part, the first partition part, the second isolation test part and the second partition part are arranged in sequence and enclosed to form a test opening, and the test electrode is arranged in the test opening.

[0057] In some possible implementations, the present application further provides a method for preparing a display panel motherboard, the method comprising:

[0058] providing a substrate;

[0059] At least one test element group is formed on one side of the substrate, the test element group includes a test electrode and an isolation test structure arranged around the test electrode, the isolation test structure includes at least two isolation test parts arranged at intervals from each other, and the orthographic projections of at least two isolation test parts on the substrate do not overlap with each other.

[0060] In some possible implementations, the step of forming at least one test element group on one side of the substrate includes:

[0061] forming a first insulating material layer on one side of the substrate;

[0062] Forming a first protrusion on the first insulating material layer by using a half-tone mask to form a first insulating layer;

[0063] forming a third insulating layer on a side of the first insulating layer away from the substrate, wherein the third insulating layer forms a second protruding portion at the first protruding portion;

[0064] forming an isolation conductive layer on a side of the third insulating layer away from the substrate, patterning the isolation conductive layer to form an isolation test structure, wherein the isolation test structure forms a first isolation test portion and a second isolation test portion spaced apart from each other at the second protruding portion, and an orthographic projection of the first isolation test portion on the substrate is outside an orthographic projection of the second isolation test portion on the substrate;

[0065] forming a second insulating layer on a side of the second protruding portion away from the substrate, wherein the second insulating layer covers at least a portion of the first isolation test portion and the second isolation test portion;

[0066] A light emitting test portion and a test electrode are sequentially formed in the test opening on a side away from the substrate, wherein the test electrode extends to be electrically connected to the first isolation test portion and the second isolation test portion;

[0067] Preferably, the display panel motherboard comprises a display panel and a test area, and the test component is arranged in the test area;

[0068] The display panel further comprises an isolation structure located at one side of the substrate, wherein the pixel isolation structure is arranged at the same layer as the first isolation test part and the second isolation test part;

[0069] The method for preparing the display panel motherboard further includes:

[0070] The isolation test structure is formed by the isolation conductive layer, and the isolation structure and the isolation opening are formed at the same time; the light emitting test part is formed, and the light emitting part is formed in the isolation opening at the same time;

[0071] forming the test electrode and forming a second electrode in the isolation opening at the same time;

[0072] Preferably, the preparation method further comprises:

[0073] Testing the test element group, and determining the overlapping effect of the second electrode and the isolation structure according to the test result of the test element group;

[0074] After the test is completed, the test area is cut to separate the display panel.

[0075] In some possible implementations, the present application further provides a method for testing a display panel motherboard, wherein the display panel motherboard includes the display panel motherboard described in the present application, and the testing method includes:

[0076] Obtaining the sum of the lap resistances of the test electrode and any two of the isolated test parts;

[0077] Determining the overlapping effect of the isolation structure of the display area of ​​the display panel motherboard and the second electrode based on the sum of the overlapping resistances of the test electrode and any two of the isolation test parts;

[0078] Preferably, any two of the isolated test parts and the test electrode are selected to form a circuit to be tested, and a test angle is determined according to a connection angle between the two isolated test parts and the center of the test electrode;

[0079] Based on the result of the test circuit, the overlapping effect of the isolation structure and the second electrode of the corresponding light-emitting unit at the test angle is determined.

[0080] Compared with the prior art, this application has the following beneficial effects:

[0081] The present application provides a display panel motherboard, a preparation method of the display panel motherboard and a testing method. By setting the isolation test structure to include at least two isolation test parts spaced apart from each other, and electrically connecting the isolation test parts through the test electrode, the overlapping electrode between the isolation test structure and the test electrode can be tested more accurately and directly, so that the overlapping effect between the isolation structure of the display area and the second electrode can be evaluated more accurately and directly, thereby improving the performance of the display panel motherboard. BRIEF DESCRIPTION OF THE DRAWINGS

[0082] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0083] Figure 1 One of the top view schematic diagrams of the display panel motherboard provided in the embodiment of the present application;

[0084] Figure 2 One of the top view schematic diagrams of the test element assembly provided in the embodiment of the present application;

[0085] Figure 3 Provided in the embodiments of this application Figure 2 One of the cross-sectional diagrams at AA in the middle;

[0086] Figure 4 An equivalent circuit diagram of a test component provided in an embodiment of the present application when the lap resistance is tested;

[0087] Figure 5 Provided in the embodiments of this application Figure 2 One of the cross-sectional diagrams at the middle BB;

[0088] Figure 6 Provided in the embodiments of this application Figure 2 The second cross-sectional diagram at the middle BB;

[0089] Figure 7 Provided in the embodiments of this application Figure 2 The third cross-sectional diagram at the middle BB;

[0090] Figure 8Provided in the embodiments of this application Figure 2 The fourth schematic diagram of the cross section at the middle BB;

[0091] Fig. 9 A cross-sectional schematic diagram of a display panel motherboard including an isolation structure provided in an embodiment of the present application;

[0092] Fig.10 Provided in the embodiments of this application Figure 2 The second cross-sectional diagram at AA in the middle;

[0093] Fig.11 The display panel motherboard provided in the embodiment of the present application includes a cross-sectional schematic diagram of a first encapsulation layer;

[0094] Fig.12 Provided in the embodiments of this application Figure 2 The third cross-sectional diagram at AA in the middle;

[0095] Fig.13 A cross-sectional schematic diagram of a display panel motherboard provided in an embodiment of the present application including a second encapsulation layer and a third encapsulation layer;

[0096] Fig.14 A schematic cross-sectional view of an isolation structure provided in an embodiment of the present application;

[0097] Fig.15 A schematic diagram of a process for preparing a display panel motherboard provided in an embodiment of the present application;

[0098] Fig.16 A schematic diagram of a specific execution flow of step S11 provided in an embodiment of the present application;

[0099] Fig.17 A cross-sectional schematic diagram of forming a first insulating material layer on one side of a substrate provided in an embodiment of the present application;

[0100] Fig.18 A cross-sectional schematic diagram of forming a first protrusion on a first insulating material layer by using a half-tone mask provided in an embodiment of the present application;

[0101] Fig.19 A cross-sectional schematic diagram of forming a third insulating layer on a side of the first insulating layer away from the substrate provided in an embodiment of the present application;

[0102] Fig. 20 A cross-sectional schematic diagram of forming an isolation conductive layer on a side of the third insulating layer away from the substrate provided in an embodiment of the present application;

[0103] Fig.21 A cross-sectional schematic diagram of an embodiment of the present application after the isolation test structure on the side of the second protrusion away from the substrate is removed;

[0104] Fig. 22 A schematic cross-sectional view of an embodiment of the present application after removing the test area;

[0105] Fig.23 A schematic flow chart of a method for testing a display panel motherboard provided in an embodiment of the present application;

[0106] Fig.24 The second schematic top view of the test component provided in the embodiment of the present application.

[0107] Figure numerals: 1, test element group; 2, pin; 3, test trace; 4, isolation test structure; 4001, isolation test part; 41, first isolation test part; 42, second isolation test part; 401, first test part; 402, second test part; 5, second insulating layer; 6, substrate; 7, conductive layer; 701, first conductive layer; 702, second conductive layer; 703, third conductive layer; 704, fourth conductive layer; 8, third insulating layer; 81, second test via; 82, second protrusion; 83, pixel opening; 84, isolation opening; 9, first insulating layer; 91, first test via; 92 , a first protruding portion; 10, a light-emitting test portion; 11, a test electrode; 12, a test opening; 13, an isolation structure; 131, a first isolation portion; 132, a second isolation portion; 133, a third isolation portion; 14, an isolation opening; 15, a first electrode; 16, a light-emitting portion; 17, a second electrode; 18, a light-emitting unit; 19, a buffer layer; 20, a first planarization layer; 21, a second planarization layer; 22, a first encapsulation layer; 221, an encapsulation unit; 23, a second encapsulation layer; 24, a third encapsulation layer; 25, a first insulating material layer; 26, a partition portion; 261, a first partition portion; 262, a second partition portion. DETAILED DESCRIPTION

[0108] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0109] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0110] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0111] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "vertical", "horizontal", "inner", "outer", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, or the positions or positional relationships in which the inventive product is usually placed when in use. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0112] It should be noted that, in the absence of conflict, different features in the embodiments of the present application may be combined with each other.

[0113] In the related art, the display panel motherboard includes a substrate, an isolation structure located on one side of the substrate, and a light-emitting unit at least partially located in an isolation opening of the isolation structure. The lap resistance between the cathode of the light-emitting unit and the isolation structure is a key indicator for measuring the process and product feasibility of the display panel motherboard.

[0114] In the related art, the non-display area of ​​the display panel motherboard includes a test area, and the test area can be used to evaluate the effect of the overlap between the cathode of the light-emitting unit in the display area and the isolation structure. However, the cathode and isolation structure of the simulated light-emitting unit tested in the test area in the related art are the same as the isolation structure of the display area, which is an overall ring shape. The isolation structure of the test area and the cathode overlapped with the isolation structure form a test point, and a test loop is also required to form a test loop with other test points. The use of this test loop can only detect whether there is an electrical signal in the test loop, and cannot accurately test the overlap resistance of the isolation structure and the cathode, thereby affecting the accuracy of evaluating the overlap resistance between the cathode of the light-emitting unit in the display area and the isolation structure, and ultimately affecting the performance of the display panel motherboard.

[0115] In view of this, the present embodiment provides a solution that can improve the accuracy of evaluating the overlap resistance between the cathode and the isolation structure of the display panel motherboard. The solution provided by the present embodiment is described in detail below.

[0116] See also Figure 1-Figure 3The present embodiment provides a display panel motherboard, which includes a substrate 6 and at least one test element group 1. The test element group 1 is located on one side of the substrate 6; the test element group 1 includes an isolation conductive layer 7 located on one side of the substrate 6, the isolation conductive layer 7 includes an isolation test structure 4, the isolation test structure 4 is provided with a test opening 12, the isolation test structure 4 includes at least two isolation test parts 4001 arranged at intervals from each other, and the orthographic projections of the at least two isolation test parts 4001 on the substrate 6 do not overlap each other, the test element group 1 also includes a test electrode 11, at least two isolation test parts 4001 are arranged on the peripheral side of the test electrode 11, the test electrode 11 is located in the test opening 12, and the test electrode 11 extends to be electrically connected to at least one isolation test part 4001.

[0117] When there are multiple test element groups 1 , the multiple test element groups 1 are insulated from each other, and the isolation test structure 4 of the test element group 1 is divided into a first isolation test portion 41 and a second isolation test portion 42 spaced apart from each other.

[0118] When the resistance of the test element group 1 is tested using the resistance display panel motherboard, the resistance of the resistance display panel motherboard test is equivalent to the sum of the overlapping resistances of any two isolated test parts 4001 and the test electrode 11 .

[0119] The material of the test electrode 11 is the same as that of the cathode of the display area AA, and the material of the isolation test structure 4 is the same as that of the isolation structure 13 of the display area AA. Therefore, the overlap resistance between any two isolation test parts 4001 and the test electrode 11 can be used to know the overlap resistance between the isolation structure 13 and the cathode. Based on the overlap resistance between the isolation structure 13 and the cathode, the overlap effect between the isolation structure 13 and the cathode can be more accurately evaluated.

[0120] For example, the overlap resistance per unit overlap area between the isolation test structure 4 and the test electrode 11 can be calculated based on the overlap resistance between any two isolation test parts 4001 and the test electrode 11. Since the material of the isolation test structure 4 is the same as that of the isolation structure 13, and the material of the test electrode 11 is the same as that of the cathode and they are formed in the same process, the overlap resistance per unit overlap area between the isolation test structure 4 and the test electrode 11 can accurately reflect the overlap area between the isolation structure 13 and the cathode in the same process, thereby more directly and accurately judging whether there is poor overlap between the isolation structure 13 and the cathode.

[0121] In addition, the solution of this embodiment can also be applied to light-emitting units 18 of different shapes, and the test structure is not affected by the size of the isolated test section 4001, that is, the sizes of the multiple isolated test sections 4001 into which the isolated test structure 4 is divided can be the same or different. In this way, the flexibility of setting the test element group 1 can be increased.

[0122] Based on the above design, this embodiment sets the isolation test structure 4 to include at least two isolation test parts 4001 spaced apart from each other, and electrically connects the test electrode 11 to the isolation test part 4001. This can more accurately and directly test the overlap resistance between the isolation test structure 4 and the test electrode 11, thereby more accurately and directly evaluating the overlap effect between the isolation structure 13 and the cathode of the display area AA, thereby improving the performance of the display panel motherboard.

[0123] For some possible implementations, see again Figure 1 and 2 The display panel motherboard includes a display area AA and a non-display area AB at least partially surrounding the display area AA, the non-display area AB includes a test area AC, the test element group 1 is located in the test area AC, and the test element group also includes at least two partitions 26, the partition 26 is arranged between two adjacent isolation test parts 4001, the partition 26 and the isolation test part 4001 are arranged around the test electrode 11, at least two isolation test parts 4001 and at least two partitions 26 are continuously arranged, and form an annular test opening 12, and the partition 26 includes an insulating material. The partition 26 can more easily divide the isolation test structure 4 into at least two isolation test parts 4001 arranged at intervals from each other.

[0124] Preferably, see again Figure 2 The isolation test structure 4 includes a first isolation test part 41 and a second isolation test part 41 which are spaced apart from each other. The test element group 1 also includes a first partition part 261 and a second partition part 262 located between the first isolation test part 41 and the second isolation test part 42. The first isolation test part 41, the first partition part 261, the second isolation test part 42 and the second partition part 262 are arranged in sequence and enclosed to form a test opening 12.

[0125] See also Figure 4 In this embodiment, the resistance tested by the resistance test element group is equivalent to the lap resistance R between the first isolation test portion 41 and the test electrode 11. 1搭接 The bridging resistance R between the second isolation test portion 42 and the test electrode 11 2搭接 The sum of the bridging resistance R1搭接 With the jumper resistor R2搭接 The sum of the resistances is the lap resistance between the isolation test structure 4 and the test electrode 11 .

[0126] For some possible implementations, see Figure 5 The display panel motherboard further includes a first insulating layer 9 and a third insulating layer 8 located on a side of the first insulating layer 9 away from the substrate 6. The third insulating layer 8 is a pixel defining layer of the display panel.

[0127] In some embodiments, please refer again to Figure 5 The first insulating layer 9 includes a first protruding portion 92 extending in a direction away from the substrate 6, and at least a portion of the first protruding portion 92 has an orthographic projection on the substrate 6 located between the orthographic projections of the first isolation test portion 41 and the second isolation test portion 42 on the substrate 6. The third insulating layer 8 includes a second protruding portion 82 extending in a direction away from the substrate 6, and at least a portion of the second protruding portion 82 has an orthographic projection on the substrate 6 located between the orthographic projections of the first isolation test portion 41 and the second isolation test portion 42 on the substrate 6.

[0128] In this embodiment, the second protrusion 82 is formed on the basis of the first protrusion 92, so that the second protrusion 82 can be formed more easily. The second protrusion 82 extends to the side of the test element group 1 away from the substrate 6. The second protrusion 82 and the first protrusion 92 form a partition 26 located between adjacent isolation test structures 4001. In this embodiment, the isolation opening 84 is formed by the second protrusion 82 and the first protrusion 92 to divide the isolation test structure 4 into at least two isolation test parts 4001 spaced apart from each other. The second protrusion 82 and the first protrusion 92 separate the first isolation test part 41 and the second isolation test part 42 to form a partition between the first isolation test part 41 and the second isolation test part 42. The second protrusion 82 insulates the first isolation test part 41 and the second isolation test part 42. In this way, the lap resistance between the isolation test structure 4 and the test electrode 11 can be accurately and more directly tested.

[0129] Preferably, see again Figure 5 , the orthographic projection of the second protrusion 82 on the substrate 6 is located within the orthographic projection of the first protrusion 92 on the substrate 6, and the center of the orthographic projection of the second protrusion 82 on the substrate 6 coincides with the center of the orthographic projection of the first protrusion 92 on the substrate 6. In this way, the second protrusion 82 can be more easily formed on the basis of the first protrusion 92, so that the second protrusion 82 can better separate the first isolation test part 41 from the second isolation test part 42.

[0130] Preferably, the second protrusion 82 contacts the side surfaces of two adjacent isolation test parts 4001. Thus, the two adjacent isolation test parts 4001 can be insulated by the second protrusion 82.

[0131] In other embodiments, see Figure 6, the first insulating layer 9 may be arranged flat, and only the second protrusion 82 is formed on the third insulating layer 8, and the second protrusion 82 extends to the side of the test element group 1 away from the substrate 6 to form a partition 26 located between adjacent isolation test structures 4001. In this embodiment, the isolation opening 84 is formed by the second protrusion 82 to divide the isolation test structure 4 into at least two isolation test sections 4001 spaced apart from each other, for example, the isolation test structure 4 is divided into a first isolation test section 41 and a second isolation test section 42 spaced apart from each other.

[0132] In some other embodiments, the first protrusion 92 is only provided on the first insulating layer 9 in the direction away from the substrate 6, and the first protrusion 92 extends to the side of the test element group 1 away from the substrate 6 on the side away from the substrate 6 to form a partition 26 located between adjacent isolation test structures 4001. The third insulating layer 8 is also provided with a partition opening 84, and at least part of the first protrusion 92 is provided in the partition opening 84. In this embodiment, the first protrusion 92 forms the partition opening 84, dividing the isolation test structure 4 into at least two isolation test parts 4001 spaced apart from each other.

[0133] For some possible implementations, see again Figure 5 and Figure 6 , the distance H1 from the side of the second protrusion 82 away from the substrate 6 to the substrate 6 is greater than or equal to the distance H2 from the side of the first isolation test section 41 and the second isolation test section 42 away from the substrate 6 to the substrate 6. The first isolation test section 41 extends to contact the side of the second protrusion 82 facing the first isolation test section 41, and the second isolation test section 42 extends to contact the side of the second protrusion 82 facing the second isolation test section 42. In this way, the second protrusion 82 can more effectively separate the first isolation test section 41 from the second isolation test section 42.

[0134] In some possible embodiments, the display panel motherboard also includes a second insulating layer 5 located on the side of the second protrusion 82 away from the substrate 6, the second insulating layer 5 covers at least part of the first isolation test part 41 and the second isolation test part 42, and the orthographic projection of the second protrusion 82 on the substrate 6 is located within the range of the orthographic projection of the second insulating layer 5 on the substrate 6.

[0135] In some embodiments, please refer again to Figure 5 and Figure 6, the second insulating layer 5 covers part of the isolation test part 4001, for example, covers the first isolation test part 41 and the second isolation test part 42. After the isolation test structure 4 on the side of the second protrusion 82 away from the substrate 6 is removed to form the first isolation test part 41 and the second isolation test part 42, part of the first isolation test part 41 and the second isolation test part 42 will be exposed to the outside, and the second insulating layer 5 covers the exposed part of the first isolation test part 41 and the second isolation test part 42, which can protect the first isolation test part 41 and the second isolation test part 42 and prevent the first isolation test part 41 and the second isolation test part 42 from being oxidized.

[0136] In some embodiments, see Figure 7 and Figure 8 , the second insulating layer 5 completely covers the first isolation test portion 41 and the second isolation test portion 42. In this way, the second insulating layer 5 has a better protection effect on the first isolation test portion 41 and the second isolation test portion 42.

[0137] For some possible implementations, see again Figure 3 The test element group 1 further includes a light emitting test portion 10 located in the test opening 12 . The light emitting test portion 10 is located on a side of the test electrode 11 close to the substrate 6 .

[0138] Preferably, see Fig. 9 The display panel motherboard includes a display panel and a test area located on the peripheral side of the display panel, the isolation conductive layer 7 extends to the display area AA, the isolation conductive layer 7 includes an isolation structure 13, the isolation structure 13 is located in the display area AA, the isolation structure 13 encloses an isolation opening 14, the display panel motherboard also includes a light-emitting unit 18 at least partially located in the isolation opening 14, the light-emitting unit 18 includes a first electrode 15, a light-emitting portion 16 and a second electrode 17 which are sequentially stacked in a direction away from the substrate 6, the isolation structure 13 and the isolation test structure 4 are arranged on the same layer, the light-emitting portion 16 and the light-emitting test portion 10 are arranged on the same layer, and the second electrode 17 and the test electrode 11 are arranged on the same layer.

[0139] The light-emitting unit includes a first light-emitting unit and a second light-emitting unit with different light-emitting colors. The test element group 1 includes a first test component for testing the first light-emitting unit and a second test component for testing the second light-emitting element. The light-emitting test part 10 of the first test component is made of the same material as the light-emitting part 16 of the first light-emitting unit, and the light-emitting test part 10 of the second test component is made of the same material as the light-emitting part 16 of the second light-emitting unit.

[0140] When forming the light-emitting functional layer, the light-emitting functional layer will be separated by the isolation structure 13 to form a plurality of light-emitting portions 16 spaced apart and located in the isolation opening 14 , and will also be separated by the isolation conductive layer 7 to form a light-emitting test portion 10 located in the test opening 12 .

[0141] When forming the second electrode layer, the second electrode layer will be separated by the isolation structure 13 to form a plurality of second electrodes 17 spaced apart and located in the isolation opening 14. The isolation structure 13 includes a conductive material, and the second electrode 17 is electrically connected to the isolation structure 13. The second electrode layer will also be separated by the isolation conductive layer 7 to form a test electrode 11 located in the test opening 12. The first isolation test section 41 and the second isolation test section 42 both include a conductive material, and the test electrode 11 extends to be electrically connected to the first isolation test section 41 and the second isolation test section 42. A first electrode 15, a light-emitting section 16 and a second electrode 17 form a light-emitting unit 18. Among them, the first electrode 15 is an anode, and the second electrode 17 is a cathode.

[0142] In this way, when the light-emitting functional layer is formed, the light-emitting portion 16 can be formed in the display area AA and the light-emitting test portion 10 can be formed in the test area AC at the same time; when the second electrode layer is formed, the second electrode 17 can be formed in the display area AA and the test electrode 11 can be formed in the test area AC at the same time, so there is no need to use a special process to set the light-emitting test portion 10 and the test electrode 11, thereby reducing the cost of forming the light-emitting test portion 10 and the test electrode 11.

[0143] For some possible implementations, see again Figure 3 The display panel motherboard also includes a conductive layer 7 located on the side of the test element group 1 close to the substrate 6, the conductive layer 7 includes a plurality of test traces 3, any test element group 1 is correspondingly provided with at least two test traces 3, the isolation test part 4001 is electrically connected to one test trace 3 respectively, for example, the first isolation test part 41 and the second isolation test part 42 are electrically connected to the test trace 3 respectively; the first insulating layer 9 is located on the side of the conductive layer 7 away from the substrate 6, and along the direction perpendicular to the substrate 6, a plurality of first test vias 91 exposing at least part of the test trace 3 are provided on the first insulating layer 9, the isolation test part 4001 is electrically connected to the test trace 3 through the first test vias 91, for example, the first isolation test part 41 and the second isolation test part 42 are electrically connected to the test trace 3 through the first test vias 91 respectively.

[0144] When the isolation test structure 4 is formed, the first isolation test part 41 and the second isolation test part 42 will be electrically connected to the test trace 3 through the first test via 91. In this way, the test trace 3 will eventually be electrically connected to the test electrode 11. By electrically connecting the resistance display panel motherboard to the test trace 3, it is easier to test the overlap resistance between the isolation test structure 4 and the test electrode 11.

[0145] Preferably, see again Figure 3, along the direction perpendicular to the substrate 6, a plurality of second test vias 81 exposing at least part of the test trace 3 are provided on the third insulating layer 8, and the isolation test part 4001 is electrically connected to the test trace 3 through the second test via 81 and the first test via 91 in sequence, for example, the first isolation test part 41 and the second isolation test part 42 are electrically connected to the test trace 3 through the second test via 81 and the first test via 91 in sequence, respectively.

[0146] Please see again Fig. 9 , the third insulating layer 8 extends to the display area AA, and the third insulating layer 8 in the display area AA further includes a pixel opening 83, and at least part of the light-emitting unit 18 is located in the pixel opening 83. The second test via hole 81 can be formed while forming the pixel opening 83. In this way, there is no need to specially set up a process for opening the second test via hole 81, thereby reducing the cost of opening the second test via hole 81.

[0147] For some possible implementations, see Fig.10 The conductive layer 7 includes a first conductive layer 701, a second conductive layer 702, a third conductive layer 703 and a fourth conductive layer 704 which are stacked in sequence in a direction away from the substrate 6. The test trace 3 is located in any one of the first conductive layer 701, the second conductive layer 702, the third conductive layer 703 and the fourth conductive layer 704. Specifically, the test trace 3 is located in the fourth conductive layer 704.

[0148] The display panel motherboard also includes a buffer layer 19 located on one side of the substrate 6 and a semiconductor layer located on the side of the buffer layer 19 away from the substrate 6, and the first conductive layer 701 is located on the side of the semiconductor layer away from the substrate 6. In the display area AA, the semiconductor layer includes a source area, a drain area and a channel area, the first conductive layer 701 includes a gate and a first capacitor plate, the second conductive layer 702 includes a second capacitor plate, the first capacitor plate and the second capacitor plate form a capacitor, the third conductive layer 703 includes a drain and a source, the drain is electrically connected to the drain area, the source is electrically connected to the source area, the gate, the source and the drain form a switching device, the metal wiring of the fourth conductive layer 704 is connected to the drain, and the metal wiring of the fourth conductive layer 704 is electrically connected to the first electrode 15. In this embodiment, the test wiring 3 of the test area AC is located in the fourth conductive layer 704.

[0149] Preferably, see again Fig.10 A first planarization layer 20 is provided between the third conductive layer 703 and the fourth conductive layer 704 , a second planarization layer 21 is provided on the side of the fourth conductive layer 704 away from the substrate 6 , the first insulating layer 9 includes the second planarization layer 21 , and the first test via 91 is provided on the second planarization layer 21 .

[0150] The second planarization layer 21 extends to the test area AC. A first test via 91 is provided on the second planarization layer 21 in a direction perpendicular to the substrate 6 . The first isolation test portion 41 and the second isolation test portion 42 are electrically connected to the test trace 3 through the first test via 91 .

[0151] For some possible implementations, see again Fig.10 , at least a portion of the third insulating layer 8 extends to the side wall of the first test via hole 91 .

[0152] The material of the second planarization layer 21 includes an organic material, and the material of the test trace 3 includes a metal material. The organic material and the metal material are in contact and easily generate water vapor. The material of the third insulating layer 8 includes an inorganic material, and water vapor is not easily transferred in the inorganic material. Therefore, in this embodiment, by setting the third insulating layer 8 to extend to the side wall of the first test via 91, it is possible to prevent the water vapor of the second planarization layer 21 from being transferred to the light-emitting unit 18, and it is possible to prevent the formation of voids when the isolation conductive layer 7 is formed, thereby improving the quality of the display panel motherboard.

[0153] Preferably, see again Fig.10 The third insulating layer 8 wraps the side wall of the first test via hole 91 . The third insulating layer 8 completely wraps the side wall of the first test via hole 91 , so that the water vapor of the second planarization layer 21 is less likely to be transferred toward the light emitting unit 18 .

[0154] Preferably, see again Fig.10 , the orthographic projection of the second test hole on the substrate 6 is located within the orthographic projection of the first test hole on the substrate 6, and the center of the orthographic projection of the first test via 91 on the substrate 6 coincides with the center of the orthographic projection of the second test via 81 on the substrate 6. In this way, the thickness of the third insulating layer 8 between the first test via 91 and the second test via 81 is equal, which not only makes it more difficult for the water vapor of the second planarization layer 21 to be transmitted toward the light-emitting unit 18, but also improves the electrical connection effect between the first isolation test portion 41 and the second isolation test portion 42 and the test trace 3.

[0155] Preferably, see again Figure 2 The test trace 3 electrically connected to the first isolation test part 41 is electrically connected to at least two pins 2, and the test trace 3 electrically connected to the second isolation test part 42 is electrically connected to at least two pins 2. The test element group can be electrically connected to at least four pins 2, so that the accuracy of the lap resistance between the test isolation test structure 4 and the test electrode 11 can be improved.

[0156] Preferably, the shape of the orthographic projection of the test opening 12 on the substrate 6 is the same as the shape of the orthographic projection of the isolation opening 14 on the substrate 6 , and the area of ​​the orthographic projection of the test opening 12 on the substrate 6 is N times the area of ​​the orthographic projection of the isolation opening 14 on the substrate 6 , where N is greater than or equal to 1.

[0157] The shape of the test opening 12 in the test area AC is set to be the same as the shape of the isolation opening 14 located in the display area AA, and the size of the test opening 12 is enlarged compared to the isolation opening 14. In this way, the test opening 12 can imitate the isolation opening 14, and the lap resistance between the isolation test structure 4 and the test electrode 11 finally tested can more easily and directly reflect the lap resistance between the isolation structure 13 and the cathode.

[0158] If the isolation opening 14 of the display area AA has isolation sub-openings of different shapes, then at least one test opening 12 and a test component located at the test opening 12 are correspondingly set for each isolation sub-opening of the shape. A test opening with the same shape as the isolation opening is prepared, and the overlap resistance between the pixel cathode and the isolation structure in the isolation openings of different shapes can be comprehensively tested through the test component group to accurately determine the overlap status.

[0159] For example, the area of ​​the orthographic projection of the test opening 12 on the substrate 6 is set to five times the area of ​​the orthographic projection of the isolation opening 14 on the substrate 6. The overlap resistance between the isolation test structure 4 and the test electrode 11 tested is reduced by five times to obtain the overlap resistance between the isolation structure 13 and the cathode of the display area AA, so that the overlap resistance between the isolation structure 13 and the cathode of the display area AA can be obtained more accurately and directly, and then the overlap effect between the isolation structure 13 and the cathode can be evaluated more easily and accurately.

[0160] For some possible implementations, see Fig.11 The display panel motherboard also includes a first packaging layer 22 located on the side of the light-emitting unit 18 away from the substrate 6. The first packaging layer 22 includes a plurality of packaging units 221 arranged at intervals. At least part of the packaging units 221 extend from the side of the isolation structure 13 to the side of the isolation structure 13 away from the substrate 6. The side of the isolation structure 13 is the surface of the isolation structure 13 facing the isolation opening 14. At least part of the packaging units 221 extend from the side of the isolation structure 13 to the side of the isolation structure 13 away from the substrate 6. Adjacent packaging units 221 are spaced apart on the side of the isolation structure 13 away from the substrate 6. There is a gap between the packaging units 221 located on the side of the isolation structure 13 away from the substrate 6 and the side of the isolation structure 13 away from the substrate 6.

[0161] The material of the first encapsulation layer 22 can be the same as that of the second insulating layer 5. During the patterning process of the light-emitting unit 18, the first encapsulation layer 22 is disconnected at the isolation structure 13 to form a encapsulation unit 221. The encapsulation unit 221 can completely and independently encapsulate the corresponding light-emitting unit 18, thereby improving the display characteristics of the display panel.

[0162] See also Fig.12 A packaging unit 221 is also formed on the side of the test electrode 11 away from the substrate 6 , and the packaging unit 221 extends from the side of the first isolation test part 41 and the second isolation test part 42 to the side of the first isolation test part 41 and the second isolation test part 42 away from the substrate 6 .

[0163] Preferably, see Fig.13 The display panel motherboard also includes a second encapsulation layer 23 located on the side of the first encapsulation layer 22 away from the substrate 6 and a third encapsulation layer 24 located on the side of the second encapsulation layer 23 away from the substrate 6. The materials of the first encapsulation layer 22 and the third encapsulation layer 24 both include inorganic materials, and the material of the second encapsulation layer 23 includes organic materials.

[0164] The second encapsulation layer 23 and the third encapsulation layer 24 can provide a better encapsulation effect on the light emitting unit 18 , thereby further improving the encapsulation quality of the display panel.

[0165] Preferably, see again Fig.13 The isolation structure 13 includes a first isolation portion 131 and a second isolation portion 132 which are stacked in sequence in a direction away from the substrate 6 , and the orthographic projection of the side of the first isolation portion 131 away from the substrate 6 on the substrate 6 is located within the orthographic projection of the second isolation portion 132 on the substrate 6 .

[0166] Since the second isolation portion 132 is located on the side of the first isolation portion 131 away from the substrate, and the lateral width of the second isolation portion 132 is greater than the lateral width of the first isolation portion 131, the second isolation portion 132 disconnects the light-emitting functional layer and the second electrode layer at the isolation structure 13. In this way, the isolation structure 13 formed by the first isolation portion 131 and the second isolation portion 132 can make it easier to package each light-emitting unit 18 independently.

[0167] Preferably, see again Fig.13 The second electrode 17 of the light-emitting unit 18 is electrically connected to the first isolation portion 131; the first isolation portion 131 includes a conductive material, and the second electrode 17 corresponding to the light-emitting unit 18 extends to contact the side wall of the first isolation portion 131 to achieve electrical connection between the second electrode 17 corresponding to the light-emitting unit 18 and the first isolation portion 131.

[0168] See also Fig.14The isolation structure 13 further includes a third isolation portion 133 located on a side of the first isolation portion 131 facing the substrate 6 , and the second electrode 17 of the light emitting unit 18 is electrically connected to the third isolation portion 133 .

[0169] The third isolation portion 133 includes a conductive material, and the second electrode 17 corresponding to the light emitting unit 18 extends to contact the sidewall of the third isolation portion 133 to achieve electrical connection between the second electrode 17 corresponding to the light emitting unit 18 and the third isolation portion 133 .

[0170] Preferably, the material of the third isolation portion 133 includes molybdenum metal; and / or, the material of the first isolation portion 131 includes aluminum metal; and / or, the material of the second isolation portion 132 includes titanium metal. In this way, when the isolation structure 13 separates the second electrode layer into the second electrode 17, the second electrode 17 is more easily electrically connected to the first isolation portion 131 and / or the third isolation portion 133.

[0171] For some possible implementations, see again Fig.12 The isolation test structure 4 includes a first test portion 401 and a second test portion 402 which are stacked in sequence in a direction away from the substrate 6. The orthographic projection of the side of the first test portion 401 away from the substrate 6 is located within the orthographic projection of the second test portion 402 on the substrate 6. The test electrode 11 extends to be electrically connected to the first test portion 401.

[0172] Since the second test section 402 is located on the side of the first test section 401 away from the substrate, and the lateral width of the second test section 402 is greater than the lateral width of the first test section 401, the second test section 402 will disconnect the light-emitting functional layer and the second electrode layer at the isolation test structure 4, and respectively form a light-emitting test section 10 and a test electrode 11 in the test opening 12, and extend the test electrode 11 to be electrically connected to the first isolation test section 41 and the second isolation test section 42.

[0173] In summary, the present application sets the isolation test structure 4 to include a first isolation test part 41 and a second isolation test part 42 that are spaced apart from each other, and electrically connects the first isolation test part 41 and the second isolation test part 42 through the test electrode 11. This allows the overlapping electrode between the isolation test structure 4 and the test electrode 11 to be tested more accurately and directly, thereby more accurately and directly evaluating the overlapping effect between the isolation structure 13 and the cathode of the display area AA, thereby improving the performance of the display panel motherboard.

[0174] In some possible implementations, the present application also provides a method for preparing a display panel motherboard, see Fig.15 , the preparation method comprises:

[0175] S10: providing a substrate 6;

[0176] S11: At least one test element group 1 is formed on one side of the substrate 6, the test element group 1 includes a test electrode 11 and an isolation test structure 4 arranged around the test electrode 11, the isolation test structure 4 includes at least two isolation test parts 4001 arranged at intervals from each other, the orthographic projections of at least two isolation test parts 4001 on the substrate 6 do not overlap with each other, and the test electrode 11 is electrically connected to at least one isolation test part 4001.

[0177] The test electrode 11 in the display panel motherboard prepared by the method of this embodiment is made of the same material as the cathode of the display area AA, and the isolation test structure 4 is made of the same material as the isolation structure 13 of the display area AA. Therefore, based on the overlapping resistance between the isolation test structure 4 and the test electrode 11, the overlapping resistance between the isolation structure 13 and the cathode can be known, and based on the overlapping resistance between the isolation structure 13 and the cathode, the overlapping effect of the isolation structure 13 and the cathode can be more accurately evaluated.

[0178] For example, the overlap resistance per unit overlap area between the isolation test structure 4 and the test electrode 11 can be calculated based on the overlap resistance between the isolation test structure 4 and the test electrode 11. Since the material of the isolation test structure 4 is the same as that of the isolation structure 13, and the material of the test electrode 11 is the same as that of the cathode, the overlap resistance per unit overlap area between the isolation test structure 4 and the test electrode 11 is equal to the overlap resistance per unit overlap area between the isolation structure 13 and the cathode. Therefore, the overlap resistance between the isolation structure 13 and the cathode can be calculated more directly and accurately.

[0179] For some possible implementations, see Figure 1 and Fig.16 The display panel motherboard includes a display area AA and a non-display area AB at least partially surrounding the display area AA, the non-display area AB includes a test area AC, the test element group 1 is located in the test area AC, and the isolation test structure 4 includes a first isolation test part 41 and a second isolation test part 41 that are spaced apart from each other. The step of forming at least one test element group 1 on one side of the substrate 6 includes:

[0180] S111 : forming a first insulating material layer 25 on one side of the substrate 6 .

[0181] See also Fig.17 A first insulating material layer 25 is formed on one side of the substrate 6. The first insulating material layer 25 is made of the same material as the second planarization layer 21 of the display panel motherboard, which is an organic material and has an insulating effect.

[0182] S112 : forming a first protrusion 92 on the first insulating material layer 25 by using a half-tone mask to form a first insulating layer 9 .

[0183] See also Fig.18A first protrusion 92 is formed on the first insulating material layer 25 through a half-tone mask, and the first protrusion 92 extends in a direction away from the substrate 6 .

[0184] S113: forming a third insulating layer 8 on a side of the first insulating layer 9 away from the substrate 6, the third insulating layer 8 forming a second protruding portion 82 at the first protruding portion 92; wherein the third insulating layer 8 is a pixel defining layer.

[0185] See also Fig.19 A third insulating layer 8 is formed on the side of the first insulating layer 9 away from the substrate 6 . Since there is a first protrusion 92 on the first insulating layer 9 , a second protrusion 82 is formed on the third insulating layer 8 at the first protrusion 92 .

[0186] S114: An isolation conductive layer 7 is formed on a side of the third insulating layer 8 away from the substrate 6, and the patterned isolation conductive layer 7 forms an isolation test structure 4. The isolation test structure 4 is provided with a test opening 12. The isolation test structure 4 forms a first isolation test portion 41 and a second isolation test portion 42 spaced apart from each other at the second protrusion 82, and the orthographic projection of the first isolation test portion 41 on the substrate 6 is outside the orthographic projection of the second isolation test portion 42 on the substrate 6.

[0187] See also Fig. 20 An isolation conductive layer 7 is formed on the side of the third insulating layer 8 away from the substrate 6. The isolation conductive layer 7 includes an isolation structure 13 and an isolation test structure 4. The isolation structure 13 is located in the display area AA, and the isolation test structure 4 is located in the test area AC. The isolation structure 13 and the isolation test structure 4 are made of the same material.

[0188] See also Fig.21 , the isolation test structure 4 on the side of the second protrusion 82 away from the substrate 6 can be removed by etching, so that the isolation test structure 4 is separated by the second protrusion 82 to form a first isolation test part 41 and a second isolation test part 42, and the first isolation test part 41 and the second isolation test part 42 are insulated by the second protrusion 82.

[0189] S115 : forming a second insulating layer 5 on a side of the second protruding portion 82 away from the substrate 6 , wherein the second insulating layer 5 covers at least a portion of the first isolation test portion 41 and the second isolation test portion 42 .

[0190] Please see again Figure 5 A second insulating layer 5 is formed on the side of the second protrusion 82 away from the substrate 6. The material of the second insulating layer 5 can be the same as the material of the first packaging layer 22 of the display panel motherboard. The second packaging layer 23 can protect the exposed parts of the first isolation test part 41 and the second isolation test part 42.

[0191] S116 : A light emitting test portion 10 and a test electrode 11 are sequentially formed on a side of the test opening 12 away from the substrate 6 . The test electrode 11 extends to be electrically connected to the first isolation test portion 41 and the second isolation test portion 42 .

[0192] Please see again Figure 3 A light emitting test portion 10 and a test electrode 11 are sequentially formed on a side of the test opening 12 away from the substrate 6 .

[0193] When forming the light-emitting functional layer, the light-emitting functional layer will be separated by the isolation structure 13 to form a plurality of light-emitting portions 16 spaced apart and located in the isolation opening 14 , and will also be separated by the isolation conductive layer 7 to form a light-emitting test portion 10 located in the test opening 12 .

[0194] When forming the second electrode layer, the second electrode layer will be separated by the isolation structure 13 to form a plurality of second electrodes 17 spaced apart and located in the isolation opening 14. The isolation structure 13 includes a conductive material, and the second electrode 17 is electrically connected to the isolation structure 13. The second electrode layer will also be separated by the isolation conductive layer 7 to form a test electrode 11 located in the test opening 12. The first isolation test section 41 and the second isolation test section 42 both include a conductive material, and the test electrode 11 extends to be electrically connected to the first isolation test section 41 and the second isolation test section 42. A first electrode 15, a light-emitting section 16 and a second electrode 17 form a light-emitting unit 18. Among them, the first electrode 15 is an anode, and the second electrode 17 is a cathode.

[0195] In this way, when the light-emitting functional layer is formed, the light-emitting portion 16 can be formed in the display area AA and the light-emitting test portion 10 can be formed in the test area AC at the same time; when the second electrode layer is formed, the second electrode 17 can be formed in the display area AA and the test electrode 11 can be formed in the test area AC at the same time, so there is no need to use a special process to set the light-emitting test portion 10 and the test electrode 11, thereby reducing the cost of forming the light-emitting test portion 10 and the test electrode 11.

[0196] In this way, the first isolation test part 41 and the second isolation test part 42 of the display panel motherboard formed by the method of this embodiment can be more easily separated, so that the overlapping resistance between the isolation structure 13 and the cathode can be calculated more directly and accurately, and then the overlapping effect of the isolation structure 13 and the cathode of the display area AA can be evaluated more directly and accurately.

[0197] See also Fig. 22 , remove the test area AC. The test area AC of the display panel motherboard will eventually be removed.

[0198] For some possible implementations, see Fig.23The present application also provides a method for testing a display panel motherboard, wherein the display panel motherboard includes the display panel motherboard in the present application, and the testing method includes:

[0199] S20: Obtain the sum of the lap resistances between the test electrode 11 and any two isolated test parts 4001 .

[0200] Please see again Figure 2 and Figure 3 For example, the resistor display panel motherboard can be electrically connected to the pin 2 of the test trace 3, and the sum of the lap resistances of the first isolation test section 41 and the second isolation test section 42 and the test electrode 11 can be directly tested through the resistor display panel motherboard.

[0201] S21 : Based on the sum of the overlapping resistances between the test electrode 11 and any two isolated test parts 4001 , determine the overlapping effect between the isolation structure 13 and the second electrode 17 in the display area AA of the display panel motherboard.

[0202] Since the test electrode 11 is made of the same material as the cathode of the display area AA, and the isolation test structure 4 is made of the same material as the isolation structure 13 of the display area AA, the overlap resistance between the isolation structure 13 and the cathode can be determined based on the sum of the overlap resistances between the test electrode 11 and any two isolation test parts 4001, for example, the sum of the overlap resistances between the test electrode 11 and the first isolation test part 41 and the second isolation part 41. Based on the overlap resistance between the isolation structure 13 and the cathode, the overlap effect between the isolation structure 13 and the cathode can be more accurately evaluated.

[0203] For example, the overlap resistance per unit overlap area between the isolation test structure 4 and the test electrode 11 can be calculated based on the overlap resistance between the isolation test structure 4 and the test electrode 11. Since the material of the isolation test structure 4 is the same as that of the isolation structure 13, and the material of the test electrode 11 is the same as that of the cathode, the overlap resistance per unit overlap area between the isolation test structure 4 and the test electrode 11 is equal to the overlap resistance per unit overlap area between the isolation structure 13 and the cathode. Therefore, the overlap resistance between the isolation structure 13 and the cathode can be calculated more directly and accurately.

[0204] Preferably, see Fig.24When multiple isolated test parts 4001 are included, any two isolated test parts 4001 are selected to form a circuit to be tested with the test electrode 11, and the test angle β is determined according to the connection angle between the two isolated test parts 4001 and the center of the test electrode 11; based on the result of the test circuit, the overlapping effect of the isolation structure 13 and the second electrode 17 in the test angle β of the light-emitting unit corresponding to the test component is determined. The light-emitting part material of the light-emitting unit corresponding to the test component is the same as the test light-emitting part material, so that the overlapping effect of the isolation structure 13 and the second electrode 17 can be evaluated by testing the overlapping resistance between any two isolated test parts 4001 and the test electrode 11.

[0205] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0206] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A display panel motherboard, characterized in that: The display panel motherboard comprises: substrate; At least one test element group is located on one side of the substrate, the test element group includes a test electrode and an isolation test structure arranged around the test electrode, the isolation test structure includes at least two isolation test parts arranged at intervals from each other, and the orthographic projections of at least two isolation test parts on the substrate do not overlap with each other.

2. The display panel motherboard according to claim 1, characterized in that: The test element group further includes at least two partition parts, wherein the partition part is arranged between two adjacent isolation test parts, and the isolation test part and the partition part are arranged around the test electrode; Preferably, the partition portion comprises an insulating material; Preferably, at least two of the isolation test parts and at least two of the partition parts are continuously arranged to form an annular test opening, and the test electrode is arranged in the test opening.

3. The display panel motherboard according to claim 1, characterized in that: The display panel motherboard also includes a conductive layer located on a side of the test element group close to the substrate, the conductive layer includes a plurality of test traces, any one of the test element groups is correspondingly provided with at least two of the test traces, and the isolation test parts are respectively electrically connected to one of the test traces; Preferably, the display panel motherboard further comprises a first insulating layer located on a side of the conductive layer away from the substrate, and the test element group is located on a side of the first insulating layer away from the substrate; Preferably, along a direction perpendicular to the substrate, a plurality of first test vias are provided on the first insulating layer, the first test vias expose at least a portion of the test traces, and the isolation test portion is electrically connected to the test traces through the first test vias; Preferably, the first insulating layer comprises a first protruding portion extending in a direction away from the substrate, and at least a portion of the orthographic projection of the first protruding portion on the substrate is located between the orthographic projections of adjacent isolation test portions on the substrate; Preferably, along a side away from the substrate, the first protrusion extends to a side of the test element group away from the substrate to form a partition portion between adjacent isolation test structures; Preferably, the test trace electrically connected to the isolation test portion is electrically connected to at least two pins.

4. The display panel motherboard according to claim 3, characterized in that: The display panel motherboard further comprises a third insulating layer located on a side of the first insulating layer away from the substrate, wherein the third insulating layer is provided with a plurality of second test vias exposing at least a portion of the test traces in a direction perpendicular to the substrate, and the isolation test portion is electrically connected to the test traces through the second test vias and the first test vias in sequence; Preferably, the third insulating layer is further provided with a partition opening, and at least part of the first protrusion is provided in the partition opening; Preferably, the orthographic projection of the second test via hole on the substrate covers the orthographic projection of the first test via hole on the substrate.

5. The display panel motherboard according to claim 1, characterized in that: The display panel motherboard further comprises a first insulating layer and a third insulating layer sequentially arranged along a side away from the substrate, and the test element group is located on a side of the third insulating layer away from the substrate; Preferably, the first insulating layer includes a first protrusion extending in a direction away from the substrate, the third insulating layer includes a second protrusion located on a side of the first protrusion away from the substrate, the second protrusion extending to a side of the test element group away from the substrate along the side away from the substrate, and the first protrusion and the second protrusion form a partition located between adjacent isolation test structures; Preferably, the orthographic projections of at least part of the first protrusion and at least part of the second protrusion on the substrate are both located between the orthographic projections of adjacent isolation test parts on the substrate; Preferably, the display panel motherboard further comprises a second insulating layer located at a side of the second protrusion away from the substrate, the second insulating layer covers at least a portion of the isolation test portion, and an orthographic projection of the second protrusion on the substrate is located within the orthographic projection range of the second insulating layer on the substrate; Preferably, the second protrusion contacts side surfaces of two adjacent isolation test portions.

6. The display panel motherboard according to claim 1, characterized in that: The display panel motherboard further comprises a first insulating layer and a third insulating layer which are sequentially arranged at a side away from the substrate, and the test element group is located at a side of the third insulating layer away from the substrate; Preferably, the third insulating layer comprises a second protrusion extending in a direction away from the substrate, and the second protrusion extends to a side of the test element group away from the substrate to form a partition portion located between adjacent isolation test structures; Preferably, at least part of the orthographic projection of the second protruding portion on the substrate is located between the orthographic projections of adjacent isolated test portions on the substrate; Preferably, the second protrusion contacts the side surfaces of two adjacent isolation test portions; Preferably, the display panel motherboard further comprises a second insulating layer located on a side of the second protruding portion away from the substrate, and the second insulating layer covers at least a portion of the isolation test portion.

7. The display panel motherboard according to claim 4, characterized in that: At least a portion of the third insulating layer extends to a side wall of the first test via hole; Preferably, the third insulating layer covers the side wall of the first test via hole; Preferably, the orthographic projection of the second test hole on the substrate is located within the orthographic projection of the first test hole on the substrate; Preferably, the center of the orthographic projection of the first test via hole on the substrate coincides with the center of the orthographic projection of the second test via hole on the substrate; Preferably, the third insulating layer extends to a display area of ​​the display panel motherboard, and the third insulating layer further includes a pixel opening located in the display area.

8. The display panel motherboard according to claim 3, characterized in that: It also includes a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer stacked in sequence in a direction away from the substrate, and the test trace is located in any one of the first conductive layer, the second conductive layer, the third conductive layer or the fourth conductive layer; Preferably, the test trace is located in the fourth conductive layer; Preferably, a first planarization layer is provided between the third conductive layer and the fourth conductive layer, a second planarization layer is provided on a side of the fourth conductive layer away from the substrate, the first insulating layer includes the second planarization layer, and the first test via is arranged on the second planarization layer.

9. The display panel motherboard according to claim 8, characterized in that: The test element group further includes a light emitting test portion located in the test opening, and the light emitting test portion is located on a side of the test electrode close to the substrate; Preferably, the display panel motherboard comprises a display panel and a test area located around the display panel, the test element group is arranged in the test area, and the display panel motherboard further comprises an isolation structure located on the display panel, the isolation structure encloses to form an isolation opening; Preferably, the isolation structure and the isolation test structure are arranged at the same layer; Preferably, the shape of the orthographic projection of the test opening on the substrate is the same as the shape of the orthographic projection of the isolation opening on the substrate; Preferably, an area of ​​an orthographic projection of the test opening on the substrate is N times an area of ​​an orthographic projection of the isolation opening on the substrate, wherein N is greater than or equal to 1.

10. The display panel motherboard according to claim 9, characterized in that: The display panel motherboard further includes a light emitting unit at least partially located in the isolation opening; Preferably, the light-emitting unit comprises a first electrode, a light-emitting portion, and a second electrode which are sequentially stacked in a direction away from the substrate, and the second electrode is electrically connected to a side of the isolation structure facing the isolation opening; Preferably, the light emitting part and the light emitting testing part are arranged on the same layer; Preferably, the second electrode is arranged in the same layer as the test electrode; Preferably, the light-emitting unit includes a first light-emitting unit and a second light-emitting unit having different light-emitting colors, the test element group includes a first test component for testing the first light-emitting unit and a second test component for testing the second light-emitting unit, the light-emitting test part of the first test component is made of the same material as the light-emitting part of the first light-emitting unit, and the light-emitting test part of the second test component is made of the same material as the light-emitting part of the second light-emitting unit.

11. The display panel motherboard according to claim 10, characterized in that: The display panel motherboard further comprises a first encapsulation layer located at a side of the light emitting unit away from the substrate, wherein the first encapsulation layer comprises a plurality of encapsulation units arranged at intervals; Preferably, at least part of the packaging unit extends from a side surface of the isolation structure to a side of the isolation structure away from the substrate, and the side surface of the isolation structure is a surface of the isolation structure facing the isolation opening; Preferably, at least part of the encapsulation unit extends from a side of the isolation structure to a side of the isolation structure away from the substrate; Preferably, adjacent packaging units are arranged at intervals on a side of the isolation structure away from the substrate; Preferably, there is a gap between the packaging unit located on a side of the isolation structure away from the substrate and a side of the isolation structure away from the substrate; Preferably, the isolation structure comprises a first isolation portion and a second isolation portion which are sequentially stacked in a direction away from the substrate, and an orthographic projection of a side of the first isolation portion away from the substrate on the substrate is located within an orthographic projection of the second isolation portion on the substrate; Preferably, the second electrode of the light-emitting unit is electrically connected to the first isolation portion; and / or the isolation structure further comprises a third isolation portion located on a side of the first isolation portion facing the substrate, and the second electrode of the light-emitting unit is electrically connected to the third isolation portion; Preferably, the material of the third isolation portion includes molybdenum metal; and / or the material of the first isolation portion includes aluminum metal; and / or the material of the second isolation portion includes titanium metal.

12. The display panel motherboard according to any one of claims 1 to 11, characterized in that: The isolation test structure comprises a first test portion and a second test portion which are sequentially stacked in a direction away from the substrate, the orthographic projection of a side of the first test portion away from the substrate on the substrate is located within the orthographic projection of the second test portion on the substrate, and the test electrode extends to be electrically connected to the first test portion; Preferably, the isolation test structure includes a first isolation test part and a second isolation test part that are spaced apart from each other, and the test element group also includes a first partition part and a second partition part located between the first isolation test part and the second isolation test part, the first isolation test part, the first partition part, the second isolation test part and the second partition part are arranged in sequence and enclosed to form a test opening, and the test electrode is arranged in the test opening.

13. A method for preparing a display panel motherboard, characterized in that: The preparation method comprises: providing a substrate; At least one test element group is formed on one side of the substrate, the test element group includes a test electrode and an isolation test structure arranged around the test electrode, the isolation test structure includes at least two isolation test parts arranged at intervals from each other, and the orthographic projections of at least two isolation test parts on the substrate do not overlap with each other.

14. The method for preparing a display panel motherboard according to claim 13, characterized in that: The step of forming at least one test element group on one side of the substrate comprises: forming a first insulating material layer on one side of the substrate; Forming a first protrusion on the first insulating material layer by using a half-tone mask to form a first insulating layer; forming a third insulating layer on a side of the first insulating layer away from the substrate, wherein the third insulating layer forms a second protruding portion at the first protruding portion; forming an isolation conductive layer on a side of the third insulating layer away from the substrate, patterning the isolation conductive layer to form an isolation test structure, wherein the isolation test structure forms a first isolation test portion and a second isolation test portion spaced apart from each other at the second protruding portion, and an orthographic projection of the first isolation test portion on the substrate is outside an orthographic projection of the second isolation test portion on the substrate; forming a second insulating layer on a side of the second protruding portion away from the substrate, wherein the second insulating layer covers at least a portion of the first isolation test portion and the second isolation test portion; A light emitting test portion and a test electrode are sequentially formed in the test opening on a side away from the substrate, wherein the test electrode extends to be electrically connected to the first isolation test portion and the second isolation test portion; Preferably, the display panel motherboard comprises a display panel and a test area, and the test component is arranged in the test area; The display panel further comprises an isolation structure located at one side of the substrate, wherein the isolation structure is arranged at the same layer as the first isolation test part and the second isolation test part; The method for preparing the display panel motherboard further includes: The isolation test structure is formed by the isolation conductive layer, and the isolation structure and the isolation opening are formed at the same time; the light emitting test part is formed, and the light emitting part is formed in the isolation opening at the same time; forming the test electrode and forming a second electrode in the isolation opening at the same time; Preferably, the preparation method further comprises: Testing the test element group, and determining the overlapping effect of the second electrode and the isolation structure according to the test result of the test element group; After the test is completed, the test area is cut to separate the display panel.

15. A method for testing a display panel motherboard, characterized in that: The display panel motherboard comprises the display panel motherboard according to any one of claims 1 to 12, and the testing method comprises: Obtaining the sum of the lap resistances of the test electrode and any two of the isolated test parts; Determining the overlapping effect of the isolation structure of the display area of ​​the display panel motherboard and the second electrode based on the sum of the overlapping resistances of the test electrode and any two of the isolation test parts; Preferably, any two of the isolated test parts and the test electrode are selected to form a circuit to be tested, and a test angle is determined according to a connection angle between the two isolated test parts and the center of the test electrode; Based on the result of the test circuit, the overlapping effect of the isolation structure and the second electrode of the corresponding light-emitting unit at the test angle is determined.

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