Storage device

Abstract

A memory device includes: a first insulator on a substrate; an oxide semiconductor covering at least a portion of the first insulator; a first conductor and a second conductor on the oxide semiconductor; a second insulator on the first conductor; a third insulator on the second conductor; a third conductor on the second insulator; a fourth conductor on the third insulator; a fourth insulator disposed on the third conductor and the fourth conductor and having a first opening overlapping between the first conductor, the second insulator and the third conductor and between the second conductor, the third insulator and the fourth conductor; a fifth insulator disposed in the first opening; a fifth conductor disposed on the fifth insulator; a sixth conductor disposed in a second opening formed in the fourth insulator and contacting a top surface of the third conductor; and a seventh conductor disposed in a third opening formed in the fourth insulator, the third insulator, and the fourth conductor and in contact with a top surface of the second conductor, in which a height of the first insulator is longer than a width of the first insulator, and a top surface of the first insulator is in contact with the fifth insulator.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device, a storage device, and an electronic device using an oxide semiconductor. Another embodiment of the present invention relates to a method for manufacturing the semiconductor device and the storage device.

[0002] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. As an example of the technical field of one embodiment of the present invention, a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, an electronic device, a lighting device, an input device (e.g., a touch sensor), an input-output device (e.g., a touch panel), a driving method of the above-mentioned device, or a manufacturing method of the above-mentioned device can be cited.

[0003] Note that in this specification, etc., semiconductor devices refer to all devices that can work by utilizing semiconductor characteristics. In addition to semiconductor elements such as transistors, semiconductor circuits, computing devices, or storage devices are also a form of semiconductor devices. Sometimes it can be said that display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, storage devices, semiconductor circuits, camera devices, electronic devices, etc. include semiconductor devices. Background Art

[0004] In recent years, semiconductor devices have been developed, and LSI, CPU, memory, etc. are mainly used for semiconductor devices. CPU is a collection of semiconductor elements including a semiconductor integrated circuit (including at least transistors and memory) formed by processing a semiconductor wafer into a chip and having electrodes as connection terminals.

[0005] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards (eg, printed wiring boards) and are used as one of the components of various electronic devices.

[0006] In addition, the technology of forming a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. The transistor is widely used in electronic devices such as integrated circuits (ICs) and image display devices (simply recorded as display devices). As a semiconductor thin film that can be applied to transistors, silicon-based semiconductor materials are widely known. As other materials, oxide semiconductors have attracted attention.

[0007] In addition, it is known that a transistor using an oxide semiconductor has extremely low leakage current in a non-conducting state. For example, Patent Document 1 has disclosed a low-power CPU that utilizes the low leakage current characteristic of a transistor using an oxide semiconductor. In addition, for example, Patent Document 2 has disclosed a storage device that can retain stored content for a long time by utilizing the low leakage current characteristic of a transistor using an oxide semiconductor.

[0008] In recent years, as electronic devices have become smaller and lighter, the demand for further high-density integrated circuits has increased. In addition, there is a demand to improve the productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technology in which a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film are stacked and a plurality of memory cells are arranged in an overlapping manner, thereby increasing the density of the integrated circuit. In addition, for example, as shown in Patent Document 4, a technology for vertically configuring the channel of a transistor using an oxide semiconductor film to achieve high density of the integrated circuit is also disclosed.

[0009] [Prior technical literature]

[0010] [Patent Document]

[0011] [Patent Document 1] Japanese Patent Application Publication No. 2012-257187

[0012] [Patent Document 2] Japanese Patent Application Publication No. 2011-151383

[0013] [Patent Document 3] International Patent Application Publication No. 2021 / 053473

[0014] [Patent Document 4] Japanese Patent Application Publication No. 2013-211537

[0015] [Non-patent literature]

[0016] [Non-patent document 1] M. Oota et al., “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig., 2019, pp. 50-53 Summary of the invention

[0017] Technical problem to be solved by the invention

[0018] One of the purposes of one embodiment of the present invention is to provide a storage device that can be miniaturized or highly integrated. Another purpose of one embodiment of the present invention is to provide a storage device with a large storage capacity. Another purpose of one embodiment of the present invention is to provide a storage device with a fast operating speed. Another purpose of one embodiment of the present invention is to provide a storage device with good electrical characteristics. Another purpose of one embodiment of the present invention is to provide a storage device with less deviation in the electrical characteristics of transistors. Another purpose of one embodiment of the present invention is to provide a highly reliable storage device. Another purpose of one embodiment of the present invention is to provide a storage device with a large on-state current. Another purpose of one embodiment of the present invention is to provide a storage device with low power consumption. Another purpose of one embodiment of the present invention is to provide a novel storage device. Another purpose of one embodiment of the present invention is to provide a novel method for manufacturing a storage device.

[0019] Note that the description of these purposes does not prevent the existence of other purposes. One embodiment of the present invention does not need to achieve all of the above purposes. Purposes other than the above can be extracted from the description of the specification, drawings, and claims.

[0020] Solutions to technical problems

[0021] One embodiment of the present invention is a storage device, comprising: a first insulator on a substrate; an oxide semiconductor covering at least a portion of the first insulator; a first conductor and a second conductor on the oxide semiconductor; a second insulator on the first conductor; a third insulator on the second conductor; a third conductor on the second insulator; a fourth conductor on the third insulator; a fourth insulator arranged on the third conductor and the fourth conductor and having a first opening overlapping the first conductor, the second insulator and the third conductor and the second conductor, the third insulator and the fourth conductor; a fifth insulator arranged in the first opening and arranged on the first insulator and on the oxide semiconductor; a fifth conductor arranged in the first opening and arranged on the fifth insulator; a sixth conductor arranged in the second opening formed in the fourth insulator and in contact with the top surface of the third conductor; and a seventh conductor arranged in the third opening formed in the fourth insulator, the third insulator and the fourth conductor and in contact with the top surface of the second conductor. When viewed from a cross section in the channel width direction, the height of the first insulator is longer than the width of the first insulator, and the top surface of the first insulator is in contact with the fifth insulator in a region that does not overlap with the first conductor and the second conductor.

[0022] In the above memory device, preferably, a height of the first insulator when viewed in a cross section in a channel width direction is not less than 2 times and not more than 20 times a width of the first insulator.

[0023] In the above memory device, preferably, the first conductor is used as one of a source electrode and a drain electrode of the transistor, the second conductor is used as the other of the source electrode and the drain electrode of the transistor, and the fifth conductor is used as a gate electrode of the transistor.

[0024] In the above storage device, preferably, the first conductor is used as one of a pair of electrodes of the capacitor element, the third conductor is used as the other of the pair of electrodes of the capacitor element, and the second insulator is used as a dielectric of the capacitor element.

[0025] In the above-mentioned memory device, preferably, the second insulator has a stacked structure in which a zirconium oxide film, an aluminum oxide film, and a zirconium oxide film are stacked in this order.

[0026] In the above storage device, preferably, a sixth insulator is provided between the seventh conductor and the fourth insulator, and the seventh conductor is insulated from the fourth conductor by the sixth insulator.

[0027] In the above-mentioned storage device, preferably, when viewed from a cross section in the channel width direction, on one side of the first insulator, the oxide semiconductor and the fifth conductor are opposite to each other with the fifth insulator sandwiched therebetween, and on the other side of the first insulator, the oxide semiconductor and the fifth conductor are opposite to each other with the fifth insulator sandwiched therebetween.

[0028] In the above-mentioned storage device, it is preferred that, when viewed from a cross section in the channel width direction, on one side of the first insulator, the first conductor and the third conductor are opposed to each other with the second insulator sandwiched therebetween, and on the other side of the first insulator, the first conductor and the third conductor are opposed to each other with the second insulator sandwiched therebetween.

[0029] In the above memory device, the oxide semiconductor preferably includes one or more selected from In, Ga, and Zn.

[0030] Effects of the Invention

[0031] According to one embodiment of the present invention, a storage device that can be miniaturized or highly integrated can be provided. In addition, according to one embodiment of the present invention, a storage device with a large storage capacity can be provided. In addition, according to one embodiment of the present invention, a storage device with a fast operating speed can be provided. In addition, according to one embodiment of the present invention, a storage device with high reliability can be provided. In addition, according to one embodiment of the present invention, a storage device with less deviation in the electrical characteristics of transistors can be provided. In addition, according to one embodiment of the present invention, a storage device with good electrical characteristics can be provided. In addition, according to one embodiment of the present invention, a storage device with a large on-state current can be provided. In addition, according to one embodiment of the present invention, a storage device with low power consumption can be provided. In addition, according to one embodiment of the present invention, a novel storage device can be provided. In addition, according to one embodiment of the present invention, a novel method for manufacturing a storage device can be provided.

[0032] Note that the description of these effects does not prevent the existence of other effects. One embodiment of the present invention does not necessarily have all of the above effects. Effects other than the above can be extracted from the description of the specification, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1A is a plan view showing an example of a storage device. Figures 1B to 1D is a cross-sectional view showing an example of a storage device.

[0034] Figure 2 is a cross-sectional view showing an example of a storage device.

[0035] Figure 3A and Figure 3B is a cross-sectional view showing an example of a storage device.

[0036] Figure 4A and Figure 4B is a cross-sectional view showing an example of a storage device.

[0037] Figure 5A and Figure 5B is a cross-sectional view showing an example of a storage device.

[0038] Fig. 6A is a plan view showing an example of a storage device. FIG. 6B to FIG. 6D is a cross-sectional view showing an example of a storage device.

[0039] Fig. 7A is a plan view showing an example of a storage device. FIG. 7B to FIG. 7D is a cross-sectional view showing an example of a storage device.

[0040] Fig. 8A is a plan view showing an example of a storage device. Figure 8B and Figure 8C is a cross-sectional view showing an example of a storage device.

[0041] Fig.9A is a plan view showing an example of a storage device. FIG. 9B to FIG. 9D is a cross-sectional view showing an example of a storage device.

[0042] Fig. 10A is a plan view showing an example of a storage device. FIG. 10B to FIG. 10D is a cross-sectional view showing an example of a storage device.

[0043] Fig.11A and Fig. 11B is a cross-sectional view showing an example of a storage device.

[0044] Fig. 12A This is a plan view showing an example of a method for manufacturing a storage device. FIG. 12B to FIG. 12D is a cross-sectional view showing an example of a method for manufacturing a storage device.

[0045] Fig.13A This is a plan view showing an example of a method for manufacturing a storage device. FIG. 13B to FIG. 13D is a cross-sectional view showing an example of a method for manufacturing a storage device.

[0046] Fig.14A This is a plan view showing an example of a method for manufacturing a storage device. FIG. 14B to FIG. 14D is a cross-sectional view showing an example of a method for manufacturing a storage device.

[0047] Fig.15A This is a plan view showing an example of a method for manufacturing a storage device. FIG. 15B to FIG. 15D is a cross-sectional view showing an example of a method for manufacturing a storage device.

[0048] Fig.16A This is a plan view showing an example of a method for manufacturing a storage device. FIG. 16B to FIG. 16D is a cross-sectional view showing an example of a method for manufacturing a storage device.

[0049] Fig.17A This is a plan view showing an example of a method for manufacturing a storage device. FIG. 17B to FIG. 17D is a cross-sectional view showing an example of a method for manufacturing a storage device.

[0050] Fig.18A This is a plan view showing an example of a method for manufacturing a storage device. FIG. 18B to FIG. 18D is a cross-sectional view showing an example of a method for manufacturing a storage device.

[0051] Fig.19A This is a plan view showing an example of a method for manufacturing a storage device. FIG. 19B to FIG. 19D is a cross-sectional view showing an example of a method for manufacturing a storage device.

[0052] Fig. 20A This is a plan view showing an example of a method for manufacturing a storage device. FIG. 20B to FIG. 20D is a cross-sectional view showing an example of a method for manufacturing a storage device.

[0053] Fig.21A This is a plan view showing an example of a method for manufacturing a storage device. FIG. 21B to FIG. 21D is a cross-sectional view showing an example of a method for manufacturing a storage device.

[0054] Fig.22A This is a plan view showing an example of a method for manufacturing a storage device. FIG. 22B to FIG. 22D is a cross-sectional view showing an example of a method for manufacturing a storage device.

[0055] Fig.23 is a block diagram showing an example of a storage device.

[0056] Fig.24A and Fig. 24B 1 is a schematic diagram and a circuit diagram showing an example of a storage device.

[0057] Fig.25A and Fig.25B is a schematic diagram showing an example of a storage device.

[0058] Fig.26 is a circuit diagram showing an example of a storage device.

[0059] Fig. 27 is a cross-sectional view showing an example of a storage device.

[0060] Fig.28 is a cross-sectional view showing an example of a storage device.

[0061] Fig.29A and Fig.29B is a diagram showing an example of a semiconductor device.

[0062] Fig. 30A and Fig. 30B It is a diagram showing an example of an electronic component.

[0063] Fig.31A and Fig.31B is a diagram showing an example of an electronic device, FIG. 31C to FIG. 31E This is a diagram showing an example of a large computer.

[0064] Fig.32 is a diagram showing an example of space equipment.

[0065] Fig.33 is a diagram showing an example of a storage system applicable to a data center. DETAILED DESCRIPTION

[0066] The embodiments are described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and a person skilled in the art can easily understand that the method and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments shown below.

[0067] Note that in the inventive structure described below, the same reference numerals are used in different drawings to represent the same parts or parts with the same function, and repeated descriptions are omitted. In addition, when representing parts with the same function, the same hatching is sometimes used without adding a reference numeral.

[0068] In addition, for ease of understanding, the positions, sizes, and ranges of various components shown in the drawings may not represent their actual positions, sizes, and ranges. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, and ranges disclosed in the drawings.

[0069] In addition, in particular, in a top view (also called a plan view) or a perspective view, in order to facilitate understanding of the invention, description of some components may be omitted. Also, description of some hidden lines may be omitted.

[0070] Note that in this specification, etc., ordinal numbers such as "first" and "second" are added for convenience, but they do not limit the number of components or the order of components (for example, the order of processes or the order of stacking). In addition, the ordinal numbers added to components in one part of this specification may not be consistent with the ordinal numbers added to the components in other parts of this specification or claims.

[0071] In addition, depending on the situation or condition, "film" and "layer" may be interchanged. For example, "conductive layer" may be interchanged with "conductive film". In addition, "insulating film" may be interchanged with "insulating layer". In addition, depending on the situation or condition, "conductive body" may be interchanged with "conductive layer" or "conductive film". In addition, depending on the situation or condition, "insulator" may be interchanged with "insulating layer" or "insulating film".

[0072] In this specification, etc., "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°. Therefore, a state where the angle is greater than -5° and less than 5° is also included. "Approximately parallel" refers to a state where the angle formed by two straight lines is greater than -30° and less than 30°. In addition, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°. Therefore, a state where the angle is greater than 85° and less than 95° is also included. "Approximately perpendicular" refers to a state where the angle formed by two straight lines is greater than 60° and less than 120°.

[0073] The opening includes, for example, a groove, a slit, etc. In addition, a region where the opening is formed may be referred to as an opening portion.

[0074] Furthermore, although the drawings used in the embodiments in this specification show the case where the side walls of the openings of the insulator are perpendicular or substantially perpendicular to the substrate surface or the formed surface, the side walls may also be tapered.

[0075] Note that in this specification, etc., a tapered shape refers to a shape in which at least a portion of the side surface of a component is inclined relative to a substrate surface or a formed surface. For example, it refers to a shape having a region where the angle formed by the inclined side surface and the substrate surface or the formed surface (hereinafter, sometimes also referred to as a taper angle) is less than 90°. Note that the side surface and the substrate surface of a component do not necessarily have to be completely flat, and may be a nearly planar shape with a slight curvature or a nearly planar shape with fine concave and convex shapes.

[0076] In addition, in this specification, etc., "high consistency or approximately consistency" refers to a structure in which the height from a reference plane (for example, a flat surface such as a substrate surface) in a cross section is equal. For example, in the manufacturing process of a semiconductor device, a flattening process (typically a CMP process) is sometimes performed to expose the surface of a single layer or multiple layers. At this time, the processed surface treated by the CMP process has a structure with the same height from the reference plane. However, depending on the processing device, processing method or material of the processed surface used in the CMP process, the heights of multiple layers may sometimes be different. In this specification, etc., this situation is also regarded as "high consistency or approximately consistency". For example, the following situation is also referred to as "high consistency or approximately consistency": including two layers (here, the first layer and the second layer) with different heights from the reference plane, wherein the difference between the top surface height of the first layer and the top surface height of the second layer is less than 20nm.

[0077] In this specification, etc., "side ends are consistent or approximately consistent" means that at least a portion of the outline of each layer in the stack overlaps when viewed from above. For example, it refers to the case where the upper layer and the lower layer are processed by the same mask pattern or a portion of the same mask pattern in the manufacturing process of the semiconductor device. However, strictly speaking, sometimes the outlines do not overlap and the outline of the upper layer is located inside the end of the lower layer or the outline of the upper layer is located outside the end of the lower layer, and these cases are also included in the case of "side ends are approximately consistent".

[0078] (Implementation Method 1)

[0079] In this embodiment, a memory device including an oxide semiconductor layer and a method for manufacturing the memory device are described with reference to FIGS. 1 to 22 .

[0080] <Configuration Example of Storage Device>

[0081] An example of the structure of the storage device will be described with reference to FIGS. 1 to 8 . Figures 1A to 1D and Figure 2It is a top view and a cross-sectional view of a storage device having a transistor 200a, a transistor 200b, a capacitor 100a and a capacitor 100b on a substrate (not shown). Here, transistor 200a and capacitor 100a, transistor 200b and capacitor 100b are storage devices used as 1T (transistor) 1C (capacitor) type storage cells. In addition, since transistor 200b has the same structure as transistor 200a, the same hatching as transistor 200a is added to the constituent elements without adding a reference numeral in particular. In addition, since capacitor 100b has the same structure as capacitor 100a, the same hatching as capacitor 100a is added to the constituent elements without adding a reference numeral in particular. In addition, the bottom surface sometimes refers to transistor 200a and transistor 200b as transistor 200. In addition, capacitor 100a and capacitor 100b are sometimes referred to as capacitor 100.

[0082] Figure 1A is a top view of the storage device. Figures 1B to 1D and Figure 2 is a cross-sectional view of the storage device. Figure 1B It is along Figure 1A The cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 1 is also a cross-sectional view of the transistor 200a in the channel length direction. Figure 2 It is along Figure 1A The cross-sectional view of the portion indicated by the dashed line B1-B2 in FIG. 1 is also a cross-sectional view of the transistor 200a in the channel length direction. Figure 1C It is along Figure 1A The cross-sectional view of the portion indicated by the dashed line A3-A4 in FIG. 1 is also a cross-sectional view of the transistor 200a and the transistor 200b in the channel width direction. Figure 1D It is along Figure 1A The cross-sectional view of the portion indicated by the dot-dash line A5-A6 in FIG. 1 is also a cross-sectional view of the capacitor element 100a and the capacitor element 100b. Here, the dot-dash line A1-A2 and the dot-dash line B1-B2 are orthogonal to the dot-dash line A3-A4 and the dot-dash line A5-A6. The dot-dash line A1-A2 and the dot-dash line B1-B2 are parallel to each other, and the dot-dash line A3-A4 and the dot-dash line A5-A6 are parallel to each other. In addition, Figure 1A In the top view of FIG. , some components are omitted for easy understanding. Figure 3A Show Figure 1B An enlarged view of the vicinity of the conductor 260. In addition, Figure 3B Show Figure 1C An enlarged view of the vicinity of the insulator 225. In addition, Figure 5A Show Figure 1B An enlarged view of the vicinity of the insulator 154a. In addition, Figure 5B Show Figure 1D An enlarged view of the vicinity of the insulator 225 .

[0083] The storage device of this embodiment includes: a conductor 205 (conductor 205a and conductor 205b) arranged in a manner of embedding an insulator 216 on a substrate (not shown); an insulator 221 on the insulator 216 and the conductor 205; an insulator 222 on the insulator 221; an insulator 225 on the insulator 222; an oxide 230 (oxide 230a and oxide 230b) arranged on the insulator 222 and covering at least a portion of the insulator 225; a conductor 242a and a conductor 242b on the oxide 230; an insulator 154a on the conductor 242a; an insulator 154b on the conductor 242b; a conductor 160a on the insulator 154a; a conductor 160b on the insulator 154b; an insulator 250 on the insulator 225 and on the oxide 230; and a conductor 260 (conductor 260a and conductor 260b) on the insulator 250. Note that in the description of the bottom surface, the conductor 242a and the conductor 242b are sometimes collectively referred to as the conductor 242. Also, the insulator 154a and the insulator 154b are sometimes collectively referred to as the insulator 154. Also, the conductor 160a and the conductor 160b are sometimes collectively referred to as the conductor 160.

[0084] An insulator 275 is provided on the conductor 160, and an insulator 280 is provided on the insulator 275. The insulator 250 and the conductor 260 are provided inside the openings of the insulator 280 and the insulator 275. In addition, an insulator 282 is provided on the insulator 280 and the conductor 260. In addition, an insulator 283 is provided on the insulator 282. In addition, an insulator 215 is provided below the insulator 216 and the conductor 205.

[0085] An insulator 241a is provided on the inner wall of the opening of the contact insulator 280, etc., and a conductor 240a is provided on the side of the contact insulator 241a. The bottom surface of the conductor 240a is in contact with the top surface of the conductor 160a. In addition, an insulator 241b is provided on the inner wall of the opening of the contact insulator 280, etc., and a conductor 240b is provided on the side of the contact insulator 241b. The bottom surface of the conductor 240b is in contact with the top surface of the conductor 242b. In addition, in the description of the bottom surface, the conductor 240a and the conductor 240b are sometimes collectively referred to as the conductor 240. In addition, the insulator 241a and the insulator 241b are sometimes collectively referred to as the insulator 241.

[0086] The oxide 230 includes a region used as a channel formation region of the transistor 200. In addition, the conductor 260 includes a region used as a first gate electrode (upper gate electrode) of the transistor 200. The insulator 250 includes a region used as a first gate insulator of the transistor 200. In addition, the conductor 205 includes a region used as a second gate electrode (lower gate electrode) of the transistor 200. The insulator 222 and the insulator 221 both include a region used as a second gate insulator of the transistor 200.

[0087] The conductor 242a has a region that functions as one of a source electrode and a drain electrode of the transistor 200. The conductor 242b has a region that functions as the other of a source electrode and a drain electrode of the transistor 200. The conductor 240b functions as a plug connected to the conductor 242b.

[0088] In addition, the capacitor element 100 includes a conductor 242a, an insulator 154a and a conductor 160a. The conductor 242a is used as one of a pair of electrodes of the capacitor element 100 (also referred to as a lower electrode), the conductor 160a is used as the other of a pair of electrodes of the capacitor element 100 (also referred to as an upper electrode), and the insulator 154a is used as a dielectric of the capacitor element 100. The conductor 240a is used as a plug connected to the conductor 160a. The capacitor element 100 constitutes a MIM (Metal-Insulator-Metal: Metal-Insulator-Metal) capacitor.

[0089] The oxide 230 preferably includes an oxide 230a covering the insulator 225 and an oxide 230b on the oxide 230a in the region overlapping with the conductor 242 and the like. Here, the oxide 230a is in contact with the top surface and side surface of the insulator 225 and the top surface of the insulator 222. The oxide 230a and the oxide 230b are as follows. Figure 1D As shown in FIG. 1 , the oxide 230a and the oxide 230b are provided so as to cover the insulator 225 having a high aspect ratio. Therefore, the oxide 230a and the oxide 230b are preferably deposited using a deposition method with high coverage such as the ALD method.

[0090] In addition, if Figure 3B As shown, the oxide 230 preferably has an oxide 230a in contact with the side surface of the insulator 225 and an oxide 230b in contact with the side surface of the oxide 230a in a region that does not overlap with the conductor 242, etc. (or in other words, a region sandwiched by the conductor 242a and the conductor 242b). Here, the oxide 230a is in contact with the side surface of the insulator 225, the side surface and bottom surface of the oxide 230b, and the top surface of the insulator 222. Furthermore, the oxide 230a and the oxide 230b are not in contact with at least a portion of the top surface of the insulator 225, as shown in FIG. Figure 1B , Figure 1CAs shown in FIG. 1 , the top surface of the insulator 225 is in contact with the bottom surface of the insulator 250. Figure 1B It seems that no oxide 230a and oxide 230b are formed between the conductor 242a and the conductor 242b, but Figure 2 As shown, oxide 230a and oxide 230b are formed near the side of insulator 225. That is, oxide 230a and oxide 230b are integrated in the region overlapping with conductor 242 in such a way that the portion on the A5 side and the portion on the A6 side are folded in half with insulator 225 sandwiched therebetween, but in the region between conductor 242a and conductor 242b, the portion on the A3 side and the portion on the A4 side are disconnected by insulator 225. In other words, although insulator 225 is almost covered by oxide 230, an opening is formed in oxide 230 in the region between conductor 242a and conductor 242b, and insulator 225 is exposed from oxide 230 in this region.

[0091] As described above, in the region between the conductor 242a and the conductor 242b, the oxide 230a and the oxide 230b are arranged in a sidewall shape on the side of the insulator 225 with a high aspect ratio. Therefore, the oxide 230a and the oxide 230b are preferably deposited using a deposition method with good coverage such as the ALD method. In addition, in the region between the conductor 242a and the conductor 242b, in the cross section in the channel width direction, the side of the A3 side and the side of the A4 side of the insulator 225 are respectively formed with oxide 230a and oxide 230b. By adopting this structure, the channel formation region of the transistor 200 can be formed on the side of the A3 side and the side of the A4 side of the insulator 225, thereby increasing the channel width per unit area. By increasing the channel width, the on-state current, field effect mobility, and frequency characteristics of the transistor 200 can be improved. Thus, by using the storage device of this embodiment as a storage unit, the write speed can be increased.

[0092] By providing the oxide 230 a below the oxide 230 b , it is possible to suppress diffusion of impurities from a structure formed below the oxide 230 a into the oxide 230 b .

[0093] This embodiment shows an example in which the oxide 230 has a two-layer structure of the oxide 230 a and the oxide 230 b , but the present invention is not limited thereto. The oxide 230 may have a single-layer structure of the oxide 230 b or a stacked-layer structure of three or more layers.

[0094] The oxide 230b has a channel formation region of the transistor 200 and a source region and a drain region disposed so as to sandwich the channel formation region. At least a portion of the channel formation region is opposed to the conductor 260. The source region overlaps with the conductor 242a, and the drain region overlaps with the conductor 242b. Note that the source region and the drain region may be swapped.

[0095] Since the channel formation region has fewer oxygen vacancies or lower impurity concentration than the source region and the drain region, the channel formation region is a high resistance region with low carrier concentration. Therefore, the channel formation region can be said to be an i-type (intrinsic) or substantially i-type region.

[0096] In addition, the source region and the drain region have many oxygen vacancies or high concentrations of impurities such as hydrogen, nitrogen, and metal elements, and are therefore low-resistance regions with high carrier concentrations. That is, the source region and the drain region are n-type regions (low-resistance regions) with higher carrier concentrations than the channel formation region.

[0097] The carrier concentration in the channel formation region is preferably 1×10 18 cm -3 Below, less than 1×10 17 cm -3 , less than 1×10 16 cm -3 , less than 1×10 15 cm -3 , less than 1×10 14 cm -3 , less than 1×10 13 cm -3 , less than 1×10 12 cm -3 , less than 1×10 11 cm -3 or less than 1×10 10 cm -3 Note that there is no particular restriction on the lower limit of the carrier concentration in the channel formation region, and it can be, for example, 1×10 -9 cm -3 .

[0098] In the case where the purpose is to reduce the carrier concentration of the oxide 230b, the impurity concentration in the oxide 230b can be reduced to reduce the defect state density. In this specification, etc., a state in which the impurity concentration is low and the defect state density is low is referred to as high-purity intrinsic or substantially high-purity intrinsic. In addition, an oxide semiconductor (or metal oxide) with a low carrier concentration is sometimes referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor (or metal oxide).

[0099] Therefore, in order to stabilize the electrical characteristics of the transistor 200, it is effective to reduce the impurity concentration in the oxide 230b. In order to reduce the impurity concentration in the oxide 230b, it is preferable to also reduce the impurity concentration in the nearby film. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, etc. Note that the impurities in the oxide 230b refer to, for example, elements other than the main component constituting the oxide 230b. For example, an element with a concentration of less than 0.1 atomic % can be said to be an impurity.

[0100] In addition, the channel formation region, the source region, and the drain region may be formed not only in the oxide 230 b but also in the oxide 230 a .

[0101] In the oxide 230, it is sometimes difficult to clearly observe the boundaries between the regions. The concentrations of the metal elements and impurity elements such as hydrogen and nitrogen detected in each region do not need to change in stages for each region, but may change continuously in each region. That is, the closer to the channel formation region, the lower the concentration of the metal elements and impurity elements such as hydrogen and nitrogen may be.

[0102] Note that a metal oxide serving as a semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used for the oxide 230 (the oxide 230 a and the oxide 230 b ).

[0103] The band gap of the metal oxide used as a semiconductor is preferably 2 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wider band gap, the off-state current of the transistor can be reduced. Therefore, a transistor containing a metal oxide in the channel formation region is called an OS transistor. The off-state current of the OS transistor is small, so the power consumption of the semiconductor device can be fully reduced. In addition, the frequency characteristics of the OS transistor are high, so the semiconductor device can be operated at high speed.

[0104] The oxide 230 preferably includes a metal oxide (oxide semiconductor). As metal oxides that can be used for the oxide 230, for example, indium oxide, gallium oxide and zinc oxide can be cited. The metal oxide preferably includes at least indium (In) or zinc (Zn). The metal oxide preferably includes two or three selected from indium, element M and zinc. In addition, the element M is a metal element or a metalloid element with a high bond energy with oxygen, for example, a metal element or a metalloid element with a bond energy with oxygen higher than that of indium. Specifically, as the element M, aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium and antimony can be cited. The element M contained in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin and yttrium, and further preferably gallium. In addition, in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements", and the "metal elements" described in this specification and the like may include metalloid elements.

[0105] The oxide 230 can use, for example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO), etc. Alternatively, indium tin oxide, gallium tin oxide (Ga—Sn oxide), aluminum tin oxide (Al—Sn oxide), or the like containing silicon may be used.

[0106] At this time, by increasing the atomic number ratio of indium contained in the metal oxide relative to the total atomic number of all metal elements, the field effect mobility of the transistor can be increased.

[0107] In addition, the metal oxide may also replace indium or contain one or more metal elements with a large period number in addition to indium. The greater the orbital overlap of the metal element, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including a metal element with a large period number, the field effect mobility of the transistor can sometimes be improved. As a metal element with a large period number, metal elements belonging to the 5th period and metal elements belonging to the 6th period can be cited. As the metal element, specifically, yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium can be cited. In addition, lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium are called light rare earth elements.

[0108] In addition, the metal oxide may also contain one or more non-metallic elements. When the metal oxide contains non-metallic elements, the field effect mobility of the transistor may sometimes be improved. Examples of the non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0109] In addition, by increasing the ratio of the number of zinc atoms contained in the metal oxide to the total number of atoms of all metal elements, the crystallinity of the metal oxide is improved, thereby suppressing the diffusion of impurities in the metal oxide. Therefore, the variation of the electrical characteristics of the transistor is suppressed, thereby improving the reliability.

[0110] In addition, by increasing the atomic number ratio of the element M contained in the metal oxide relative to the sum of the atomic numbers of all metal elements, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, the generation of carriers caused by oxygen vacancies is suppressed, thereby realizing a transistor with a small off-state current. In addition, the change of the electrical characteristics of the transistor is suppressed, thereby improving reliability.

[0111] As described above, the electrical characteristics and reliability of the transistor vary depending on the composition of the metal oxide used for the oxide 230. Therefore, by varying the composition of the metal oxide according to the electrical characteristics and reliability required of the transistor, a semiconductor device having both excellent electrical characteristics and high reliability can be realized.

[0112] The oxide 230 preferably has a stacked structure of a plurality of oxide layers having different chemical compositions. For example, the atomic number ratio of the element M in the metal oxide used for the oxide 230a to the metal element of the main component is preferably greater than the atomic number ratio of the element M in the metal oxide used for the oxide 230b to the metal element of the main component. In addition, the atomic number ratio of the element M in the metal oxide used for the oxide 230a to In is preferably greater than the atomic number ratio of the element M in the metal oxide used for the oxide 230b to In. By adopting this structure, it is possible to suppress the diffusion of impurities and oxygen from the structure formed below the oxide 230a to the oxide 230b.

[0113] In addition, the atomic number ratio of In in the metal oxide used for oxide 230b to element M is preferably greater than the atomic number ratio of In in the metal oxide used for oxide 230a to element M. With this structure, transistor 200 can obtain large on-state current and high frequency characteristics.

[0114] In addition, since oxide 230a and oxide 230b contain a common element as a main component in addition to oxygen, the defect state density at the interface between oxide 230a and oxide 230b can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and transistor 200 can obtain a large on-state current and high frequency characteristics.

[0115] Specifically, as the oxide 230a, a metal oxide having a composition of In:M:Zn=1:3:2 [atomic ratio] or a composition close thereto, In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto, or In:M:Zn=1:1:0.5 [atomic ratio] or a composition close thereto can be used. In addition, as the oxide 230b, a metal oxide having a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:1.2 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:2 [atomic ratio] or a composition close thereto, In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto, or In:Zn=4:1 [atomic ratio] or a composition close thereto which does not contain the element M can be used. Note that the nearby composition includes a range of ±30% of the desired atomic ratio. In addition, gallium is preferably used as the element M. In addition, when a single layer of oxide 230b is provided as oxide 230, the metal oxide that can be used for oxide 230a can also be used as oxide 230b. In addition, the composition of the metal oxide that can be used for oxide 230a and oxide 230b is not limited thereto. For example, the composition of the metal oxide that can be used for oxide 230a can also be applied to oxide 230b. Similarly, the composition of the metal oxide that can be used for oxide 230b can also be applied to oxide 230a. In addition, the metal oxide of the above composition can be stacked on one or both of oxide 230a and oxide 230b.

[0116] Furthermore, when the metal oxide is deposited by sputtering, the above-mentioned atomic number ratio is not limited to the atomic number ratio of the deposited metal oxide, but may also be the atomic number ratio of the sputtering target used for the deposition of the metal oxide.

[0117] The oxide 230 b preferably has crystallinity. In particular, CAAC-OS (c-axis aligned crystalline oxide semiconductor) is preferably used as the oxide 230 b.

[0118] CAAC-OS has a dense structure with high crystallinity and is a metal oxide with few impurities and defects (e.g., oxygen vacancies). In particular, by heat treating the metal oxide at a temperature at which the metal oxide is not polycrystallized (e.g., above 400°C and below 600°C) after forming the metal oxide, the CAAC-OS can have a dense structure with higher crystallinity. In this way, by further increasing the density of CAAC-OS, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

[0119] In addition, it is not easy to observe clear grain boundaries in CAAC-OS, so it is not easy to cause a decrease in electron mobility due to grain boundaries. Therefore, the physical properties of the metal oxide containing CAAC-OS are stable. Therefore, the metal oxide with CAAC-OS has heat resistance and high reliability.

[0120] In addition, by using a crystalline oxide such as CAAC-OS as the oxide 230 b, the source electrode or the drain electrode can suppress the extraction of oxygen from the oxide 230 b. Therefore, even if heat treatment is performed, the extraction of oxygen from the oxide 230 b can be reduced, so that the transistor 200 is also stable to the high temperature (so-called thermal budget) in the manufacturing process.

[0121] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in the region where the oxide semiconductor forms a channel, the electrical characteristics are easily changed, and reliability is sometimes reduced. In addition, hydrogen near the oxygen vacancy forms a defect where hydrogen enters the oxygen vacancy (the bottom surface is sometimes called V O H) and may generate electrons that become carriers. Therefore, when oxygen vacancies are included in the channel formation region of the oxide semiconductor, the transistor will have a normally-on characteristic (a characteristic in which a channel exists and current flows in the transistor even when no voltage is applied to the gate electrode). Therefore, in the channel formation region of the oxide semiconductor, it is preferable to minimize impurities, oxygen vacancies, and V O H. In other words, it is preferable that the carrier concentration of the channel formation region in the oxide semiconductor is reduced and the oxide semiconductor is made i-type (intrinsic) or substantially i-type.

[0122] In contrast, by providing an insulator containing oxygen that is released by heating (hereinafter sometimes referred to as excess oxygen) near the oxide semiconductor and performing heat treatment, oxygen can be supplied from the insulator to the oxide semiconductor to reduce oxygen vacancies and V OH. Note that when too much oxygen is supplied to the source region or the drain region, the on-state current of the transistor 200 may decrease or the field effect mobility may decrease. Furthermore, when the amount of oxygen supplied to the source region or the drain region is uneven within the substrate surface, the characteristics of the semiconductor device including the transistor become uneven. In addition, when the oxygen supplied from the insulator to the oxide semiconductor diffuses to the conductor such as the gate electrode, the source electrode and the drain electrode, the conductor is sometimes oxidized, which leads to a loss of conductivity, thereby having a negative impact on the electrical characteristics and reliability of the transistor.

[0123] Therefore, in the oxide semiconductor, it is preferred that the carrier concentration of the channel formation region is reduced and the region is i-type or substantially i-type, while it is preferred that the carrier concentration of the source region and the drain region is high and the region is n-type. In other words, it is preferred to reduce oxygen vacancies and V O H. In addition, it is preferable that the source region and the drain region are not supplied with excessive oxygen and the V of the source region and the drain region are not excessively reduced. O H content. In addition, it is preferable to have a structure that suppresses a decrease in the conductivity of the conductor 260, the conductor 242a, the conductor 242b, and the like. For example, it is preferable to have a structure that suppresses oxidation of the conductor 260, the conductor 242a, the conductor 242b, and the like. Note that hydrogen in the oxide semiconductor may form V O H, so in order to reduce V O H amount, it is necessary to reduce the hydrogen concentration.

[0124] Therefore, the semiconductor device in this embodiment has a structure in which the hydrogen concentration in the channel formation region is reduced, oxidation of the conductors 242a, 242b, and 260 is suppressed, and reduction in the hydrogen concentration in the source region and the drain region is suppressed.

[0125] The insulator 250 in contact with the channel formation region in the oxide 230b preferably has a function of trapping or fixing hydrogen. Thus, the hydrogen concentration in the channel formation region of the oxide 230b can be reduced. Therefore, the V O H makes the channel formation region i-type or substantially i-type.

[0126] Here, if Figure 3A As shown, the insulator 250 preferably has a stacked structure of an insulator 250a in contact with the oxide 230, an insulator 250b on the insulator 250a, an insulator 250c on the insulator 250b, and an insulator 250d on the insulator 250c. At this time, the insulator 250a and the insulator 250c preferably have the function of capturing or fixing hydrogen.

[0127] As an insulator having the function of capturing or fixing hydrogen, a metal oxide having an amorphous structure can be cited. As the insulator 250a and the insulator 250c, for example, a metal oxide such as magnesium oxide or an oxide containing one or both of aluminum and hafnium is preferably used. The above-mentioned metal oxide having an amorphous structure sometimes has the following property: the oxygen atom has a dangling bond and hydrogen is captured or fixed by the dangling bond. That is, it can be said that the metal oxide having an amorphous structure has a high ability to capture or fix hydrogen.

[0128] In addition, the insulator 250a and the insulator 250c preferably use a high dielectric constant (high-k) material. As an example of a high-k material, there is an oxide containing one or both of aluminum and hafnium. When a high-k material is used as the insulator 250a and the insulator 250c, the gate potential applied when the transistor is operating can be reduced while maintaining the physical thickness of the gate insulator. In addition, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced.

[0129] As the insulator 250 a and the insulator 250 c , it is preferable to use an oxide containing one or both of aluminum and hafnium, and it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium.

[0130] In this embodiment, an aluminum oxide film is used as the insulator 250a. In addition, the aluminum oxide preferably has an amorphous structure. Here, by providing the insulator 250a in contact with the oxide 230b, hydrogen contained in the oxide 230b and the like can be more effectively captured and fixed.

[0131] In this embodiment, hafnium oxide is used for the insulator 250c. Here, by providing the insulator 250c between the insulator 250b and the insulator 250d, hydrogen contained in the insulator 250b and the like can be more effectively captured and fixed.

[0132] Next, as the insulator 250b, an insulator having thermal stability, such as silicon oxide or silicon oxynitride, is preferably used. Note that in this specification, etc., "oxynitride" refers to a material whose oxygen content is higher than the nitrogen content, and "nitride oxide" refers to a material whose nitrogen content is higher than the oxygen content. For example, "silicon oxynitride" refers to a material whose oxygen content is higher than the nitrogen content, and "silicon nitride oxide" refers to a material whose nitrogen content is higher than the oxygen content.

[0133] Furthermore, in order to suppress oxidation of the conductors 242a, 242b, and 260, an oxygen blocking insulator is preferably provided near each of the conductors 242a, 242b, and 260. In the semiconductor device described in this embodiment, the insulators are, for example, the insulators 250a, 250d, 250c, and 275.

[0134] Note that in this specification, etc., a blocking insulator refers to an insulator having a barrier property. In this specification, etc., having a barrier property means having a property of hindering the penetration of a corresponding substance (also referred to as low permeability). For example, an insulator having a barrier property has a property that a corresponding substance does not easily diffuse into the inside of the insulator. For example, an insulator having a barrier property has a function of capturing or fixing (also referred to as gettering) a corresponding substance inside the insulator.

[0135] Examples of oxygen blocking insulators include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon oxynitride. In addition, examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). For example, the insulators 250a, 250c, 250d, and 275 preferably have a single-layer structure or a stacked-layer structure of the above-mentioned oxygen blocking insulators.

[0136] The insulator 250a preferably has an oxygen barrier property. The insulator 250a is preferably less likely to allow oxygen to penetrate than the insulator 280 at least. The insulator 250a is provided in a manner in contact with the top surface of the insulator 250, the top surface and side surface of the oxide 230b, the side surface of the oxide 230a, and the top surface of the insulator 222. When the insulator 250a has an oxygen barrier property, it is possible to suppress the detachment of oxygen from the channel formation region of the oxide 230b during heat treatment or the like. Therefore, the formation of oxygen vacancies in the oxides 230a and 230b can be reduced.

[0137] In addition, by providing the insulator 250a, the insulator 280 can be prevented from supplying an excessive amount of oxygen to the oxide 230a and the oxide 230b, thereby supplying an appropriate amount of oxygen to the oxide 230a and the oxide 230b. Thus, the source region and the drain region can be prevented from being excessively oxidized, thereby suppressing a decrease in the on-state current of the transistor 200 or a decrease in the field effect mobility.

[0138] Since an oxide containing one or both of aluminum and hafnium has an oxygen barrier property, it can be suitably used as the insulator 250 a .

[0139] The insulator 250d also preferably has oxygen barrier properties. The insulator 250d is provided between the channel formation region of the oxide 230 and the conductor 260 and between the insulator 280 and the conductor 260. By adopting this structure, it is possible to suppress the diffusion of oxygen in the channel formation region of the oxide 230 into the conductor 260 and the formation of oxygen vacancies in the channel formation region of the oxide 230. In addition, it is possible to suppress the diffusion of oxygen in the oxide 230 and oxygen in the insulator 280 into the conductor 260 and the oxidation of the conductor 260. The insulator 250d is preferably at least less likely to allow oxygen to permeate than the insulator 280. For example, a silicon nitride film is preferably used as the insulator 250d. In this case, the insulator 250d is an insulator containing at least nitrogen and silicon.

[0140] In addition, the insulator 250d preferably has a hydrogen barrier property, so that impurities such as hydrogen contained in the conductor 260 can be prevented from diffusing into the oxide 230b.

[0141] Insulator 275 also preferably has oxygen barrier properties. Insulator 275 is provided between insulator 280 and conductor 160a, between insulator 280 and conductor 160b, between insulator 280 and conductor 240a, and between insulator 280 and conductor 240b. Insulator 275 is provided in a manner in contact with the top surface of conductor 160, the side surface of conductor 160, the side surface of insulator 154, the side surface of conductor 242, the side surface of oxide 230, and the top surface of insulator 222. By adopting this structure, it is possible to suppress the diffusion of oxygen contained in insulator 280 to conductor 160 and conductor 242. Therefore, it is possible to suppress the increase in resistivity caused by oxidation of conductor 160 and conductor 242 by oxygen contained in insulator 280. Insulator 275 is preferably at least less likely to allow oxygen to permeate than insulator 280. For example, silicon nitride is preferably used as insulator 275. At this time, the insulator 275 is an insulator containing at least nitrogen and silicon.

[0142] In order to suppress a decrease in the hydrogen concentration in the source region and the drain region in the oxide 230 , a hydrogen blocking insulator is preferably provided near the source region and near the drain region. In the memory device described in this embodiment, the hydrogen blocking insulator is, for example, the insulator 275 .

[0143] Examples of the hydrogen barrier insulator include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride. For example, the insulator 275 preferably has a single-layer structure or a stacked-layer structure of the above hydrogen barrier insulators.

[0144] By providing the insulator 275, the diffusion of hydrogen from the source region and the drain region to the outside can be reduced, thereby suppressing the reduction of the hydrogen concentration in the source region and the drain region. Therefore, the source region and the drain region can be made n-type.

[0145] By adopting the above structure, the channel forming region can be i-type or substantially i-type and the source region and the drain region can be n-type, and a storage device with good electrical characteristics can be provided. By adopting the above structure, even if the storage device is miniaturized or highly integrated, it can have good electrical characteristics. In addition, by miniaturizing the transistor 200, the frequency characteristics can be improved. Specifically, the cut-off frequency can be increased.

[0146] Insulators 250a to 250d are used as part of the gate insulator. Insulators 250a to 250d are arranged in an opening formed in insulator 280 together with conductor 260. In order to achieve miniaturization of transistor 200, the thickness of insulators 250a to 250d is preferably thin. The thickness of insulators 250a to 250d is preferably 0.1nm or more and 10nm or less, more preferably 0.1nm or more and 5.0nm or less, further preferably 0.5nm or more and 5.0nm or less, further preferably 1.0nm or more and less than 5.0nm, and further preferably 1.0nm or more and 3.0nm or less. In addition, at least a portion of insulators 250a to 250d may include an area of ​​the above-mentioned thickness.

[0147] In order to reduce the thickness of the insulators 250a to 250d as described above, it is preferred to use an atomic layer deposition (ALD) method for deposition. In addition, in order to set the insulators 250a to 250d in the openings of the insulator 280, etc., it is preferred to use an ALD method for deposition. The ALD method includes a thermal ALD method that uses only thermal energy to react precursors and reactants, and a PEALD (Plasma Enhanced ALD) method that uses reactants excited by plasma. In the PEALD method, deposition can be performed at a lower temperature by using plasma, so it is sometimes preferred.

[0148] The ALD method can deposit atoms in layers, and thus has the advantages of being able to deposit extremely thin films, being able to deposit structures with high aspect ratios, being able to deposit with fewer defects such as pinholes, being able to deposit with high coverage, and being able to deposit at low temperatures. Therefore, the insulator 250 can be deposited with a small thickness and high coverage on the side surfaces of the opening formed in the insulator 280 and the side ends of the conductors 242a and 242b.

[0149] The precursor used in the ALD method sometimes contains carbon, etc. Therefore, the film formed by the ALD method sometimes contains more impurities such as carbon than the film formed by other deposition methods. In addition, the quantitative analysis of impurities can be performed by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry), X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy) or Auger electron spectroscopy (AES: Auger Electron Spectroscopy).

[0150] Note that, in the above description, the insulator 250 has a four-layer structure of the insulators 250a to 250d, but the present invention is not limited thereto. The insulator 250 may have a structure including at least one of the insulators 250a to 250d. By forming the insulator 250 with one, two, or three layers of the insulators 250a to 250d, the manufacturing process of the storage device can be simplified, thereby improving productivity.

[0151] For example, Figure 4A As shown, the insulator 250 may also have a two-layer structure. In this case, the insulator 250 preferably has a stacked structure of an insulator 250a and an insulator 250d on the insulator 250a. A high-k material may be used for at least one of the insulator 250a and the insulator 250d. Thus, the equivalent oxide thickness (EOT) can be reduced while the thickness of the insulator 250a and the insulator 250d is maintained to a degree that suppresses leakage current.

[0152] In addition, for example, Figure 4B As shown, the insulator 250 may also adopt a three-layer structure. In this case, the insulator 250 preferably adopts a stacked structure of an insulator 250a, an insulator 250b on the insulator 250a, and an insulator 250d on the insulator 250b. Figure 4A An insulator 250b is further provided on the basis of the structure shown.

[0153] In this embodiment, it is preferred that the storage device has a structure for suppressing the mixing of hydrogen into the transistor 200, etc. in addition to the above-mentioned structure. For example, it is preferred that an insulator having a function of suppressing the diffusion of hydrogen is provided in a manner covering one or both of the upper and lower parts of the transistor 200, etc. In the storage device described in this embodiment, the insulator is, for example, an insulator 283, an insulator 282, an insulator 222, and an insulator 221, etc. In addition, the insulator 215 under the transistor 200 may also have the same structure as either or both of the insulator 282 and the insulator 283. In this case, the insulator 215 may have a stacked structure of the insulator 282 and the insulator 283, and may adopt a structure in which the insulator 282 is located at the bottom and the insulator 283 is located at the top, or may adopt a structure in which the insulator 282 is located at the top and the insulator 283 is located at the bottom.

[0154] One or more of the insulator 283, the insulator 282, the insulator 222, and the insulator 221 are preferably used as a blocking insulator for inhibiting the diffusion of impurities such as water and hydrogen from the substrate side or the top of the transistor 200 to the transistor 200. Therefore, one or more of the insulator 283, the insulator 282, the insulator 222, and the insulator 221 preferably include an insulating material having a function of inhibiting the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (not allowing the above impurities to pass through). In addition, it is preferred to include an insulating material having a function of inhibiting the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (not allowing the above oxygen to pass through).

[0155] Insulator 283, insulator 282, insulator 222, and insulator 221 preferably all include an insulator having a function of inhibiting the diffusion of impurities such as water and hydrogen and oxygen, and for example, aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and zirconium (hafnium zirconium oxide), gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon oxynitride, etc., can be used. For example, silicon nitride with higher hydrogen barrier properties is preferably used for insulator 283 and insulator 221. In addition, for example, aluminum oxide with high ability to capture or fix hydrogen is preferably used for insulator 282. In addition, for example, hafnium oxide with high ability to capture or fix hydrogen and a high dielectric constant (high-k) material is preferably used for insulator 222.

[0156] By adopting such a structure, it is possible to suppress impurities such as water and hydrogen from diffusing from an interlayer insulating film or the like disposed above the insulator 283 to the transistor 200 or the like. In addition, it is possible to suppress impurities such as water and hydrogen from diffusing from an interlayer insulating film or the like disposed below the insulator 221 to the transistor 200 or the like. In addition, hydrogen in the insulator 280 and the insulator 250 or the like can be captured or fixed to the insulator 282 or the insulator 222. In addition, by providing the insulator 282 and the insulator 283, it is possible to suppress oxygen in the insulator 280 or the like from diffusing to the top of the transistor 200 or the like. In addition, by providing the insulator 222 and the insulator 221, it is possible to suppress oxygen in the oxide 230 or the like from diffusing to the bottom of the transistor 200 or the like. In this way, by adopting a structure in which the upper and lower parts of the transistor 200 are surrounded by an insulator having a function of suppressing the diffusion of impurities such as water and hydrogen and oxygen, it is possible to reduce the diffusion of excess oxygen and hydrogen into the oxide semiconductor. As a result, it is possible to achieve improvement in the electrical characteristics and reliability of the memory device.

[0157] In addition, the insulator 275 and the insulator 250d are preferably made of silicon nitride having a higher hydrogen barrier property. In addition, for example, the insulator 250a is preferably made of aluminum oxide having a high ability to capture or fix hydrogen. In addition, the insulator 250c is preferably made of hafnium oxide having a high ability to capture or fix hydrogen.

[0158] The insulator 225 is formed on the insulator 222 in such a manner as to be in contact with the insulator 222. Figure 3B As shown in FIG. 1 , when viewed from a cross section in the channel width direction, the insulator 225 has a shape with a high aspect ratio. Here, the aspect ratio of the insulator 225 when viewed from a cross section in the channel width direction refers to the ratio of the length L in the A3-A4 direction of the insulator 225 (which may also be referred to as the width L of the insulator 225) to the length H in the direction perpendicular to the formed surface of the insulator 225 (e.g., the insulator 222) (which may also be referred to as the height H of the insulator 225). In the insulator 225, the height H of the insulator 225 is at least longer than the width L of the insulator 225. The height H of the insulator 225 is greater than 1 times the width L of the insulator 225, preferably more than 2 times, more preferably more than 5 times, and further preferably more than 10 times. In addition, it is preferred that the height H of the insulator 225 is less than 20 times the width L of the insulator 225.

[0159] In the region overlapping with the conductor 242, etc., the oxide 230a, oxide 230b, the conductor 242, the insulator 154, and the conductor 160 are provided to cover the insulator 225 having a high aspect ratio. Figure 5BAs shown, in the mode of becoming the state of folding in half by clamping insulator 225, conductor 242a, insulator 154a and conductor 160a are provided.Thus, when looking at the cross section from the channel width direction, at the top of insulator 225, the side of A5 side and the side of A6 side, conductor 242a and conductor 160a clamp insulator 154a opposite.That is to say, capacitor element 100 can be formed respectively at the top of insulator 225, the side of A5 side and the side of A6 side.Therefore, compared with the situation that insulator 225 is not provided, the area of ​​capacitor element 100 increases because of the side of A5 side and the side of A6 side of insulator 225.

[0160] As described above, by increasing the area of ​​capacitor element 100, the electrostatic capacitance of capacitor element 100 can be increased. In addition, in the above structure, by providing insulator 225, the electrostatic capacitance of capacitor element 100 can be increased without increasing the occupied area of ​​capacitor element. Thus, miniaturization or high integration of storage device can be realized. In addition, the storage capacity of storage device can be increased.

[0161] In the region not overlapping with the conductor 242 and the like, the sidewall-shaped oxide 230a and the oxide 230b are provided on the side surface of the high aspect ratio insulator 225. Thus, in the vicinity of the channel formation region of the transistor 200, as shown in FIG. Figure 3B As shown, oxide 230a and oxide 230b are formed which are divided into a portion on the A3 side and a portion on the A4 side by the insulator 225. Furthermore, an insulator 250 and a conductor 260 are provided to cover the insulator 225, the oxide 230a, and the oxide 230b. Here, the oxide 230a and the oxide 230b are not in contact with the top surface of the insulator 225, and the top surface of the insulator 225 is in contact with the insulator 250. When viewed from the cross section in the channel width direction, in the side surface on the A3 side and the side surface on the A4 side, the oxide 230 and the conductor 260 are both opposed to each other with the insulator 250 sandwiched therebetween. That is, the oxide 230b formed on the side surface on the A3 side and the side surface on the A4 side of the insulator 225 are both used as channel formation regions. Therefore, by increasing the side surface on the A3 side and the side surface on the A4 side of the insulator 225, for example, by increasing the height of the insulator 225, Figure 3B The height H shown may increase the channel width of the transistor 200 .

[0162] As described above, by increasing the channel width, the on-state current, field effect mobility, and frequency characteristics of the transistor 200 can be improved. Thus, a storage device with a fast operating speed can be provided. In addition, in the above structure, by providing the insulator 225, the channel width can be increased without increasing the occupied area of ​​the transistor 200. Thus, the miniaturization or high integration of the storage device can be achieved. In addition, the storage capacity of the storage device can be increased.

[0163] The insulator 225 may be made of an insulating material that can be used for the insulator 222, the insulator 280, the insulator 250, etc. In addition, since the insulator 225 has a high aspect ratio, it is preferably formed in a sidewall shape on the side of the sacrificial layer (the insulator 223 described later). Therefore, the insulator 225 is preferably formed by an ALD method with high coverage. For example, the insulator 225 can use hafnium oxide deposited by a thermal ALD method.

[0164] Thus, by forming the insulator 225 into a sidewall shape in a manner of contacting the side surface of the sacrificial layer, as shown in FIG. Figure 1A As shown in the figure, the insulator 225 of the transistor 200a and the capacitor 100a and the insulator 225 of the transistor 200b and the capacitor 100b can be formed at the same time. In this way, by forming two insulators 225 at the same time, the distance between the two insulators 225 can be set according to the size of the sacrificial layer. Thus, the distance between the insulators 225 can be shortened, and the occupied area of ​​the transistor 200a, the transistor 200b, the capacitor 100a and the capacitor 100b can be reduced, thereby realizing the high integration of the storage device.

[0165] However, the insulator 225 is not limited to an insulating material in a strict sense. For example, a metal oxide having relatively high insulating properties may be used. For example, the metal oxide that can be used for the oxide 230a described above may be used.

[0166] In addition, the upper portion of the insulator 225 may also have a curved shape. By having this curved shape, defects such as voids can be prevented from being formed in the oxide 230a, the oxide 230b, the conductor 242, the insulator 154, and the conductor 160 near the upper portion of the insulator 225. Figure 3B As shown in FIG. 1 , in the region not overlapping with the conductor 242, the upper portions of the oxide 230a and the oxide 230b preferably also have a curved shape. Figure 3B and Figure 5B The A3 side (A5 side) and the A4 side (A6 side) of the upper part of the insulator 225 are both symmetrical structures with curved shapes, but the present invention is not limited to this. For example, sometimes only the A3 side (A5 side) of the upper part of the insulator 225 may have an asymmetrical structure with a curved shape.

[0167] In addition, although Figure 1A The structure in which the insulator 225 is extended in the A1-A2 direction is shown in FIG. 1 , but the present invention is not limited thereto. FIG. 6A to FIG. 6D As shown, the insulator 225 is provided in a perimetrical shape (also referred to as a frame shape or a closed curve shape). Fig. 6A is a top view of the storage device. FIG. 6B to FIG. 6Dis a cross-sectional view of the storage device. Figure 6B It is along Fig. 6A The cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. Figure 6C It is along Fig. 6A The cross-sectional view of the portion indicated by the dashed line A3-A4 in FIG. Fig.6D It is along Fig. 6A The cross-sectional view of the portion indicated by the dashed line A7-A8 in FIG. Fig. 6A In the top view, some components are omitted for easy understanding.

[0168] like Fig.6D As shown in the cross section of A7-A8 of FIG. 1 , the insulator 225 is integrated with the transistor 200a and the transistor 200b. Therefore, between the transistor 200a and the transistor 200b, the insulator 275 contacts the top surface of the insulator 225. As described above, the insulator 225 is preferably formed in a sidewall shape in contact with the side surface of the sacrificial layer. FIG. 6A to FIG. 6D In the illustrated memory device, the insulator 225 is formed by providing a sacrificial layer in a region surrounded by the insulator 225 .

[0169] In addition, if FIG. 8A to FIG. 8C As shown, the insulator 225 may be extended to increase the area of ​​the capacitor element 100 . Fig. 8A is a top view of the storage device. Figure 8B and Figure 8C is a cross-sectional view of the storage device. Figure 8B It is along Fig. 8A The cross-sectional view of the portion indicated by the dashed line A11-A12 in FIG. Figure 8C It is along Fig. 8A The cross-sectional view of the portion indicated by the dashed line A13-A14 in FIG. Fig. 8A In the top view of FIG. , some components are omitted for easy understanding. Fig. 8A In the top view of FIG. 2 , the insulator 225 is shown with a solid line for ease of understanding.

[0170] exist FIG. 8A to FIG. 8C In the structure shown in FIG. 1 , the insulator 225 is extended in a circumferential shape in the region where the capacitor element 100 is formed to increase the area of ​​the capacitor element 100. Figure 8C As shown, the area where the conductor 242a, the insulator 154a, and the conductor 160a overlap with the insulator 225 is larger than Figures 1A to 1D As a result, the capacitor element 100 formed on the side surface of the insulator 225 is increased, so that the electrostatic capacitance of the capacitor element 100 can be greatly increased compared to the area of ​​the capacitor element 100 in a plan view.

[0171] In the transistor 200, the conductor 205 is arranged so as to overlap with the oxide 230 and the conductor 260. Here, the conductor 205 is preferably provided so as to be embedded in the opening formed in the insulator 216. Figure 1A and Figure 1C As shown in FIG. 1 , the conductor 205 is preferably arranged to extend in the channel width direction. By adopting such a structure, the conductor 205 can be used as wiring when a plurality of transistors are arranged.

[0172] like Figure 1B and Figure 1C As shown, the conductor 205 preferably includes a conductor 205a and a conductor 205b. The conductor 205a is provided in a manner of contacting the bottom surface and the side wall of the above-mentioned opening. The conductor 205b is provided in a manner of being embedded in the concave portion of the conductor 205a formed along the above-mentioned opening. Here, the height of the top surface of the conductor 205 is consistent or substantially consistent with the height of the top surface of the insulator 216.

[0173] Here, as the conductor 205a, it is preferred that the conductor 205a includes a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), copper atoms, etc. Alternatively, it is preferred that the conductor 205a includes a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0174] By using a conductive material having a function of reducing hydrogen diffusion as the conductor 205a, impurities such as hydrogen contained in the conductor 205b can be prevented from diffusing to the oxide 230 through the insulator 216 and the like. In addition, by using a conductive material having a function of inhibiting oxygen diffusion as the conductor 205a, it is possible to inhibit the conductor 205b from being oxidized and the conductivity from being reduced. As the conductive material having a function of inhibiting oxygen diffusion, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide can be cited. The conductor 205a can have a single-layer structure or a laminated structure of the above-mentioned conductive material. For example, the conductor 205a preferably contains titanium nitride.

[0175] In addition, the conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. For example, the conductor 205b preferably contains tungsten.

[0176] The conductor 205 can be used as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by independently changing the potential applied to the conductor 205 without linking it with the potential applied to the conductor 260. In particular, by applying a negative potential to the conductor 205, the Vth of the transistor 200 can be further increased and the off-state current can be reduced. Thus, compared with the case where the negative potential is not applied to the conductor 205, when the negative potential is applied to the conductor 205, the drain current when the potential applied to the conductor 260 is 0V can be reduced.

[0177] In addition, the resistivity of the conductor 205 is designed in consideration of the potential applied to the conductor 205, and the thickness of the conductor 205 is set according to the resistivity. In addition, the thickness of the insulator 216 is substantially the same as that of the conductor 205. Here, it is preferred to reduce the thickness of the conductor 205 and the insulator 216 within the range allowed by the design of the conductor 205. By reducing the thickness of the insulator 216, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, so the diffusion of the impurities into the oxide 230 can be suppressed.

[0178] Note that in the above structure, a stacked structure of the conductor 205a and the conductor 205b is shown, but the present invention is not limited thereto, and the conductor 205 may have a single-layer structure or a stacked structure of three or more layers. For example, when the conductor 205 has a three-layer stacked structure, the stacked structure of the conductor 205a and the conductor 205b described above may be adopted, and a conductor made of the same material as the conductor 205a may be provided on the conductor 205b. In this case, the conductor may be formed in a manner embedded in a recess formed by the conductor 205a and the conductor 205b, and the recess is formed in a manner such that the top surface of the conductor 205b is lower than the uppermost portion of the conductor 205a.

[0179] In addition, the storage device of this embodiment can also be FIG. 7A to FIG. 7D As shown in FIG. 1 , a structure without the conductor 205 is adopted. Figure 3B As shown in FIG. 2 , in the transistor 200, the oxide 230 is in contact with the side surface on the A3 side and the side surface on the A4 side of the insulator 225. Thus, the conductor 260 facing the oxide 230 with the insulator 225 sandwiched therebetween may have the same function as the conductor 205 described above. FIG. 7A to FIG. 7D Although the conductor 205 is not provided as shown, a part of the conductor 260 may have the function of the second gate electrode.

[0180] As the conductor 242a, the conductor 242b, and the conductor 260, it is preferable to use a conductive material that is not easily oxidized or a conductive material having a function of inhibiting oxygen diffusion. As the conductive material, for example, a conductive material containing nitrogen and a conductive material containing oxygen can be cited. Thus, the conductivity of the conductor 242a, the conductor 242b, and the conductor 260 can be suppressed from decreasing. When a conductive material containing metal and nitrogen is used as the conductor 242a, the conductor 242b, and the conductor 260, the conductor 242a, the conductor 242b, and the conductor 260 are conductors containing at least metal and nitrogen.

[0181] The conductor 242a and the conductor 242b are disposed separately from each other on the oxide 230b in such a manner as to be in contact with the oxide 230b. Figure 5A and Figure 5B As shown in FIG. 1 , the conductor 242 is provided in a manner covering the insulator 225 having a high aspect ratio. Therefore, the conductor 242 is preferably deposited by a deposition method having high coverage, such as the ALD method or the CVD method. Figure 5B As shown, in the cross section in the channel width direction, the conductor 242 is formed in a folded state sandwiching the insulator 225. By adopting this structure, the capacitor element 100 can be formed on the upper part of the insulator 225, the side surface on the A5 side, and the side surface on the A6 side, thereby increasing the electrostatic capacitance per unit area.

[0182] Since the conductor 242a and the conductor 242b are in contact with the oxide 230b, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has the function of inhibiting oxygen diffusion. Thus, the decrease in the conductivity of the conductors 242a and 242b can be suppressed. In addition, it is possible to suppress the extraction of oxygen from the oxide 230b to form excessive oxygen vacancies. In addition, by using a material that easily absorbs (extracts) hydrogen as the conductors 242a and 242b, the hydrogen concentration of the oxide 230 can be reduced, so it is preferred.

[0183] The conductor 242 preferably uses a metal nitride, for example, preferably uses a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, a nitride containing titanium and aluminum, etc. In one embodiment of the present invention, it is particularly preferred to use a nitride containing tantalum. In addition, for example, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. can also be used. These materials are conductive materials that are not easily oxidized or materials that maintain conductivity even if oxygen is absorbed, so they are preferred.

[0184] Note that hydrogen contained in the oxide 230b or the like may diffuse into the conductor 242a or the conductor 242b. In particular, when a nitride containing tantalum is used as the conductor 242a or the conductor 242b, hydrogen contained in the oxide 230b or the like may easily diffuse into the conductor 242a or the conductor 242b, and the diffused hydrogen may bond with nitrogen contained in the conductor 242a or the conductor 242b. In other words, hydrogen contained in the oxide 230b or the like may be absorbed by the conductor 242a or the conductor 242b.

[0185] In addition, the conductor 242 may also adopt a stacked structure. In this case, a layer of a conductive material with high conductivity may be formed on the layer of the conductive material that is not easily oxidized. As the conductive material with high conductivity, the conductive material that can be used for the conductor 205b may be used. For example, the conductor 242 may have a two-layer structure of a tantalum nitride film and a tungsten film on the tantalum nitride film. Thus, the on-state current of the transistor 200 may be increased, thereby improving the operating speed of the storage device according to this embodiment.

[0186] In addition, in order to suppress the decrease in the conductivity of the conductor 242a and the conductor 242b, a crystalline oxide such as CAAC-OS is preferably used as the oxide 230b. In particular, it is preferable to use a metal oxide containing indium, zinc, and one or more selected from gallium, aluminum, and tin. When CAAC-OS is used, it is possible to suppress the conductor 242a or the conductor 242b from extracting oxygen from the oxide 230b. In addition, it is possible to suppress the decrease in the conductivity of the conductor 242a and the conductor 242b.

[0187] like Figure 1B and Figure 1C As shown, the conductor 260 is arranged in the opening formed in the insulator 280 and the insulator 275. In the opening, the conductor 260 is provided so as to cover the top surface of the insulator 225, the top surface of the insulator 222, the side surface of the oxide 230a, the side surface of the oxide 230b, and the top surface of the oxide 230b via the insulator 250. In addition, the top surface of the conductor 260 is arranged so as to be consistent or substantially consistent with the height of the uppermost portion of the insulator 250 and the top surface of the insulator 280.

[0188] In the above-mentioned opening where the conductor 260 and the insulator 250 are arranged, the side wall of the opening may be vertical or substantially vertical to the top surface of the insulator 222, or may have a tapered shape. The tapered side wall can improve the coverage of the insulator 250 and the like provided in the opening of the insulator 280, thereby reducing defects such as voids.

[0189] The conductor 260 is used as a first gate electrode of the transistor 200. Figure 1A and Figure 1CAs shown in FIG. 1 , the conductor 260 is preferably arranged to extend in the channel width direction. By adopting such a structure, the conductor 260 can be used as wiring when a plurality of transistors are arranged.

[0190] In this specification, etc., a transistor structure in which a channel forming region is surrounded by an electric field of at least a first gate electrode is referred to as a surrounded channel (S-channel) structure. In addition, the S-channel structure disclosed in this specification, etc. is different from a Fin-type structure and a planar structure. On the other hand, the S-channel structure disclosed in this specification, etc. can be regarded as a type of Fin-type structure. In addition, in this specification, etc., a Fin-type structure refers to a structure in which a gate electrode is configured in a manner that surrounds at least two or more surfaces of a channel (specifically, two surfaces, three surfaces, or four surfaces, etc.). By adopting a Fin-type structure and an S-channel structure, resistance to short channel effects can be improved, in other words, a transistor that is not prone to short channel effects can be realized.

[0191] By adopting the above-mentioned S-channel structure as transistor 200, the channel formation region can be electrically surrounded. The S-channel structure is a structure that electrically surrounds the channel formation region, so it can also be said that the structure is substantially the same as the GAA (Gate All Around: full surround gate) structure or the LGAA (Lateral Gate All Around: lateral full surround gate) structure. By making the transistor 200 have an S-channel structure, a GAA structure, or a LGAA structure, the channel formation region formed at or near the interface between the oxide 230 and the gate insulator can be regarded as the entire bulk of the oxide 230. Therefore, the current density flowing through the transistor can be increased, so it can be expected that the on-state current of the transistor or the field effect mobility of the transistor will be improved.

[0192] exist Figure 1B In the embodiment, the conductor 260 has a two-layer structure. Here, the conductor 260 preferably includes a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a is preferably disposed so as to surround the bottom surface and the side surface of the conductor 260b. At this time, as the conductor 260a, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has a function of inhibiting oxygen diffusion.

[0193] As the conductor 260a, it is preferred to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. In addition, it is preferred to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0194] In addition, when the conductor 260a has a function of suppressing oxygen diffusion, it is possible to suppress the decrease in conductivity caused by oxidation of the conductor 260b by oxygen contained in the insulator 280, etc. As a conductive material having a function of suppressing oxygen diffusion, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. are preferably used.

[0195] In addition, the conductor 260b preferably uses a conductor with high conductivity. For example, the conductor 260b can use a conductive material with tungsten, copper or aluminum as a main component. In addition, the conductor 260b can have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive materials.

[0196] The insulator 154a and the insulator 154b are arranged separately from each other. The insulator 154a is arranged on the conductor 240a in a manner of contacting the conductor 240a, and the insulator 154b is arranged on the conductor 240b in a manner of contacting the conductor 240b. Figure 5A and Figure 5B As shown in FIG. 1 , the insulator 154 is provided in a manner covering the insulator 225 having a high aspect ratio. Therefore, the insulator 154 is preferably deposited by a deposition method having high coverage, such as the ALD method or the CVD method. Figure 5B As shown, in the cross section in the channel width direction, the insulator 154 is formed in a folded state sandwiching the insulator 225. By adopting this structure, the capacitor element 100 can be formed on the upper part of the insulator 225, the side surface on the A5 side, and the side surface on the A6 side, thereby increasing the electrostatic capacitance per unit area.

[0197] The insulator 154 preferably uses a high dielectric constant (high-k) material (a material with a relatively high dielectric constant). As an insulator of a high dielectric constant (high-k) material, an oxide, an oxynitride, an oxynitride, or a nitride containing one or more metal elements selected from aluminum, hafnium, zirconium, and gallium can be used. In addition, the above oxide, oxynitride, oxynitride, or nitride may also contain silicon. In addition, an insulating layer composed of the above materials may also be stacked.

[0198] For example, as an insulator of a high dielectric constant (high-k) material, aluminum oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, an oxide containing silicon and zirconium, an oxynitride containing silicon and zirconium, an oxide containing hafnium and zirconium, an oxynitride containing hafnium and zirconium, etc. can be used. By using such a high-k material, the insulator 154 can be thickened to a degree that can suppress leakage current and the electrostatic capacitance of the capacitor 100 can be sufficiently ensured.

[0199] In addition, it is preferable to stack the insulating layers formed of the above materials, and it is preferable to use a stacked structure of a high dielectric constant (high-k) material and a material having a dielectric strength greater than that of the high dielectric constant (high-k) material. Figure 5A and Figure 5B As shown in the case where the insulator 154 adopts the structure of sequentially stacking insulator 154a1, insulator 154a2, and insulator 154a3, insulator 154a1 and insulator 154a3 can use zirconium oxide, and insulator 154a2 can use aluminum oxide. In addition, for example, as insulator 154, an insulating film sequentially stacked with zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide can be used. In addition, for example, as insulator 154, an insulating film sequentially stacked with hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide can be used. By using the stacking of an insulator with a larger dielectric strength such as aluminum oxide, the dielectric strength is improved, and therefore the electrostatic destruction of capacitor element 100 can be suppressed.

[0200] The conductor 160a and the conductor 160b are arranged separately from each other. The conductor 160a is arranged on the insulator 154a in a manner of contacting the insulator 154a, and the conductor 160b is arranged on the insulator 154b in a manner of contacting the insulator 154b. Figure 5A and Figure 5B As shown in FIG. 1 , the conductor 160 is provided in a manner covering the insulator 225 having a high aspect ratio. Therefore, the conductor 160 is preferably deposited by a deposition method having high coverage, such as the ALD method or the CVD method. Figure 5B As shown, in the cross section in the channel width direction, the conductor 160 is formed in a folded state sandwiching the insulator 225. By adopting this structure, the capacitor element 100 can be formed on the upper part of the insulator 225, the side surface on the A5 side, and the side surface on the A6 side, thereby increasing the electrostatic capacitance per unit area.

[0201] The conductor 160 can use any conductor that can be used for the conductor 205, the conductor 260, or the conductor 242. For example, titanium nitride or tantalum nitride can be used as the conductor 160.

[0202] Although the insulator 154b and the conductor 160b do not function as capacitors, they are manufactured at the same time as the insulator 154a and the conductor 160a and therefore have the same structure as the insulator 154a and the conductor 160a. For example, when the insulator 154a has a structure in which the insulator 154a1, the insulator 154a2, and the insulator 154a3 are stacked in sequence, the insulator 154b also has a structure in which the insulator 154b1, the insulator 154b2, and the insulator 154b3 are stacked in sequence.

[0203] The dielectric constant of each of the insulator 216 and the insulator 280 is preferably lower than that of the insulator 222. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0204] For example, the insulator 216 and the insulator 280 preferably include one or more of silicon oxide, silicon oxynitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having pores.

[0205] In particular, silicon oxide and silicon oxynitride are preferred because they have thermal stability. In particular, silicon oxide, silicon oxynitride, silicon oxide having pores and the like are preferred because they easily form a region containing oxygen released by heating.

[0206] In addition, the top surfaces of the insulator 216 and the insulator 280 may also be planarized.

[0207] The concentration of impurities such as water and hydrogen in the insulator 280 is preferably reduced. For example, an oxide containing silicon, such as silicon oxide or silicon oxynitride, is preferably used as the insulator 280 .

[0208] Conductor 240a is formed in the openings of insulator 275, insulator 280, insulator 282, and insulator 283. The bottom surface of conductor 240a is in contact with the top surface of conductor 160a. In addition, conductor 240b is formed in the openings of insulator 154b, conductor 160b, insulator 275, insulator 280, insulator 282, and insulator 283. The bottom surface of conductor 240b is in contact with the top surface of conductor 242b. Here, the height of the top surface of conductor 240 is substantially the same as the height of the top surface of insulator 283.

[0209] The conductor 240 preferably uses a conductive material mainly composed of tungsten, copper or aluminum. In addition, the conductor 240 may also adopt a laminated structure in which a first conductor is provided in contact with the side of the insulator 241 and a second conductor is provided inside the first conductor. In this case, the above-mentioned conductive materials can be used as the second conductor.

[0210] In addition, when a laminated structure is used as the conductor 240, a conductive material having a function of inhibiting the penetration of impurities such as water and hydrogen is preferably used as the first conductive material disposed near the insulator 283, the insulator 282, the insulator 280, and the insulator 275. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. are preferably used. In addition, a single layer or a laminated layer of a conductive material having a function of inhibiting the penetration of impurities such as water and hydrogen may also be used. By adopting such a structure, impurities such as water and hydrogen contained in the layer above the insulator 283 can be prevented from being mixed into the oxide 230 through the conductor 240a and the conductor 240b.

[0211] The insulator 241a is formed so as to contact the inner walls of the openings of the insulators 275, 280, 282, and 283. The inner side surface of the insulator 241a is in contact with the conductor 240a. In addition, the insulator 241b is formed so as to contact the inner walls of the openings of the insulator 154b, the conductor 160b, the insulator 275, the insulator 280, the insulator 282, and the insulator 283. The inner side surface of the insulator 241b is in contact with the conductor 240b.

[0212] As the insulator 241, a blocking insulating film that can be used for the insulator 275 or the like can be used. For example, as the insulator 241, an insulator such as silicon nitride, aluminum oxide, or silicon oxynitride can be used. By providing the insulator 241, impurities such as water and hydrogen contained in the insulator 280 or the like can be prevented from being mixed into the oxide 230 through the conductors 240a and 240b. In particular, silicon nitride is preferred because it has a high barrier property against hydrogen. In addition, it is possible to prevent oxygen contained in the insulator 280 from being absorbed by the conductors 240a and 240b.

[0213] The insulator 241 has a Figure 1B In the case of a stacked structure as shown, it is preferable to use an oxygen blocking insulating film and a hydrogen blocking insulating film in combination as a first insulator in contact with the inner wall of the opening such as the insulator 280 and a second insulator inside the first insulator.

[0214] For example, aluminum oxide deposited by thermal ALD may be used as the first insulator, and silicon nitride deposited by PEALD may be used as the second insulator. By adopting such a structure, oxidation of the conductor 240 can be suppressed, and the intrusion of hydrogen into the conductor 240 can be reduced.

[0215] In addition, since the conductor 240b is used as a contact plug for one of the source and the drain of the transistor 200, it is preferable that the conductor 240b and the conductor 160b are not electrically connected. Figure 1B As shown in FIG. 1 and FIG. 2 , it is preferred that an insulator 241b be provided between the conductor 240b and the conductor 160b.

[0216] Note that, although the above example shows that the insulator 241 has a two-layer stacked structure, the present invention is not limited to this. For example, the insulator 241 may also have a single-layer structure or a stacked structure of three or more layers. In addition, although the above example shows that the conductor 240 has a two-layer stacked structure, the present invention is not limited to this. For example, the conductor 240 may also have a single-layer structure or a stacked structure of three or more layers.

[0217] In addition, in the above description, Figure 1AAs shown in FIG. 1 and FIG. 2 , in a plan view, the conductor 242a is consistent with or substantially consistent with the insulator 154a and the conductor 160a, and the conductor 242b is consistent with or substantially consistent with the insulator 154b and the conductor 160b, but the present invention is not limited thereto. For example, 9A to 9D As shown, a portion of the conductor 242a and the conductor 242b may be formed in a region that does not overlap with the conductor 160a, the conductor 160b, and the like. Fig.9A is a top view of the storage device. FIG. 9B to FIG. 9D is a cross-sectional view of the storage device. Fig. 9B It is along Fig.9A The cross-sectional view of the portion indicated by the dashed line C1-C2. Fig. 9C It is along Fig.9A The cross-sectional view of the portion indicated by the dashed line A3-A4. Fig.9D It is along Fig.9A The cross-sectional view of the portion indicated by the dashed line B3-B4. Note that Fig.9A The cross-sectional view of the portion indicated by the dashed line A1-A2 can be referred to Figure 1B , along Fig.9A The cross-sectional view of the portion indicated by the dashed line B1-B2 can be referred to Figure 2 , along Fig.9A The cross-sectional view of the portion indicated by the dashed line A5-A6 can be referred to Figure 1D In addition, Fig.9A In the top view, some components are omitted for ease of understanding.

[0218] like Fig.9A , Fig. 9B and Fig.9D As shown, a portion of the conductor 242a and the conductor 242b is formed in a side wall shape on the side of the oxide 230a in the region between the conductor 160a (conductor 160b) and the insulator 250. As a result, the side and bottom surfaces of a portion of the conductor 242a and the conductor 242b are in contact with the oxide 230b. In addition, in the region between the conductor 160a (conductor 160b) and the insulator 250, the conductor 242a (conductor 242b), the oxide 230b, the oxide 230a, and the insulator 225 are covered by the insulator 275. In addition, as shown in FIG. Fig. 9B As shown in FIG. 1 , the end of the conductor 242a on the C2 side and the end of the conductor 242b on the C1 side are in contact with the insulator 250. Fig. 9C As shown, the lower portions of the oxide 230 a and the oxide 230 b may be formed in a shape that protrudes from the side surface of the upper portion of the oxide 230 b toward the A3 side or the A4 side.

[0219] By adopting 9A to 9DThe structure shown can shorten the distance between the conductor 242a and the conductor 242b, thereby shortening the channel length of the transistor 200. As a result, the on-state current, field effect mobility, and frequency characteristics of the transistor 200 can be improved, thereby providing a memory device with a high operating speed.

[0220] In addition, in the above description, Figure 1D As shown in FIG. 1 and FIG. 2 , near the source or drain of the transistor 200, the oxide 230a, the oxide 230b, the conductor 242a, the conductor 242b, the insulator 154a, the insulator 154b, the conductor 160a, and the conductor 160b are folded in half with the insulator 225 sandwiched therebetween, but the present invention is not limited thereto. For example, FIG. 10A to FIG. 10D , Fig.11A and Fig. 11B As shown, oxide 230a, oxide 230b, conductor 242a, conductor 242b, insulator 154a, insulator 154b, conductor 160a and conductor 160b can also be divided into a portion on the A3 side and a portion on the A4 side by the dotted line A1-A2. Fig. 10A is a top view of the storage device. FIG. 10B to FIG. 10D , Fig.11A and Fig. 11B is a cross-sectional view of the storage device. Fig. 10B It is along Fig. 10A The cross-sectional view of the portion indicated by the dashed line D1-D2. Fig. 10C It is along Fig. 10A The cross-sectional view of the portion indicated by the dashed line A3-A4. Fig. 10D It is along Fig. 10A The cross-sectional view of the portion indicated by the dashed line A5-A6. Fig.11A It is along Fig. 10A The cross-sectional view of the portion indicated by the dashed line E1-E2. Fig. 11B It is along Fig. 10A The cross-sectional view of the portion indicated by the dashed line A1-A2. Fig. 10A In the top view, some structural elements are omitted for ease of understanding.

[0221] FIG. 10A to FIG. 10D , Fig.11A and Fig. 11B The memory device shown in the figure has a transistor 200aD and a capacitor 100aD on the A3 side and a transistor 200aE and a capacitor 100aE on the A4 side, with the dashed line A1-A2 (insulator 225) as the boundary. Figures 1A to 1D and Figure 2In the memory device shown, the transistor 200a is divided into the transistor 200aD and the transistor 200aE, and the capacitor 100a is divided into the capacitor 100aD and the capacitor 100aE without significantly increasing the occupied area. FIG. 10A to FIG. 10D , Fig.11A and Fig. 11B The storage device shown does not show the corresponding Figures 1A to 1D and Figure 2 The transistor 200b and the capacitor 100b of the memory device shown in FIG. Figures 1A to 1D and Figure 2 The memory device shown in the figure is similarly provided with components corresponding to the transistor 200b and the capacitor 100b.

[0222] therefore, FIG. 10A to FIG. 10D , Fig.11A and Fig. 11B The components of the storage device shown are Figures 1A to 1D and Figure 2 The components of the memory device shown are represented by adding D or E. That is, the components included in the transistor 200aD and the capacitor 100aD on the A3 side are described as oxide 230D (oxide 230aD and oxide 230bD), conductor 242aD, conductor 242bD, insulator 154aD, insulator 154bD, conductor 160aD, conductor 160bD, conductor 240aD, conductor 240bD, insulator 241aD, and insulator 241bD. In addition, the components included in the transistor 200aE and the capacitor 100aE on the A4 side are denoted as oxide 230E (oxide 230aE and oxide 230bE), conductor 242aE, conductor 242bE, insulator 154aE, insulator 154bE, conductor 160aE, conductor 160bE, conductor 240aE, conductor 240bE, insulator 241aE, and insulator 241bE. For detailed description of these components, refer to the above description.

[0223] like Fig. 10B and Fig. 10C As shown in FIG. 1 , on the insulator 225, the oxide 230aD, the oxide 230bD, the conductor 242aD (conductor 242bD), the insulator 154aD (insulator 154bD), and the conductor 160aD (conductor 160bD) are separately provided from the oxide 230aE, the oxide 230bE, the conductor 242aE (conductor 242bE), the insulator 154aE (insulator 154bE), and the conductor 160aE (conductor 160bE). Thus, as shown in FIG. Fig. 11BAs shown, oxide 230aD, oxide 230bD, conductor 242aD, conductor 242bD, insulator 154aD, insulator 154bD, conductor 160aD, conductor 160bD, oxide 230aE, oxide 230bE, conductor 242aE, conductor 242bE, insulator 154aE, insulator 154bE, conductor 160aE and conductor 160bE are not formed above at least a portion of the insulator 225.

[0224] In addition, if Fig. 10B As shown in FIG. 1 , an oxide 230D (oxide 230aD and oxide 230bD) is formed on the side surface of the insulator 225 on the A3 side, and a channel formation region is provided in the oxide 230bD. Fig.11A As shown, an oxide 230E (an oxide 230aE and an oxide 230bE) is formed on the side surface of the insulator 225 on the A4 side in contact with each other, and a channel formation region is provided in the oxide 230bE.

[0225] By adopting FIG. 10A to FIG. 10D , Fig.11A and Fig. 11B The structure shown can form twice the number of memory cells without increasing the occupied area, thereby realizing miniaturization or high integration of the memory device. In addition, the storage capacity of the memory device can be increased.

[0226] <Constituent Materials of Storage Device>

[0227] The constituent materials that can be used for the memory device are described below. Note that each layer constituting the memory device may have a single-layer structure or a stacked-layer structure.

[0228] <<Substrate>>

[0229] As a substrate for forming a transistor, for example, an insulator substrate, a semiconductor substrate or a conductor substrate can be used. As an insulator substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (yttria stabilized zirconia substrate, etc.) and a resin substrate can be cited. In addition, as a semiconductor substrate, for example, a semiconductor substrate made of silicon or germanium, and a compound semiconductor substrate composed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide or gallium oxide can be cited. In addition, a semiconductor substrate having an insulator region inside the above-mentioned semiconductor substrate can also be cited, such as an SOI (Silicon On Insulator) substrate. As a conductor substrate, for example, a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate can be cited. In addition, as a substrate, for example, a substrate containing a metal nitride, a substrate containing a metal oxide, an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, and a conductor substrate provided with a semiconductor or an insulator can be cited. Alternatively, a substrate having one or more elements provided on these substrates can also be used. Examples of the element provided over the substrate include a capacitor, a resistor, a switching element, a light emitting element, and a memory element.

[0230] <<Insulator>>

[0231] Examples of the insulator include oxides, nitrides, oxynitrides, oxynitrides, metal oxides, metal oxynitrides, and metal oxynitrides having insulating properties.

[0232] For example, when miniaturization and high integration of transistors are being carried out, problems such as leakage current sometimes occur due to the thin film of the gate insulator. By using a high-k material as an insulator used as a gate insulator, it is possible to achieve low voltage when the transistor is operating while maintaining the physical thickness. On the other hand, by using a material with a low relative dielectric constant for an insulator used as an interlayer film, the parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select a material according to the function of the insulator.

[0233] Examples of insulators having a relatively high dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0234] Examples of insulators having a relatively low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, and resins.

[0235] In addition, by surrounding a transistor using a metal oxide with an insulator having the function of inhibiting the permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. As an insulator having the function of inhibiting the permeation of impurities such as hydrogen and oxygen, for example, a single layer or stack of an insulator containing one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium and tantalum can be used. Specifically, as an insulator having the function of inhibiting the permeation of impurities such as hydrogen and oxygen, for example, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride can be cited.

[0236] In addition, the insulator used as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with oxide 230, oxygen vacancies contained in oxide 230 can be filled.

[0237] <<Conductor>>

[0238] As the conductor, it is preferred to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium and lanthanum, an alloy with the above metal elements as a component, or an alloy combining the above metal elements. As the conductor, for example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel can be cited. In addition, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel are conductive materials that are not easily oxidized or materials that absorb oxygen and maintain conductivity, so they are preferred. Alternatively, a semiconductor having high conductivity, such as polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

[0239] In the case of using a conductor with a stacked structure, for example, a stacked structure combining a material containing the above-mentioned metal element and a conductive material containing oxygen, a stacked structure combining a material containing the above-mentioned metal element and a conductive material containing nitrogen, or a stacked structure combining a material containing the above-mentioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be used.

[0240] In addition, when an oxide is used in the channel formation region of the transistor, a laminated structure combining a material containing the above-mentioned metal element and a conductive material containing oxygen is preferably used as a conductor used as a gate electrode. In this case, the conductive material containing oxygen is preferably arranged on one side of the channel formation region. By arranging the conductive material containing oxygen on one side of the channel formation region, oxygen separated from the conductive material is easily supplied to the channel formation region.

[0241] In particular, as a conductor used as a gate electrode, it is preferred to use a conductive material containing a metal element contained in a metal oxide forming a channel and oxygen. In addition, a conductive material containing the above-mentioned metal element and nitrogen can also be used. For example, a conductive material containing nitrogen such as titanium nitride and tantalum nitride can be used. In addition, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide added with silicon can also be used. In addition, indium gallium zinc oxide containing nitrogen can also be used. By using the above-mentioned materials, hydrogen contained in the metal oxide forming the channel can sometimes be captured. Alternatively, hydrogen mixed from an external insulator can sometimes be captured.

[0242] <<Metal Oxides>>

[0243] A metal oxide that functions as a semiconductor (oxide semiconductor) is preferably used as the oxide 230. Next, a metal oxide that can be used for the oxide 230 according to one embodiment of the present invention will be described.

[0244] The metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition, it preferably contains aluminum, gallium, yttrium, tin, antimony, etc. In addition, it may also contain one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt.

[0245] Here, the case where the metal oxide is an In-M-Zn oxide containing indium, element M and zinc is considered. Note that element M is aluminum, gallium, yttrium, tin or antimony. Other elements that can be applied to element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc. Note that as element M, multiple of the above elements can sometimes be combined. In particular, element M is preferably selected from one or more of gallium, aluminum, yttrium and tin.

[0246] In addition, in this specification and the like, a metal oxide containing nitrogen may also be referred to as a metal oxide (metal oxide). In addition, a metal oxide containing nitrogen may also be referred to as a metal oxynitride (metal oxynitride).

[0247] Hereinafter, In—Ga—Zn oxide will be described as an example of the metal oxide.

[0248] Examples of the crystalline structure of an oxide semiconductor include amorphous (including completely amorphous), CAAC (c-axis-aligned crystalline), nc (nanocrystalline), CAC (cloud-aligned composite), single crystal, and polycrystal.

[0249] In addition, when focusing on the structure of oxide semiconductors, the classification of oxide semiconductors is sometimes different from the above. For example, oxide semiconductors can be classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors other than single-crystal oxide semiconductors. As non-single-crystal oxide semiconductors, for example, the above-mentioned CAAC-OS and nc-OS can be cited. In addition, non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, a-like OS (amorphous-like oxide semiconductor) and amorphous oxide semiconductors.

[0250] Here, the details of the above-mentioned CAAC-OS, nc-OS and a-like OS are explained.

[0251] [CAAC-OS]

[0252] CAAC-OS is an oxide semiconductor including a plurality of crystalline regions, wherein the c-axes of the plurality of crystalline regions are oriented in a specific direction. In addition, the specific direction refers to the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. In addition, as Figure 3B As shown in Figures 2 and 3, in the region where the oxide 230 is in contact with the insulator 225, the c-axis is preferably oriented in the normal direction of the surface of the film of the insulator 225. In addition, a crystalline region is a region having a periodic atomic arrangement. Note that when the atomic arrangement is regarded as a lattice arrangement, the crystalline region is also a region having a consistent lattice arrangement. Furthermore, CAAC-OS has a region where a plurality of crystalline regions are connected in the ab plane direction, and sometimes the region has a distortion. In addition, distortion refers to a portion where the direction of the lattice arrangement changes between a region having a consistent lattice arrangement and other regions having a consistent lattice arrangement in a region where a plurality of crystalline regions are connected. In other words, CAAC-OS refers to an oxide semiconductor that is oriented along the c-axis and has no obvious orientation in the ab plane direction.

[0253] In addition, each of the above-mentioned multiple crystallization regions is composed of one or more tiny crystals (crystallizations with a maximum diameter less than 10 nm). In the case where a crystallization region is composed of one tiny crystal, the maximum diameter of the crystallization region is less than 10 nm. In addition, in the case where a crystallization region is composed of multiple tiny crystals, the maximum diameter of the crystallization region is sometimes about tens of nm.

[0254] CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries can be confirmed. Therefore, it can be said that in CAAC-OS, the reduction in electron mobility caused by grain boundaries is not easy to occur. In addition, the crystallinity of the oxide semiconductor is sometimes reduced due to the mixing of impurities or the generation of defects, so it can be said that CAAC-OS is an oxide semiconductor with few impurities and defects (oxygen vacancies, etc.). Therefore, the physical properties of the oxide semiconductor including CAAC-OS are stable. Therefore, the oxide semiconductor including CAAC-OS has high heat resistance and high reliability. In addition, CAAC-OS is also stable to high temperatures (so-called heat accumulation) in the manufacturing process. Therefore, by using CAAC-OS in the OS transistor, the degree of freedom of the manufacturing process can be expanded.

[0255] [nc-OS]

[0256] In nc-OS, the atomic arrangement in a tiny region (e.g., a region of more than 1 nm and less than 10 nm, especially a region of more than 1 nm and less than 3 nm) is periodic. In other words, nc-OS has tiny crystals. In addition, for example, the size of the tiny crystal is more than 1 nm and less than 10 nm, especially more than 1 nm and less than 3 nm, and the tiny crystal is called a nanocrystal. In addition, in nc-OS, no regularity of crystal orientation is observed between different nanocrystals. Therefore, no orientation is observed in the entire film. Therefore, sometimes nc-OS is no different from a-like OS or amorphous oxide semiconductor in certain analysis methods.

[0257] [a-like OS]

[0258] A-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductor. A-like OS contains voids or low-density regions. In other words, the crystallinity of a-like OS is lower than that of nc-OS and CAAC-OS. In addition, the hydrogen concentration in the film of a-like OS is higher than that in the film of nc-OS and CAAC-OS.

[0259] Next, the details of the above-mentioned CAC-OS will be described. In addition, CAC-OS is related to the material composition.

[0260] [CAC-OS]

[0261] CAC-OS refers to, for example, a structure in which elements contained in a metal oxide are unevenly distributed, wherein the size of the material containing the unevenly distributed elements is greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 3 nm, or a similar size. Note that the state in which one or more metal elements are unevenly distributed in the metal oxide and regions containing the metal elements are mixed on the bottom surface is also referred to as a mosaic or patch shape, and the size of the region is greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 3 nm, or a similar size.

[0262] Furthermore, CAC-OS refers to a structure in which the material is divided into a first region and a second region to form a mosaic shape, and the first region is distributed in the film (the bottom surface is also called a cloud shape). That is, CAC-OS refers to a composite metal oxide having a structure in which the first region and the second region are mixed.

[0263] In addition, CAC-OS in In-Ga-Zn oxide refers to a structure in which a region (first region) in which a part of the main component is In and a region (second region) in which a part of the main component is Ga exist irregularly in a mosaic shape in a material composition containing In, Ga, Zn, and O. Therefore, it can be inferred that CAC-OS has a structure in which metal elements are unevenly distributed.

[0264] CAC-OS can be formed, for example, by sputtering without heating the substrate. When CAC-OS is formed by sputtering, as the deposition gas, any one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas can be used. In addition, the lower the flow rate ratio of the oxygen gas in the total flow rate of the deposition gas during deposition, the better. For example, the flow rate ratio of the oxygen gas in the total flow rate of the deposition gas during deposition is set to be greater than 0% and less than 30%, preferably greater than 0% and less than 10%.

[0265] Here, the first region is a region having higher conductivity than the second region. That is, when carriers flow through the first region, the conductivity as a metal oxide is exhibited. Therefore, when the first region is distributed in the metal oxide in a cloud-like manner, a high field effect mobility (μ) can be achieved.

[0266] On the other hand, the second region is a region having higher insulation than the first region. That is, when the second region is distributed in the metal oxide, leakage current can be suppressed.

[0267] Thus, when CAC-OS is used for a transistor, the complementary effect of the conductivity of the first region and the insulation of the second region can give CAC-OS a switch function (a function of controlling on / off). In other words, a portion of the CAC-OS material has a conductive function and another portion has an insulating function, and the entire material has a semiconductor function. By separating the conductive function and the insulating function, each function can be maximized. Therefore, by using CAC-OS for a transistor, a large on-state current (I on ), high field effect mobility (μ) and good switching performance.

[0268] In addition, transistors using CAC-OS have high reliability. Therefore, CAC-OS is most suitable for various memory devices such as display devices.

[0269] Oxide semiconductors have various structures and various characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0270] <<Other semiconductor materials>>

[0271] As the semiconductor layer of the transistor, a semiconductor material having a band gap (a semiconductor material that is not a zero-band gap semiconductor) may be used. For example, a semiconductor of a single element such as silicon or a compound semiconductor such as gallium arsenide may be used.

[0272] In addition, as the semiconductor layer of the transistor, for example, a transition metal chalcogenide used as a semiconductor is preferably used. As transition metal chalcogenides that can be used for the semiconductor layer of the transistor, specifically molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), zirconium selenide (typically ZrSe2), etc. can be cited. By using the above-mentioned transition metal chalcogenides for the semiconductor layer of the transistor, a storage device with a large on-state current can be provided.

[0273] <Example of Method for Manufacturing Storage Device>

[0274] use FIG. 12A to FIG. 22D An example of a method for manufacturing a storage device according to one embodiment of the present invention is described. Figures 1A to 1D The case of the storage device shown is described as an example.

[0275] A in each figure is a top view. In addition, B in each figure is a cross-sectional view of a portion along the dashed line A1-A2 in A, which is equivalent to a cross-sectional view in the channel length direction of the transistor 200. In addition, C in each figure is a cross-sectional view of a portion along the dashed line A3-A4 in A, which is equivalent to a cross-sectional view in the channel width direction of the transistor 200. In addition, D in each figure is a cross-sectional view of a portion along the dashed line A5-A6 in A, which is equivalent to a cross-sectional view in the channel width direction of the transistor 200. Note that for clarity, some components are omitted in the top view of A in each figure.

[0276] Hereinafter, the insulating material used to form an insulator, the conductive material used to form a conductor, or the semiconductor material used to form a semiconductor can be appropriately deposited using sputtering, chemical vapor deposition (CVD: Chemical Vapor Deposition), molecular beam epitaxy (MBE: Molecular Beam Epitaxy), pulsed laser deposition (PLD: Pulsed Laser Deposition), ALD, or the like.

[0277] As the sputtering method, there can be cited an RF sputtering method using a high frequency power supply as a sputtering power supply, a DC sputtering method using a direct current power supply, and a pulsed DC sputtering method in which the voltage applied to the electrode is changed in a pulsed manner. The RF sputtering method is mainly used when depositing insulating films, and the DC sputtering method is mainly used when depositing metal conductive films. In addition, the pulsed DC sputtering method is mainly used when depositing compounds such as oxides, nitrides, and carbides using a reactive sputtering method.

[0278] Note that the CVD method can be divided into a plasma enhanced CVD (PECVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, and a photo CVD (Photo CVD) method using light, etc. Furthermore, it can be classified into a metal CVD (MCVD: Metal CVD) method and an organic metal CVD (MOCVD: Metal Organic CVD) method according to the source gas used.

[0279] By utilizing the plasma CVD method, a high-quality film can be obtained at a lower temperature. In addition, since plasma is not used, the thermal CVD method is a deposition method that can reduce plasma damage to the object being processed. For example, the wiring, electrodes, components (transistors, capacitors, etc.) included in the storage device sometimes generate charge accumulation due to receiving charges from plasma. At this time, the wiring, electrodes, components, etc. included in the storage device are sometimes damaged due to the accumulated charge. On the other hand, since the above-mentioned plasma damage does not occur in the case of the thermal CVD method without using plasma, the yield of the storage device can be improved. In addition, in the thermal CVD method, plasma damage during deposition is not generated, so a film with fewer defects can be obtained.

[0280] As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, a PEALD method using a reactant excited by plasma, or the like is used.

[0281] The CVD method and the ALD method are different from the sputtering method in which particles released from a target material or the like are deposited. Therefore, the CVD method and the ALD method are deposition methods that are not easily affected by the shape of the object to be processed and have high step coverage. In particular, the ALD method has high step coverage and thickness uniformity, so the ALD method is suitable for covering the surface of an opening with a high aspect ratio. However, the deposition rate of the ALD method is relatively slow, so it is sometimes preferred to use it in combination with other deposition methods such as the CVD method with a fast deposition rate.

[0282] In addition, when the CVD method is used, a film of any composition can be deposited by adjusting the flow ratio of the source gas. For example, when the CVD method is used, a film whose composition continuously changes can be deposited by changing the flow ratio of the source gas while depositing. When depositing while changing the flow ratio of the source gas, since the time required for conveying or adjusting the pressure is not required, the deposition time can be shortened compared to the case where deposition is performed using a plurality of deposition chambers. Therefore, the productivity of the storage device can sometimes be improved.

[0283] When the ALD method is used, a film of any composition can be deposited by introducing different precursors at the same time. Alternatively, when introducing different precursors, a film of any composition can be deposited by controlling the number of cycles of each precursor.

[0284] First, a substrate (not shown) is prepared, and an insulator 215 is deposited on the substrate (see FIG. 12A to FIG. 12D). As described above, the insulator 215 may use the same insulator as the laminated film of any one or more of the insulators 282 and the insulator 283. For example, the insulator 215 may be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. By using a sputtering method that does not require the use of molecules containing hydrogen as a deposition gas, the hydrogen concentration in the insulator 215 can be reduced, so it is preferred.

[0285] Next, an insulator 216 is deposited on the insulator 215. The insulator 216 is preferably deposited by a sputtering method. By using a sputtering method that does not require the use of molecules containing hydrogen for a deposition gas, the hydrogen concentration in the insulator 216 can be reduced. Note that the deposition method of the insulator 216 is not limited to the sputtering method, and for example, a CVD method, an MBE method, a PLD method, an ALD method, or the like can also be used appropriately. In this embodiment, silicon oxide is deposited as the insulator 216 by a sputtering method.

[0286] The insulator 215 and the insulator 216 are preferably deposited continuously without being exposed to the atmosphere. For example, a multi-chamber deposition apparatus may be used. Thus, the insulator 215 and the insulator 216 can be deposited while reducing hydrogen in the film, and the mixing of hydrogen into the film between each deposition step can be reduced.

[0287] Next, an opening reaching the insulator 215 is formed in the insulator 216. When forming the opening, wet etching can be used, but dry etching is preferred for microfabrication. As the insulator 215, it is preferable to select an insulator that is used as an etching stopper film when etching the insulator 216 to form a groove. For example, when silicon oxide or silicon oxynitride is used as the insulator 216 for forming the groove, silicon nitride, aluminum oxide, hafnium oxide, or the like is preferably used as the insulator 215.

[0288] After the opening is formed, a conductive film to be the conductor 205a is deposited. The conductive film to be the conductor 205a preferably includes a conductor having a function of inhibiting the transmission of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, etc. can be used as the conductive film. In addition, the conductive film can use a laminated film of a conductor having a function of inhibiting the transmission of oxygen and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. The conductive film to be the conductor 205a can be deposited, for example, by sputtering, CVD, MBE, PLD, ALD, or the like.

[0289] In this embodiment, titanium nitride is deposited as a conductive film used as the conductor 205a. By using the above-mentioned metal nitride as the lower layer of the conductor 205b, it is possible to suppress the conductor 205b from being oxidized by the insulator 216. In addition, even if a metal that easily diffuses, such as copper, is used as the conductor 205b, it is possible to prevent the metal from diffusing outward from the conductor 205a.

[0290] Next, a conductive film to be the conductor 205b is deposited. As the conductive film to be the conductor 205b, for example, tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy can be used. The conductive film can be deposited by, for example, a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, tungsten is deposited as the conductive film to be the conductor 205b.

[0291] Next, a CMP treatment is performed to remove a portion of the conductive film to be the conductor 205a and the conductive film to be the conductor 205b, thereby exposing the insulator 216 (see FIG. 214 ). FIG. 12A to FIG. 12D ). As a result, the conductor 205a and the conductor 205b remain only in the opening. Note that part of the insulator 216 may be removed by the CMP process.

[0292] Next, an insulator 221 is deposited on the insulator 216 and the conductor 205 (see FIG. 13A to FIG. 13D ).

[0293] An insulator having barrier properties against oxygen, hydrogen, and water may be used as the insulator 221. The insulator 221 may be deposited by, for example, sputtering, CVD, MBE, PLD, or ALD. In this embodiment, silicon nitride is deposited by PEALD as the insulator 221.

[0294] Next, an insulator 222 is deposited on the insulator 221 (see FIG. 13A to FIG. 13D ).

[0295] As the insulator 222, an insulator containing an oxide of one or both of aluminum and hafnium is preferably deposited. As the insulator containing an oxide of one or both of aluminum and hafnium, for example, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. are preferably used. Alternatively, hafnium zirconium oxide is preferably used. The insulator containing an oxide of one or both of aluminum and hafnium has a barrier property to oxygen, hydrogen, and water. When the insulator 222 has a barrier property to hydrogen and water, the hydrogen and water contained in the structure surrounding the transistor can be suppressed from diffusing into the inside of the transistor through the insulator 222, thereby suppressing the generation of oxygen vacancies in the oxide 230.

[0296] The insulator 222 can be deposited by, for example, sputtering, CVD, MBE, PLD, ALD, etc. In this embodiment, hafnium oxide is deposited as the insulator 222 by ALD.

[0297] Next, an insulating film is deposited on the insulator 222 and the insulating film is etched to form an insulator 223 (see FIG. 13A to FIG. 13D). The insulator 223 is used as a sacrificial layer for forming the insulator 225. As the insulator 223, for example, an insulator that can be used for the insulator 216 can be used.

[0298] The insulator 223 can be deposited by, for example, sputtering, CVD, MBE, PLD, ALD, etc. In this embodiment, silicon oxide is deposited by sputtering as the insulator 223 .

[0299] The insulator 223 can be processed into an island shape by photolithography. This processing can be done by dry etching or wet etching. The processing by dry etching is more suitable for micro-processing.

[0300] like Fig. 13B As shown, a structure may be adopted in which the side surface of the insulator 223 is perpendicular or substantially perpendicular to the top surface of the insulator 222. By adopting such a structure, it is possible to realize a reduction in area and a high density when arranging a plurality of transistors.

[0301] In addition, heat treatment may be performed before depositing the insulator 223. The heat treatment may also be performed under reduced pressure, wherein the insulator 223 is continuously deposited without being exposed to the atmosphere. By performing such a treatment, moisture and hydrogen attached to the surface of the insulator 222 can be removed, and the moisture concentration and hydrogen concentration of the insulator 222 can be reduced. Here, when the insulator 221 is provided in contact with the bottom surface of the insulator 222, impurities such as moisture or hydrogen can be prevented from entering from below the insulator 221 due to the heat treatment. The temperature of the heat treatment is preferably not less than 100°C and not more than 400°C. In this embodiment, the temperature of the heat treatment is set to 250°C.

[0302] Next, an insulating film 225f (see FIG. 225 ) is deposited to cover the insulator 223 and to become the insulator 225. FIG. 14A to FIG. 14D The insulating film 225f is an insulating film that becomes the insulator 225 in a later step, and the insulator described above can be used. The insulating film 225f can be deposited by sputtering, CVD, MBE, PLD, or ALD.

[0303] Since the insulating film 225f is deposited along the insulator 223, it is preferred that the coverage is high. Therefore, the insulating film 225f is preferably deposited using an ALD method with high coverage, etc. In addition, the insulator 225 preferably has a high aspect ratio, so the thickness of the insulating film 225f is preferably thin. Therefore, it is preferred to deposit the insulating film 225f using an ALD method that can adjust the film thickness to be thinner. For example, as the insulating film 225f, it is preferred to deposit hafnium oxide using a thermal ALD method. By depositing the insulating film 225f in this way, the insulating film 225f is formed in a manner that contacts the top surface and side surfaces of the insulator 223.

[0304] Next, a portion of the insulating film 225f is removed by anisotropic etching, and then the insulator 223 is removed (see FIG. 15A to FIG. 15D ). Thus, an insulator 225 with a high aspect ratio can be formed. By using the insulator 225, the channel width of the transistor 200 can be increased without increasing the occupied area, thereby improving the on-state current, field effect mobility and frequency characteristics of the transistor 200. In addition, the area of ​​the capacitor 100 can be increased without increasing the occupied area, thereby increasing the electrostatic capacitance of the capacitor 100.

[0305] like FIG. 15A to FIG. 15D As shown, by forming two insulators 225, the distance between the two insulators 225 can be set according to the size of the insulator 223. Thus, the distance between the insulators 225 can be shortened, and the occupied areas of the transistors 200a, 200b, the capacitors 100a, and the capacitors 100b can be reduced, thereby achieving high integration of the memory device.

[0306] It is preferable to use a dry etching method for anisotropic etching of the insulating film 225f.

[0307] As an etching gas for dry etching treatment, an etching gas containing halogen can be used. Specifically, an etching gas containing one or more of fluorine, chlorine and bromine can be used. As an etching gas, for example, one or a mixed gas of C4F6 gas, C5F6 gas, C4F8 gas, CF4 gas, SF6 gas, CHF3 gas, CH2F2 gas, Cl2 gas, BCl3 gas, SiCl4 and BBr3 gas can be used. In addition, oxygen gas, carbon dioxide gas, nitrogen gas, helium gas, argon gas, hydrogen gas or hydrocarbon gas can be appropriately added to the above-mentioned etching gas. In addition, depending on the object to be processed by dry etching treatment, a gas that does not contain halogen gas but contains hydrocarbon gas or hydrogen gas can also be used as an etching gas. As hydrocarbons used for etching gas, methane (CH4), ethane (C2H6), propane (C3H8), butane (C4H 10 ), ethylene (C2H4), propylene (C3H6), acetylene (C2H2) and propyne (C3H4) One or more. The etching conditions can be appropriately set according to the etching object.

[0308] As a dry etching device, a capacitively coupled plasma (CCP: Capacitively Coupled Plasma) etching device including parallel plate electrodes can be used. The capacitively coupled plasma etching device including parallel plate electrodes can also adopt a structure in which a high-frequency voltage is applied to one of the parallel plate electrodes. Alternatively, a structure in which a plurality of different high-frequency voltages are applied to one of the parallel plate electrodes can be adopted. Alternatively, a structure in which a high-frequency voltage with the same frequency is applied to each of the parallel plate electrodes can be adopted. Alternatively, a structure in which a high-frequency voltage with different frequencies is applied to each of the parallel plate electrodes can be adopted. Alternatively, a dry etching device with a high-density plasma source can be used. For example, as a dry etching device with a high-density plasma source, an inductively coupled plasma (ICP: Inductively Coupled Plasma) etching device can be used. The etching device can be appropriately set according to the etching object.

[0309] For example, when hafnium oxide is used for the insulating film 225f, a mixed gas of C4F8, H2, and Ar can be used as an etching gas in the CCP etching apparatus.

[0310] In addition, the above processing may use dry etching or wet etching to remove the insulator 223. For example, the insulator 223 may be removed by wet etching.

[0311] In addition, when the insulator 225 is formed by anisotropic etching, it is formed in a side wall shape that contacts the side surface of the insulator 223. That is, the insulator 225 is formed in a circumferential shape around the insulator 223. When the storage device is manufactured while the insulator 225 is maintained in a circumferential shape, as shown in FIG. FIG. 6A to FIG. 6D As shown, the insulator 225 is integrated through the transistor 200a and the transistor 200b.

[0312] 15, the unnecessary portion of the sidewall-shaped insulator in terms of the structure of the memory device is removed to form the insulator 225. When forming the insulator 225, the unnecessary portion of the insulator 225 may be etched away before anisotropically etching the insulating film 225f.

[0313] Next, an oxide film 230af is deposited on the insulator 222 and the insulator 225, and an oxide film 230bf is deposited on the oxide film 230af (see FIG. 16A to FIG. 16D). As the oxide film 230af, a metal oxide corresponding to the above-mentioned oxide 230a can be used, and as the oxide film 230bf, a metal oxide corresponding to the above-mentioned oxide 230b can be used. It is preferable to continuously deposit the oxide film 230af and the oxide film 230bf without exposing them to the atmospheric environment. By performing deposition without exposing them to the atmosphere, impurities or moisture from the atmospheric environment can be prevented from adhering to the oxide film 230af and the oxide film 230bf, so that the interface between the oxide film 230af and the oxide film 230bf or the vicinity of the interface can be kept clean.

[0314] The oxide film 230af and the oxide film 230bf may be deposited by, for example, sputtering, CVD, MBE, PLD, or ALD.

[0315] The oxide film 230af and the oxide film 230bf are preferably deposited using an ALD method with high coverage. By using the ALD method, the oxide film 230af and the oxide film 230bf can be deposited with high coverage on the side of the insulator 225. Thus, in the transistor 200, a channel formation region can also be provided on the side of the A3 side and the side of the A4 side of the insulator 225, thereby increasing the channel width of the transistor 200. Thus, the field effect mobility, on-state current and frequency characteristics of the transistor 200 can be improved.

[0316] The oxide film 230af can be deposited by the ALD method to form a metal oxide layer with In:Ga:Zn=1:3:2 [atomic ratio], a metal oxide layer with In:Ga:Zn=1:3:4 [atomic ratio], or a metal oxide layer with In:Ga:Zn=1:1:1 [atomic ratio]. In addition, the oxide film 230bf can be deposited by the ALD method to form a metal oxide layer with In:Ga:Zn=1:1:1 [atomic ratio] or a metal oxide layer with In:Zn=4:1 [atomic ratio]. In addition, the oxide film 230af and the oxide film 230bf can adopt a stacked structure of the above-mentioned metal oxide layers. For example, the oxide film 230bf can adopt a stacked film in which a metal oxide layer with In:Zn=4:1 [atomic ratio] and a metal oxide layer with In:Ga:Zn=1:1:1 [atomic ratio] are stacked in sequence. In addition, in the above-mentioned oxide film 230bf, a metal oxide layer with In:Ga:Zn=1:3:2 [atomic ratio] or a metal oxide layer with In:Ga:Zn=1:3:4 [atomic ratio] may be used instead of the metal oxide layer with In:Ga:Zn=1:1:1 [atomic ratio].

[0317] In addition, the oxide film 230af and the oxide film 230bf may also be deposited by sputtering. For example, when the oxide film 230af and the oxide film 230bf are deposited by sputtering, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. By increasing the ratio of oxygen contained in the sputtering gas, the excess oxygen in the deposited oxide film can be increased. In addition, when the above-mentioned oxide film is deposited by sputtering, an In-M-Zn oxide target or the like can be used.

[0318] In the case of forming the oxide film 230bf by sputtering, an oxygen-excess oxide semiconductor can be formed by depositing under the condition that the ratio of oxygen contained in the sputtering gas is greater than 30% and less than 100%, preferably greater than 70% and less than 100%. A transistor using an oxygen-excess oxide semiconductor in a channel formation region can obtain relatively high reliability. Note that one embodiment of the present invention is not limited to this. In the case of forming the oxide film 230bf by sputtering, an oxygen-deficient oxide semiconductor is formed when deposition is performed under the condition that the ratio of oxygen contained in the sputtering gas is set to greater than 1% and less than 30%, preferably greater than 5% and less than 20%. A transistor using an oxygen-deficient oxide semiconductor in a channel formation region can have a higher field effect mobility. In addition, by depositing while heating the substrate, the crystallinity of the oxide film can be improved.

[0319] In the present embodiment, the oxide film 230af is deposited by sputtering using an oxide target of In:Ga:Zn=1:3:2 [atomic ratio], an oxide target of In:Ga:Zn=1:3:4 [atomic ratio], an oxide target of In:Ga:Zn=1:1:1 [atomic ratio], or an oxide target of In:Ga:Zn=1:1:1.2 [atomic ratio]. In addition, the oxide film 230bf is deposited by sputtering using an oxide target of In:Ga:Zn=1:1:1 [atomic ratio], an oxide target of In:Ga:Zn=1:1:1.2 [atomic ratio], an oxide target of In:Ga:Zn=4:2:4.1 [atomic ratio], an oxide target of In:Ga:Zn=1:1:2 [atomic ratio], or an oxide target of In:Zn=4:1 [atomic ratio]. Each oxide film is preferably formed by appropriately selecting deposition conditions and atomic number ratios according to the properties required for the oxide 230 a and the oxide 230 b .

[0320] In addition, for example, the oxide film 230af can be deposited by sputtering, and the oxide film 230bf can be deposited by ALD. Here, one or both of the oxide film 230af and the oxide film 230bf can also adopt a stacked structure. For example, the oxide film 230af can be deposited by sputtering using any of an oxide target with In:Ga:Zn=1:1:1 [atomic ratio], an oxide target with In:Ga:Zn=1:1:1.2 [atomic ratio], an oxide target with In:Ga:Zn=1:3:2 [atomic ratio], or an oxide target with In:Ga:Zn=1:3:4 [atomic ratio].

[0321] The oxide film 230bf may be a metal oxide layer deposited by ALD. For example, the oxide film 230bf may be a stacked film of a metal oxide layer having an In:Zn=4:1 [atomic ratio] and a metal oxide layer having an In:Ga:Zn=1:1:1 [atomic ratio] stacked in sequence.

[0322] The crystallinity of the oxide film 230af can be improved by depositing the oxide film 230af by sputtering. For example, by first improving the crystallinity of the oxide film 230af and then depositing the oxide film 230bf on the oxide film 230af, part or all of the oxide film 230bf can be crystallized. In other words, the crystallinity of the oxide film 230af can be improved. For example, when the oxide film 230af is an oxide semiconductor film of a CAAC structure, the oxide film 230bf formed on the oxide film 230af can also be changed into an oxide semiconductor of a CAAC structure.

[0323] In addition, by depositing the oxide film 230bf using the ALD method, a thinner film can be deposited with high controllability. Thus, the oxide film 230bf can be made into a desired thinner film. By using the oxide film 230af and the oxide film 230bf, the electrical characteristics and reliability of the transistor 200 can be improved.

[0324] Note that the oxide film 230af and the oxide film 230bf are preferably deposited without being exposed to the atmosphere. For example, a multi-chamber deposition apparatus is preferably used. This can reduce the mixing of hydrogen into the oxide film 230af and the oxide film 230bf between each deposition step.

[0325] Next, heat treatment is preferably performed. The heat treatment may be performed within a temperature range where polycrystallization does not occur in the oxide film 230af and the oxide film 230bf. The heat treatment temperature is preferably 100°C or higher, 250°C or higher, or 350°C or higher and 650°C or lower, 600°C or lower, or 550°C or lower.

[0326] The heat treatment is carried out in a nitrogen gas or inert gas atmosphere or an atmosphere containing an oxidizing gas of more than 10ppm, more than 1% or more than 10%. For example, when the heat treatment is carried out in a mixed atmosphere of nitrogen gas and oxygen gas, the ratio of the oxygen gas is preferably set to about 20%. The heat treatment can also be carried out under reduced pressure. Alternatively, the heat treatment can also be carried out in a nitrogen gas or inert gas atmosphere, and then the heat treatment is carried out in an atmosphere containing an oxidizing gas of more than 10ppm, more than 1% or more than 10% to fill the oxygen that has been separated.

[0327] In addition, the gas used in the above heat treatment is preferably highly purified. For example, the amount of water contained in the gas used in the above heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and further preferably 0.05 ppb or less. By using highly purified gas for heat treatment, it is possible to prevent moisture and the like from being absorbed by the oxide film 230af and the oxide film 230bf as much as possible.

[0328] In this embodiment, as a heat treatment, a treatment is performed for 1 hour under the conditions of a flow ratio of nitrogen gas to oxygen gas of 4:1 and a temperature of 450°C. Such a heat treatment containing oxygen gas can reduce impurities such as carbon, water, and hydrogen in the oxide film 230af and the oxide film 230bf. By reducing the impurities in the film in this way, the crystallinity of the oxide film 230af and the oxide film 230bf is improved, and a denser structure with a higher density can be achieved. Therefore, the crystallized area in the oxide film 230af and the oxide film 230bf can be increased, and the in-plane unevenness of the crystallized area in the oxide film 230af and the oxide film 230bf can be reduced. Therefore, the in-plane unevenness of the electrical characteristics of the transistor can be reduced.

[0329] In addition, by performing the heat treatment, hydrogen in the insulator 216, the oxide film 230af, and the oxide film 230bf is absorbed by the insulator 225 and the insulator 222. In other words, hydrogen in the insulator 216, the oxide film 230af, and the oxide film 230bf diffuses into the insulator 225 and the insulator 222. Therefore, although the hydrogen concentration in the insulator 225 and the insulator 222 increases, the hydrogen concentration in the insulator 216, the oxide film 230af, and the oxide film 230bf decreases. Here, when the insulator 221 is provided in contact with the bottom surface of the insulator 222, impurities such as moisture or hydrogen can be prevented from entering from below the insulator 221 due to the heat treatment.

[0330] In particular, the oxide film 230af and the oxide film 230bf (later oxide 230a and oxide 230b) are used as a channel formation region of the transistor 200. The transistor 200 formed using the oxide film 230af and the oxide film 230bf with reduced hydrogen concentration has excellent reliability and is therefore preferred.

[0331] Next, a conductive film 242f is deposited on the oxide film 230bf (see FIG. 16A to FIG. 16D ). As the conductive film 242f, a conductive material corresponding to the above-mentioned conductive materials 242a and 242b can be used. After the oxide film 230bf is deposited, the conductive film 242f is deposited on and in contact with the oxide film 230bf without an etching process, so that the top surface of the oxide film 230bf can be protected by the conductive film 242f. As a result, since the diffusion of impurities into the oxide 230 constituting the transistor can be reduced, the electrical characteristics and reliability of the memory device can be improved.

[0332] The conductive film 242f can be deposited by, for example, sputtering, CVD, MBE, PLD, or ALD. By using the ALD method, the conductive film 242f can be deposited with high coverage on the side surface of the insulator 225. For example, tantalum nitride can be deposited as the conductive film 242f by using the ALD method.

[0333] Next, an insulating film 154f is deposited on the conductive film 242f (see FIG. 16A to FIG. 16D As the insulating film 154f, a High-k material corresponding to the above-mentioned insulators 154a and 154b can be used.

[0334] The insulating film 154f can be deposited by sputtering, CVD, MBE, PLD, ALD, etc. The insulating film 154f can be deposited with high coverage on the side of the insulator 225 by the ALD method. For example, as the insulating film 154f, a zirconium oxide film, an aluminum oxide film on the zirconium oxide film, and a stacked film of a zirconium oxide film on an aluminum oxide film can be deposited by thermal ALD.

[0335] When a stacked film is used as the insulating film 154f, it is preferable to continuously deposit the insulating film 154f without exposing it to the atmosphere. By depositing the insulating film 154f without exposing it to the atmosphere, the interface of the stacked film or the vicinity of the interface can be kept clean.

[0336] Next, a conductive film 160f is deposited on the insulating film 154f (see FIG. 16A to FIG. 16D ) As the conductive film 160f, a conductive material corresponding to the above-mentioned conductive materials 160a and 160b can be used.

[0337] The conductive film 160f can be deposited by sputtering, CVD, MBE, PLD, ALD, etc. The conductive film 160f can be deposited with high coverage on the side of the insulator 225 by the ALD method. For example, titanium nitride can be deposited as the conductive film 160f by the ALD method.

[0338] Next, the oxide film 230af, the oxide film 230bf, the conductive film 242f, the insulating film 154f, and the conductive film 160f are processed into island shapes by photolithography, thereby forming oxide 230a, oxide 230b, conductor 242a, conductor 242b, insulator 154a, insulator 154b, conductor 160a, and conductor 160b (see FIG. 17A to FIG. 17D ). The above processing can be performed by dry etching or wet etching. Processing by dry etching is suitable for micro-processing. For the conditions of dry etching and dry etching equipment, reference can be made to the previous description. In addition, the oxide film 230af, the oxide film 230bf, the conductive film 242f, the insulating film 154f and the conductive film 160f can also be processed under different conditions.

[0339] Through the above processing, the oxide 230a, oxide 230b, conductor 242a, conductor 242b, insulator 154a, insulator 154b, conductor 160a, and conductor 160b forming the transistor 200a and the capacitor 100a are separated from the oxide 230a, oxide 230b, conductor 242a, conductor 242b, insulator 154a, insulator 154b, conductor 160a, and conductor 160b forming the transistor 200b and the capacitor 100b. At this time, it is preferred that the oxide 230a, oxide 230b, conductor 242a, conductor 242b, insulator 154a, insulator 154b, conductor 160a, and conductor 160b are formed so as to cover at least a portion of the insulator 225 forming the transistor 200a and at least a portion of the insulator 225 forming the transistor 200b, respectively.

[0340] Furthermore, if Fig.17A As shown, the conductor 242a, the insulator 154a and the conductor 160a are opposite to the conductor 242b, the insulator 154b and the conductor 160b with the dotted line A3-A4. Thus, the conductor 242a used as one of the source electrode and the drain electrode of the transistor 200a and the conductor 242b used as the other of the source electrode and the drain electrode are formed. In addition, the capacitor 100a and the capacitor 100b including the conductor 242a, the insulator 154a on the conductor 242a and the conductor 160a on the insulator 154a are formed. Here, it is preferred that the side ends of the conductor 242a, the insulator 154a and the conductor 160a are consistent or roughly consistent, and the side ends of the conductor 242b, the insulator 154b and the conductor 160b are consistent or roughly consistent with each other.

[0341] In addition, oxide 230a and oxide 230b are formed so that at least a portion thereof overlaps with conductor 205. In addition, insulator 222 is exposed in a region that does not overlap with oxide 230a and oxide 230b. Parts of oxide 230a and oxide 230b overlap with conductor 242a, insulator 154a, and conductor 160a, and conductor 242b, insulator 154b, and conductor 160b. Here, it is preferred that, in the portion of oxide 230a and oxide 230b that overlaps with conductor 242a, conductor 242b, etc., two or more side ends of oxide 230a, oxide 230b, conductor 242a, insulator 154a, and conductor 160a coincide with or substantially coincide with each other, and two or more side ends of oxide 230a, oxide 230b, conductor 242b, insulator 154b, and conductor 160b coincide with or substantially coincide with each other.

[0342] In addition, the portion of the oxide 230a and the oxide 230b that does not overlap with the conductor 242a and the conductor 242b (or the portion of the oxide 230a and the oxide 230b located between the conductor 242a and the conductor 242b) is formed in a sidewall shape on the side of the insulator 225. Fig. 17C As shown, the side surface of oxide 230 a contacts insulator 225 , the bottom surface of oxide 230 a contacts insulator 222 , the side surface and bottom surface of oxide 230 b contact oxide 230 a , and oxide 230 a and oxide 230 b do not contact the top surface of insulator 225 .

[0343] As described above, in order to form the oxide 230a and the oxide 230b into a sidewall shape, it is preferred to process the oxide film 230af and the oxide film 230bf by anisotropic etching. The anisotropic etching of the oxide film 230af and the oxide film 230bf is preferably performed by dry etching. In addition, the conditions of the dry etching method and the dry etching apparatus can refer to the above description.

[0344] For example, a mask is formed by photolithography, and the conductive film 242f, the insulating film 154f, and the conductive film 160f are processed into an island shape, thereby forming the conductor 242a, the conductor 242b, the insulator 154a, the insulator 154b, the conductor 160a, and the conductor 160b, and then the oxide film 230af and the oxide film 230bf are anisotropically etched using the same mask. Thus, the oxide 230a and the oxide 230b are formed in a manner overlapping with the conductor 242a, the conductor 242b, etc., and in the area not overlapping with the conductor 242a, the conductor 242b, etc., they are formed in the shape of a side wall on the side of the insulator 225. In this way, it is preferred to process the oxide 230a, the oxide 230b, the conductor 242a, the conductor 242b, the insulator 154a, the insulator 154b, the conductor 160a, and the conductor 160b at one time. Thus, the number of steps of the storage device according to one embodiment of the present invention can be reduced. Thus, a method for manufacturing a storage device with high productivity can be provided.

[0345] like Fig. 17B As shown, the side surfaces of oxide 230a, oxide 230b, conductor 242a, conductor 242b, insulator 154a, insulator 154b, conductor 160a, and conductor 160b may also be perpendicular or substantially perpendicular to the top surface of insulator 222. By adopting such a structure, it is possible to realize a small area and high density when arranging a plurality of transistors.

[0346] However, the structure is not limited to the above, and the side surfaces of oxide 230a, oxide 230b, conductor 242a, conductor 242b, insulator 154a, insulator 154b, conductor 160a, and conductor 160b may also have a tapered shape. The taper angle of the side surfaces of oxide 230a, oxide 230b, conductor 242a, conductor 242b, insulator 154a, insulator 154b, conductor 160a, and conductor 160b may be, for example, 60° or more and less than 90°. In this way, by having the side surfaces have a tapered shape, the coverage of insulator 275 and the like is improved in the subsequent process, and defects such as voids can be reduced.

[0347] Note that in photolithography, first, the resist is exposed through a mask. Then, a developer is used to remove or leave the exposed area to form a resist mask. Then, an etching process is performed through the resist mask to process the conductor, semiconductor, or insulator into a desired shape. For example, a KrF excimer laser, ArF excimer laser, EUV (Extreme Ultraviolet) light, etc. can be used to expose the resist to form a resist mask. In addition, a liquid immersion technique in which the exposure is performed in a state where a liquid (for example, water) is filled between the substrate and the projection lens can also be used. In addition, an electron beam or an ion beam can also be used instead of the above-mentioned light. In addition, when an electron beam or an ion beam is used, a mask may sometimes not be used.

[0348] The resist mask that is unnecessary after processing can be removed by dry etching treatment such as ashing using oxygen plasma (hereinafter sometimes referred to as oxygen plasma treatment), wet etching treatment, dry etching treatment followed by wet etching treatment, or wet etching treatment followed by dry etching treatment.

[0349] Furthermore, a hard mask made of an insulator or a conductor may be used under the resist mask. When a hard mask is used, an insulating film or a conductive film serving as a hard mask material may be formed on the conductive film 160f and a resist mask may be formed thereon, and then the hard mask material may be etched to form a hard mask of a desired shape. The etching of the conductive film 160f and the like may be performed after removing the resist mask or without removing the resist mask. In the case of the latter, the resist mask may disappear during etching. The hard mask may be removed by etching after etching the oxide film 230bf and the like. On the other hand, in the case where the hard mask material does not affect the subsequent process or can be used in the subsequent process, it is not necessarily necessary to remove the hard mask.

[0350] In addition, a SOC (Spin On Carbon) film and a SOG (Spin On Glass) film may be deposited between the workpiece and the resist mask. By using the SOC film and the SOG film as a mask, the adhesion between the workpiece and the resist mask can be improved, thereby improving the durability of the mask pattern. For example, a SOC film, a SOG film, and a resist mask may be deposited sequentially on the workpiece to perform photolithography.

[0351] In addition, in the above description, the structure in which anisotropic etching is performed on the oxide film 230af and the oxide film 230bf is shown, but the present invention is not limited to this. For example, a structure in which anisotropic etching is performed on the conductive film 242f in addition to the oxide film 230af and the oxide film 230bf can also be adopted. In this case, a conductive film 242f is formed whose side surface in contact with the oxide 230b is processed into a sidewall shape. Similarly, a structure in which anisotropic etching is also performed on the insulating film 154f and the conductive film 160f can also be adopted.

[0352] Next, an insulator 275 is deposited to cover the oxide 230a, the oxide 230b, the conductor 242a, the conductor 242b, the insulator 154a, the insulator 154b, the conductor 160a, and the conductor 160b, and an insulator 280 is deposited on the insulator 275 (see 18A to 18D ) The insulator 275 and the insulator 280 can use the above-mentioned insulators.

[0353] Here, the insulator 275 is preferably in contact with the top surface of the insulator 222 .

[0354] As insulator 280, it is preferable to form an insulator with a flat top surface by forming an insulating film to be insulator 280 and then subjecting the insulating film to CMP. Alternatively, silicon nitride may be deposited on insulator 280 by, for example, sputtering and then subjected to CMP until it reaches insulator 280.

[0355] The insulator 275 and the insulator 280 can each be deposited by, for example, sputtering, CVD, MBE, PLD, or ALD.

[0356] The insulator 275 preferably uses an insulator that has a function of inhibiting oxygen transmission. For example, silicon nitride is preferably deposited by the PEALD method as the insulator 275. In addition, aluminum oxide is preferably deposited by the sputtering method as the insulator 275, and silicon nitride is deposited thereon by the PEALD method. When the insulator 275 has the above structure, the function of inhibiting the diffusion of impurities such as water and hydrogen and oxygen can be improved.

[0357] Thus, the oxide 230a, the oxide 230b, the conductors 242a, and the conductors 242b can be covered by the insulator 275 having the function of suppressing oxygen diffusion. Thus, direct diffusion of oxygen from the insulator 280 and the like into the oxide 230a, the oxide 230b, the conductors 242a, and the conductors 242b in the subsequent steps can be reduced.

[0358] In addition, silicon oxide is preferably deposited by sputtering as the insulator 280. By depositing the insulating film to be the insulator 280 by sputtering in an oxygen-containing atmosphere, an insulator 280 containing excess oxygen can be formed. By using a sputtering method that does not require the use of molecules containing hydrogen as a deposition gas, the hydrogen concentration in the insulator 280 can be reduced. In addition, heat treatment can also be performed before depositing the insulating film. The heat treatment can also be performed under reduced pressure, and the insulating film is continuously deposited without being exposed to the atmosphere. By performing this treatment, moisture and hydrogen attached to the surface of the insulator 275 can be removed, and the moisture concentration and hydrogen concentration in the oxide 230a and the oxide 230b can be reduced. The heat treatment can adopt the conditions of the above-mentioned heat treatment.

[0359] Next, the insulator 280 and the insulator 275 are processed by photolithography to form openings reaching the insulator 225, the oxide 230a, the oxide 230b, and the insulator 222 (see FIG. 19A to FIG. 19D ). The opening is formed in a region where the insulator 225, the oxide 230a, the oxide 230b, and the conductor 205 overlap. In addition, the opening is preferably formed between the conductor 240a and the conductor 240b.

[0360] The above method can be appropriately used in the photolithography method. In order to process the openings of the insulator 280 and the insulator 275 to be fine, it is preferable to use a photolithography method using light with a short wavelength such as EUV light or an electron beam.

[0361] The above processing is preferably performed by dry etching. Dry etching can perform anisotropic etching, so it is suitable for forming an opening with a high aspect ratio. Note that the dry etching conditions and dry etching equipment can refer to the above content.

[0362] In addition, FIG. 17A to FIG. 17D In the process shown in FIG. 1 , when the conductive film 242f is also anisotropically etched, it is preferred that FIG. 19A to FIG. 19D In the process shown in FIG. 1 , the remaining portion of the conductive film 242f is etched to form the conductive body 242a and the conductive body 242b. 9A to 9D As shown, conductors 242a and 242b are partially formed in regions that do not overlap conductors 160a and 160b, etc. Thus, conductors 242a and 242b are formed as sidewalls between conductors 242 and 160 so as to contact the side surfaces of oxide 230b.

[0363] After the openings of the insulator 280 and the insulator 275 are formed, an ashing treatment using oxygen plasma may be performed. By performing such an oxygen plasma treatment, impurities generated in the above-mentioned etching process and diffused into the oxide 230 and the like can be removed. Examples of such impurities include impurities resulting from components in the workpiece subjected to the above-mentioned etching process and impurities resulting from components in the gas used in the etching and the like. For example, chlorine, fluorine, tantalum, silicon, hafnium, and the like may be mentioned. In particular, when chlorine gas is used in the above-mentioned etching process, the oxide 230 is exposed to an atmosphere containing chlorine gas, and therefore, it is preferred to remove chlorine attached to the oxide 230. By removing impurities attached to the oxide 230 in this way, the electrical characteristics and reliability of the transistor may be improved.

[0364] In order to remove impurities and the like attached to the surface of the oxide 230b in the above-mentioned etching process, a washing process may also be performed. As a washing method, there are wet washing using a washing liquid or the like (which may also be referred to as a wet etching process), plasma treatment using plasma, washing using a heat treatment, etc., and the above-mentioned washings may be appropriately combined. Note that the above-mentioned groove may become deeper by performing this washing process.

[0365] As wet cleaning, an aqueous solution, pure water or carbonated water etc. formed by diluting one or more of ammonia, oxalic acid, phosphoric acid or hydrofluoric acid with carbonated water or pure water can be used. Alternatively, ultrasonic cleaning can be performed using the above aqueous solution, pure water or carbonated water. In addition, the above cleaning can also be appropriately combined.

[0366] Note that in this specification, etc., an aqueous solution of hydrofluoric acid diluted with pure water is sometimes referred to as dilute hydrofluoric acid, and an aqueous solution of ammonia diluted with pure water is sometimes referred to as dilute ammonia water. In addition, the concentration, temperature, etc. of the aqueous solution are appropriately adjusted according to the impurities to be removed, the structure of the storage device to be washed, etc. The ammonia concentration of the dilute ammonia water is preferably set to 0.01% or more and 5% or less, and more preferably set to 0.1% or more and 0.5% or less. In addition, the hydrogen fluoride concentration of the dilute hydrofluoric acid is preferably set to 0.01ppm or more and 100ppm or less, and more preferably set to 0.1ppm or more and 10ppm or less.

[0367] In addition, it is preferable to use a frequency of 200 kHz or higher, and more preferably a frequency of 900 kHz or higher for ultrasonic cleaning. By using such a frequency, damage to the oxide 230 b and the like can be reduced.

[0368] In addition, the above-mentioned washing treatment may be performed multiple times, and the washing liquid may be changed for each washing treatment. For example, the first washing treatment may be a treatment using dilute hydrofluoric acid or dilute ammonia water, and the second washing treatment may be a treatment using pure water or carbonated water.

[0369] In this embodiment, the cleaning process is performed by wet cleaning using dilute ammonia water. This cleaning process can remove impurities attached to the surface of the oxide 230a, the oxide 230b, etc. or diffused into the inside thereof. In addition, the crystallinity of the oxide 230a, the oxide 230b, etc. can be improved.

[0370] It is preferred to perform heat treatment after the above-mentioned etching or the above-mentioned washing. The temperature of the heat treatment is preferably above 100°C, above 250°C, or above 350°C and below 650°C, below 600°C, below 550°C, or below 400°C. The heat treatment is performed in an atmosphere of nitrogen gas, inert gas, or an oxidizing gas containing 10 ppm or more, 1% or more, or 10% or more. For example, it is preferred to perform the heat treatment in an oxygen-containing atmosphere, preferably at a flow ratio of nitrogen gas to oxygen gas of 4:1 and a temperature of 350°C for 1 hour. Thus, oxygen is supplied to the oxide 230a and the oxide 230b, thereby reducing oxygen vacancies. In addition, by performing the above-mentioned heat treatment, the crystallinity of the oxide 230b can be improved. Furthermore, the hydrogen remaining in the oxide 230a and the oxide 230b reacts with the supplied oxygen and the hydrogen can be removed (dehydrated) in the form of H2O. Thus, the hydrogen remaining in the oxide 230a and the oxide 230b can be inhibited from recombinating with oxygen vacancies to form V O H. Thus, the electrical characteristics of the transistor provided with the oxide 230 can be improved and the reliability can be improved. In addition, the non-uniformity of the electrical characteristics of the plurality of transistors formed on the same substrate can be suppressed. The above-mentioned heat treatment can also be performed under reduced pressure. Alternatively, the heat treatment can be performed in an oxygen atmosphere and then continuously in a nitrogen atmosphere without being exposed to the atmosphere.

[0371] When heat treatment is performed in a state where the conductor 242a and the conductor 242b are in contact with the oxide 230b, the sheet resistance of the region where the oxide 230b overlaps with the conductor 242a and the region where the oxide 230b overlaps with the conductor 242b may be reduced. In addition, the carrier concentration may be increased. Therefore, the region where the oxide 230b overlaps with the conductor 242a and the region where the oxide 230b overlaps with the conductor 242b can be made low-resistance in a self-aligned manner.

[0372] Next, an insulating film 250A (see FIG. 25A ) to be the insulator 250 is deposited so as to be embedded in the opening formed in the insulator 280 or the like. FIG. 20A to FIG. 20D Here, the insulating film 250A is in contact with the insulator 280, the insulator 275, the insulator 222, the insulator 225, the oxide 230a, and the oxide 230b.

[0373] The insulating film 250A can be deposited by sputtering, CVD, MBE, PLD or ALD. For example, the insulating film 250A is preferably deposited by the ALD method. As with the above-mentioned insulator 250, the insulating film 250A is preferably formed thin, and the thickness non-uniformity needs to be suppressed to a small value. In this regard, the ALD method is a deposition method that alternately introduces precursors and reactants (for example, oxidants, etc.). Since the thickness of the film can be adjusted according to the number of times the cycle is repeated, the thickness can be precisely adjusted. In addition, the insulating film 250A needs to be deposited on the bottom and side surfaces of the opening with high coverage. By using the ALD method, since each atomic layer can be deposited on the bottom and side surfaces of the above-mentioned opening, the insulating film 250A can be formed in the opening with high coverage.

[0374] When the insulating film 250A is deposited by the ALD method, ozone (O3), oxygen (O2), water (H2O), etc. can be used as an oxidant. By using ozone (O3), oxygen (O2), etc. that do not contain hydrogen as an oxidant, hydrogen diffused into the oxide 230b can be reduced.

[0375] The insulator 250 may adopt a laminated structure as shown in FIG. 3 and the like. Figure 3A As shown, the insulator 250 may adopt a stacked structure of insulators 250a to 250d. In this case, aluminum oxide may be deposited as the insulator 250a by thermal ALD, silicon oxide may be deposited as the insulator 250b by PEALD, hafnium oxide may be deposited as the insulator 250c by thermal ALD, and silicon nitride may be deposited as the insulator 250d by PEALD.

[0376] In addition, it is preferable to perform microwave treatment in an oxygen-containing atmosphere after the insulating film 250A is deposited or after any insulator constituting the insulating film 250A is deposited. Here, microwave treatment refers to, for example, treatment using an apparatus including a power source for generating high-density plasma using microwaves. In addition, in this specification, etc., microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0377] Microwave treatment, for example, preferably uses a microwave processing device including a power supply that generates high-density plasma using microwaves. Here, the frequency of the microwave processing device is preferably set to be above 300 MHz and below 300 GHz, more preferably above 2.4 GHz and below 2.5 GHz, for example, it can be 2.45 GHz. By using high-density plasma, high-density oxygen free radicals can be generated. In addition, the power of the power supply that applies microwaves in the microwave processing device is preferably above 1000 W and below 10000 W, more preferably above 2000 W and below 5000 W. In addition, the microwave processing device may also include a power supply that applies RF to one side of the substrate. In addition, by applying RF to one side of the substrate, the oxygen ions generated by the high-density plasma can be efficiently introduced into the oxide 230 b.

[0378] In addition, the microwave treatment is preferably carried out under reduced pressure, and the pressure is preferably 10Pa or more and 1000Pa or less, more preferably 300Pa or more and 700Pa or less. In addition, the treatment temperature is preferably 750°C or less, more preferably 500°C or less, for example, about 250°C. In addition, it is also possible to continuously perform heat treatment without being exposed to the outside air after the oxygen plasma treatment. The temperature of the heat treatment is, for example, preferably 100°C or more and 750°C or less, more preferably 300°C or more and 500°C or less.

[0379] In addition, for example, the above-mentioned microwave treatment can be performed using oxygen gas and argon gas. Here, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 0% and less than 100%. Preferably, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 0% and less than 50%. More preferably, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 10% and less than 40%. Further preferably, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 10% and less than 30%. In this way, by performing microwave treatment in an oxygen-containing atmosphere, the carrier concentration in the oxide 230b can be reduced. In addition, by preventing excessive oxygen from being introduced into the processing chamber during microwave treatment, the carrier concentration in the oxide 230b can be prevented from being excessively reduced.

[0380] By performing microwave treatment in an oxygen-containing atmosphere, microwaves or high frequencies such as RF can be used to convert oxygen gas into plasma and the oxygen plasma can be applied to the region between the conductors 242a and 242b of the oxide 230b. The V O H is separated into oxygen vacancies and hydrogen, and hydrogen is removed from the region. Figure 3AWhen the structure shown in the figure is used, it is preferable to use an insulating film (for example, aluminum oxide, etc.) having the function of capturing or fixing hydrogen as the insulator 250a. By adopting the above structure, the insulator 250a can capture or fix hydrogen generated by microwave treatment. In this way, the V contained in the channel formation region can be reduced. O H. Thus, oxygen vacancies and V O H and thus reduce the carrier concentration. In addition, by supplying oxygen radicals generated in the above oxygen plasma to oxygen vacancies formed in the channel formation region, the oxygen vacancies in the channel formation region can be further reduced, thereby reducing the carrier concentration.

[0381] As oxygen injected into the channel formation region, there are various forms such as oxygen atoms, oxygen molecules, oxygen ions and oxygen free radicals (also called O free radicals, atoms, molecules or ions containing unpaired electrons). The oxygen injected into the channel formation region can be any one or more of the above forms, and oxygen free radicals are particularly preferred. In addition, since the film quality of the insulator 250 can be improved, the reliability of the transistor is improved.

[0382] In addition, impurities such as carbon in the oxide 230b can be removed by performing microwave treatment. By removing carbon as an impurity in the oxide 230b, the crystallinity of the oxide 230b can be improved. Thus, the oxide 230b can be formed into a CAAC-OS. In particular, when the oxide 230b is deposited by the ALD method, carbon contained in the precursor sometimes enters the oxide 230b, so it is preferable to remove carbon by microwave treatment.

[0383] On the other hand, the oxide 230b has a region overlapping with any one of the conductors 242a and 242b. This region can be used as a source region or a drain region. Here, the conductors 242a and 242b are preferably used as a shielding film to protect against microwaves, RF and other high frequencies or oxygen plasma when microwave treatment is performed in an oxygen-containing atmosphere. Therefore, the conductors 242a and 242b preferably have a function of shielding electromagnetic waves of 300 MHz or more and 300 GHz or less, for example, 2.4 GHz or more and 2.5 GHz or less.

[0384] The conductors 242a and 242b shield the microwaves, high frequencies such as RF, oxygen plasma, etc., and thus do not act on the region of the oxide 230b that overlaps with any of the conductors 242a and 242b. Thus, the microwave treatment does not cause V to occur in the source region and the drain region. O The decrease in H and the supply of excessive oxygen can prevent the decrease in carrier concentration.

[0385] As described above, oxygen vacancies and V can be selectively removed in the channel formation region of the oxide semiconductor. OH makes the channel formation region i-type or substantially i-type. In addition, it is possible to suppress the region used as the source region or the drain region from being supplied with excessive oxygen and maintain the conductivity (the state of the low resistance region) before the microwave treatment. Thus, it is possible to suppress the change of the electrical characteristics of the transistor and suppress the non-uniformity of the electrical characteristics of the transistor within the substrate surface.

[0386] In addition, during the microwave treatment, sometimes the microwave and the molecules in the oxide 230b directly transfer heat energy to the oxide 230b due to electromagnetic interaction. Sometimes the oxide 230b is heated by the heat energy. Sometimes this heat treatment is called microwave annealing. By performing the microwave treatment in an oxygen-containing atmosphere, sometimes an effect equivalent to oxygen annealing can be obtained. In addition, it is considered that: when the oxide 230b contains hydrogen, the above heat energy is transferred to the hydrogen in the oxide 230b and the activated hydrogen is released from the oxide 230b.

[0387] Furthermore, by performing microwave treatment to modify the film quality of the insulator 250, diffusion of hydrogen, water, impurities, etc. can be suppressed. Thus, diffusion of hydrogen, water, impurities, etc. through the insulator 250 to the oxide 230b, the oxide 230a, etc. due to post-processes such as deposition of a conductive film to become the conductor 260 or post-processes such as heat treatment can be suppressed. In this way, by improving the film quality of the insulator 250, the reliability of the transistor can be improved.

[0388] In addition, heat treatment can be performed while maintaining a reduced pressure state after microwave treatment. By performing such treatment, hydrogen in the insulating film, oxide 230b and oxide 230a can be efficiently removed. In addition, a portion of hydrogen is sometimes doped by conductors 242a and 242b. In addition, the step of maintaining a reduced pressure state and performing heat treatment after microwave treatment can be repeated. By repeatedly performing heat treatment, hydrogen in the insulating film, oxide 230b and oxide 230a can be further efficiently removed. Note that the heat treatment temperature is preferably above 300°C and below 500°C. The above-mentioned microwave treatment, i.e., microwave annealing, can also serve as the heat treatment. When oxide 230b and the like are sufficiently heated by microwave annealing, the heat treatment may not be performed.

[0389] When the insulator 250 adopts a stacked structure of insulators 250a to 250d, it is preferred to perform microwave treatment after the insulator 250b is deposited. Furthermore, microwave treatment may be performed again after the insulator 250c is deposited. In this way, microwave treatment in an oxygen-containing atmosphere may be performed multiple times (at least twice or more).

[0390] Next, a conductive film 260A to be the conductor 260a and a conductive film 260B to be the conductor 260b are sequentially deposited (see FIG. 21A to FIG. 21D). The conductive film 260A and the conductive film 260B can be deposited by, for example, sputtering, CVD, MBE, PLD, electroplating, or ALD. In this embodiment, titanium nitride is deposited as the conductive film 260A by the ALD method, and tungsten is deposited as the conductive film 260B by the CVD method.

[0391] Next, the insulating film 250A, the conductive film 260A, and the conductive film 260B are polished by CMP until the insulator 280 is exposed. That is, the portion of the insulating film 250A, the conductive film 260A, and the conductive film 260B exposed from the above-mentioned opening is removed. As a result, the insulator 250 and the conductor 260 (conductor 260a and conductor 260b) are formed in the opening overlapping with the conductor 205 (see FIG. 22A to FIG. 22D ).

[0392] Thus, the insulator 250 is provided in the opening so as to be in contact with the insulator 280, the insulator 275, the insulator 225, the oxide 230b, the oxide 230a, and the insulator 222. Furthermore, the conductor 260 is arranged so as to be embedded in the opening via the insulator 250. Thus, the transistor 200 is formed.

[0393] Next, an insulator 282 is formed on the insulator 250, the conductor 260, and the insulator 280. The insulator 282 can be deposited, for example, by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulator 282 is preferably deposited by a sputtering method. By using a sputtering method that does not require the use of molecules containing hydrogen as a deposition gas, the hydrogen concentration in the insulator 282 can be reduced.

[0394] In addition, by depositing the insulator 282 in an oxygen-containing atmosphere by sputtering, oxygen can be added to the insulator 280 while the deposition is being performed. Thus, the insulator 280 can contain excess oxygen. At this time, it is preferable to deposit the insulator 282 while heating the substrate. By depositing the insulator 282 in this way, oxygen can diffuse from the insulator 280 through the insulator 250 into the oxide 230b, thereby supplying an appropriate amount of oxygen to the oxide 230b. In addition, by providing the insulator 250a in the insulator 250, it is possible to prevent excessive oxygen from being supplied to the insulator 250 and causing the conductors 242a and 242b near the insulator 250 to be over-oxidized.

[0395] In this embodiment, aluminum oxide is deposited as the insulator 282 by sputtering using an aluminum target in an atmosphere containing an oxygen gas. The amount of oxygen injected into the lower layer of the insulator 282 can be controlled according to the magnitude of the RF power applied to the substrate. For example, the smaller the RF power, the less oxygen is injected into the lower layer of the insulator 282, and the oxygen amount is easily saturated even if the insulator 282 is thin. In addition, the greater the RF power, the more oxygen is injected into the lower layer of the insulator 282. By reducing the RF power, the amount of oxygen injected into the insulator 280 can be suppressed. Alternatively, an insulator 282 having a two-layer stacked structure can also be deposited. At this time, for example, RF power is not applied to the substrate to deposit the lower layer of the insulator 282, and RF power is applied to the substrate to deposit the upper layer of the insulator 282.

[0396] In addition, the frequency of RF is preferably 10 MHz or higher, and is typically 13.56 MHz. The higher the frequency of RF, the less damage to the substrate can be caused.

[0397] In addition, heat treatment may be performed before depositing the insulator 282. The heat treatment may be performed under reduced pressure, and the insulator 282 may be continuously deposited without being exposed to the atmosphere. By performing such treatment, moisture and hydrogen attached to the surface of the insulator 280 may be removed, and the moisture concentration and hydrogen concentration in the insulator 280 may be reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the temperature of the heat treatment is set to 250° C.

[0398] Next, an insulator 283 is formed on the insulator 282. The insulator 283 can be deposited by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulator 283 is preferably deposited by a sputtering method. By using a sputtering method that does not require molecules containing hydrogen to be used for a deposition gas, the hydrogen concentration in the insulator 283 can be reduced. In this embodiment, silicon nitride is deposited by a sputtering method as the insulator 283.

[0399] Here, it is preferable to continuously deposit insulator 282 and insulator 283 without exposing them to the atmosphere. By depositing them without exposing them to the atmosphere, impurities or moisture from the atmosphere can be prevented from adhering to insulator 282 and insulator 283, so that the interface between insulator 282 and insulator 283 or the vicinity of the interface can be kept clean.

[0400] In addition, heat treatment may be performed after the insulator 283 is deposited. The temperature of the heat treatment is preferably 100° C. or more and 400° C. or less. By performing the heat treatment, hydrogen in the insulator 280, the insulator 250, and the oxide 230 is absorbed by the insulator 282. In other words, hydrogen in the insulator 280, the insulator 250, and the oxide 230 diffuses to the insulator 282. Therefore, although the hydrogen concentration of the insulator 282 increases, the hydrogen concentrations of the insulator 280, the insulator 250, and the oxide 230 all decrease. In addition, by providing the insulator 283 in contact with the top surface of the insulator 282, impurities such as moisture or hydrogen can be prevented from entering from above the insulator 283 during the heat treatment. In addition, by performing the heat treatment, hydrogen in the oxide 230 is absorbed by the insulator 222. In other words, hydrogen in the oxide 230 diffuses to the insulator 222. Therefore, although the hydrogen concentration of the insulator 222 increases, the hydrogen concentration of the oxide 230 decreases. By providing the insulator 221 in contact with the bottom surface of the insulator 222 , it is possible to prevent impurities such as moisture and hydrogen from entering from below the insulator 221 during the heat treatment.

[0401] Next, openings reaching the conductor 160a are formed in the insulators 275, 280, 282, and 283, and openings reaching the conductor 242b are formed in the insulators 154b, 160b, 275, 280, 282, and 283 (see FIG. Figures 1A to 1D ). The opening can be formed by photolithography. Figure 1A The shape of the opening when viewed from above is circular, but is not limited to this. For example, when viewed from above, the opening may also have a roughly circular shape such as an ellipse, a polygonal shape such as a quadrangle, or a shape in which the corners of a polygon such as a quadrangle are curved.

[0402] Next, an insulating film to be the insulator 241 is deposited, and the insulating film is anisotropically etched to form the insulator 241a in the opening reaching the conductor 160a and the insulator 241b in the opening reaching the conductor 242b (see FIG. 24). Figures 1A to 1D ). The insulating film that becomes the insulator 241 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film that becomes the insulator 241, an insulating film having a function of suppressing the permeation of oxygen is preferably used. For example, it is preferable to deposit aluminum oxide by an ALD method, and to deposit silicon nitride thereon by a PEALD method. Silicon nitride is preferred because it has a high barrier property against hydrogen.

[0403] In addition, as anisotropic etching of the insulating film to be the insulator 241, for example, a dry etching method or the like can be used. By providing the insulator 241 on the side wall portion of the opening, it is possible to suppress the penetration of oxygen from the outside and prevent oxidation of the conductors 240a and 240b to be formed next. In addition, it is possible to prevent impurities such as water and hydrogen contained in the insulator 280 from diffusing into the conductors 240a and 240b.

[0404] Next, a conductive film to be the conductor 240a and the conductor 240b is formed. The conductive film to be the conductor 240a and the conductor 240b is preferably a laminated structure including a conductor having a function of suppressing the permeation of impurities such as water and hydrogen. For example, it may be a laminated structure of tantalum nitride, titanium nitride, etc. and tungsten, molybdenum, copper, etc. The conductive film to be the conductor 240a and the conductor 240b can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0405] Next, a portion of the conductive film to be the conductors 240a and 240b is removed by CMP treatment, thereby exposing the top surface of the insulator 283. As a result, the conductive film remains only in the opening, thereby forming the conductors 240a and 240b with flat top surfaces (see FIG. Figures 1A to 1D ). Note that sometimes a portion of the top surface of the insulator 283 is removed by this CMP process.

[0406] By providing the conductor 240 a in contact with the conductor 160 a as described above, the conductor 160 a serving as one terminal of the capacitor 100 can be electrically connected to the wiring.

[0407] Furthermore, by providing the conductor 240b in contact with the conductor 242b, the conductor 240b serving as one of the source and the drain of the transistor 200 can be electrically connected to a wiring. Here, the conductor 240b is preferably electrically insulated from the conductor 160b by the insulator 241b.

[0408] In addition, a conductive film serving as wiring or a conductive film serving as a plug can be formed over the conductors 240a and 240b.

[0409] Through the above steps, the memory device shown in FIG. 1 can be manufactured.

[0410] This embodiment mode can be appropriately combined with other embodiment modes. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be appropriately combined.

[0411] (Implementation Method 2)

[0412] In this embodiment, a comparison between the OS transistor described in the above embodiment and a transistor including silicon in a channel formation region (also referred to as a Si transistor) is described.

[0413] [OS Transistor]

[0414] It is preferable to use an oxide semiconductor with a low carrier concentration for the OS transistor. For example, the carrier concentration of the channel formation region of the oxide semiconductor is 1×10 18 cm -3 Below, preferably below 1×10 17 cm -3 , more preferably less than 1×10 16 cm -3 , and more preferably less than 1×10 13 cm -3 , and further preferably less than 1×10 10 cm -3 , and is 1×10 -9 cm -3 In the case of reducing the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film can be reduced to reduce the defect state density. In this specification, etc., a state in which the impurity concentration is low and the defect state density is low is referred to as high-purity intrinsic or substantially high-purity intrinsic. In addition, an oxide semiconductor with a low carrier concentration is sometimes referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0415] Since high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors have a low defect state density, they sometimes have a low trap state density. In addition, it takes a long time for the charges captured by the trap states of the oxide semiconductor to disappear, and sometimes they act like fixed charges. Therefore, sometimes the electrical characteristics of a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap state density are unstable.

[0416] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the nearby film. As impurities, hydrogen, nitrogen, etc. can be cited. Note that impurities in oxide semiconductors refer to, for example, elements other than the main components that constitute the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be said to be an impurity.

[0417] In an OS transistor, when impurities and oxygen vacancies exist in the channel formation region of an oxide semiconductor, the electrical characteristics are easily changed and reliability may be reduced. In addition, in an OS transistor, hydrogen enters the oxygen vacancies in the oxide semiconductor to form defects (the bottom surface is sometimes called V OH), electrons that become carriers may be generated. In addition, when V O When the voltage is V, the donor concentration in the channel formation region may increase. As the donor concentration in the channel formation region increases, the threshold voltage may become uneven. Therefore, when oxygen vacancies are included in the channel formation region of the oxide semiconductor, the transistor may have a normally-on characteristic (a characteristic in which a channel exists and current flows in the transistor even when no voltage is applied to the gate electrode). Therefore, in the channel formation region of the oxide semiconductor, it is preferable to minimize impurities, oxygen vacancies, and V. O H.

[0418] In addition, the band gap of the oxide semiconductor is preferably larger than the band gap of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and more preferably 3.0 eV or more. By using an oxide semiconductor with a larger band gap than silicon, the off-state current (also called Ioff) of the transistor can be reduced.

[0419] For example, in Si transistors, as the miniaturization of transistors progresses, short channel effects (Short Channel Effect: also called SCE) appear. Therefore, miniaturization of Si transistors is difficult. One of the reasons for the short channel effect is that the band gap of silicon is small. On the other hand, in OS transistors, oxide semiconductors, which are semiconductor materials with large band gaps, are used, so the short channel effect can be suppressed. In other words, OS transistors are transistors with no short channel effect or very little short channel effect.

[0420] The short channel effect refers to the degradation of electrical characteristics that occurs with the miniaturization of transistors (reduction of channel length). Specific examples of the short channel effect include a reduction in threshold voltage, an increase in subthreshold swing value (sometimes recorded as S value), and an increase in leakage current. Here, the S value refers to the change in gate voltage in the subthreshold region that changes the drain current value by one digit with a fixed drain voltage.

[0421] As an indicator of resistance to short channel effects, characteristic length is widely used. Characteristic length refers to an indicator of the curvature of the potential in the channel formation region. The smaller the characteristic length, the more rapidly the potential rises, so it can be said that the ability to resist short channel effects is high.

[0422] OS transistors are accumulation-type transistors, and Si transistors are inversion-type transistors. Therefore, compared with Si transistors, the characteristic length between the source region and the channel formation region and the characteristic length between the drain region and the channel formation region in OS transistors are smaller. Therefore, OS transistors have a higher ability to resist short channel effects than Si transistors. That is, when you want to manufacture transistors with a small channel length, OS transistors are more suitable than Si transistors.

[0423] Even when the carrier concentration of the oxide semiconductor is reduced to the point where the channel formation region is i-type or substantially i-type, the conduction band bottom of the channel formation region is lowered due to the conduction-band-lowering (CBL) effect in the short channel transistor, so the energy difference of the conduction band bottom between the source region or the drain region and the channel formation region is likely to be reduced to more than 0.1 eV and less than 0.2 eV. Thus, the OS transistor can be regarded as having n + / n - / n + The accumulation type junction-less (junctionless) transistor structure or n + / n - / n + The accumulation type non-junction transistor structure, in which the channel formation region is n - Type region, source region and drain region are n + Type area.

[0424] When the above structure is used as an OS transistor, good electrical characteristics can be achieved even if the semiconductor device is miniaturized or highly integrated. For example, even if the gate length of the OS transistor is less than 20nm, less than 15nm, less than 10nm, less than 7nm or less than 6nm and more than 1nm, more than 3nm or more than 5nm, good electrical characteristics can be obtained. On the other hand, in Si transistors, it is sometimes difficult to have a gate length of less than 20nm or less than 15nm due to the occurrence of short channel effects. Therefore, compared with Si transistors, OS transistors are more suitable for use as transistors with a small channel length. The gate length is the length of the gate electrode in the direction of the carrier movement channel formation region when the transistor is working, and is the width of the bottom surface of the gate electrode in the plan view of the transistor.

[0425] In addition, the frequency characteristics of the transistor can be improved by miniaturizing the OS transistor. Specifically, the cutoff frequency of the transistor can be increased. When the gate length of the OS transistor is within the above range, for example, at room temperature, the cutoff frequency of the transistor can be 50 GHz or more, preferably 100 GHz or more, and more preferably 150 GHz or more.

[0426] As described above, the OS transistor has advantages superior to the Si transistor, such as a small off-state current and the ability to manufacture a transistor with a small channel length.

[0427] The configuration, structure, method, and the like described in this embodiment mode can be used in combination with the configuration, structure, method, and the like described in other embodiments mode and the like as appropriate.

[0428] (Implementation 3)

[0429] In this embodiment, refer to Figure 23 to Figure 28 A storage device using one embodiment of the present invention will be described.

[0430] In this embodiment mode, a structural example of a memory device using a memory cell including the structure described in the above embodiment mode is described. In this embodiment mode, a structural example of a memory device is described in which a layer including stacked memory cells and a layer including a functional circuit having a function of amplifying a data potential held in the memory cell and outputting it are provided.

[0431] [Configuration Example of Storage Device]

[0432] Fig.23 This is a block diagram showing a storage device according to one embodiment of the present invention.

[0433] Fig.23 The memory device 300 shown includes a driving circuit 21 and a memory array 20. The memory array 20 includes a plurality of memory cells 10 and a functional layer 50 having a plurality of functional circuits 51.

[0434] Fig.23 The example in which the memory array 20 includes a plurality of memory cells 10 arranged in a matrix of m rows and n columns (m and n are integers greater than or equal to 2) is shown. Fig.23 An example is shown in which a functional circuit 51 is provided for each wiring BL serving as a bit line, and an example is also shown in which the functional layer 50 includes n functional circuits 51 provided corresponding to n wirings BL.

[0435] exist Fig.23 , the 1st row and 1st column storage cell 10 is represented as storage cell 10[1, 1], and the mth row and nth column storage cell 10 is represented as storage cell 10[m, n]. In addition, in the present embodiment, etc., sometimes "row i" is written to represent an arbitrary row. In addition, sometimes "column j" is written to represent an arbitrary column. Therefore, i is an integer greater than 1 and less than m, and j is an integer greater than 1 and less than n. In addition, in the present embodiment, etc., the i-th row and j-th column storage cell 10 is represented as storage cell 10[i, j]. Note that in the present embodiment, etc., when expressed as "i+α" (α is a positive integer or a negative integer), "i+α" is not less than 1 and not greater than m. Similarly, when expressed as "j+α", "j+α" is not less than 1 and not greater than n.

[0436] In addition, the memory array 20 includes m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction. In the present embodiment and the like, the first (1st row) wiring WL is represented as wiring WL[1], and the mth (mth row) wiring WL is represented as wiring WL[m]. Similarly, the first (1st row) wiring PL is represented as wiring PL[1], and the mth (mth row) wiring PL is represented as wiring PL[m]. Similarly, the first (1st column) wiring BL is represented as wiring BL[1], and the nth (nth column) wiring BL is represented as wiring BL[n].

[0437] The plurality of memory cells 10 arranged in the i-th row are electrically connected to the i-th row wiring WL (wiring WL[i]) and the i-th row wiring PL (wiring PL[i]). The plurality of memory cells 10 arranged in the j-th column are electrically connected to the j-th column wiring BL (wiring BL[j]).

[0438] The memory array 20 can use DOSRAM (registered trademark) (Dynamic Oxide Semiconductor Random Access Memory). DOSRAM is a RAM including 1T (transistor) 1C (capacitor) type memory cells, and is a memory in which the access transistor is an OS transistor. The current flowing between the source and the drain of the OS transistor in the off state, that is, the leakage current is extremely small. In DOSRAM, by turning off the access transistor (making it in a non-conducting state), the charge based on the data stored in the capacitor element (capacitor) can be maintained for a long time. Therefore, compared with a DRAM composed of a transistor (Si transistor) containing silicon in the channel formation region, the refresh operation frequency of the DOSRAM can be lower. As a result, low power consumption can be achieved. In addition, since the frequency characteristics of the OS transistor are high, high-speed reading and writing of the storage device can be performed. Thus, a storage device with a high operating speed can be provided.

[0439] For example, Fig.23 The memory array 20 shown may include a plurality of memory arrays 20[1] to 20[m] stacked together. By arranging the memory arrays 20[1] to 20[m] included in the memory array 20 in a direction perpendicular to the substrate surface on which the drive circuit 21 is disposed, the storage density of the memory cell 10 may be increased.

[0440] Wiring BL is used as a bit line for writing and reading data. Wiring WL is used as a word line for controlling the opening or closing (conduction state or non-conduction state) of the access transistor used as a switch. Wiring PL is used as a constant potential line connected to the capacitor element. In addition, wiring CL (not shown) can be separately provided as a wiring for transmitting the back gate potential to the back gate of the OS transistor of the access transistor. In addition, a structure in which wiring PL also serves as a transmission back gate potential can also be adopted.

[0441] The memory cells 10 included in the memory arrays 20[1] to 20[m] are connected to the functional circuit 51 through the wiring BL. The wiring BL can be arranged in a direction perpendicular to the surface of the substrate on which the driving circuit 21 is provided. By arranging the wiring BL extending from the memory cells 10 included in the memory arrays 20[1] to 20[m] in a direction perpendicular to the surface of the substrate, the length of the wiring between the memory array 20 and the functional circuit 51 can be shortened. Therefore, since the signal transmission distance between the two circuits connected to the bit line can be shortened and the resistance and parasitic capacitance of the bit line can be greatly reduced, the power consumption and signal delay can be reduced. In addition, even if the capacitance of the capacitor element included in the memory cell 10 is reduced, the memory device can operate.

[0442] The functional circuit 51 has a function of amplifying the data potential held in the memory cell 10 and outputting it to the sense amplifier 46 included in the drive circuit 21 through the wiring GBL (not shown) described later. By adopting this structure, a small potential difference of the wiring BL can be amplified when reading data. The wiring GBL can be arranged in a direction perpendicular to the surface of the substrate on which the drive circuit 21 is provided, similarly to the wiring BL. By arranging the wiring BL and the wiring GBL extending from the memory cell 10 included in the memory array 20[1] to 20[m] in a direction perpendicular to the substrate surface, the length of the wiring between the functional circuit 51 and the sense amplifier 46 can be shortened. Therefore, since the signal transmission distance between the two circuits connected to the wiring GBL can be shortened and the resistance and parasitic capacitance of the wiring GBL can be greatly reduced, power consumption and signal delay can be reduced.

[0443] Furthermore, the wiring BL is provided in such a manner as to be in contact with the semiconductor layer of the transistor included in the memory cell 10. Alternatively, the wiring BL is provided in such a manner as to be in contact with a region of the semiconductor layer of the transistor included in the memory cell 10 that functions as a source or a drain. Alternatively, the wiring BL is provided in such a manner as to be in contact with a conductor that is in contact with a region of the semiconductor layer of the transistor included in the memory cell 10 that functions as a source or a drain. That is, the wiring BL can be said to be a wiring that electrically connects one of the source and the drain of the transistor included in the memory cell 10 in each layer of the memory array 20 to the functional circuit 51 in the vertical direction.

[0444] The memory array 20 can be overlapped on the drive circuit 21. By overlapping the drive circuit 21 and the memory array 20, the signal transmission distance between the drive circuit 21 and the memory array 20 can be shortened. Therefore, the resistance and parasitic capacitance between the drive circuit 21 and the memory array 20 are reduced, and the power consumption and signal delay can be reduced. In addition, the storage device 300 can be miniaturized.

[0445] By using OS transistors similar to the transistors included in the memory cell 10 of the DOSRAM, the functional circuit 51 can be freely arranged on a circuit using Si transistors similar to the memory array 20[1] to 20[m], thereby making it easy to integrate. By adopting a structure in which the functional circuit 51 amplifies the signal, the circuit of the subsequent circuit such as the sense amplifier 46 can be miniaturized, thereby achieving miniaturization of the memory device 300.

[0446] The drive circuit 21 includes a PSW 22 (power switch), a PSW 23 , and a peripheral circuit 31 . The peripheral circuit 31 includes a peripheral circuit 41 , a control circuit 32 , and a voltage generation circuit 33 .

[0447] In the storage device 300, each circuit, each signal, and each voltage can be appropriately selected as needed. Alternatively, other circuits or other signals can be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are signals input from the outside, and signal RDA is a signal output to the outside. Signal CLK is a clock signal.

[0448] In addition, the signal BW, the signal CE, and the signal GW are control signals. The signal CE is a chip enable signal, the signal GW is a global write enable signal, and the signal BW is a byte write enable signal. The signal ADDR is an address signal. The signal WDA is write data, and the signal RDA is read data. The signal PON1 and the signal PON2 are power gating control signals. In addition, the signal PON1 and the signal PON2 can also be generated in the control circuit 32.

[0449] The control circuit 32 is a logic circuit that has the function of controlling the overall operation of the storage device 300. For example, the control circuit performs a logic operation on the signal CE, the signal GW, and the signal BW to determine the operation mode (for example, writing operation, reading operation) of the storage device 300. Alternatively, the control circuit 32 generates a control signal for the peripheral circuit 41 to execute the above operation mode.

[0450] The voltage generating circuit 33 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 33. For example, when the signal WAKE is applied with an H level signal, the signal CLK is input to the voltage generating circuit 33, and the voltage generating circuit 33 generates a negative voltage.

[0451] The peripheral circuit 41 is a circuit for writing and reading data to the memory cell 10. In addition, the peripheral circuit 41 is a circuit for outputting various signals for controlling the functional circuit 51. The peripheral circuit 41 includes a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, an output circuit 48, and a sense amplifier 46.

[0452] The row decoder 42 and the column decoder 44 have the function of decoding the signal ADDR. The row decoder 42 is a circuit for specifying a row to be accessed, and the column decoder 44 is a circuit for specifying a column to be accessed. The row driver 43 has the function of selecting the wiring WL specified by the row decoder 42. The column driver 45 has the following functions: a function of writing data to the memory cell 10; a function of reading data from the memory cell 10; a function of holding the read data, etc.

[0453] The input circuit 47 has a function of holding the signal WDA. The data held in the input circuit 47 is output to the column driver 45. The output data of the input circuit 47 is the data (Din) written to the memory cell 10. The data (Dout) read from the memory cell 10 by the column driver 45 is output to the output circuit 48. The output circuit 48 has a function of holding Dout. In addition, the output circuit 48 has a function of outputting Dout to the outside of the memory device 300. The data output from the output circuit 48 is the signal RDA.

[0454] PSW22 has a function of controlling the supply of VDD to the peripheral circuit 31. PSW23 has a function of controlling the supply of VHM to the row driver 43. Here, the high power supply voltage of the memory device 300 is VDD, and the low power supply voltage is GND (ground potential). In addition, VHM is a high power supply voltage for making the word line high level, which is higher than VDD. The on / off of PSW22 is controlled by the signal PON1, and the on / off of PSW23 is controlled by the signal PON2. Fig.23 In the embodiment, the number of power domains to which VDD is supplied in the peripheral circuit 31 is one, but it may be more than one. In this case, a power switch may be provided for each power domain.

[0455] The memory array 20 includes memory arrays 20[1] to 20[m] (m is an integer greater than or equal to 2) and a functional layer 50. A plurality of layers of memory arrays 20 may be overlapped on the drive circuit 21. By overlapping a plurality of layers of memory arrays 20, the storage density of the memory cell 10 may be increased. Fig.24A 1 is a perspective view of a storage device 300 in which a functional layer 50 and five-layer (m=5) memory arrays 20 [ 1 ] to 20 [ 5 ] are stacked on a drive circuit 21 .

[0456] exist Fig.24A In the embodiment, the memory array 20 provided in the first layer is referred to as the memory array 20[1], the memory array 20 provided in the second layer is referred to as the memory array 20[2], and the memory array 20 provided in the fifth layer is referred to as the memory array 20[5]. Fig.24A The wiring WL, wiring PL, and wiring CL extending in the X direction and the wiring BL extending in the Z direction (a direction perpendicular to the substrate surface on which the driver circuit is provided) are shown. Note that in order to make the drawings easier to understand, description of a part of the wiring WL and wiring PL included in each of the memory arrays 20 is omitted.

[0457] Fig. 24B Show instructions Fig.24A FIG. 1 is a schematic diagram showing an example of a structure of a functional circuit 51 connected to the wiring BL and a memory cell 10 included in the memory array 20 [1] to 20 [5] connected to the wiring BL. Fig. 24B The wiring GBL provided between the functional circuit 51 and the driving circuit 21 is shown. In addition, a structure that electrically connects one wiring BL to a plurality of memory cells (memory cells 10) is also referred to as a "memory string." Note that in the drawings, the wiring GBL is sometimes shown with a thick line for improved visibility.

[0458] Fig. 24B An example of a circuit structure of a memory cell 10 connected to a wiring BL is shown. The memory cell 10 includes a transistor 11 and a capacitor 12. Regarding the transistor 11, the capacitor 12, and each wiring (wiring BL, wiring WL, etc.), for example, the wiring BL[1] and the wiring WL[1] are sometimes referred to as the wiring BL and the wiring WL, etc. Here, the transistor 11 corresponds to the transistor 200 described in Embodiment 1. In addition, the capacitor 12 corresponds to the capacitor 100 described in Embodiment 1.

[0459] In the memory cell 10, one of the source and the drain of the transistor 11 is connected to the wiring BL. The other of the source and the drain of the transistor 11 is connected to one electrode of the capacitor 12. The other electrode of the capacitor 12 is connected to the wiring PL. The gate of the transistor 11 is connected to the wiring WL. The back gate of the transistor 11 is connected to the wiring CL.

[0460] Wiring PL is a wiring for supplying a constant potential for maintaining the potential of capacitor 12. Wiring CL is a wiring for supplying a constant potential for controlling the threshold voltage of transistor 11. Wiring PL and wiring CL may also be at the same potential. In this case, by connecting the two wirings, the number of wirings connected to memory cell 10 can be reduced.

[0461] Fig. 24B The wiring GBL shown is provided so as to electrically connect the driving circuit 21 and the functional layer 50 . Fig.25A FIG. 3 is a schematic diagram of a memory device 300 with a functional circuit 51 and memory arrays 20 [ 1 ] to 20 [ m ] as a repeating unit 70 . Fig.25A One wiring GBL is shown in the figure, but the wiring GBL may be appropriately provided according to the number of functional circuits 51 in the functional layer 50 .

[0462] Furthermore, the wiring GBL is provided in such a manner as to be in contact with the semiconductor layer of the transistor included in the functional circuit 51. Alternatively, the wiring GBL is provided in such a manner as to be in contact with a region of the semiconductor layer of the transistor included in the functional circuit 51 that functions as a source or a drain. Alternatively, the wiring GBL is provided in such a manner as to be in contact with a conductor that is in contact with a region of the semiconductor layer of the transistor included in the functional circuit 51 that functions as a source or a drain. That is, the wiring GBL can be said to be a wiring that electrically connects one of the source and the drain of the transistor included in the functional circuit 51 of the functional layer 50 to the drive circuit 21 in the vertical direction.

[0463] Alternatively, a structure may be provided in which a repeating unit 70 including a functional circuit 51 and memory arrays 20[1] to 20[m] is stacked. Fig.25B The repeating units 70 [1] to 70 [p] (p is an integer greater than or equal to 2) may be included. The wiring GBL is connected to the functional layer 50 included in the repeating unit 70. The wiring GBL may be appropriately provided according to the number of the functional circuits 51.

[0464] In one embodiment of the present invention, while stacking OS transistors, wiring used as a bit line is arranged in a direction perpendicular to the substrate surface provided with the driver circuit 21. By providing wiring used as a bit line extending from the memory array 20 in a direction perpendicular to the substrate surface, the length of the wiring between the memory array 20 and the driver circuit 21 can be shortened. Therefore, the parasitic capacitance of the bit line can be greatly reduced.

[0465] In addition, one embodiment of the present invention includes a functional layer 50 in a layer provided with a memory array 20, and the functional layer 50 includes a functional circuit 51 having a function of amplifying the data potential held in the memory cell 10 and outputting it. By adopting this structure, a small potential difference of the wiring BL used as a bit line when reading data can be amplified to drive the sense amplifier 46 included in the drive circuit 21. Since the circuit such as the sense amplifier can be miniaturized, the memory device 300 can be miniaturized. In addition, even if the capacitance of the capacitor 12 included in the memory cell 10 is reduced, the memory device 300 can operate.

[0466] [Configuration Example of Memory Array 20 and Functional Circuit 51]

[0467] Reference Fig.26 illustrate Figure 23 to Figure 2 5 and the structural examples of the functional circuit 51 and the sense amplifier 46 included in the memory array 20 and the driver circuit 21. Fig.26 The driving circuit 21 is shown, and the driving circuit 21 is connected to the wiring GBL (wiring GBL_A, wiring GBL_B), and the wiring GBL is connected to the functional circuit 51 (functional circuit 51_A, functional circuit 51_B), and the functional circuit 51 is connected to the memory cell 10 (memory cell 10_A, memory cell 10_B) connected to the different wiring BL (wiring BL_A, wiring BL_B). Fig.26 The driving circuit 21 shown in the figure shows a precharge circuit 71_A, a precharge circuit 71_B, a switch circuit 72_A, a switch circuit 72_B, and a write / read circuit 73 in addition to the sense amplifier 46 .

[0468] Transistors 52_a, 52_b, 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b are shown as the functional circuits 51_A and 51_B. Fig.26 The transistors 52_a, 52_b, 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b shown are OS transistors like the transistor 11 included in the memory cell 10. The functional layer 50 including the functional circuit 51 can be stacked on the driving circuit 21 like the memory arrays 20[1] to 20[m].

[0469] The wiring BL_A is connected to the gate of the transistor 52_a, and the wiring BL_B is connected to the gate of the transistor 52_b. The wiring GBL_A is connected to one of the source and drain of the transistors 53_a and 54_a. The wiring GBL_B is connected to one of the source and drain of the transistors 53_b and 54_b. Similar to the wiring BL_A and BL_B, the wiring GBL_A and GBL_B are arranged in the vertical direction and connected to the transistors included in the driving circuit 21. Fig.26 As shown, the gates of the transistors 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b are supplied with the selection signal MUX, the control signal WE, or the control signal RE.

[0470] constitute Fig.26 The transistors 81_1 to 81_6 and 82_1 to 82_4 of the sense amplifier 46, the precharge circuit 71_A and the precharge circuit 71_B shown are composed of Si transistors. The switches 83_A to 83_D constituting the switch circuit 72_A and the switch circuit 72_B can also be composed of Si transistors. One of the source and drain of the transistors 53_a, 53_b, 54_a, and 54_b is connected to the transistor or switch constituting the precharge circuit 71_A, the precharge circuit 71_B, the sense amplifier 46, and the switch circuit 72_A.

[0471] Precharge circuit 71_A includes n-channel transistors 81_1 to 81_3 and precharges wiring BL_A and wiring BL_B to an intermediate potential VPC corresponding to VDD / 2 between high power supply potential (VDD) and low power supply potential (VSS) according to a precharge signal supplied to precharge line PCL1.

[0472] The precharge circuit 71_B includes n-channel transistors 81_4 to 81_6 and precharges the wirings GBL_A and GBL_B to an intermediate potential VPC corresponding to a potential VDD / 2 between VDD and VSS in accordance with a precharge signal supplied to the precharge line PCL2.

[0473] The sense amplifier 46 includes p-channel transistors 82_1 and 82_2 and n-channel transistors 82_3 and 82_4 connected to the wiring VHH or the wiring VLL. The wiring VHH or the wiring VLL is a wiring having a function of supplying VDD or VSS. The transistors 82_1 to 82_4 are transistors constituting an inverter loop. The potential of the wiring BL_A and the wiring BL_B precharged by selecting the memory cells 10_A and 10_B changes, and the potential of the wiring GBL_A and the wiring GBL_B is set to VDD or VSS according to the change. The potential of the wiring GBL_A and the wiring GBL_B can be output to the outside through the switch 83_C and the switch 83_D and the write-read circuit 73. The wiring BL_A and the wiring BL_B and the wiring GBL_A and the wiring GBL_B are equivalent to a bit line pair. The writing of the data signal of the write-read circuit 73 is controlled by the signal EN_data.

[0474] The switch circuit 72_A is a circuit for controlling the conduction state between the sense amplifier 46 and the wiring GBL_A and the wiring GBL_B. The switch circuit 72_A can be switched on or off by controlling the switching signal CSEL1. In the case where the switches 83_A and 83_B are n-channel transistors, they are turned on when the switching signal CSEL1 is at a high level, and are turned off when the switching signal CSEL1 is at a low level. The switch circuit 72_B is a circuit for controlling the conduction state between the write read circuit 73 and the bit line pair connected to the sense amplifier 46. The switch circuit 72_B can be switched on or off by controlling the switching signal CSEL2. The switches 83_C and 83_D can operate in the same manner as the switches 83_A and 83_B.

[0475] like Fig.26 As shown, the memory device 300 may have a structure in which the memory cell 10, the functional circuit 51, and the sense amplifier 46 are connected by the wiring BL and the wiring GBL arranged in the shortest vertical direction. Although the functional layer 50 including the transistor constituting the functional circuit 51 increases, the load of the wiring BL is reduced, so that the writing time can be shortened and the data can be easily read.

[0476] In addition, if Fig.26 As shown, each transistor included in the functional circuit 51_A, 51_B is controlled by the control signal WE, RE and the selection signal MUX. Each transistor can output the potential of the wiring BL to the driving circuit 21 through the wiring GBL according to the control signal and the selection signal. The functional circuits 51_A, 51_B can be used as a sense amplifier composed of OS transistors. By adopting this structure, a small potential difference of the wiring BL can be amplified during reading, and the sense amplifier 46 using Si transistors can be driven.

[0477] <Structure example of storage unit>

[0478] use Fig. 27 A configuration example of the storage unit 10 used in the above-mentioned storage device will be described.

[0479] Note that Fig. 27 In the figure, the X direction is parallel to the channel length direction of the transistor, the Y direction is perpendicular to the X direction, and the Z direction is perpendicular to the X direction and the Y direction.

[0480] like Fig. 27 As shown, the memory cell 10 includes a transistor 11 and a capacitor 12. An insulator 284 is provided on the transistor 11. The insulator 284 can use an insulator that can be used as the insulator 216. In addition, the transistor 11 has the same structure as the transistor 200 shown in the above embodiment, and the same symbols are attached to the same components. For details of the transistor 200, reference can be made to the above embodiment. In addition, the conductor 240b is provided in a manner that contacts one of the source and drain of the transistor 11 (conductor 242b). The conductor 240 extends in the Z direction and is used as the wiring BL. In addition, the capacitor 12 has the same structure as the capacitor 100 shown in the previous embodiment, and the same symbols are used for the same components. The detailed description of the capacitor 100 can refer to the previous embodiment.

[0481] The conductor 242b provided on the oxide 230 so as to overlap with the oxide 230 is used as a wiring electrically connected to the conductor 240b. Fig. 27 In the embodiment, the top surface and side end of the conductor 242b are electrically connected to the conductor 240b extending in the Z direction. Fig. 27 In the embodiment, the top surface and side end portions of the conductor 242b are in contact with the conductor 240b.

[0482] When the conductor 240b is in direct contact with at least one of the top surface and the side end of the conductor 242b, there is no need to separately provide an electrode for connection, so the occupied area of ​​the memory array can be reduced. In addition, the integration of the memory cell is improved, and the storage capacity of the memory device can be increased. In addition, the conductor 240b is preferably in contact with a portion of the top surface and the side end of the conductor 242b. By the conductor 240b being in contact with multiple surfaces of the conductor 242b, the contact resistance between the conductor 240b and the conductor 242b can be reduced.

[0483] The conductor 240 b is disposed in an opening formed in the insulator 216 , the insulator 221 , the insulator 222 , the insulator 154 b , the conductor 160 b , the insulator 275 , the insulator 280 , the insulator 282 , the insulator 283 , and the insulator 284 .

[0484] In addition, if Fig. 27As shown, it is preferred that the insulator 241b is provided in a manner in contact with the side surface of the conductor 240b. Specifically, the insulator 241b is provided in a manner in contact with the inner wall of the openings of the insulator 216, the insulator 221, the insulator 222, the insulator 154b, the conductor 160b, the insulator 275, the insulator 280, the insulator 282, the insulator 283, and the insulator 284. In addition, the insulator 241 is also formed on the side surface of the oxide 230 protruding in the opening. Here, at least a portion of the conductor 242b is exposed from the insulator 241b and is in contact with the conductor 240b. That is, the conductor 240b is provided in a manner embedded in the inside of the above-mentioned opening via the insulator 241b.

[0485] like Fig. 27 As shown in FIG. 1 , the uppermost portion of the insulator 241b formed below the conductor 242b is preferably located below the top surface of the conductor 242b. By adopting this structure, the conductor 240b can be in contact with at least a portion of the side end portion of the conductor 242b. In addition, the insulator 241 formed below the conductor 242b preferably includes a region in contact with the side surface of the oxide 230. By adopting this structure, impurities such as water and hydrogen contained in the insulator 280 and the like can be suppressed from mixing into the oxide 230 through the conductor 240b.

[0486] In the opening where the conductor 240b and the insulator 241b are arranged, the side wall of the opening may be perpendicular or substantially perpendicular to the top surface of the insulator 222, or may be tapered. The tapered side wall improves the coverage of the insulator 241b and the like provided in the opening.

[0487] In addition, it is preferable to provide the conductor 246 used as wiring in a manner of contacting the top surface of the conductor 240a. The conductor 246 is provided in a manner of embedding the insulator 284. The conductor 246 is used as Fig.24A and Fig. 24B The conductor 246 can have the same structure as the conductor 205, for example.

[0488] <Configuration Example of Storage Device 300>

[0489] use Fig.28 A configuration example of the above-mentioned storage device 300 will be described.

[0490] The memory device 300 includes: a driver circuit 21 including a layer of transistors 310 and the like; a functional layer 50 including a layer of transistors 52, 53, 54, 55 and the like on the driver circuit 21; and a memory array 20[1] to 20[m] on the functional layer 50. The transistor 52 corresponds to the above-mentioned transistors 52_a and 52_b, the transistor 53 corresponds to the above-mentioned transistors 53_a and 53_b, the transistor 54 corresponds to the above-mentioned transistors 54_a and 54_b, and the transistor 55 corresponds to the above-mentioned transistors 55_a and 55_b.

[0491] Fig.28 2 shows a transistor 310 included in the driving circuit 21. The transistor 310 is provided on a substrate 311 and includes a conductor 316 used as a gate, an insulator 315 used as a gate insulator, a semiconductor region 313 including a portion of the substrate 311, and a low resistance region 314a and a low resistance region 314b used as a source region or a drain region. The transistor 310 may be a p-channel transistor or an n-channel transistor. As the substrate 311, for example, a single crystal silicon substrate may be used.

[0492] Here, in Fig.28 In the transistor 310 shown, the semiconductor region 313 (a part of the substrate 311) forming the channel has a convex shape. In addition, a conductor 316 is provided in a manner that covers the side and top surfaces of the semiconductor region 313 via an insulator 315. In addition, the conductor 316 can use a material that adjusts the work function. Because the convex portion of the semiconductor substrate is utilized, this transistor 310 is also referred to as a FIN-type transistor. In addition, an insulator having a mask for forming a convex portion in a manner that contacts the upper portion of the convex portion may also be provided. In addition, although a portion of the semiconductor substrate is shown here to be processed to form a convex portion, an SOI substrate may also be processed to form a semiconductor film having a convex shape.

[0493] Notice, Fig.28 The structure of the transistor 310 shown is just an example and is not limited to the above structure, and an appropriate transistor can be used according to the circuit structure or driving method.

[0494] A wiring layer including an interlayer film, wiring, and plugs may be provided between the structures. In addition, the wiring layer may be provided in a plurality of layers according to the design. In addition, in this specification, wiring and a plug electrically connected to the wiring may also be one component. That is, a part of the conductor may be used as wiring, and a part of the conductor may be used as a plug.

[0495] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked as interlayer films on the transistor 310. In addition, a conductor 328 and the like are embedded in the insulator 320 and the insulator 322. In addition, a conductor 330 and the like are embedded in the insulator 324 and the insulator 326. In addition, the conductor 328 and the conductor 330 are used as contact plugs or wirings.

[0496] Furthermore, the insulator used as an interlayer film may also be used as a planarization film to cover the concavo-convex shape thereunder. For example, in order to improve the flatness of the top surface of the insulator 322, planarization may be achieved by a planarization process such as chemical mechanical polishing (CMP).

[0497] also, Fig.28 Transistors 52, 53, and 55 are shown in the functional layer 50. The transistors 52, 53, and 55 have the same structure as the transistor 11 in the memory cell 10. The sources and drains of the transistors 52, 53, and 55 are connected in series.

[0498] An insulator 208 is provided on transistors 52, 53, and 55, and a conductor 207 is provided in an opening formed in the insulator 208. Furthermore, an insulator 210 is provided on the insulator 208, and a conductor 209 is provided in an opening formed in the insulator 210. Furthermore, an insulator 212 is provided on the insulator 210, and an insulator 214 is provided on the insulator 212. A portion of the conductor 240 provided in the memory array 20[1] is embedded in the openings formed in the insulators 212 and 214. Here, an insulator that can be used as the insulator 216 can be used as the insulator 208 and the insulator 210. In addition, an insulator that can be used as the insulator 283 can be used as the insulator 212. In addition, an insulator that can be used as the insulator 282 can be used as the insulator 214.

[0499] The bottom surface of the conductor 207 is provided in contact with the top surface of the conductor 260 of the transistor 52. In addition, the top surface of the conductor 207 is provided in contact with the bottom surface of the conductor 209. In addition, the top surface of the conductor 209 is in contact with the bottom surface of the conductor 240 provided in the memory array 20[1]. By adopting this structure, the conductor 240 corresponding to the wiring BL can be electrically connected to the gate of the transistor 52.

[0500] Each of the memory arrays 20[1] to 20[m] includes a plurality of memory cells 10. The conductor 240 included in each memory cell 10 is electrically connected to the conductor 240 of the upper layer and the conductor 240 of the lower layer.

[0501] like Fig.28As shown, the adjacent memory cells 10 share the conductor 240b. In addition, in the adjacent memory cells 10, the structure on the right and the structure on the left are arranged symmetrically with the conductor 240b as the boundary.

[0502] In the memory array 20, a plurality of memory arrays 20[1] to 20[m] may be stacked. By arranging the memory arrays 20[1] to 20[m] included in the memory array 20 in a direction perpendicular to the substrate surface on which the drive circuit 21 is disposed, the storage density of the memory cell 10 may be increased. In addition, the memory array 20 may be manufactured repeatedly using the same manufacturing process in the vertical direction. The memory device 300 may reduce the manufacturing cost of the memory array 20.

[0503] This embodiment mode can be combined with other embodiment modes as appropriate.

[0504] (Implementation 4)

[0505] In this embodiment, an example of a chip on which a storage device according to one embodiment of the present invention is mounted is described with reference to FIG. 29 .

[0506] exist Fig.29A and Fig.29B A plurality of circuits (systems) are mounted on the illustrated chip 1200. The technology of integrating a plurality of circuits (systems) on one chip is sometimes referred to as a system on chip (SoC).

[0507] like Fig.29A As shown, the chip 1200 includes a CPU 1211, a GPU 1212, one or more simulation operation units 1213, one or more storage controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0508] Bumps (not shown) are provided on the chip 1200. Fig.29B As shown in FIG. 1 , the first surface of the package substrate 1201 is connected to the first surface of the package substrate 1201 . In addition, a plurality of bumps 1202 are provided on the back side of the first surface of the package substrate 1201 , and the bumps 1202 are connected to the motherboard 1203 .

[0509] In addition, a storage device such as DRAM 1221 and flash memory 1222 may be provided on the motherboard 1203. For example, the DOSRAM described in the above embodiment may be used for DRAM 1221. Thus, the DRAM 1221 can have low power consumption, high speed, and large capacity.

[0510] The CPU 1211 preferably has a plurality of CPU cores. In addition, the GPU 1212 preferably has a plurality of GPU cores. In addition, the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory used jointly by the CPU 1211 and the GPU 1212 may be provided on the chip 1200. The above-mentioned DOSRAM may be used for the memory. In addition, the GPU 1212 is suitable for parallel calculation of multiple data, which may be used for image processing or product-sum calculation.

[0511] In addition, since CPU1211 and GPU1212 are provided on the same chip, the wiring between CPU1211 and GPU1212 can be shortened, and data can be transferred from CPU1211 to GPU1212, data can be transferred between memories possessed by CPU1211 and GPU1212, and calculation results can be transferred from GPU1212 to CPU1211 after calculations in GPU1212 are completed at high speed.

[0512] The analog operation unit 1213 includes one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. In addition, the above-mentioned product-sum operation circuit may be provided in the analog operation unit 1213.

[0513] The memory controller 1214 has a circuit that functions as a controller of the DRAM 1221 and a circuit that functions as an interface of the flash memory 1222 .

[0514] The interface 1215 has an interface circuit with external connection devices such as a display device, a speaker, a microphone, a camera, a controller, etc. The controller includes a mouse, a keyboard, a game console controller, etc. As the above-mentioned interface, USB (Universal Serial Bus), HDMI (High-Definition Multimedia Interface) (registered trademark), etc. can be used.

[0515] The network circuit 1216 has a circuit for connecting to a network such as a LAN (Local Area Network) and may also have a circuit for network security.

[0516] The above circuits (systems) can be formed on the chip 1200 through the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at a low cost.

[0517] The motherboard 1203 including the package substrate 1201 provided with the chip 1200 having the GPU 1212 , the DRAM 1221 , and the flash memory 1222 may be referred to as a GPU module 1204 .

[0518] The GPU module 1204 can reduce its size due to having the chip 1200 using SoC technology. In addition, the GPU module 1204 is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop personal computers, and portable (portable) game consoles due to its high image processing capabilities. In addition, by utilizing a product-sum operation circuit using the GPU 1212, methods such as deep neural networks (DNNs), convolutional neural networks (CNNs), recursive neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks (DBNs) can be performed, thereby enabling the chip 1200 to be used as an AI chip, or the GPU module 1204 can be used as an AI system module.

[0519] This embodiment mode can be combined with other embodiment modes as appropriate.

[0520] (Implementation 5)

[0521] In this embodiment, electronic components, electronic devices, large computers, space equipment, and data centers (also referred to as DC) that can use the storage device described in the above embodiment are described. Electronic components, electronic devices, large computers, space equipment, and data centers that use the storage device of one embodiment of the present invention are effective in achieving high performance such as low power consumption.

[0522] [Electronic components]

[0523] Fig. 30A A perspective view of a substrate (circuit board 704 ) on which an electronic component 700 is mounted is shown. Fig. 30A The electronic component 700 shown includes a semiconductor device 710 within a mold 711. Fig. 30A 700 is partially omitted to show the inside thereof. The electronic component 700 includes a land 712 on the outside of the mold 711. The land 712 is electrically connected to the electrode pad 713, and the electrode pad 713 is electrically connected to the semiconductor device 710 through the lead 714. The electronic component 700 is mounted on, for example, a printed circuit board 702. By combining a plurality of these electronic components and electrically connecting them on the printed circuit board 702, a circuit board 704 is completed.

[0524] In addition, the semiconductor device 710 includes a driving circuit layer 715 and a storage layer 716. The storage layer 716 has a structure in which a plurality of memory cell arrays are stacked. The structure in which the driving circuit layer 715 and the storage layer 716 are stacked can adopt a monolithic stacked structure. In the monolithic stacked structure, it is possible to connect the layers without using through-electrode technologies such as TSV (Through Silicon Via) and bonding technologies such as Cu-Cu direct bonding. When the driving circuit layer 715 and the storage layer 716 are stacked in a monolithic manner, for example, a so-called on-chip memory structure in which a memory is directly formed on a processor can be realized. By adopting the on-chip memory structure, high-speed operation of the interface portion between the processor and the memory can be achieved.

[0525] In addition, by adopting an on-chip memory structure, the size of the connection wiring can be reduced compared to the technology using through-electrodes such as TSV, so the number of pins can be increased. By increasing the number of pins, parallel operation can be performed, thereby increasing the bandwidth of the memory (also called memory bandwidth).

[0526] In addition, it is preferred that a plurality of memory cell arrays in the memory layer 716 are formed using the memory device shown in the previous embodiment, and the plurality of memory cell arrays are stacked in a monolithic manner. When a plurality of memory cell arrays are stacked in a monolithic manner, either or both of the bandwidth of the memory and the access delay of the memory can be improved. The bandwidth refers to the amount of data transmitted per unit time, and the access delay refers to the time between accessing and starting the exchange of data. When Si transistors are used in the memory layer 716, it is more difficult to implement a monolithic stacked structure compared to OS transistors. Therefore, in a monolithic stacked structure, OS transistors are superior to Si transistors.

[0527] In addition, the semiconductor device 710 may be referred to as a bare chip. In this specification, etc., a bare chip refers to a chip obtained by forming a circuit pattern on a disc-shaped substrate (also called a wafer) in the manufacturing process of a semiconductor chip, for example, and cutting it into rectangular small pieces. As semiconductor materials that can be used for bare chips, for example, silicon (Si), silicon carbide (SiC) or gallium nitride (GaN) can be cited. For example, a bare chip obtained from a silicon substrate (also called a silicon wafer) is sometimes called a silicon chip.

[0528] then, Fig. 30B The electronic component 730 is a perspective view. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi Chip Module). In the electronic component 730, an interposer 731 is provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 are provided on the interposer 731.

[0529] The electronic component 730 shows an example of using the semiconductor device 710 as a high bandwidth memory (HBM). In addition, the semiconductor device 735 can be used in an integrated circuit such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), or an FPGA (Field Programmable Gate Array).

[0530] The package substrate 732 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 may be, for example, a silicon interposer or a resin interposer.

[0531] The interposer 731 has a plurality of wirings and has the function of electrically connecting a plurality of integrated circuits with different terminal spacings. The plurality of wirings are composed of a single layer or a plurality of layers. In addition, the interposer 731 has the function of electrically connecting the integrated circuit disposed on the interposer 731 to the electrode disposed on the package substrate 732. Therefore, the interposer is sometimes also referred to as a "rewiring substrate" or "intermediate substrate". In addition, sometimes a through electrode is provided in the interposer 731, and the integrated circuit is electrically connected to the package substrate 732 through the through electrode. In addition, in the case of using a silicon interposer, TSV can also be used as a through electrode.

[0532] In HBM, many wirings need to be connected to achieve a wide memory bandwidth. For this reason, it is required that fine wirings can be formed at a high density on the interposer on which the HBM is mounted. Therefore, a silicon interposer is preferably used as the interposer on which the HBM is mounted.

[0533] In addition, in SiP and MCM using silicon interposers, the reliability degradation caused by the difference in expansion coefficient between the integrated circuit and the interposer is not easy to occur. In addition, since the surface flatness of the silicon interposer is high, the connection between the integrated circuit arranged on the silicon interposer and the silicon interposer is not easy to occur. It is particularly preferred to use the silicon interposer for 2.5D packaging (2.5D mounting) in which a plurality of integrated circuits are arranged horizontally and configured on the interposer.

[0534] On the other hand, when a plurality of integrated circuits with different terminal pitches are electrically connected using silicon interposers and TSV, etc., a space such as the width of the terminal pitch is required. Therefore, when the size of the electronic component 730 is to be reduced, the width of the terminal pitch becomes a problem, and it is sometimes difficult to set up a large number of wirings required to achieve a wider memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferred. In addition, a composite structure combining a memory cell array stacked using TSV and a memory cell array stacked in a monolithic manner can also be used.

[0535] In addition, a heat sink (heat sink plate) may be provided so as to overlap with the electronic component 730. When a heat sink is provided, it is preferable to make the heights of the integrated circuits provided on the interposer 731 consistent. For example, in the electronic component 730 shown in this embodiment, it is preferable to make the heights of the semiconductor device 710 and the semiconductor device 735 consistent.

[0536] In order to mount the electronic component 730 on another substrate, an electrode 733 may be provided on the bottom of the package substrate 732 . Fig. 30B An example of forming the electrode 733 using solder balls is shown. By arranging solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrode 733 can be formed using conductive needles. By arranging conductive needles in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0537] The electronic component 730 can be mounted on other substrates by various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0538] [Electronic equipment]

[0539] then, Fig.31A A perspective view of electronic device 6500 is shown. Fig.31AThe electronic device 6500 shown is a portable information terminal that can be used as a smart phone. The electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. The control device 6509 includes, for example, any one or more selected from a CPU, a GPU, and a storage device. The storage device of one embodiment of the present invention can be used for the control device 6509, etc.

[0540] Fig.31B The electronic device 6600 shown is an information terminal that can be used as a notebook personal computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display unit 6615, a control device 6616, etc. The control device 6616 includes, for example, any one or more selected from a CPU, a GPU, and a storage device. A storage device of one embodiment of the present invention can be used for the control device 6616, etc. In addition, by using a storage device of one embodiment of the present invention for the above-mentioned control device 6509 and the control device 6616, power consumption can be reduced, so it is preferred.

[0541] [Mainframe computer]

[0542] then, Fig.31C A perspective view of a mainframe computer 5600 is shown. Fig.31C In the illustrated mainframe computer 5600, a plurality of rack-mounted computers 5620 are housed in a rack 5610. The mainframe computer 5600 may also be referred to as a supercomputer.

[0543] Computer 5620 may have, for example, Fig.31D The structure of the stereogram is shown. Fig.31D In the embodiment, the computer 5620 includes a motherboard 5630, and the motherboard 5630 includes a plurality of slots 5631 and a plurality of connection terminals. A personal computer card 5621 is inserted into the slot 5631. The personal computer card 5621 includes connection terminals 5623, 5624, and 5625, which are connected to the motherboard 5630.

[0544] Fig.31E The personal computer card 5621 shown is an example of a processing board including a CPU, a GPU, a storage device, etc. The personal computer card 5621 has a board 5622. In addition, the board 5622 includes a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that Fig.31ESemiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 are shown. For description of these semiconductor devices, refer to the description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 described below.

[0545] The connection terminal 5629 has a shape that can be inserted into the slot 5631 of the motherboard 5630, and is used as an interface for connecting the personal computer card 5621 and the motherboard 5630. Examples of the standard of the connection terminal 5629 include PCIe and the like.

[0546] The connection terminals 5623, 5624, and 5625 can be used as interfaces for supplying power to the personal computer card 5621 or inputting signals, for example. In addition, for example, they can be used as interfaces for outputting signals calculated by the personal computer card 5621, for example. Examples of the specifications of the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). In addition, when video signals are output from the connection terminals 5623, 5624, and 5625, HDMI (registered trademark) and the like can be cited as the specifications.

[0547] The semiconductor device 5626 includes a terminal (not shown) for inputting and outputting a signal. By inserting the terminal into a socket (not shown) included in the board 5622 , the semiconductor device 5626 and the board 5622 can be electrically connected.

[0548] The semiconductor device 5627 includes a plurality of terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring included in the board 5622 by reflow soldering. Examples of the semiconductor device 5627 include FPGA, GPU, and CPU. For example, the electronic component 730 can be used as the semiconductor device 5627.

[0549] The semiconductor device 5628 includes a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring included in the board 5622 by reflow soldering. As the semiconductor device 5628, for example, a memory device can be cited. As the semiconductor device 5628, for example, the electronic component 700 can be used.

[0550] The mainframe computer 5600 can be used as a parallel computer. By using the mainframe computer 5600 as a parallel computer, for example, large-scale calculations required for learning and inference of artificial intelligence can be performed.

[0551] [Space Equipment]

[0552] The storage device of one embodiment of the present invention can be applied to space equipment such as equipment that processes and stores information.

[0553] A storage device according to one embodiment of the present invention may include an OS transistor. The OS transistor has a small change in electrical characteristics due to exposure to radiation. In other words, it has high resistance to radiation, so it can be appropriately used in an environment where radiation may be incident. For example, an OS transistor can be appropriately used when used in outer space.

[0554] exist Fig.32 In FIG. 6 , an artificial satellite 6800 is shown as an example of a space device. The artificial satellite 6800 includes a main body 6801, a solar cell panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Fig.32 An example is shown in which the outer space includes the planet 6804. Note that the outer space refers to, for example, an altitude of 100 km or more, but the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.

[0555] In addition, although Fig.32 Although not shown in the figure, a battery management system (also called BMS) or a battery control circuit may be provided in the secondary battery 6805. When an OS transistor is used for the above-mentioned battery management system or battery control circuit, power consumption is low and high reliability is achieved even in outer space, so it is preferable.

[0556] In addition, outer space is an environment where the radiation dose is more than 100 times that of the ground. Examples of radiation include: electromagnetic waves (electromagnetic radiation) represented by X-rays and gamma rays; and particle radiation represented by alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, muon rays, etc.

[0557] When sunlight shines on the solar cell panel 6802, the power required for the artificial satellite 6800 to operate is generated. However, for example, when sunlight does not shine on the solar cell panel or when the amount of sunlight shining on the solar cell panel is small, the amount of power generated is reduced. Therefore, there is a possibility that the power required for the artificial satellite 6800 to operate may not be generated. In order to operate the artificial satellite 6800 even when the generated power is small, it is preferable to provide a secondary battery 6805 in the artificial satellite 6800. In addition, the solar cell panel is sometimes referred to as a solar cell module.

[0558] The artificial satellite 6800 can generate a signal. The signal is transmitted through the antenna 6803, and a receiver on the ground or other artificial satellites can receive the signal. By receiving the signal transmitted by the artificial satellite 6800, the position of the receiver receiving the signal can be measured. Thus, the artificial satellite 6800 can constitute a satellite positioning system.

[0559] In addition, the control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is composed of, for example, any one or more selected from a CPU, a GPU, and a storage device. In addition, as the control device 6807, it is preferable to use a storage device of one embodiment of the present invention. Compared with Si transistors, the electrical characteristics of OS transistors due to radiation exposure change less. That is, OS transistors have high reliability and can be used appropriately even in an environment where radiation may be incident.

[0560] In addition, the artificial satellite 6800 may include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 may have a function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 6800 may have a function of detecting thermal infrared rays released from the ground. Thus, the artificial satellite 6800 may be used as an earth observation satellite, for example.

[0561] Note that in this embodiment, an artificial satellite is described as an example of a space device, but the present invention is not limited to this. For example, a storage device according to one embodiment of the present invention can be appropriately applied to space devices such as a spacecraft, a space capsule, and a space probe.

[0562] As described above, OS transistors have superior effects compared to Si transistors, such as being able to achieve a wider memory bandwidth and having high radiation resistance.

[0563] [Data Center]

[0564] For example, a storage device according to one embodiment of the present invention can be applied to a storage system used in a data center or the like. A data center is required to ensure data invariance and to manage data over a long period of time. When managing data over a long period of time, it is necessary to enlarge facilities, such as installing a storage device and a server for storing a large amount of data, ensuring a stable power supply to maintain data, or ensuring cooling equipment required for maintaining data.

[0565] By using a storage device of one embodiment of the present invention in a storage system used in a data center, it is possible to reduce the power required for data retention and miniaturize the storage device for data retention. Therefore, it is possible to miniaturize the storage system, miniaturize the power supply for data retention, and reduce the scale of cooling equipment. As a result, it is possible to save space in the data center.

[0566] In addition, the storage device of one embodiment of the present invention consumes less power, so the heat generation of the circuit can be reduced. As a result, the negative impact of the heat generation on the circuit itself, the peripheral circuits and the modules can be reduced. In addition, by using the storage device of one embodiment of the present invention, a data center that can operate stably even in a high temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0567] Fig.33 A storage system that may be used in a data center is shown. Fig.33 The storage system 7000 shown includes a plurality of servers 7001sb as a host 7001 (shown as a host computer). In addition, it includes a plurality of storage devices 7003md as a memory 7003 (shown as a memory). The host 7001 and the memory 7003 are shown to be connected via a storage area network 7004 (shown as a SAN: Storage Area Network) and a storage control circuit 7002 (shown as a storage controller).

[0568] The host 7001 is equivalent to a computer that accesses data stored in the memory 7003. The hosts 7001 may be connected to each other via a network.

[0569] In the memory 7003, the access speed of data is shortened by using a flash memory, that is, the time required for storing and outputting data is shortened, but this time is much longer than the time required for a DRAM that can be used as a cache memory in the memory 7003. In the storage system, in order to solve the problem of the long access speed of the memory 7003, a cache memory is generally provided in the memory 7003 to shorten the time required for storing and outputting data.

[0570] The cache memory described above is used in the storage control circuit 7002 and the memory 7003. Data exchanged between the host 7001 and the memory 7003 is stored in the cache memory in the storage control circuit 7002 and the memory 7003 and then output to the host 7001 or the memory 7003.

[0571] When an OS transistor is used as a transistor for storing data in the cache memory to hold a potential corresponding to the data, the refresh frequency can be reduced to reduce power consumption. In addition, the memory can be miniaturized by stacking memory cell arrays.

[0572] Note that by using a storage device of one embodiment of the present invention for any one or more selected from electronic components, electronic devices, large computers, space equipment, and data centers, the effect of reducing power consumption can be expected. Therefore, it is currently believed that as the energy demand for high performance or high integration of storage devices increases, the emission of greenhouse gases represented by carbon dioxide (CO2) can also be reduced by using a storage device of one embodiment of the present invention. In addition, a storage device of one embodiment of the present invention has low power consumption, so it is also effective as a measure for global warming.

[0573] The configuration, structure, method, and the like described in this embodiment mode can be used in combination with the configuration, structure, method, and the like described in other embodiments mode and the like as appropriate.

[0574] [Explanation of symbols]

[0575] ADDR: signal, BL[1]: wiring, BL[j]: wiring, BL[n]: wiring, BL_A: wiring, BL_B: wiring, BL: wiring, BW: signal, CE: signal, CLK: signal, EN_data: signal, GBL_A: wiring, GBL_B: wiring, GBL: wiring, GW: signal, MUX: selection signal, PL[1]: wiring, PL[i]: wiring, PL[m]: wiring, PL: wiring, RDA: signal, RE: control signal, VHH: wiring, VLL: wiring, VPC: intermediate potential, WAKE: signal, WDA: signal, WE: control signal, WL[1]: wiring, WL[i]: wiring, WL[m]: wiring, W L: wiring, 10[1,1]: memory cell, 10[i,j]: memory cell, 10[m,n]: memory cell, 10_A: memory cell, 10_B: memory cell, 10: memory cell, 11: transistor, 12: capacitor, 20[1]: memory array, 20[2]: memory array, 20[5]: memory array, 20[m]: memory array, 20: memory array, 21: drive circuit, 22: PSW, 23: PSW, 31: peripheral circuit, 32: control circuit, 33: voltage generating circuit, 41: peripheral circuit, 42: row decoder, 43: row driver, 44: column decoder, 45: column driver, 46: sense amplifier, 47: input circuit, 4 8: output circuit, 50: functional layer, 51_A: functional circuit, 51_B: functional circuit, 51: functional circuit, 52_a: transistor, 52_b: transistor, 52: transistor, 53_a: transistor, 53_b: transistor, 53: transistor, 54_a: transistor, 54_b: transistor, 54: transistor, 55_a: transistor, 55_b: transistor, 55: transistor, 70[1]: repeating unit, 70: repeating unit, 71_A: precharge circuit, 71_B: precharge circuit, 72_A: switch circuit, 72_B: switch circuit, 73: write-read circuit, 81_1: transistor, 81_3: transistor, 81_4: transistor, 81_6: transistor, 8 2_1: transistor, 82_2: transistor, 82_3: transistor, 82_4: transistor, 83_A: switch, 83_B: switch, 83_C: switch, 83_D: switch, 100a: capacitor, 100aD: capacitor, 100aE: capacitor, 100b: capacitor, 100: capacitor, 154A: insulator, 154a: insulator, 154aD: insulator, 154aE: insulator, 154b: insulator, 154bD: insulator, 154bE: insulator, 154f: insulating film, 154: insulator, 160a: conductor, 160aD: conductor, 160aE: conductor, 160b: conductor, 160bD: conductor,160bE: conductor, 160f: conductive film, 160: conductor, 200a: transistor, 200aD: transistor, 200aE: transistor, 200b: transistor, 200: transistor, 205a: conductor, 205b: conductor, 205: conductor, 207: conductor, 208: insulator, 209: conductor, 210: insulator, 212: insulator, 214: insulator, 215: insulator, 216: insulator, 221: insulator, 222: insulator, 223: insulator, 225f: insulating film, 225: insulator, 230a: oxide, 230aD: oxide, 230aE: oxide, 230af: oxide film, 230b: Oxide, 230bD: Oxide, 230bE: Oxide, 230bf: Oxide Film, 230D: Oxide, 230E: Oxide, 230: Oxide, 240a: Conductor, 240aD: Conductor, 240aE: Conductor, 240b: Conductor, 240bD: Conductor, 240bE: Conductor, 240: Conductor, 241a: Insulator, 241aD: Insulator, 241aE: Insulator, 241b: Insulator, 241bD: Insulator, 241bE: Insulator, 241: Insulator, 242a: Conductor, 242aD: Conductor, 242aE: Conductor, 242b: Conductor, 242bD: Conductor, 242bE: Conductor body, 242f: conductive film, 242: conductor, 246: conductor, 250a: insulator, 250A: insulating film, 250b: insulator, 250c: insulator, 250d: insulator, 250: insulator, 260a: conductor, 260A: conductive film, 260b: conductor, 260B: conductive film, 260: conductor, 275: insulator, 280: insulator, 282: insulator, 283: insulator, 284: insulator, 300A: storage device, 300: storage device, 310: transistor, 311: substrate, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulator, 316: conductor, 32 0: insulator, 322: insulator, 324: insulator, 326: insulator, 328: conductor, 330: conductor, 700: electronic component, 702: printed circuit board, 704: circuit board, 710: semiconductor device, 711: mold, 712: connection pad, 713: electrode pad, 714: lead, 715: drive circuit layer, 716: storage layer, 730: electronic component, 731: plug board, 732: package substrate, 733: electrode, 735: semiconductor device, 1200: chip, 1201: package substrate, 1202: bump, 1203: motherboard, 1204: GPU module, 1211: CPU, 1212: GPU, 1213: simulation operation unit,1214: memory controller, 1215: interface, 1216: network circuit, 1221: DRAM, 1222: flash memory, 5600: mainframe computer, 5610: rack, 5620: computer, 5621: computer card, 5622: board, 5623: connection terminal, 5624: connection terminal, 5625: connection terminal, 5626: semiconductor device, 5627: semiconductor device, 5628: semiconductor device, 5629: connection terminal, 5630: motherboard, 5631: slot, 6500: electronic device, 6501: housing, 6502: display unit, 6503: power button, 6504: button, 6505: speaker, 6506: microphone, 6507: camera, 6508: light source, 6509: control device, 6600: electronic device, 6611: housing, 6612: keyboard, 6613: pointing device, 6614: external connection port, 6615: display unit, 6616: control device, 6800: artificial satellite, 6801: main body, 6802: solar panel, 6803: antenna, 6804: planet, 6805: secondary battery, 6807: control device, 7000: storage system, 7001sb: server, 7001: host, 7002: storage control circuit, 7003md: storage device, 7003: memory,

Claims

1. A storage device, comprising: a first insulator on the substrate; an oxide semiconductor covering at least a portion of the first insulator; A first conductor and a second conductor on the oxide semiconductor; a second insulator on the first electrical conductor; a third insulator on the second conductor; a third conductor on the second insulator; a fourth conductor on the third insulator; a fourth insulator disposed on the third conductor and the fourth conductor and having a first opening overlapping the first conductor, the second insulator, the third conductor, and the second conductor, the third insulator, and the fourth conductor; a fifth insulator disposed in the first opening and disposed on the first insulator and the oxide semiconductor; a fifth conductor disposed in the first opening and on the fifth insulator; a sixth conductor disposed in the second opening formed in the fourth insulator and in contact with the top surface of the third conductor; as well as a seventh conductor disposed in a third opening formed in the fourth insulator, the third insulator, and the fourth conductor and in contact with a top surface of the second conductor, When viewed from a cross section in the channel width direction, the height of the first insulator is longer than the width of the first insulator. Furthermore, the top surface of the first insulator is in contact with the fifth insulator in a region that does not overlap with the first conductor and the second conductor.

2. The storage device according to claim 1, When viewed from a cross section in the channel width direction, a height of the first insulator is greater than or equal to 2 times and less than or equal to 20 times a width of the first insulator.

3. The storage device according to claim 1, wherein the first conductor is used as one of a source electrode and a drain electrode of a transistor, The second conductor serves as the other of a source electrode and a drain electrode of the transistor. And the fifth conductor serves as a gate electrode of the transistor.

4. The storage device according to claim 3, wherein the first conductor is used as one of a pair of electrodes of a capacitor element, The third conductor serves as the other of the pair of electrodes of the capacitor element. And the second insulator serves as a dielectric of the capacitive element.

5. The storage device according to claim 4, The second insulator has a stacked structure in which a zirconium oxide film, an aluminum oxide film, and a zirconium oxide film are stacked in sequence.

6. The storage device according to claim 4, A sixth insulator is disposed between the seventh conductor and the fourth insulator. And due to the sixth insulator, the seventh electrical conductor is insulated from the fourth electrical conductor.

7. The storage device according to claim 4, When viewed from a cross section in the channel width direction, On one side of the first insulator, the oxide semiconductor and the fifth conductor face each other with the fifth insulator interposed therebetween. On the other side surface of the first insulator, the oxide semiconductor and the fifth conductor face each other with the fifth insulator interposed therebetween.

8. The storage device according to claim 4, When viewed from a cross section in the channel width direction, On one side of the first insulator, the first conductor and the third conductor are opposed to each other with the second insulator sandwiched therebetween. On the other side surface of the first insulator, the first conductor and the third conductor face each other with the second insulator interposed therebetween.

9. The storage device according to any one of claims 1 to 8, The oxide semiconductor includes one or more selected from In, Ga and Zn.

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