Silicon carbide lateral power semiconductor device

Abstract

A lateral silicon carbide power semiconductor device (31; 101; 101; 141, 142; 161; 162; 181) for a motor vehicle. The device includes a substrate (102) and a silicon carbide semiconductor structure (105) disposed on the substrate and having a main surface (106). The semiconductor structure includes a layer (107) of a first conductivity type disposed on the substrate and a layered drift region (111) of a second conductivity type opposite the first conductivity type disposed directly on the layer to form an interface (108) between the layer and the drift region. The drift region extends laterally along the major surface between the first and second ends (112, 113). The doping and layer in the drift region is arranged to deplete the drift region. The device comprises a first contact region (121) of the drift region. The device includes a second contact region (124) of the second end of the drift region, the second contact region being highly doped, of the first or second conductivity type, adjoining the second end of the drift region, disposed in the drift region, or in a region adjoining the second end of the drift region. The device includes a highly doped region (128) of the first conductivity type extending from the main surface into the semiconductor structure and adjoining a first end of the drift region, where the highly doped region has a thickness greater than that of the drift region.

Description

Technical Field

[0001] The invention relates to a silicon carbide lateral power semiconductor device. Background Art

[0002] Wide-bandgap power semiconductor devices are beginning to replace traditional silicon-based devices in many terrestrial applications, including electric vehicles and solar inverters. Leveraging the ability of 600-1700V silicon carbide (SiC) to operate at higher frequencies and temperatures than Si devices, this helps provide lighter, smaller, and more efficient power converter solutions for a variety of applications. Both NASA and ESA have emphasized the need to develop radiation-hardened SiC power devices for use in space applications, including satellite power supplies, ion thrusters, and solar arrays. Refer to ESA "ESCC Radiation Test Methods and Guidelines". However, in order to replicate the success of SiC power devices in space, they must be immune to the gradual accumulation of charge, known as the total ionizing dose (TID), as well as single event effects (SEE) and single event burnouts (SEB) caused by the interaction of high-energy particles such as protons, neutrons, and heavy ions.

[0003] Fundamentally, SiC has many positive material properties in terms of withstanding high radiation conditions. This includes high thermal conductivity and atomic displacement energy, while the average energy of 8-9 eV is required to generate electron-hole pairs in SiC (about 3 times higher than Si). Commercially available SiC MOSFETs have shown excellent TID immunity that exceeds the ESA's ESCC standard, such as A. Akturke et al., "Radiation Effects in Commercial 1200V 24A Silicon Carbide Power MOSFETs", IEEE Transactions on Nuclear Science, volume 59, pages 3258-3264 (2012) (A. Aktak et al., "Radiation Effects in Commercial 1200V 24A Silicon Carbide Power MOSFETs", "IEEE Transactions on Nuclear Science", volume 59, pages 3258-3264 (2012)) (hereinafter referred to as "Akturk"). However, under heavy ion bombardment, commercially available SiC devices have poor SEB and SEGR resilience at energies far below the ESA’s ESCC requirement (i.e., 60 MeV.cm 2 1×10 / mg under linear energy transfer (LET) 7 Particles / cm 2of injection), such as A.F. Witulski et al., “Single-Event Burnout Mechanisms in SiC Power MOSFETs” IEEE Transactions on Nuclear Science, volume 65, number 8, pages 1951-1955 (2018) (hereinafter referred to as “Witulski”), E. Maset et al., “Prototyping and Characterization of 1.2KV SIC Schottky Diodes for TWTA Application: The Challenge to Meet the User Specification” in E3S Web of Conferences, volume 16, page 12005 (2017) (hereinafter referred to as “Witulski”), E. Maset et al., “Prototyping and Characterization of 1.2KV SIC Schottky Diodes for TWTA Application: The Challenge to Meet the User Specification” in E3S Web of Conferences, volume 16, page 12005 (2017) Prototyping and Characterization of SiC Schottky Diodes: The Challenge of Meeting User Specifications” E3S Conference Web, volume 16, page 12005 (2017)) (hereinafter referred to as “Maset”), Akturk and C. Abbate et al., “Gate Damages Induced in SiC Power MOSFETs During Heavy-Ion Irradiation—Part II,” IEEE Transactions on Electron Devices, volume 66, number 10, pages 4243-4250 (2019) (hereinafter referred to as “Abbate”).

[0004] Multiple groups have shown that current SiC devices, including Schottky diodes and MOSFETs, suffer severe, permanent degradation in leakage current at any LET above 10 MeV.cm2 / mg, even at reduced standoff voltages (e.g., 200-500V for 1.2kV power MOSFETs), possibly due to damage caused by self-heating, as shown in Witulski, Maset, and Akturk. At higher voltages, catastrophic breakdown occurs. Since only vertical unipolar devices are available on the market, and there is a lack of radiation-hardened SiC products, their use requires significant derating. Summary of the invention

[0005] According to a first aspect of the present invention, a lateral silicon carbide power semiconductor device is provided. The semiconductor device includes a substrate and a silicon carbide semiconductor structure disposed on the substrate and having a main surface. The semiconductor structure includes a layer of a first conductivity type disposed on the substrate and a layered drift region of a second conductivity type opposite to the first conductivity type, the layered drift region being directly disposed on the layer to form an interface between the layer and the drift region. The drift region extends laterally along the main surface between the first and second ends. The doping and layer in the drift region are arranged to deplete the drift region (in other words, the drift region and the layer have a RESURF configuration). The semiconductor device includes a first contact region at a first end of the drift region. The semiconductor device includes a second contact region at a second end of the drift region, the second contact region being highly doped, being of a first or second conductivity type, and being able to extend from the main surface into the semiconductor structure, and being adjacent to the second end of the drift region, being disposed in the drift region or being disposed in a region adjacent to the second end of the drift region. The semiconductor device includes a highly doped region of the first conductivity type, the highly doped region extending from the main surface into the semiconductor structure and being adjacent to the first end of the drift region, wherein the highly doped region has a thickness greater than that of the drift region.

[0006] This can provide a radiation-hardened device. In particular, the RESURF structure enables a lateral configuration, which helps reduce the statistical likelihood of catastrophic ion collisions, while the highly doped region can provide an escape route for charged carriers of the first conductivity type (e.g., holes) when recovering from a single-particle failure; and can also be used to charge compensate the drift region: the deeper the highly doped region, the higher the concentration that the drift region can be doped, which can reduce the device resistance.

[0007] The layered drift region may include at least first and second sections between first and second ends of the drift region, wherein the doping concentration in the first region is lower than the doping concentration in the second region. Dividing the drift region into two or more regions may help improve the electric field distribution in the drift region and may help with leakage current recovery or faster recovery after ion impact.

[0008] The layered drift region may have a doping profile such that the doping concentration increases between the first and second ends of the drift region.

[0009] The drift region may have a thickness between 0.1 and 10 μm, between 0.1 and 2 μm, or between 0.2 and 0.8 μm. The drift region preferably has a thickness between 0.45 μm and 0.55 μm, for example 0.5 μm. The drift region may have a length between 2 and 35 μm or between 5 and 20 μm between the first and second ends. The drift region may have a length between 5×10 15 cm –3 and 1×10 18 cm –3 Between or between 1×10 16 cm –3 and 5×10 17 cm –3 A first doping concentration in a first portion (or "first section") of the drift region near the first end of the drift region is preferably lower than a second doping concentration in a second portion (or "second section") near the second end.

[0010] The highly doped region may extend below the interface between the layer and the drift region by a distance Δ between 0.1 and 10 μm, between 1 and 6 μm, or between 2.5 and 5 μm. The highly doped region may have a 18 cm –3 of doping concentration.

[0011] The first conductivity type may be a p-type, and the second conductivity type may be an n-type.

[0012] The semiconductor device may include a dielectric layer disposed directly on a drift region having first and second ends, the dielectric layer partially covering the drift region. The dielectric layer may include a first contact window for contacting the first contact region. The dielectric layer may include a second contact window for contacting the second contact region.

[0013] The first contact region may include a portion of the drift region. The portion may be an end of the drift region near the first end. The first contact region may be more heavily doped than the drift region and be of the first or second conductivity type. The first contact region may extend from the main surface into the semiconductor structure. The first contact region may be adjacent to the first end of the drift region or be disposed in the drift region.

[0014] The semiconductor device may include a first terminal or a first metallization layer arranged to contact the first contact region.

[0015] The semiconductor device may also include a shallowly doped region of the first conductivity type, the shallowly doped region being located at one end of the dielectric layer at the main surface, preferably adjacent to the anode region or the Schottky contact. The shallowly doped region 140 may help suppress off-state leakage. The shallowly doped region may be p-type. The shallowly doped region may be arranged as a ring. The shallowly doped region may have a value between 5×10 17 cm –3 and 1×10 19 cm –3 The doping concentration is preferably about 1×10 18 cm –3 The thickness of the shallow doped region may be between 10% and 50% of the thickness of the drift region, preferably between 15% and 25% of the thickness of the drift region. The shallow doped region may have a thickness between 50 nm and 250 nm, and may have a thickness of about 100 nm. The shallow doped region may have a width w of at most the drift region. n-漂移 Half the width, and can have a width between 100 nm and 5 μm.

[0016] The semiconductor device may also include another doped region of the second conductivity type located below and in direct contact with the doped region. This may be used to form a dual RESURF structure. The other doped region may be n-type. The other doped region may be arranged as a ring. The other doped region may have a conductivity between 1×10 17 cm –3 and 1×10 19 cm –3 The thickness of the further doped region may be between 10% and 50% of the thickness of the drift region, preferably between 15% and 25% of the thickness of the drift region. The doped region may have a thickness of at least 50 nm and may extend to the upper surface of the layer of the first conductivity type. The further doped region may be adjacent to the shallow doped region.

[0017] The semiconductor device may include a second terminal or a second metallization layer arranged to contact the second contact region.

[0018] The drift region may extend from the main surface into the structure, and the drift region may have a thickness between the interface and the main surface. In the case of a single RESURF configuration where the top of the drift region is the main surface, the drift region may be depleted between the interface and the main surface.

[0019] The lateral silicon carbide power semiconductor device may further include a layered region of the first conductivity type disposed directly on the drift region. Thus, a double RESURF structure may be used.

[0020] The lateral silicon carbide power semiconductor device can be configured to have a breakdown voltage between 400 and 1000V. The doping in the drift region can be constant between the first and second ends (in other words, a single-segment drift region). The lateral silicon carbide power semiconductor device can have a breakdown voltage between 1000 and 1400V. The lateral silicon carbide power semiconductor device can have a breakdown voltage between 1400 and 3500V or between 1400 and 4000V. The layered drift region can include at least a first and a second segment between the first and second ends of the drift region, wherein the doping concentration in the first region is lower than the doping concentration in the second region, or the layered drift region has a doping profile such that the doping concentration increases between the first and second ends of the drift region.

[0021] The lateral silicon carbide power semiconductor device may be configured as a Schottky barrier diode or a PiN diode.The first contact region may be an anode and the second contact region may be a cathode.

[0022] The lateral silicon carbide power semiconductor device may be configured as a MOSFET.The first contact region may be a source, and the second contact region may be a drain.

[0023] The lateral silicon carbide power semiconductor device may be configured as an IGBT.The first contact may be an emitter and the second contact may be a collector.

[0024] A lateral silicon carbide power semiconductor device may include a gate and a gate dielectric, wherein the gate dielectric is disposed directly on a portion of a drift region and interposed between the gate and the drift region.

[0025] According to a second aspect of the present invention, there is provided a monolithic semiconductor device comprising a plurality of lateral silicon carbide power semiconductor devices according to the first aspect.

[0026] According to a third aspect of the present invention, there is provided a vehicle, the vehicle comprising the lateral silicon carbide power semiconductor device of the first aspect. The vehicle may be a (space) launch vehicle, a spacecraft (such as a satellite), an aircraft or other vehicle, the environment in which the vehicle can travel is subjected to ionizing radiation, heavy ion irradiation and / or proton irradiation (for example, 10 MeV.cm 2 / mg or 60MeV.cm 2 / mg of linear energy transfer (LET) at most 1×10 7 Particles / cm 2 Such environments include altitudes above 7500 m, low Earth orbit or beyond, beyond Earth orbit, or the atmosphere of another planet (such as Mars).

[0027] According to a fourth aspect of the present invention, there is provided an apparatus comprising the lateral silicon carbide power semiconductor device of the first aspect. The apparatus can be deployed in a device subjected to ionizing radiation, heavy ion irradiation and / or proton irradiation (e.g., 10 MeV.cm 2 / mg or 60MeV.cm 2 / mg of linear energy transfer (LET) at most 1×10 7 Particles / cm 2 The environment may be near a cyclotron, near a reactor, above 7500 m above sea level, in low earth orbit or beyond low earth orbit, beyond earth orbit, or in the atmosphere of another planet (such as Mars).

[0028] According to a third aspect of the present invention, there is provided a method for operating a lateral silicon carbide power semiconductor device of the first aspect, the method comprising placing the lateral silicon carbide power semiconductor device in an environment subjected to ionizing radiation, heavy ion irradiation and / or proton irradiation; and applying a bias voltage of at least 400V, at least 650V, at least 1200V, at least 2000V or at least 3000V across the drift region. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Certain embodiments of the present invention will now be described by way of example with reference to the accompanying drawings, in which:

[0030] Figure 1 is a schematic cross-section of a vertical SiC Schottky barrier diode device and first, second, third and fourth paths taken by ions through the device during heavy ion bombardment;

[0031] Figure 2A is the simulated peak electric field as the heavy ions pass vertically along the first path. Figure 1 A graph showing the linear energy transfer and reverse voltage variation achieved by the device shown in FIG.

[0032] Figure 2B is the maximum temperature of the simulation as the heavy ions pass vertically along the first path. Figure 1 A graph showing the linear energy transfer and reverse voltage variation achieved by the device shown in FIG.

[0033] Figure 3A is the simulated peak electric field as the heavy ions pass vertically along the third path Figure 1 A graph showing the linear energy transfer and reverse voltage variation achieved by the device shown in FIG.

[0034] Figure 3B is the maximum temperature of the simulation as the heavy ions pass vertically along the third path. Figure 1 A graph showing the linear energy transfer and reverse voltage variation achieved by the device shown in FIG.

[0035] Figure 4 For a reverse voltage of 800 V and 60 MeV·cm 2 / mg linear energy transfer for ion impacts along the first, third, and fifth paths during recovery from heavy ion impacts, Figure 1 The device shown in Figure 7 A graph of simulated current versus time for a SiC lateral RESURF Schottky barrier diode device is shown in;

[0036] Figure 5 A is for a reverse voltage of 800 V and 60 MeV·cm 2 / mg linear energy transfer, along Figure 1 Graphs of electric field versus distance along a center section line of the drift region at t=0 s, 0.1 ns, 0.12 ns, and 0.135 ns after an ion impact of the first path shown in FIG.

[0037] Figure 5 B is for a reverse voltage of 800 V and 60 MeV·cm 2 / mg linear energy transfer, along Figure 1 Graphs of electron density versus distance along a center section line of the drift region at t=0 s, 0.1 ns, 0.12 ns, and 0.135 ns after an ion impact of the first path shown in FIG.

[0038] Figure 5 C is for a reverse voltage of 800 V and 60 MeV·cm 2 / mg linear energy transfer, along Figure 1 Graphs of hole density versus distance along a center section line of the drift region at t=0 s, 0.1 ns, 0.12 ns, and 0.135 ns after an ion impact of the first path shown in FIG.

[0039] Figure 5 D is for a reverse voltage of 800 V and 60 MeV·cm 2 / mg linear energy transfer, along Figure 1 Graphs of electric field versus distance along a center section line of the drift region at t=0.3 ns, 0.7 ns, 1.5 ns, and 2 ns after an ion impact of the first path shown in FIG.

[0040] Figure 5 E is for a reverse voltage of 800 V and 60 MeV·cm 2 / mg linear energy transfer, along Figure 1Graphs of electron density versus distance along a center section line of the drift region at t=0.3 ns, 0.7 ns, 1.5 ns, and 2 ns after an ion impact of the first path shown in FIG.

[0041] Figure 5 F is for a reverse voltage of 800 V and 60 MeV·cm 2 / mg linear energy transfer, along Figure 1 Graphs of hole density versus distance along a center section line of the drift region at t=0.3 ns, 0.7 ns, 1.5 ns, and 2 ns after an ion impact of the first path shown in FIG.

[0042] Figure 6 A is for a reverse voltage of 800 V and 60 MeV·cm 2 / mg linear energy transfer, along Figure 1 Graphs of electric field versus distance along a center section line of the drift region at t=0 s, 0.1 ns, 0.12 ns, and 0.135 ns after ion impact of the third path shown in FIG.

[0043] Figure 6 B is for a reverse voltage of 800 V and 60 MeV·cm 2 / mg linear energy transfer, along Figure 1 Graphs of electron density versus distance along a center section line of the drift region at t=0 s, 0.1 ns, 0.12 ns, and 0.135 ns after an ion impact of the third path shown in FIG.

[0044] Figure 6 C is for a reverse voltage of 800 V and 60 MeV·cm 2 / mg linear energy transfer, along Figure 1 Graphs of hole density versus distance along a center section line of the drift region at t=0s, 0.1ns, 0.12ns, and 0.135ns after ion impact of the third path shown in FIG.

[0045] Figure 6 D is for a reverse voltage of 800 V and 60 MeV·cm 2 / mg linear energy transfer, along Figure 1 Graphs of electric field versus distance along a center section line of the drift region at t=0.3 ns, 0.7 ns, 1.5 ns, and 2 ns after ion impact of the third path shown in FIG.

[0046] Figure 6 E is for a reverse voltage of 800 V and 60 MeV·cm 2 / mg linear energy transfer, along Figure 1 Graphs of electron density versus distance along a center section line of the drift region at t=0.3 ns, 0.7 ns, 1.5 ns, and 2 ns after an ion impact of the third path shown in FIG.

[0047] Figure 6 F is for a reverse voltage of 800 V and 60 MeV·cm 2 / mg linear energy transfer, along Figure 1 A graph of hole density versus distance along a center section line of the drift region at t=0.3 ns, 0.7 ns, 1.5 ns and 2 ns after ion impact by the third path shown in FIG.

[0048] Figure 7 is a schematic cross section of a simplified SiC lateral RESURF Schottky barrier diode device and the fifth path taken by ions through the device during heavy ion bombardment;

[0049] Fig. 8A is the simulated peak electric field as the heavy ions pass vertically along the fifth path Figure 7 A graph showing the linear energy transfer and reverse voltage variation achieved by the device shown in FIG.

[0050] Figure 8B is the maximum temperature of the simulation as the heavy ions pass vertically along the fifth path. Figure 7 A graph showing the linear energy transfer and reverse voltage variation achieved by the device shown in FIG.

[0051] Fig. 9 is an orthogonal view of a two-segment RESURF Schottky barrier diode device and the sixth path taken by ions through the device during heavy ion bombardment;

[0052] Fig.10 The lateral surface electric field distribution of the single-segment and two-segment RESURF Schottky barrier diode devices along the section line 50 nm below the interface between the field oxide and the N-drift region is shown;

[0053] Fig.11A is a graph of current versus forward voltage for single-segment and two-segment RESURF Schottky barrier diode devices;

[0054] Fig. 11B is a graph of current versus reverse voltage for single-segment and two-segment RESURF Schottky barrier diode devices;

[0055] Fig. 11C is a graph of leakage current versus time after heavy ion impact, which shows that for V R=1200V and LET = 60MeV·cm 2 / mg, SEB in single-segment RESURF Schottky barrier diode device and recovery in two-segment Schottky barrier diode device;

[0056] Fig.12 is a graph of the electric field at t=0s, 0.1ns, 0.15ns, 0.25ns, 0.5ns, 0.7ns and 1ns versus distance along a 50nm section line below the SiC surface in the N-drift region in a single-segment RESURF Schottky barrier diode device that supports 1200V while resisting 60MeV·cm 2 / mg heavy ions pass through it and burn it;

[0057] Fig.13 is a graph of the electric field at t=0s, 0.1ns, 0.15ns, 0.25ns, 0.5ns, 0.7ns and 1ns versus distance along a 50nm section line below the SiC surface in the N-drift region in a two-segment RESURF Schottky barrier diode device that supports 1200V while resisting 60MeV·cm 2 / mg heavy ions pass through it and burn it;

[0058] Fig.14 is a graph of breakdown voltage versus first segment doping concentration in a RESURF Schottky barrier diode device having a pillar depth of 1 μm, 1.5 μm, 2.5 μm, 3 μm, and 5 μm;

[0059] Fig.15 is a cross-sectional view of a radiation-hardened Schottky barrier diode device;

[0060] Fig.16 yes Fig.16 A plan view of a Schottky barrier diode device shown in FIG.

[0061] Fig.17 is a plan view of a modified Schottky barrier diode device with an inserted high-doped region;

[0062] Fig.18 is a cross-sectional view of a radiation-hardened PiN diode;

[0063] Fig.19 is a cross-sectional view of a radiation-hardened MOSFET;

[0064] Fig. 20 is a cross-sectional view of a radiation-hardened IGBT;

[0065] Fig.21A shows the doping profile in a single-segment drift region;

[0066] Fig.21B The doping profile in the two-segment drift region is shown;

[0067] Fig. 21C shows the doping profile in the graded drift region;

[0068] Fig. 22 is a flow chart of a method for manufacturing a radiation-hardened device;

[0069] Fig.23 The layer structure used in the dual RESURF layer structure is shown;

[0070] Fig.24 A first structure for helping to suppress off-state leakage is shown;

[0071] Figures 25A to 25I An alternative structure is shown to help suppress off-state leakage. DETAILED DESCRIPTION

[0072] Overview

[0073] In this paper, SiC power device geometries are disclosed that can help achieve radiation-hardened layouts that can achieve the desired SEE conditions. Single-particle simulations of a 1200V-rated vertical SiC Schottky barrier diode (SBD) structure are performed in TCAD to expose the weaknesses of this layout. This is then further exploited by first traversing ions laterally through the same SBD and then considering an optimized reduced surface field (RESURF) topology to explore the relative strengths of lateral designed SiC devices.

[0074] Simulation Methods

[0075] refer to Figure 1 , shows a simplified 1200V rated vertical SBD 1.

[0076] The SBD 1 includes an N+ substrate 2 with a thickness of 2.5 μm and an N- drift region 3 with a thickness of 10 μm disposed on the substrate 2, and a cathode 4 and an anode 5 connected to the substrate 2 and the drift region, respectively. The device 1 has a width of 1 μm.

[0077] The SBD 1 is simulated in Synopsys (RTM) Sentaurus TCAD to study the SEE caused by heavy ions 6. Four ion paths 7, 8, 9, 10 across the drift region are considered to study the effect of the collision position on the device response. Given the layout of the vertical device with a thin drift region (10μm in this case) and the device area is not in the order of square millimeters, the heavy ions will typically traverse both terminals of the device. This is represented by the first path 7. However, the simulation can also use this same model to observe what happens in an idealized lateral device. Therefore, the second, third and fourth paths 8, 9, 10 corresponding to the top, middle and bottom of the device are considered.

[0078] The model parameters are listed in Table I below. At each position (i.e., for each path), the model was constructed by using a 10 to 60 MeV·cm 2 / mg of heavy ions simulated by linear energy transfer (LET) with reverse voltages ranging from 100 to 1200 V R A 2D matrix of the results is derived across SBD 1. In the dynamic simulations, the heavy ion impact occurs 0.1 ns after the start of the simulation to give the device simulation enough time to reach steady state. For each simulation, the peak electric field and maximum temperature in the drift region 3 are recorded and plotted.

[0079] Table I

[0080]

[0081] Results and discussion

[0082] Peak electric field and maximum temperature

[0083] refer to Figure 2A and 2B , shows the peak electric field and temperature simulation results for the case where heavy ions pass through the device vertically, i.e. along the first path 7, where the ion path is in the same direction as the electric field vector.

[0084] The peak electric field and temperature simulation results are in good agreement with previously reported experimental and simulation results on SEE in SBDs (such as Akturk and Abbate). It can be seen that at low LET and / or low voltage, the increase in temperature can be limited to a local peak of less than 700K.

[0085] Special References Figure 2A, the dashed line indicates the boundary, beyond which the peak electric field exceeds 3.5 MV / cm. It can be seen that this result is similar to the threshold presented in Witulski between the experimentally tested JBS diodes (one part exhibited no observable damage at low reverse voltage values, while the other part suffered damage and permanently increased leakage current at about 200-500 V). In this voltage range, the temperature is shown to exceed 1000K where the ion impact occurs, i.e. at the semiconductor surface below the Schottky contact. This explains the reason for the continuous increase in leakage: the heating is equivalent to a local rapid thermal annealing of the contact, thereby producing a Schottky barrier inhomogeneity area and thus leakage. Beyond this, the simulations reach extreme peak temperatures of up to 2000K and electric fields exceeding 5 MV / cm, which lead to catastrophic failure.

[0086] For comparison, refer to Figure 3A and 3B The potential for immunity in lateral SiC devices is demonstrated by simulations of SBDs subjected to horizontal ion impact along the second, third and fourth paths 8, 9, 10, where the ion impact is perpendicular to the electric field vector. The three ion paths produce similar results, with the worst being the third path, where the simulation results are in Figure 3A and 3B At 800 V and 60 MeV·cm2 / mg, simulations for the second, third, and fourth paths produce peak electric fields of 3.47, 3.50, and 3.53 MV / cm, respectively, and maximum temperatures of 353, 360, and 346 K, respectively.

[0087] Dynamic current and electric field characteristics

[0088] refer to Figure 4 , shows the dynamic evolution of the current of ion impact along the first and third paths 7 , 9 .

[0089] refer to Figure 5 A to 5F and 6A to 6F, show the dynamic electric field, electron density, and hole density, which provide a more detailed understanding of these contrasting events.

[0090] The results are for a reference voltage of 800 V and an LET of 60 MeV·cm2 / mg. In all these cases, the steady-state leakage current is extremely low at t < 0.1 ns, and the electric field peak is 0.89 V / cm. At t = 0.1 ns, the heavy ion event generates 10 19 cm -3 This immediately leads to the destruction of the previously uniform depletion region, and the charge extraction process generates a current flow; at the same time, the device remains locked at the rated voltage, resulting in huge instantaneous power.

[0091] In the vertical case, the current filament leads to the anode 5 ( Figure 1 ) and cathode 4 ( Figure 1 ) between the two terminals, thus allowing current to flow.

[0092] refer to Figure 5 A to 5F, there is a large density of electrons and holes in the entire ion path vector, which means that there is almost no space to support the 800V supply voltage. Therefore, in the drift region 3 ( Figure 1 ) two electric field peaks appear at the edge of the metal and N-drift region 3 ( Figure 1 ) exceeds 5.5 MV / cm at the interface between the N-drift region and the N+ substrate regions 2, 3 ( Figure 1 ) exceeds 3.9 MV / cm. Hindered by the influx of external charge, carrier sweep out is slow, but by 2 ns, depletion regions have formed from each end and the remaining charge is concentrated in the middle. The final excess charge carriers recombine, and the drain current slowly decreases to its initial value.

[0093] There are two possible advantages in cases involving horizontal paths. First, at terminals 4, 5 ( Figure 1 ) and any charge generated is localized in a narrow region along the center cut line. This means that there is enough space above and below the ion track to support the reverse voltage, and the electric field only reaches 2MV / cm at the surface. Second, the current sweep is more orderly, whereby electrons are swept toward the cathode and holes are swept toward the anode. By 0.8ns, the electric field distribution returns to its steady-state distribution and the final excess charge carriers begin to recombine.

[0094] The peak current and peak power of the vertical path are 284 times that of the horizontal device, while the total charge extracted by the vertical path ( Figure 4 The area under the trace shown in Figure 1 is 130 times that of a horizontal device. These values ​​highlight the effect of ions passing between the two terminals causing a temporary short circuit.

[0095] This initial study demonstrated the catastrophic effects of vertical ion pathways through the SiC drift region with high electric fields. Employing lateral device topologies can help to greatly reduce the likelihood of such catastrophic effects.

[0096] First Simplified SiC RESURF Schottky Diode

[0097] The simulation results described above show that lateral topology is potentially beneficial for radiation-hardened SiC power devices. The lateral topology not only has geometric advantages in terms of the location of ion impact, but also produces efficient charge compensation structures. In particular, the reduced surface field (RESURF) topology allows the addition of a p-layer below the drift region, which helps extract the holes generated during a single event.

[0098] refer to Figure 7 , a first simplified 1200V rated lateral RESURF SBD 11 is shown.

[0099] The first lateral RESURF SBD 11 includes a substrate (not shown) including a P-layer 13 having a thickness of 0.5 μm, an N-drift region 14 having a thickness of 0.5 μm disposed on the P-layer 13, and a field oxide 15 disposed on the N-drift region 14. A P+ pillar 16 is formed adjacent to the P-layer and N-layers 13, 14. An anode 17 is formed on the top of the P+ pillar 16 and on one end of the N-layer 14. Anode metallization extends onto the field oxide 15 to form a field plate 18. An N+ well 19 is formed in the N-drift region 14 at the other end of the field oxide 15. A cathode 20 is formed on the N+ well 19. The P-layer and N-layers 13, 14 both have a 1×10 17 cm –3 The doping concentration of the drift region is 11 μm. The breakdown voltage (BV) can be maximized by optimizing the field plate and oxide thickness.

[0100] The first lateral RESURF SBD 11 was simulated using Synopsys (RTM) Sentaurus TCAD to study the SEE caused by heavy ions 21. The path 22 of the vertical ion impact occurs perpendicular to the electric field vector and is located at the edge of the Schottky contact where the electric field reaches a maximum in the off state.

[0101] refer to Fig. 8A and 8B , shows the peak electric field and temperature simulation results when heavy ions pass through the first transverse RESURF SBD 11 vertically, ie, along the fifth path 22 .

[0102] The simulations demonstrate the immunity of the first transverse RESURF SBD 11. The peak field reaches 5.29 MV / cm, while the temperature rise is limited to 64 K.

[0103] Also refer to Figure 4 , will be 60MeV·cm at 800V 2 The current response after a / mg heavy ion strike is compared with the vertical and lateral paths through the device 1 described above. During the first 1ns, the response of the first lateral RESURF SBD 11 to a single event is almost identical to the previous lateral device 1. The total amount of charge extracted is only 4% higher.

[0104] Simulations of a simplified lateral RESURF device11 show that it can support 1800 V, but with lower resistivity due to high drift region doping. Therefore, an improved device is considered.

[0105] Second SiC RESURF Schottky Device

[0106] Simulations of the devices described above indicate that lateral RESURF-based devices have the potential to be successful in high-radiation applications.

[0107] refer to Fig. 9 , a second lateral RESURF device 31 is shown.

[0108] The second lateral RESURF device 31 includes a heavily doped n-type 4H-SiC substrate 32 (substrate 32 is referred to as "N+ substrate" hereinafter). An epitaxial layer 33 of heavily doped p-type single-crystal SiC is grown on the N+ substrate 32, which acts as a field stop layer (layer 33 is referred to as "P+ layer" or "Psub" hereinafter). In this example, the P+ layer 33 has a depth (or "thickness") d of 1 μm. Psub and 1×10 19 cm -3 of doping concentration.

[0109] The P+ layer 33 has an upper surface 34 that supports a layer structure 35 having a major surface 36 (or "upper surface"). The layer structure 35 includes an epitaxial layer 37 (also referred to herein as a "P-epi layer") of lightly doped p-type single crystal SiC having an upper surface 38 (also referred to herein as an "interface") and a layer 39 (also referred to herein as an "n-drift layer") of lightly doped n-type single crystal SiC having an upper surface 40 and providing a drift region 41. In this case, the depth (or "thickness") of the P-epi layer 37 is d P-epi is 11 μm, and the depth of the n-drift layer d n-漂移 is 0.5 μm and its width w between the first and second ends 42, 43 n-漂移 To completely deplete the drift region 39 before breakdown, the P-epi layer 37 has a thickness of 1×10 15 cm -3 The doping concentration N A,p-epi .

[0110] There are two versions of the device 31. The first version of the device has a single-segment drift region 41 with a doping concentration N D,SZ,区段1 、N D,SZ,区段2 8.5×10 16 cm –3 In a second version of the device, the drift region 41 is divided into a first and a second section 41 1 , 41 2 , which have 6×10 16 cm –3 and 1.5×10 17 cm–3 The doping concentration N D,SZ,区段1 、N D,SZ,区段2 , to improve charge balance and optimize breakdown voltage. The first and second sections 41 1 , 41 2 Separated by segment boundaries 44 .

[0111] A dielectric layer 45 in the form of a field oxide is provided on the drift region 41. The thickness d of the dielectric layer 45 is ox is 0.3 μm, and its width w between the first and second ends 46, 47 is ox The dielectric thickness d is 16.5 μm. ox It may be between 200 nm and 3 μm. The dielectric layer 45 partially covers the drift region 41 and leaves a first contact window 48 at the first end 42 of the drift region 41 .

[0112] A metallization contact layer 50 in the form of a nickel layer extends over the first end 42 of the drift region 41 to provide a first contact 51 in the form of a Schottky barrier contact and extends over the dielectric layer 45 to form a field plate 52 for protruding the junction corner. The metallization layer 50 also extends in the opposite direction to provide a contact 53 to the p-column 58.

[0113] A contact region 54 in the form of a heavily doped n-type region is provided in the layer structure 35 adjacent to the second end 43 of the drift region 41 at the main surface 36. A metallization layer 55 in the form of a nickel layer extends over the contact region 54 to provide a second contact 55 and over the dielectric layer 45 to form a field plate 56.

[0114] A deep heavily doped region 58 in the form of a heavily doped p-type region (also referred to herein as a "P+ pillar") is disposed in the layer structure 35 adjacent to the first end 42 of the drift region 41 at the main surface 36. As will be explained in more detail later, the P+ pillar 58 penetrates beyond the thickness of the drift layer 39, i.e., d p-柱 =d n-漂移 +Δ.

[0115] The n+ region 54 provides an escape path for electrons generated in the device following a single event when the device is turned off and reverse biased, while the P+ pillar 58 extracts holes generated by ion collisions.

[0116] Table II below summarizes the device dimensions and doping concentrations.

[0117] Table II

[0118]

[0119] On and Off Performance

[0120] refer to Fig.10, shows the lateral surface electric field distribution during breakdown of the single-segment two-segment version. The electric field distribution is a distance d below the interface 40 between the n-drift region 41 and the field oxide 45. 剖切线 =50nm section line 59 was collected.

[0121] See also Fig.11A , 11B and 11C, showing the electrical characteristics of the single-segment and two-segment versions.

[0122] Special References Fig.10 , single-segment devices are 8.5×10 16 cm –3 The drift region doping concentration of 60° achieves an ideal charge balance. In this case, the slope of the electric field along the drift region 41 is uniform, and the area under the electric field distribution is maximized, with three electric field peaks 60°. 1 , 60 2 , 60 3 Three peaks 60 1 , 60 2 , 60 3 The values ​​in the drift region below each end of the anode field plate 52 and at one end of the cathode field plate 56 above the field oxide 44 are 3.01, 2.68, and 2.79 MV / cm, respectively.

[0123] Special References Fig. 11B , the breakdown voltage of a single-segment Schottky barrier device is 1974V.

[0124] Again special reference Fig.10 The two-segment device divides the drift region into 6×10 16 cm –3 The first low-doped section 41 1 (“Segment 1”) and 1.5×10 17 cm –3 The second highly doped section 41 2 (“Section 2”). Compared with the single-segment drift region, the first segment 41 1 The electric field slope in the second section 41 is positive, and 1 The electric field slope in the first and second sections 41 is negative. 1 , 41 2 An additional peak 60 is generated at the interface 44 between 4 Therefore, the addition of the fourth electric field peak increases the area under the electric field distribution and reduces the highest peak value.

[0125] Still reference Fig.10 , from left to right, the first, second, third and fourth peaks 60 1 , 60 2 , 603 , 60 4 Now it reaches 2.79, 2.67, 1.70 and 2.25 MV / cm.

[0126] Special References Fig. 11B , the resulting breakdown voltage of the two-section RESURF SBD reaches 2061 V. The electric field distribution can still be improved by a lower doping concentration in the first section 1 , but this also results in a worse on-resistance.

[0127] The forward characteristics of the single-segment and two-segment RESURF SBD are Fig.11A Visible in.

[0128] refer to Fig.11A The on-state voltage of the single-segment and two-segment RESURF SBD is about 1.5V, which is consistent with the nickel work function of 5.1eV. In the on-state, the current only flows through the n-drift region 41 ( Fig. 9 ), so the on-state resistance is determined by its doping. Therefore, the first low-doped section 41 of the two-section RESURF SBD 1 ( Fig. 9 ) leads to a high on-resistance of 3.63×10 4 Ω·μm, which is 3.66×10 4 Overall, both the on-state and off-state performances are improved in this two-segment RESURF SBD.

[0129] Ideally, a thinner n-drift region could be used to further increase the doping to favor both the on and off states, but the geometry is limited due to manufacturing constraints.

[0130] Single Event Effects

[0131] The single event immunity of both devices was tested via simulations in accordance with the ESA standard, where the device is turned off and supports its rated voltage (V R = 1200V), and at the same time experience a heavy ion LET of 60MeV·cm2 / mg. At 0.1ns, the simulated heavy ion is at the cathode field plate 56 ( Fig. 9 ) crosses the SBD perpendicularly (parallel to the y-axis) at the midpoint of one end. Arrow 59 shows the location and direction. Other entry locations were simulated but the results were similar and therefore not presented. The dynamic evolution of the current in each device is shown in Fig. 11C Shown in.

[0132] refer to Fig.12 and 13, showing the dynamic electric field. The electric field distribution is collected along the same section line 59 50 nm below the oxide-drift region interface 40.

[0133] The response to heavy ion interactions is different, with the single-segment device burning out due to local electric field spikes, impact ionization, and ultimately thermal runaway. The two-segment design is resilient, with the electric field remaining below critical levels.

[0134] Without wishing to be bound by theory, the different results for the two devices will now be explained.

[0135] Before the heavy ion event (t < 0.1 ns), the single-segment and two-segment rectifiers are at room temperature and their steady-state leakage current is extremely low (~10 20 At this point, with 1200 V applied, the two-segment device with its additional electric field spike has a maximum electric field of 2.27 MV / cm, 16% lower than the single-segment design.

[0136] At t = 0.1 ns, narrow filaments of electron-hole pairs are generated instantly along each ion path by impact ionization. Fig.12 and 13 This breaks the uniform depletion region and suppresses the electric field through which the ions pass. In both cases, the charge extraction process leads to a sharp rise in the current, as shown in Fig. 11C Visible in.

[0137] In both devices, after 0.1 ns, the electric field distribution in the center of the drift region collapses, reflected by an increase in the electric field at the anode and cathode. Electrons and holes are swept out of the drift region and attracted by the electric field to the n+ cathode 54 and the P+ injection region 58 in the anode, respectively.

[0138] In a single-segment SBD, the electric field at the edge of the anode contact 51 reaches 2.90 MV / cm at t=0.1 ns. Thereafter, the peak decreases with the peak field shifting toward the corner of the n+ cathode, where the electric field increases to 3.92 MV / cm at 0.7 ns.

[0139] This is because the huge electric field causes local impact ionization, thereby generating more carriers. The impact ionization coefficient of a semiconductor is based on a modified form of Chynoweth's Law, which is defined as:

[0140] α= aE n .e –(b / E)^m (2)

[0141] Where E represents the electric field, and a and b are temperature-dependent parameters. According to Equation 2, the presence of a high local electric field leads to an increase in the impact ionization rate. The generated carriers accumulate around the cathode, which also makes the electric field more intense. Therefore, Fig. 11C The current in the single-segment device in the circuit continues to increase. As the device heats up, more carriers are generated, the current increases, and the temperature rises, the thermal runaway process will occur in a cycle. At about 0.5ns, SEB occurs in the single-segment RESURF SBD, and as the current and temperature increase exponentially, it eventually burns out.

[0142] In contrast, in the two-segment SBD, the electric field spike of 3.35 MV / cm at the edge of the anode field plate at t = 0.15 ns is the highest field experienced during its recovery. Carrier sweeping initially increases the current in the same way as in the single-segment design, so the highest temperature in the device also occurs at the n+ cathode 54 ( Fig. 9 ). Similar to the single-segment device, thereafter, the anode side peak shrinks and the cathode side peak increases, reaching a maximum of 1.73 MV / cm at 0.5 ns. At this point, the current has reached its peak and there is no impact ionization, so no more charge is generated and the current begins to decrease. By 1 ns, most of the charge has been extracted and the electric field distribution resembles the steady-state value again, with the peak moving back to the anode side again.

[0143] The different results of these two layouts and the Fig.12 and 13 The field distribution visible in highlights the importance of managing the electric field spike on the cathode side.

[0144] Reference again Fig.10 If the two-segment device is modified to maximize only the breakdown voltage of the device, the doping of the second segment can be increased so that the cathode-side electric field spike reaches the critical field at the same voltage as the rest of the device. However, in this structure, it is more critical to achieve balance of the electric field when the device recovers from a single event at 1200V. Given that the dynamic field moves from one end of the drift region to the other, the balance of the 3.35MV / cm spike on the anode side at 0.15ns and the 1.73MV / cm spike on the cathode side at 0.5ns can only be achieved by adding 41V to the second segment. 2 This is achieved by overdoping in.

[0145] Reference again Fig.13 , which explains the seemingly non-uniform electric field distribution in the two sections at 1200 V, which is seen to be tilted towards the anode side at 0 ns. This highlights the importance of adopting a radiation-hardened design approach to the development of these diodes.

[0146] P-pillar depth

[0147] Reference again Fig. 9 , a P+ pillar 58 is formed under the anode-side Schottky contact 53 and is used to help extract holes generated during a single event.

[0148] Fig.14 It is shown that for column depth d p-柱 The range of the first section 41 is also referred to as the “extension” in this article. 1 The doping concentration range in the second section 41 2 1.5×10 17 cm –3 For a fixed doping concentration, the two-segment device maintains the capability of a single event.

[0149] refer to Fig.14 , solid symbols indicate that it can support 1200V while being able to 2 / mg heavy ions passed through the device and recovered, while the open symbols represent devices that could not recover after such an event.

[0150] With a doping concentration of 6×10 16 cm –3 The first section 41 has a column depth of 1 μm. 1 Although the breakdown voltage of the device can reach 1808V, the device cannot 2 / mg heavy ions were restored through the device at 1200V. The doping was reduced to 5.5×10 16 cm –3 , the breakdown voltage increased to 2053 V, and the device successfully switched from 60 MeV·cm 2 / mg heavy ions recovered through the device at 1200V. 5.5×10 16 cm –3 is the highest doping tested that was shown to be successfully recovered.

[0151] The first section 41 as a column with a depth of 1.5 μm 1 Devices, 7×10 16 cm –3 The doping is shown to be successful from 60 MeV·cm 2 / mg heavy ions recovered through the highest doping tested in the device at 1200 V. The breakdown voltage of the device was 1590 V.

[0152] As a device of the first section 411 with a column depth of 5 μm, 1×10 17 cm –3 The doping is shown to be successful from 60 MeV·cm 2 / mg heavy ions recovered through the highest doping tested in the device at 1200 V. The breakdown voltage of the device was 1255V.

[0153] A deeper p-column extension results in a higher first segment doping concentration in the RESURF SBD that can achieve the desired SEE condition. Therefore, the process window for first segment implantation becomes larger and the on-state performance is improved. This is because as the P+ column area becomes larger, the first segment doping concentration can be further increased to achieve charge balance as the P-column depth increases. Therefore, the on-state resistance is reduced without sacrificing the latch-up capability.

[0154] Notes

[0155] Existing diodes suffer from unacceptable off-state leakage degradation and catastrophic failure when SEE tested at any appreciable voltage and LET. As shown in this article, vertical topologies lead to short circuits in the drift region, which is often catastrophic for vertical devices. Lateral devices with RESURF layout can help provide significant single event immunity, prevent SEB, limit electric field spikes and internal temperature rise.

[0156] Therefore, rather than simply focusing on the breakdown voltage, the lateral device with RESURF layout is configured to be a laterally charge-balanced device in terms of SEE recovery and radiation-hardened. 2 Equilibrium recovery in / mg heavy ion events can be achieved by spatially varying the doping of the drift region, for example by dividing it into two segments, which can produce an additional electric field spike in the center of the drift region. The device is arranged so that the doping concentration is lower closer to the anode (for example, in the first segment of the two-segment drift region) and the doping concentration is higher closer to the anode, which can limit the electric field spike that appears at the cathode end of the drift region. The presence of a deep p-column region at the anode side of the device further improves device performance.

[0157] The methods described herein can be used for different types of lateral power semiconductor devices, including two-terminal devices, such as Schottky barrier diodes and PiN diodes; and three-terminal devices, such as metal oxide semiconductor field effect transistors (MOSFETs) and insulated gate bipolar transistors (IGBTs), which will now be described in more detail.

[0158] Schottky Barrier Diode

[0159] refer to Fig.15 and 16 , shows a lateral RESURF-based SiC Schottky barrier diode 101. The Schottky barrier diode 101 is based on the second lateral RESURF device 31 ( Fig. 9 ).

[0160] Special References Fig.15, the Schottky barrier diode 101 is formed in the form of heavily doped, n-type, single-crystal four-layer hexagonal silicon carbide (4H-SiC) on a substrate 102. However, the substrate 102 may be a heavily doped p-type 4H-SiC substrate, or a substrate of a different material, such as silicon (Si), such as a silicon substrate or a silicon-on-insulator (SOI) substrate.

[0161] The substrate 102 may support a first epitaxial layer 103, which may be used to transform the base substrate 102, which may have a given conductivity type (e.g., n-type), polytype, crystal orientation, defect density, and / or material, into a more suitable substrate. In this case, the semiconductor layer 103 takes the form of a heavily doped p-type single crystal 4H-SiC layer and serves as a field stop layer. The first epitaxial layer 103 has a thickness d of 1 μm. epi1 and 1×10 19 cm -3 The doping concentration N epi1 However, the thickness d epi1 and / or doping concentration N epi1 Can be lower or higher.

[0162] The first epitaxial layer 103 has an upper surface 104 that supports a layer structure 105 having a main surface 106 (or “upper surface”).

[0163] The layer structure 105 comprises a second epitaxial layer 107 in the form of a lightly doped SiC layer having a first conductivity type (in this case p-type) and having an upper surface 108 (also referred to herein as an "interface"), and a lightly doped SiC layer 109 (also referred to herein as a "drift layer") having a second conductivity type opposite to the first conductivity type (in this case n-type), having an upper surface 110 and providing a drift region 111. The second epitaxial layer 107 has a depth d of 11 μm. epi2 and 1×10 15 cm -3 The doping concentration N epi2 The depth d of the drift layer 109 is 漂移 is 0.5 μm, and its width w between the first and second ends 112, 113 is 漂移 To completely deplete the drift region 109 before breakdown, the second epitaxial layer 107 has a thickness of 1×10 15 cm -3 The doping concentration N epi2 .

[0164] The drift region 111 may be laterally divided into two or more sections 111 between the first and second ends 112, 113. 1 ,111 2 , these segments have corresponding width w区段1 、w 区段2 and the corresponding doping concentration N 区段1 、N 区段2 , where N 区段1 <N 区段2 In this example, the width w 区段1 、w 区段2 11μm and 7.5μm respectively, and the doping concentration N 区段1 、N 区段2 6×10 16 cm –3 and 8.5×10 16 cm –3 As will be explained in more detail later, the doping concentration in the drift region 111 may be graded. 1 ,111 2 Separated by segment boundaries 114 .

[0165] A dielectric layer 115 in the form of a field oxide is disposed on the drift region 111. The thickness d of the dielectric layer 115 is die is 0.3 μm, and its width w between the first and second ends 116, 117 is die The dielectric layer 115 is 20 μm. However, the dielectric layer 115 may be thinner or thicker, and / or include another suitable dielectric material. The dielectric layer 115 partially covers the drift region 111 and leaves a gap having a width w from the first end 112 of the drift region 111. c1 The first contact window 118 has a width w. c1 3μm.

[0166] A first metallization layer 120 in the form of a nickel layer extends over the first end 112 of the drift region 111 to provide a first contact 121 in the form of a Schottky barrier contact and extends over the dielectric layer 115 to form a first contact having a width w for protruding the junction angle. fp1 The first field plate has a width w fp1 The metallization layer 120 also extends in the opposite direction to provide a contact 123 to the p-column 128 .

[0167] A contact region 124 in the form of a heavily doped n-type region is provided in the layer structure 105 adjacent the second end 113 of the drift region 111 at the main surface 106. The contact region 124 is formed by implanting a portion of a third epitaxial layer (not shown) providing the drift layer 109.

[0168] A second metallization layer 125 in the form of a nickel layer extends over the contact region 124 to provide a second contact 126 and extends over the dielectric layer 115 to form a field plate 127 .

[0169] A deep heavily doped region 128 in the form of a heavily doped p-type region (also referred to herein as a “pillar”) is arranged in the layer structure 35 adjacent to the first end 112 of the drift zone 111 at the main surface 106 .

[0170] The pillar 128 is formed using a trench 129 through the drift layer 109 and into the second epitaxial layer 107. The trench has a depth d of, for example, 2 μm. 沟槽 The trench 129 has a bottom 130 and sidewalls 131 , and the pillar 128 is formed by implanting dopants into the bottom 130 and the sidewalls 130 , 131 .

[0171] See also Fig.16 , the Schottky barrier diode 101 is formed around the trench 129 in a rectangular self-terminating structure having a circular doping pattern 132. Fig.16 In FIG. 1 , the field oxide 115 and the first and second metallization layers 120 , 125 are omitted for clarity.

[0172] The device 101 has an edge 134 at the trench sidewall 131 1 , 134 2 , 134 3 , 134 4 Four active channels 133 are formed in the middle of each edge of 1 , 133 2 , 133 3 , 133 4 The groove 129 has a side L of 180 and 480 μm. 1 , L 2 The corners may be curved. Active channel 134 1 , 133 2 , 134 3 , 134 4 With length l 1 , l 2 , l 3 , l 4 , they are 100μm, 400μm, 100μm and 400μm respectively. Therefore, the total length of the active channel is 1000μm.

[0173] The device 101 may be smaller, for example, where the trench 131 has a side L of 130 and 280 μm. 1 , L 2 to provide a total active channel length of 500 μm. The device can be smaller or larger.

[0174] Inserted high doping region

[0175] refer to Fig.17 , showing a modified doping layout 132 ′.

[0176] The improved doped layout 132' is different from the doped layout 132' shown in FIG. 132 in that an inserted highly doped region 128' with a castellated boundary is used.

[0177] Along the channel 133 1 ’, 133 2 ’, 133 3 ’, 133 4 ’, the width of the highly doped region 128' for providing a highly doped column (e.g., a p-column) increases and decreases periodically with a pitch p. In the wide portion 135, the highly doped region 128' extends along the main surface 108 under the dielectric layer 115 to the edge 136 of the first field plate 122. In the narrow portion 137, the highly doped region 128' reaches the main surface 108 but terminates at one end of the drift region 111. The pitch p can be between 0 and 10 μm (i.e., 0 < p ≤ 10 μm), for example 4 and 5 μm.

[0178] PiN diode

[0179] Reference Fig.18 , shows a lateral RESURF-based SiC PiN diode 141.

[0180] The PiN diode 141 is the same as the Schottky barrier diode 101 described above ( Fig.15 ), but is different in that the Schottky barrier contact is replaced by an ohmic contact with a highly doped material region of the first conduction type (in this case p-type), and the drift region is modified to accommodate the highly doped p-region. In this case, the highly doped p-type material is provided by an implantation for providing a p-column.

[0181] Along the length of the channel, the highly doped p-type SiC region 128” extends along the main surface 108 under the dielectric layer 115 and under the first field plate 122 (but does not extend to the edge 136), so a shorter drift region 111’ is used. Thus, the highly doped p-type region 128’ provides a heavily doped p-type region that forms a junction with the lightly doped n-type region 111’ and also forms a junction with the heavily doped n-type region 124, thereby providing a p-i-n diode structure.

[0182] In this case, the highly doped p-type region 128” extends an overlapping distance w of 1.5 μm under the first field plate 122 r , the first contact window size w c1 is 1.5 μm, and the field plate size w fp1 is 1.5 μm. Other values of the first contact window size w c1 can be used, and the overlapping distance w rCan be 0 <w r <w fp1 , preferably 0.2w fp1 ≤w r ≤0.8w fp1 .

[0183] MOSFET

[0184] refer to Fig.19 , a lateral RESURF-based SiC MOSFET 161 is shown.

[0185] MOSFET 161 and Schottky barrier diode 101 described above ( Fig.15 ) but differs in that the Schottky barrier contact is replaced by an ohmic contact to a region of highly doped material of the second conductivity type (in this case n-type), a reversely doped region of the first conductivity type (in this case p-type) providing a channel is introduced, and a gate structure is provided over the channel.

[0186] At the main surface 106, a reverse doped p-type region 162 is inserted between the high doped p-type region 128 and the n-type drift region 111". The reverse doped p-type region 162 has a doping profile with a concentration increasing from the main surface 106 to the substrate 102. The thickness of the reverse doped p-type region 162 is the same as or similar to the thickness of the n-type drift region 111".

[0187] A highly doped n-type well 163 is disposed within the counter-doped p-type region 162 at the main surface 106 offset from one end 112 ′ of the drift region 111 ″, leaving a channel 164 between the n-type well 163 and the one end 112 ′ of the drift region 111 ″.

[0188] A gate dielectric 165 is disposed on the main surface 106 above the channel 164. The gate dielectric 165 may include a silicon dioxide layer having a thickness, for example, between 20 and 100 nm, such as about 60 nm, but thinner or thicker layers may also be used. The gate dielectric 165 extends along the main surface 106 between another dielectric layer 167 covering a channel side portion 168 of the highly doped n-type well 163 and adjacent to the field dielectric 115, forming a step 169. A third metallization layer 170 is disposed on the gate dielectric 165 and extends over the step 169 to the field dielectric 115, and provides gate metallization for gating the channel 164.

[0189] The modified first metallization layer 120' extends over the p-pillar 128 and the highly doped n-type well 163 to provide a first contact 121' on the p-pillar side portion 171 of the highly doped n-type well 163. In this case, the metallization layer 120' does not extend onto the dielectric layer 115 to form a field plate, but terminates at the edge of another dielectric layer 167.

[0190] In this case, the first contact window width w c1 ' is 1.5 μm, the width w of the dielectric layer 167 fd The gate dielectric width w is 1.5 μm. gd is 1.5 μm, and the gate metallization overlap width w gmo The width of the second field plate is 1.5 μm. 2fp is 3 μm, and the highly doped n-region 124 extends under the field dielectric 115 by w, ie, 1.5 μm.

[0191] In this example, the width w zone1 、w zone2 7.5μm and 7.5μm respectively, and the doping concentration N zone1 、N zone2 3×10 16 cm –3 and 1.5×10 17 cm –3 .

[0192] IGBT

[0193] refer to Fig. 20 , showing a lateral RESURF-based SiC IGBT 181 .

[0194] IGBT 181 and MOSFET 161 described above ( Fig.19 ) but differs in that the highly doped contact region of the second conductivity type (in this case n-type) is replaced by a highly doped contact region of the first conductivity type (in this case p-type).

[0195] The n-type drift region 111'' extends beyond one end of the dielectric layer 115, and a highly doped p-type region 182 is disposed in the n-type drift region 111'' at the main surface 106 to provide a contact 126' to the second metallization 125. The highly doped p-type region 182 extends from an edge 183 located below the field plate 127. The overlap between the edge 183 of the dielectric layer 115 and the second end 117 is a width w r , that is 1.5μm.

[0196] Drift Zone

[0197] In the devices described herein, the drift region and the underlying epitaxial layers have a reduced surface field (RESURF) configuration to reduce the slope of the electric field distribution in the drift region parallel to the main surface.

[0198] refer to Fig.21A , the drift region 111 may be uniformly doped (for a given thickness of the drift region) to a doping density N for achieving RESURF DU .

[0199] refer to Fig.21B In some embodiments, a two-segment drift region 111 may be used, wherein the first segment 111 1 (which is closer to the anode) in the doping concentration N D1 Below the second section 111 2 (which is closer to the cathode) in the doping concentration N D2 , while still meeting the requirements for implementing RESURF.

[0200] Additional segments may be included, for example three or more segments following the same rule, i.e. N Di <N D(i+1) , where i = 1, 2, etc.

[0201] refer to Fig. 21C , a gradient drift region 111 can be used, in which the doping concentration is changed from a first value N at the first end to DA Increase to the second value N at the second end DB , while still meeting the requirements for achieving RESURF. Preferably, the doping concentration increases monotonically, and may increase linearly.

[0202] manufacture

[0203] refer to Fig. 22 , a method of fabricating a lateral RESURF-based SiC device 101 , 141 , 161 , 181 will now be described.

[0204] Provide a substrate 102 ( Fig.15 ) (Step S1). Substrate 102 ( Fig.15 ) takes the form of an n-type or p-type 4H-SiC substrate. However, other forms of substrates, such as silicon substrates, may also be used. If necessary, on the base substrate 102 ( Fig.15 ) is grown on the first epitaxial layer 103 ( Fig.15 )(Step S2). For example, the substrate 102 ( Fig.15 ) may take the form of an n-type 4H-SiC substrate, and the first epitaxial layer 103 ( Fig.15 ) may take the form of a heavily doped p-type 4H-SiC layer.

[0205] On the substrate or the first epitaxial layer 103 ( Fig.15 ) is grown on the second epitaxial layer 107 ( Fig.15 ) (Step S3). The second epitaxial layer 107 ( Fig.15 ) may take the form of a lightly doped p-type 4H-SiC layer.

[0206] Directly in order to provide the drift region 111 ( Fig.15 ) of the second epitaxial layer 107 ( Fig.15 ) is formed (eg, grown) on a region or layer (not shown) of a 4H-SiC layer (step S4). For example, the 4H-SiC layer may take the form of a lightly doped n-type 4H-SiC layer.

[0207] Then the anode side trench may be formed (step S5). For example, this may include applying a photoresist layer (not shown) on the structure and patterning the photoresist layer to form a mask (not shown). The mask pattern is transferred to the underlying structure by dry etching.

[0208] Pillar 128 is formed by side injection ( Fig.15 ) (Step S6). Alternatively, deep pillars (without trenches) may be formed by implantation from the main surface.

[0209] Additional regions such as the drift region 111 and the contact region 124 ( Fig.15 )、128”( Fig.18 )、163( Fig.19 )、183( Fig. 20 ) is doped in sections or gradually (step S7). For example, for each region, a suitable mask (not shown) is formed, and suitable dopant ions (donors or acceptors) are implanted under suitable ion implantation conditions (eg, energy, dose, etc.).

[0210] Forming a dielectric layer 115 ( Fig.15 ) (Step S8 ). For example, the dielectric layer 115 may be in the form of a silicon dioxide layer, which may be thermally grown or deposited by a suitable CVD process.

[0211] The dielectric layer 115 may be patterned ( Fig.15 ) (step S9), and if necessary, a gate dielectric layer may be formed (step S10) and patterned (step S11). The gate dielectric may take the form of a thermally growable silicon dioxide layer. Other gate dielectric materials may be used.

[0212] If not already formed, contact region 124 may be formed ( Fig.15 )、128”( Fig.18 )(Step S12). For example, the region may be injected.

[0213] Contacts are formed, in other words, metallization is formed (step S13). For example, this may include depositing a metallization layer, applying a photoresist layer (not shown) on the metallization, and patterning the photoresist layer to form a mask (not shown). The mask pattern is transferred to the underlying metallization by dry etching to form the first and second metallizations 120, 125 and the optional third gate metallization 170 ( Fig.19 ).

[0214] Double RESURF structure

[0215] In the example described above, a single RESURF structure is used. However, other RESURF structures, such as a double RESURF structure, may also be used.

[0216] refer to Fig.23 , showing the middle layer structure 105 of the drift region 111 D . Layer structure 105 D Similar to the previously described structure 105 ( Fig.15 ), except that an additional region 138 (or "top region") of the first conductivity type (in this case, p-type) is disposed between the surface 106 and the drift region 111 (which is of the second conductivity type). The thickness d of the top region 138 is 顶部 The thickness of the top layer 138 may be between 50 and 300 nm, for example between 100 and 200 nm, and its doping concentration is about half of the doping concentration of the drift region 111. The top region 138 may be formed by implantation. Therefore, the thickness of the epitaxial layer (not shown) grown on the underlying epitaxial layer 103 may be made thicker. For example, if the drift layer 111 is intended to have a thickness of 500 nm and the top layer 138 is intended to have a thickness of 200 nm, the epitaxial layer (not shown) may be grown to have a thickness of 700 nm. The drift region 111 may be divided into segments 111. 1 ,111 2 Or a gradient.

[0217] Suppress off-state leakage

[0218] refer to Fig.24 A short shallowly doped region 140 of a composite type opposite to the drift region 111, in other words, of a first conductivity type (in this case, p-type), may be provided at one end 116 of the dielectric layer 115, adjacent to the Schottky contact 121 at the main surface 106. The shallowly doped region 140 may help suppress off-state leakage.

[0219] The shallowly doped region 140 extends along the edge of the annular Schottky contact 121 (ie, the anode), and is therefore also referred to as a “shallowly doped ring” or simply a “ring.” In this case, the shallowly doped ring 140 is p-type, and is therefore also referred to as a “p-ring.”

[0220] The p-ring 140 surrounds the Schottky contact 121 with an overlap to control the magnitude of the electric field experienced by the Schottky contact 121 under latched conditions. The p-ring 140 can be considered similar to a junction barrier Schottky (JBS), where the Schottky contact 121 opening determines the electric field. Metal contacts with high barrier heights, such as titanium, can be used to help reduce leakage.

[0221] If the n-layer located below the extension is enhanced, it is beneficial to surround the p-ring 140 of the Schottky contact with an overlap extending toward the anode, which helps to "kill" the junction-gate field effect transistor (JFET) and also have a superjunction (SJ) structure. This will be referred to below Figures 25A to 25I Describe in more detail.

[0222] The doping concentration of the p-ring 140 may be between 5×10 17 cm –3 and 1×10 19 cm –3 between 1×10 18 cm –3 The p-ring 140 has a thickness d p-环 and width w p-环 . p-ring depth d p-环 The thickness d of the drift region 111 may be between n-漂移 Between 10% and 50%, i.e. 0.1d n-漂移 ≤d p-环 ≤0.5d n-漂移 , and preferably between the thickness d of the drift region 111 n-漂移 Between 15% and 25%, i.e. 0.15d n-漂移 <d p-环 ≤0.25d n-漂移 For example, in the drift region thickness d n-漂移 When the p-ring depth is 0.5 μm, p-环 It can be between 50nm and 250nm, preferably around 100nm. The width of the p-ring w p-环 It can be at most the width w of the drift region 111 n-漂移 and may be, for example, 100 nm ≤ w p-环 ≤5μm.

[0223] The off-state leakage suppression ring 140 can be incorporated into the RESURF-based SiC devices described above in a variety of different ways, such as device 31 ( Fig. 9 )、Device 101( Fig.15 )、141( Fig.18 )、Device 161( Fig.19 ) and device 181( Fig. 20 ).

[0224] Figures 25A to 25I RESURF based SiC devices are shown, each comprising an epitaxial layer 107, a drift region 111, a dielectric layer 115, a metallization contact layer 120 (which forms a Schottky barrier), a contact region 124 and a second metallization layer 125. For clarity, the highly doped pillars 128 are omitted.

[0225] refer to Fig.25A , the device may include a buried doped region 141 (or "implanted region") below the shallow doped region 140, which is of the same conductivity type as the drift region 111 and of the opposite conductivity type to the shallow doped region 140. Thus, in the case of a p-ring, the buried doped region 141 is an n-type ring 141. The p-type and n-type regions 140, 141 may be contiguous (in a plan view). The p-type and n-type regions 140, 141 may produce a dual RESURF / SJ effect. The buried doped region 141 may have a conductivity between 1×10 17 cm –3 and 1×10 19 cm –3 The buried doped region 141 may have a thickness of at least 50 nm and may extend to the bottom of the drift region 111 , ie, to the upper surface 108 of the epitaxial layer 107 .

[0226] The addition of the implant region 141 may help suppress leakage by preventing the highest electric fields from reaching the anode Schottky metal 120 .

[0227] See also Fig.25B , the injection region 141 can be used for the two-segment drift region 111 1 ,111 2 The addition of the injection region 141 allows the first segment 111 1 The section (of the two sections closer to the anode) is more highly doped, helping to lower resistance.

[0228] refer to Fig.25C , a shallowly doped region 140 may be used without the underlying implanted region 141 ( Fig.25A ).

[0229] refer to Fig.25D, the two regions 140 , 141 may be thinner. In particular, the regions 140 , 141 do not need to extend as far as the upper surface 108 of the epitaxial layer 107 .

[0230] refer to Fig.25E , similar to multiple vertical JBS diodes, can be connected along the Schottky contact 121 ( Fig.24 ) width and laterally spaced apart using implant regions 141 with or without the following 1 , 141 2 , 141 3 Multiple off-state leakage suppression rings 140 1 , 140 2 , 140 3 .

[0231] exist Figures 25A to 25E In the device shown, the off-state leakage suppression ring 140 with or without the underlying implantation region 141 may be narrower than the length of the drift region 111, for example, its width w p-环 between 100 nm and 5 μm, preferably 3 μm; and arranged so that it spans equally across each side of the oxide-metal interface, e.g., over a width w p-环 In the case of 3 μm, each side spans 1.5 μm.

[0232] refer to Fig.25F , the off-state leakage suppression ring 140 with or without the underlying implant region 141 may extend through a large portion of the drift region 111, thereby producing a double RESURF SJ, such as w p-环 ≥5μm.

[0233] refer to Figures 25G to 25I , a combination of an extended off-state leakage suppression ring 140 and a plurality of off-state leakage suppression rings 140 in the drift region 111 described above may be used.

[0234] Revise

[0235] It will be appreciated that various modifications may be made to the embodiments described above. Such modifications may involve equivalent and other features known in the design, manufacture and use of silicon carbide semiconductor devices and component parts thereof, as well as equivalent and other features that may replace or supplement the use of features already described herein. Features of one embodiment may be replaced or supplemented by features of another embodiment.

[0236] The drift layer may be p-type. Therefore, the underlying epitaxial layer may be n-type, and the pillars may be heavily doped n-type.

[0237] 3-layer cubic silicon carbide (3C-SiC) can be used instead of 4H-SiC. Dielectrics such as silicon nitride, silicon oxynitride, or high-k dielectrics can be used. Metallization can include titanium, molybdenum, aluminum, silicon silicide, or titanium nitride.

[0238] The semiconductor device may include a triple RESURF structure.

[0239] Although the claims in this application have described a specific combination of features, it should be understood that the disclosure scope of the present invention also includes any novel features or any novel combination of features disclosed explicitly or implicitly herein, or any generalization thereof, whether or not it relates to the same invention as currently claimed in any claim, and whether or not it alleviates any or all technical problems that are the same as the present invention. The applicant hereby notifies that new claims may be made for these features and / or combinations of these features during the examination of this application or any other application derived therefrom.

Claims

1. A lateral silicon carbide power semiconductor device, comprising: substrate; A silicon carbide semiconductor structure is provided on the substrate and has a main surface, the semiconductor structure comprising: A layer of a first conductivity type disposed on the substrate; and a layered drift region of a second conductivity type opposite to the first conductivity type, the layered drift region being disposed directly on the layer to form an interface between the layer and the drift region, the drift region extending laterally along the major surface between a first end and a second end, wherein doping in the drift region and the layer are arranged to deplete the drift region; a first contact region at the first end of the drift region; a second contact region of the second end of the drift region, the second contact region being highly doped, being of the first or second conductivity type, and being adjacent to the second end of the drift region and being disposed in the drift region or in a region adjacent to the second end of the drift region; and The highly doped region of the first conductivity type extends from the main surface into the semiconductor structure and adjoins the first end of the drift region, wherein the highly doped region has a thickness greater than that of the drift region.

2. The lateral silicon carbide power semiconductor device according to claim 1, wherein the layered drift region comprises at least first and second segments between the first end and the second end of the drift region, wherein the doping concentration in the first region is lower than the doping concentration in the second region. 3 . The lateral silicon carbide power semiconductor device of claim 1 , wherein the layered drift region has a doping profile such that the doping concentration increases between the first end and the second end of the drift region. 4 . The lateral silicon carbide power semiconductor device according to claim 1 , wherein the drift region has a thickness between 0.1 and 10 μm, between 0.1 and 2 μm or between 0.2 and 0.8 μm. 5 . The lateral silicon carbide power semiconductor device according to claim 1 , wherein the drift region has a length between the first end and the second end of between 2 and 35 μm or between 5 and 20 μm.

6. The lateral silicon carbide power semiconductor device according to any one of claims 1 to 5, wherein the drift region has a width between 5×10 15 cm –3 and 1×10 18 cm –3 Between or between 1×10 16 cm –3 and 5×10 17 cm –3 between the doping concentrations. 7 . The lateral silicon carbide power semiconductor device according to claim 1 , wherein the highly doped region extends below the interface between the layer and the drift region by a distance Δ between 0.1 and 10 μm.

8. The lateral silicon carbide power semiconductor device according to any one of claims 1 to 7, wherein the highly doped region has a doping area of ​​at least 1×10 18 cm –3 of doping concentration. 9 . The lateral silicon carbide power semiconductor device according to claim 1 , wherein the first conductivity type is p-type, and the second conductivity type is n-type.

10. The lateral silicon carbide power semiconductor device according to any one of claims 1 to 9, further comprising: A dielectric layer is disposed on the drift region having a first end and a second end, the dielectric layer partially covering the drift region.

11. The lateral silicon carbide power semiconductor device according to any one of claims 1 to 10, further comprising: A first terminal or a first metallization layer is arranged to contact the first contact area.

12. The lateral silicon carbide power semiconductor device according to any one of claims 1 to 11, further comprising: A doped region of a first conductivity type, located at an end of the dielectric layer at the major surface, is used to help suppress off-state leakage.

13. The lateral silicon carbide power semiconductor device according to claim 12, further comprising: Another doped region of the second conductivity type is located below the doped region and directly contacts the doped region to form a double RESURF structure.

14. The lateral silicon carbide power semiconductor device according to any one of claims 1 to 13, further comprising: A second terminal or a second metallization layer is arranged to contact the second contact area.

15. The lateral silicon carbide power semiconductor device according to any one of claims 1 to 14, further comprising: A further layered region of the first conductivity type is disposed directly on the drift region. 16 . The lateral silicon carbide power semiconductor device according to claim 1 , having a breakdown voltage between 400 and 1000 V. 17 . The lateral silicon carbide power semiconductor device of claim 16 , wherein doping in the drift region is constant between the first end and the second end.

18. The lateral silicon carbide power semiconductor device according to any one of claims 1 to 15, having a breakdown voltage between 1000 and 1400V.

19. A lateral silicon carbide power semiconductor device according to any one of claims 1 to 15, having a breakdown voltage between 1400 and 4000V.

20. A lateral silicon carbide power semiconductor device according to claim 16, 18 or 19, wherein the layered drift region includes at least a first and a second segment between the first end and the second end of the drift region, wherein the doping concentration in the first region is lower than the doping concentration in the second region, or the layered drift region has a doping profile such that the doping concentration increases between the first end and the second end of the drift region. 21 . The lateral silicon carbide power semiconductor device according to claim 1 , configured as a Schottky barrier diode. 22 . The lateral silicon carbide power semiconductor device according to claim 1 , configured as a PiN diode. 23 . The lateral silicon carbide power semiconductor device according to claim 1 , configured as a MOSFET. 24 . The lateral silicon carbide power semiconductor device according to claim 1 , configured as an IGBT.

25. A monolithic semiconductor device comprising a plurality of lateral silicon carbide power semiconductor devices according to any one of claims 1 to 24.

26. A vehicle or apparatus comprising a lateral silicon carbide power semiconductor device according to any one of claims 1 to 24.

27. A method of operating a lateral silicon carbide power semiconductor device according to any one of claims 1 to 24, the method comprising: placing the lateral silicon carbide power semiconductor device in an environment subjected to ionizing radiation, heavy ion irradiation and / or proton irradiation; as well as A bias of at least 400V, at least 650V, at least 1200V, or at least 2000V is applied across the drift region.

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