Semiconductor device

Abstract

A semiconductor device (1) is provided with a semiconductor layer (40) and a first longitudinal MOS transistor (10) and a second longitudinal MOS transistor (20) formed in the semiconductor layer (40), in a plan view of the semiconductor layer (40), a total length of one side in an outer periphery of a first gate electrode region (G1) and a total length of one side in an outer periphery of a first resistance element region (R1) coincide with a portion of one side in an outer periphery of the semiconductor layer (40) that is orthogonal to a boundary line (90) and that is closest to the first gate pad (119), and in the plan view of the semiconductor layer (40), only one corner portion of four corner portions of the outer periphery of the first gate electrode region (G1) in the outer periphery of the first resistance element region (R1) includes a corner portion that is closest to the boundary line (90) and that is closest to the side in the outer periphery of the semiconductor layer (40) that is orthogonal to the boundary line (90).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device, and particularly to a semiconductor device of a chip size package type. BACKGROUND

[0002] A vertical MOS transistor of a double structure capable of controlling bidirectional conduction with one chip requires reduction in on-resistance and downsizing. With regard to the vertical MOS transistor of the double structure, a 4-pad structure having only a minimum required number of pads is disclosed.

[0003] PRIOR ART DOCUMENTS

[0004] PATENT DOCUMENTS

[0005] Patent Document 1: Japanese Patent Application Publication No. 2008-53623 A SUMMARY

[0006] PROBLEMS TO BE SOLVED BY THE INVENTION

[0007] In a semiconductor device in which a vertical MOS transistor is formed, in order to improve the resistance to ESD (Electro Static Discharge), there is a case where a resistance element is provided to the semiconductor device. However, by providing the resistance element, there is a case where the area of a region contributing to the conduction of the vertical MOS transistor is reduced, and thus reduction in on-resistance becomes difficult.

[0008] MEANS FOR SOLVING THE PROBLEMS

[0009] To solve the above problems, a semiconductor device according to the present disclosure is a flip-chip mounted chip size package type semiconductor device including a semiconductor layer including a semiconductor substrate, a first vertical MOS transistor formed entirely in a first region of the semiconductor layer on a top surface side of the semiconductor layer, a second vertical MOS transistor formed entirely in a second region adjacent to the first region in a plan view of the semiconductor layer, and a metal layer formed on a bottom surface side of the semiconductor layer and connected to the semiconductor substrate. The semiconductor substrate is a common drain region of the first vertical MOS transistor and the second vertical MOS transistor. In the plan view, the semiconductor layer is a square. In the plan view, the first region and the second region are arranged in a first direction. In the plan view, a boundary line between the first region and the second region is orthogonal to the first direction and is a straight line that bisects the semiconductor layer in area and passes through a center of the semiconductor layer. In the plan view, pads provided in the first region are only one first source pad connected to a first source electrode of the first vertical MOS transistor and one first gate pad connected to a first gate electrode of the first vertical MOS transistor. The first vertical MOS transistor includes a first gate resistance element connected to the first gate electrode, a first gate electrode region that is a rectangular region including the first gate pad inside in the plan view and is a region having the largest area in a range that does not include the first source electrode or the first gate resistance element, and a first resistance element region that is a rectangular region including the first gate resistance element inside in the plan view and is a region having the largest area in a range that does not include the first source electrode or the first gate electrode region. In the plan view, a total length of one side of an outer periphery of the first gate electrode region and a total length of one side of an outer periphery of the first resistance element region coincide with a portion of a side of an outer periphery of the semiconductor layer that is orthogonal to the boundary line and has the shortest distance from the first gate pad. In the plan view, only one corner of four corners of the outer periphery of the first resistance element region that has the shortest distance from the boundary line and the shortest distance from a side of the outer periphery of the semiconductor layer that is orthogonal to the boundary line is included in the outer periphery of the first resistance element region.

[0010] Effects of the Invention

[0011] According to the semiconductor device of the present disclosure, a small double-structure vertical MOS transistor can improve ESD resistance and reduce on-resistance. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 is a cross-sectional schematic view of a structure of a semiconductor device of an embodiment.

[0013] Figure 2 is a plan schematic view of an example of a configuration of a pad of a semiconductor device of an embodiment.

[0014] Figure 3 is a plan schematic view of an example of shapes and a configuration of constituent elements of a semiconductor device of an embodiment.

[0015] Figure 4 is a circuit diagram of an equivalent circuit of a semiconductor device of an embodiment.

[0016] Figure 5A is a plan schematic view of a substantially unit structure of a first transistor of an embodiment.

[0017] Figure 5B is a perspective schematic view of a substantially unit structure of a first transistor of an embodiment.

[0018] Figure 6 is a plan view of an example of shapes and a configuration of constituent elements of a semiconductor device of an embodiment.

[0019] Figure 7A is a plan schematic view of shapes and a configuration of constituent elements of a semiconductor device of Comparative Example 1.

[0020] Figure 7B is a plan schematic view of shapes and a configuration of constituent elements of a semiconductor device of Comparative Example 1.

[0021] Figure 8 is a plan schematic view of an example of shapes and a configuration of constituent elements of a semiconductor device of an embodiment.

[0022] Figure 9A is a plan schematic view of a configuration of constituent elements of a semiconductor device of Comparative Example 2.

[0023] Figure 9B is a plan schematic view of a configuration of constituent elements of a semiconductor device of Comparative Example 3.

[0024] Figure 9C is a plan schematic view of a configuration of constituent elements of a semiconductor device of Comparative Example 4.

[0025] Figure 9D is a plan schematic view of a configuration of constituent elements of a semiconductor device of Comparative Example 5.

[0026] Figure 9E is a plan schematic view of a configuration of constituent elements of a semiconductor device of Comparative Example 6.

[0027] Figure 10 is a plan view schematically showing an example of the shape and the arrangement of a constituent element of the semiconductor device of the embodiment.

[0028] Figure 11 is a plan view schematically showing an example of the shape and the arrangement of a constituent element of the semiconductor device of the embodiment.

[0029] Figure 12 is a plan view schematically showing an example of the shape and the arrangement of a constituent element of the semiconductor device of the embodiment.

[0030] Figure 13 is a plan view schematically showing an example of the shape and the arrangement of a constituent element of the semiconductor device of the embodiment.

[0031] Figure 14 is a plan view schematically showing an example of the shape and the arrangement of a constituent element of the semiconductor device of the embodiment. DETAILED DESCRIPTION

[0032] The embodiments described below are mere examples of the present disclosure. The numerical values, shapes, materials, constituent elements, arrangement positions of constituent elements, connection modes, and the like indicated in the following embodiments are examples and are not intended to limit the present disclosure.

[0033] In the present disclosure, the so-called "A and B are electrically connected" includes the case where A and B are directly connected via a wiring, the case where A and B are directly connected without a wiring, and the case where A and B are indirectly connected via a resistance component (resistance element, resistance wiring).

[0034] (Embodiment)

[0035] [1. Configuration of Semiconductor Device]

[0036] Hereinafter, the configuration of the semiconductor device of the embodiment will be described.

[0037] The semiconductor device of the embodiment is a chip size package (CSP) type semiconductor device capable of face-down mounting in which two longitudinal MOS (Metal Oxide Semiconductor) transistors are formed on a semiconductor substrate. The two longitudinal MOS transistors are power transistors, and are so-called trench MOS type FETs (Field Effect Transistors).

[0038] Figure 1 is a cross-sectional view schematically showing an example of the configuration of the semiconductor device 1 of the embodiment. Figure 2is a plan view showing one example of a configuration of a pad of the semiconductor device 1. Figure 1 Figure 2

[0039] As shown in Figure 1 Figure 2 The semiconductor device 1 has a semiconductor layer 40, a metal layer 30, a first vertical MOS transistor 10 (hereinafter also referred to as transistor 10) formed integrally within a first region Al of the semiconductor layer 40, and a second vertical MOS transistor 20 (hereinafter also referred to as transistor 20) formed integrally within a second region A2 of the semiconductor layer 40.

[0040] The transistor 10 formed integrally within the first region Al means that all elements constituting the transistor 10 are contained within the first region Al in a plan view and are not contained within the second region A2. Similarly, the transistor 20 formed integrally within the second region A2 means that all elements constituting the transistor 20 are contained within the second region A2 in a plan view and are not contained within the first region Al.

[0041] In the present disclosure, the semiconductor substrate 32 and the low-concentration impurity layer 33 are collectively referred to as the semiconductor layer 40. The semiconductor substrate 32 is disposed on the lower surface side (also referred to as the back surface side) of the semiconductor layer 40 and is composed of silicon containing impurities of the first conductivity type.

[0042] The low-concentration impurity layer 33 is disposed on the upper surface side (also referred to as the surface side) of the semiconductor layer 40, is formed in contact with the semiconductor substrate 32, and is an impurity layer of the first conductivity type containing impurities of the first conductivity type at a lower concentration than the concentration of the impurities of the first conductivity type of the semiconductor substrate 32. The low-concentration impurity layer 33 can be formed on the semiconductor substrate 32, for example, by epitaxial growth.

[0043] The metal layer 30 is formed in contact with and connected to the back surface side of the semiconductor layer 40, that is, the back surface side of the semiconductor substrate 32, and is composed of silver (Ag) or copper (Cu). In addition, the metal layer 30 can contain, in a trace amount, elements other than metals that are mixed as impurities in the manufacturing process of metal materials. Furthermore, the metal layer 30 can not be formed on the entire surface of the back surface side of the semiconductor layer 40.

[0044] As shown in Figure 1 In the first region Al of the low-concentration impurity layer 33, a first body region 18 of the second conductivity type containing impurities of the second conductivity type different from the first conductivity type is formed. In the first body region 18, a first source region 14 of the first conductivity type containing impurities of the first conductivity type is formed.

[0045] ​​​Further, in the first region Al, a plurality of first gate trenches 17 are formed in a depth reaching a portion of the low-concentration impurity layer 33, the first source region 14 and the first body region 18 being penetrated from the upper surface of the semiconductor layer 40, and further, a first gate conductor 15 is formed on a first gate insulating film 16 inside the first gate trench 17. The first gate conductor 15 is a buried gate electrode buried inside the semiconductor layer 40, and is electrically connected to the first gate pad 119.

[0046] The first source electrode 11 includes a portion 12 and a portion 13, the portion 12 being connected to the first source region 14 and the first body region 18 via the portion 13.

[0047] The portion 12 of the first source electrode 11 is a layer to be joined with solder at reflow in a face-down mounting, and can be composed of a metal material containing one or more of nickel, titanium, tungsten, and palladium, for example. A plating layer of gold or the like can be applied to the surface of the portion 12.

[0048] The portion 13 of the first source electrode 11 is a layer to connect the portion 12 and the semiconductor layer 40, and can be composed of a metal material containing one or more of aluminum, copper, gold, and silver, for example.

[0049] In the second region A2 of the low-concentration impurity layer 33, a second body region 28 of the second conductivity type containing an impurity of the second conductivity type is formed. In the second body region 28, a second source region 24 of the first conductivity type containing an impurity of the first conductivity type is formed.

[0050] Further, in the second region A2, a plurality of second gate trenches 27 are formed in a depth reaching a portion of the low-concentration impurity layer 33, the second source region 24 and the second body region 28 being penetrated from the upper surface of the semiconductor layer 40, and further, a second gate conductor 25 is formed on a second gate insulating film 26 inside the second gate trench 27. The second gate conductor 25 is a buried gate electrode buried inside the semiconductor layer 40, and is electrically connected to the second gate pad 129.

[0051] The second source electrode 21 includes a portion 22 and a portion 23, the portion 22 being connected to the second source region 24 and the second body region 28 via the portion 23.

[0052] The portion 22 of the second source electrode 21 is a layer to be joined with solder at reflow in a face-down mounting, and can be composed of a metal material containing one or more of nickel, titanium, tungsten, and palladium, for example. A plating layer of gold or the like can be applied to the surface of the portion 22.

[0053] The portion 23 of the second source electrode 21 is a layer that connects the portion 22 and the semiconductor layer 40. As a non-limiting example, it may be made of a metal material including aluminum, copper, gold, and silver.

[0054] With the aforementioned structures of transistors 10 and 20, the area directly above the semiconductor substrate 32 and the low-concentration impurity layer 33 forms a common drain region that combines the first drain region of transistor 10 and the second drain region of transistor 20. Furthermore, the metal layer 30 forms a common drain electrode that combines the first drain electrode of transistor 10 and the second drain electrode of transistor 20.

[0055] like Figure 1 As shown, the first body region 18 is covered by an interlayer insulating layer 34 with an opening, and a portion 13 of the first source electrode 11, which is connected to the first source region 14, is provided through the opening of the interlayer insulating layer 34. The interlayer insulating layer 34 and the portion 13 of the first source electrode 11 are covered by a passivation layer 35 with an opening, and a portion 12, which is connected to the portion 13 of the first source electrode 11, is provided through the opening of the passivation layer 35.

[0056] The second body region 28 is covered by an interlayer insulating layer 34 with an opening, and a portion 23 of a second source electrode 21 connected to the second source region 24 is provided through the opening of the interlayer insulating layer 34. The interlayer insulating layer 34 and the portion 23 of the second source electrode 21 are covered by a passivation layer 35 with an opening, and a portion 22 connected to the portion 23 of the second source electrode 21 is provided through the opening of the passivation layer 35.

[0057] Therefore, the first source pad 111 and the second source pad 121 refer to the areas where the first source electrode 11 and the second source electrode 21 are partially exposed on the surface of the semiconductor device 1, the so-called terminal portions. Similarly, the first gate pad 119 and the second gate pad 129 refer to the areas where the first gate electrode 19 (on the surface of the semiconductor device 1) is partially exposed, the so-called terminal portions. Figure 1 , Figure 2 (not shown in the diagram) and the second gate electrode 29 (in Figure 1 , Figure 2 (Not shown in the figure) The area partially exposed on the surface of semiconductor device 1, the so-called terminal portion.

[0058] The materials constituting the first gate electrode 19 and the second gate electrode 29 can be the same as the materials constituting the first source electrode 11 and the second source electrode 21.

[0059] Regarding the thickness of each structure in the semiconductor device 1, for example, the thickness of the semiconductor layer 40 is 10-90 μm, the thickness of the metal layer 30 is 10-90 μm, and the sum of the thicknesses of the interlayer insulating layer 34 and the passivation layer 35 is 3-13 μm.

[0060] As Figure 1 and Figure 2 shown, the transistor 10 has, on the surface of the semiconductor layer 40, the first source pad 111 and the first gate pad 119 which are to be joined to the mounting substrate via the joining members at the face-down mounting. Further, the transistor 20 has, on the surface of the semiconductor layer 40, the second source pad 121 and the second gate pad 129 which are to be joined to the mounting substrate via the joining members at the face-down mounting.

[0061] As Figure 2 shown, the semiconductor layer 40 is square in the plan view.

[0062] In Figure 2 , a virtual boundary line 90 which distinguishes the first region Al and the second region A2 of the semiconductor layer 40 is shown by a broken line. The boundary line 90 of the first region Al and the second region A2 can also be understood as a virtual line along the center position of the interval between the portion 13 of the first source electrode 11 and the portion 23 of the second source electrode 21. Further, it can also be understood as the interval itself, although it is of a limited width. Even in the case of the interval, it can be recognized as a line in the naked eye or the appearance at a low magnification.

[0063] In the plan view, the boundary line 90 is a straight-line-shaped virtual line which is orthogonal to the first direction, bisects the area of the semiconductor layer 40 in the first direction, and passes through the center of the semiconductor layer 40. The center of the semiconductor layer 40 is the intersection point of the two diagonal lines of the semiconductor layer 40 in the plan view.

[0064] The first direction is a direction in which the first region Al and the second region A2 are arranged among the directions parallel to the outer periphery of the semiconductor device 1 in the plan view.

[0065] As Figure 2 shown, in the plan view, the first region Al and the second region A2 are adjacent to each other, are one and the other which bisect the area of the semiconductor layer 40, and are rectangular regions, respectively. In the plan view, there is no semiconductor layer 40 which does not correspond to either the first region Al or the second region A2.

[0066] Further, the outer periphery is a side which forms the outline of the shape, and in the case of a square like the semiconductor layer 40 or a rectangle like the first region Al, is four sides which form the respective shapes. Further, in the case of not a rectangle, is a plurality of sides which form the outer periphery of the shape.

[0067] As Figure 2As shown, in the present disclosure, in a plan view, of the 2 sides in the outer periphery of the semiconductor layer 40 that are parallel to the boundary line 90, the side of which the distance to the first gate pad 119 is shortest is set as the 1st side S1, and the other side of which the distance to the second gate pad 129 is shortest and is opposite to the 1st side S1 is set as the 2nd side S2.

[0068] Also, in the plan view, of the 2 sides in the outer periphery of the semiconductor layer 40 that are orthogonal to the boundary line 90, the side of which the distance to the first gate pad 119 is shortest is set as the 3rd side S3, and the other side of which the distance to the first source pad 111 is shortest and is opposite to the 3rd side S3 is set as the 4th side S4.

[0069] In addition, in the plan view, since the semiconductor layer 40 is a square, the length of the 1st side S1, the length of the 2nd side S2, the length of the 3rd side S3, and the length of the 4th side S4 are the same length.

[0070] The number of the first source pads 111 of the transistor 10 and the number of the second source pads 121 of the transistor 20 are respectively one as shown. Figure 2 Further, the number of the first gate pads 119 of the transistor 10 and the number of the second gate pads 129 of the transistor 20 are respectively one as shown. Figure 2

[0071] That is, the semiconductor device 1 in the present disclosure is a vertical MOS transistor of a double structure having a common drain electrode, 2 vertical MOS transistors being provided in one semiconductor device, and is a 4-pad structure semiconductor device each having one corresponding pad for the source electrode and the gate electrode of each vertical MOS transistor.

[0072] Figure 3 The shape, size, and arrangement of the pads in the plan view shown are an example, and the shape and size of the 4 pads (the first source pad 111, the first gate pad 119, the second source pad 121, and the second gate pad 129) are preferably uniform, and more preferably circular with the same diameter.

[0073] Figure 3 is a plan view schematically showing an example of the shape and arrangement of the constituent elements of the semiconductor device 1 in a plan view. Figure 2 In the plan view, in order to easily show the configuration of the upper surface of the semiconductor layer 40 which cannot actually be recognized, the passivation layer 35 and the interlayer insulating layer 34 are omitted as if they are transparent and are shown in the drawing. Each pad shown by a dotted line is shown for easy understanding of the correspondence with Figure 3 .

[0074] As shown in Figure 3 ​As shown, in the plan view, the shapes and configurations of the constituent elements in the first region A1 and the shapes and configurations of the constituent elements in the second region A2, which correspond to these constituent elements on a 1:1 basis, are arranged in a linear symmetrical relationship about the boundary line 90 as the axis of symmetry. The 1:1 corresponding constituent elements are, for example, the first gate electrode 19 and the second gate electrode 29, the first source pad 111 and the second source pad 121, and the first gate resistor element 41 and the second gate resistor element 51, which will be described later. The first control region C1 and the second control region C2, which will be described later, are similarly arranged. They are configured in a linear symmetrical relationship about the boundary line 90 as the axis of symmetry in the plan view.

[0075] like Figure 3 As shown, a first gate resistor element 41 connected to the first gate electrode 19 is formed in the first region A1 of the semiconductor device 1, and a second gate resistor element 51 connected to the second gate electrode 29 is formed in the second region A2 of the semiconductor device 1.

[0076] As a non-limiting example, the first gate resistor element 41 and the second gate resistor element 51 are made of polycrystalline silicon implanted with impurities of the first conductivity type or the second conductivity type, and each gate resistor element is made of a material with a large resistance value compared with the metal material constituting the source electrode, etc.

[0077] The first gate resistor element 41 and the second gate resistor element 51 are respectively provided to prevent damage to transistors 10 and 20 when excessive voltage is applied to the gate electrode or when surge current flows. That is, the first gate resistor element 41 and the second gate resistor element 51 are provided to improve the ESD resistance of semiconductor device 1.

[0078] In addition, such as Figure 3 As shown, in the first region A1 of the semiconductor device 1, a first gate wiring 42 is provided, which is connected to the first gate electrode 19 via a first gate resistor element 41 and surrounds the first source electrode 11. Similarly, in the second region A2 of the semiconductor device 1, a second gate wiring 52 is provided, which is connected to the second gate electrode 29 via a second gate resistor element 51 and surrounds the second source electrode 21.

[0079] As a non-limiting example, the first gate wiring 42 and the second gate wiring 52 are formed of polysilicon implanted with impurities of the first conductivity type or the second conductivity type, or of the same metal as the first gate electrode 19 and the second gate electrode 29. The first gate wiring 42 and the second gate wiring 52 are respectively connected to the first gate conductor 15 and the second gate conductor 25.

[0080] In addition, such as Figure 3As shown, in the plan view, in the first region Al, a first Zener diode 43 connected to the first source electrode 11 and the first gate electrode 19 and disposed around the periphery of the first gate electrode 19 is provided. Similarly, in the second region A2, a second Zener diode 53 connected to the second source electrode 21 and the second gate electrode 29 and disposed around the periphery of the second gate electrode 29 is provided.

[0081] The first Zener diode 43 and the second Zener diode 53 can be, as a non- limiting example, a bidirectional Zener diode having one or more PN junctions composed of polysilicon into which impurities of the first conductivity type or the second conductivity type are implanted.

[0082] The first Zener diode 43 and the second Zener diode 53 are provided to prevent the transistors 10 and 20 from being damaged when an excessive voltage is applied to the gate electrodes or the source electrodes or a surge current flows. That is, the first Zener diode 43 and the second Zener diode 53 are elements provided to improve the ESD resistance of the semiconductor device 1.

[0083] Further, Figure 14 Although not shown, in the first region Al, a first connection region in which the first Zener diode 43 is connected to the first source electrode 11 is provided, and in the second region A2, a second connection region in which the second Zener diode 53 is connected to the second source electrode 21 is provided (see Figure 3 ).

[0084] In addition, the first connection region and the second connection region are composed of the same metal as the portions 13 of the first source electrode 11 and the portions 23 of the second source electrode 21, and in the plan view, the first gate trench 17 and the second gate trench 27 are not disposed directly below them.

[0085] Further, as shown, Figure 3 in the plan view, around the periphery of the first region Al, a first EQR (Equi potential Ring) 44 electrically connected to the semiconductor substrate 32 as a common drain region can be provided. Similarly, in the plan view, around the periphery of the second region A2, a second EQR 54 electrically connected to the semiconductor substrate 32 as a common drain region can be provided. In the plan view, the first EQR 44 and the second EQR 54 can be commonized in the portion where the transistor 10 and the transistor 20 are adjacent to each other.

[0086] In addition, the portion in which the first EQR 44 and the second EQR 54 are commonized and orthogonal to the first direction can be understood as a boundary line 90.

[0087] For transistor 10, a first EQR44 is intended to prevent leakage current from flowing between the external region and the first body region 18. Furthermore, for transistor 20, a second EQR54 is intended to prevent leakage current from flowing between the external region and the second body region 28.

[0088] As a non-limiting example, the first EQR44 and the second EQR54 may be made of one or more metallic materials including aluminum, copper, gold, and silver. Furthermore, the first EQR44 and the second EQR54 may be electrically connected to the metal layer 30 via the semiconductor substrate 32, which serves as a common drain region.

[0089] like Figure 3 As shown, in the plan view, in the first region A1, the rectangular region with the largest area that contains the first gate pad 119 and does not contain the first source electrode 11 or the first gate resistor element 41 is called the first gate electrode region G1.

[0090] Similarly, as Figure 3 As shown, in the plan view, in the second region A2, the rectangular region containing the second gate pad 129 and having the largest area within the range that does not contain the second source electrode 21 or the second gate resistor element 51 is called the second gate electrode region G2.

[0091] In addition, such as Figure 3 As shown, in the plan view, in the first region A1, the rectangular region containing the first gate resistor element 41 and having the largest area in the region G1 that does not contain the first source electrode 11 or the first gate electrode is called the first resistor element region R1.

[0092] Similarly, as Figure 3 As shown, in the plan view, in the second region A2, the rectangular region containing the second gate resistor element 51 and having the largest area in the region G2 that does not contain the second source electrode 21 or the second gate electrode is called the second resistor element region R2.

[0093] In a plan view, the first gate electrode region G1 and the first resistive element region R1 are defined by the extent of each region and do not overlap. However, in a plan view, the outer perimeters of each region can also be contiguous parts of each other.

[0094] Similarly, in a plan view, the second gate electrode region G2 and the second resistive element region R2 are defined by the extent of each region and do not overlap. However, in a plan view, the outer peripheries of each region can also be contiguous parts of each other.

[0095] Furthermore, in this disclosure, in a plan view, if the outer perimeter of a certain area appears to be consistent with the outer perimeter of other areas, it can also be understood that the outer perimeters overlap or are common.

[0096] like Figure 3 As shown, in the plan view, at least one side of the outer periphery of the first gate electrode region G1 and at least one side of the outer periphery of the first resistive element region R1 coincide with a portion of the third side S3 of the semiconductor layer 40.

[0097] Similarly, as Figure 3 As shown, in a plan view, at least one side of the outer periphery of the second gate electrode region G2 and at least one side of the outer periphery of the second resistive element region R2 coincide with a portion of the third side S3 of the semiconductor layer 40.

[0098] In addition, such as Figure 3 As shown in the plan view, in the outer periphery of the first resistive element region R1, only one corner (also called the first corner P1) is included among the four corners of the outer periphery of the first gate electrode region G1, which has the shortest distance to the boundary line 90 and the shortest distance to the third side S3 of the semiconductor layer 40, and the other corners are not included.

[0099] Similarly, as Figure 3 As shown in the plan view, in the outer periphery of the second resistive element region R2, only one corner (also called the second corner P2) is included among the four corners of the outer periphery of the second gate electrode region G2, which has the shortest distance to the boundary line 90 and the shortest distance to the third side S3 of the semiconductor layer 40, and the other corners are not included.

[0100] like Figure 3 As shown, in the plan view, the region obtained by adding the first gate electrode region G1 and the first resistive element region R1 in the first region A1 is called the first control region C1. Similarly, in the plan view, the region obtained by adding the second gate electrode region G2 and the second resistive element region R2 in the second region A2 is called the second control region C2.

[0101] like Figure 3 As shown, regarding the semiconductor device 1, in a plan view, at least one side of the outer periphery of the first control region C1 and at least one side of the outer periphery of the second control region C2 are consistent with a portion of the third side S3 of the semiconductor layer 40, and the outer periphery of the first control region C1 and the outer periphery of the second control region C2 do not have a portion consistent with the fourth side S4 of the semiconductor layer 40.

[0102] In addition, such as Figure 3As shown, in the plan view, as for the length of the portion in which the outer periphery of the first control region C1 coincides with the outer periphery of the semiconductor layer 40, the length of the portion in which the outer periphery of the first control region C1 coincides with the third side S3 of the semiconductor layer 40 is the longest.

[0103] Also, as Figure 3 shown, in the plan view, as for the length of the portion in which the outer periphery of the second control region C2 coincides with the outer periphery of the semiconductor layer 40, the length of the portion in which the outer periphery of the second control region C2 coincides with the third side S3 of the semiconductor layer 40 is the longest.

[0104] In Figure 4 the plan view, an example is shown in which the outer periphery of the first control region C1 and the outer periphery of the second control region C2 respectively coincide with a portion of the first side S1 and a portion of the second side S2 of the semiconductor layer 40. However, the semiconductor device 1 of the present embodiment can also not have, in the plan view, a portion in which the outer periphery of the first control region C1 and the outer periphery of the second control region C2 respectively coincide with a portion of the first side S1 and a portion of the second side S2 of the semiconductor layer 40.

[0105] Further, in Figure 4 the plan view, an example is shown in which the outer periphery of the first control region C1 and the outer periphery of the second control region C2 respectively coincide with a portion of the boundary line 90. However, the semiconductor device 1 of the present embodiment can also not have, in the plan view, a portion in which the outer periphery of the first control region C1 and the outer periphery of the second control region C2 respectively coincide with a portion of the boundary line 90.

[0106] Figure 5A is a circuit diagram showing the equivalent circuit of the semiconductor device 1 of the present embodiment.

[0107] As Figure 5B shown, in the transistor 10, the first gate resistor element 41 and the first Zener diode 43 are connected in parallel between the first gate pad 119 and the first source pad 111.

[0108] Here, due to the function of the first Zener diode 43, in the case where an excessive voltage is applied to the first gate pad 119 or the first source pad 111 or a surge current flows, a path for flowing a current between the first gate pad 119 and the first source pad 111 via the first Zener diode 43 is turned on.

[0109] Generally, as a damage mode of the vertical MOS transistor caused by the application of an excessive voltage, the flow of a surge current, there is damage to the gate insulating film. By shunting the surge current by providing the first Zener diode 43 in the transistor 10, it is possible to reduce the load acting on the first gate insulating film 16. Thus, it is possible to prevent damage to the first gate insulating film 16, so it is possible to improve the ESD resistance of the transistor 10.

[0110] Further, by providing the first gate resistance element 41 in parallel with the first Zener diode 43, it is possible to further greatly reduce the surge current flowing through the first gate insulating film 16, so it is possible to further improve the ESD resistance of the transistor 10.

[0111] In the above description, the case where an excessive voltage is applied to the first gate pad 119 or the first source pad 111 of the transistor 10 or a surge current flows therethrough was described as an example. This is the same in the case where an excessive voltage is applied to the second gate pad 129 or the second source pad 121 of the transistor 20 or a surge current flows therethrough. By providing the second Zener diode 53 and the second gate resistance element 51 in the transistor 20, it is possible to prevent damage to the second gate insulating film 26, so it is possible to improve the ESD resistance of the transistor 20.

[0112] [2. Operation of semiconductor device]

[0113] Figure 5A and Figure 5B are a plan view and a perspective view of a substantially unit structure of the transistor 10 or the transistor 20, respectively, repeatedly formed in the X direction and the Y direction of the semiconductor device 1. In Figure 5A and Figure 5B , the semiconductor substrate 32, the metal layer 30, and the passivation layer 35 and the first source electrode 11 or the second source electrode 21, the interlayer insulating layer 34 are not illustrated for ease of understanding.

[0114] Further, the Y direction is a direction parallel to the upper surface of the semiconductor layer 40 and in which the first gate trench 17 extends. Further, the X direction refers to a direction parallel to the upper surface of the semiconductor layer 40 and orthogonal to the Y direction. The Z direction refers to a direction orthogonal to both the X direction and the Y direction and indicating the height direction of the semiconductor device 1.

[0115] As Figure 6 and Figure 6As shown, in the transistor 10, a first connecting portion 18a electrically connecting the first bulk region 18 and the first source electrode 11 is provided. The first connecting portion 18a is a region of the first bulk region 18 in which the first source region 14 is not formed, and contains the same impurities of the second conductivity type as the first bulk region 18. The first source region 14 and the first connecting portion 18a are alternately and periodically arranged along the Y direction. The same applies to the transistor 20.

[0116] In the semiconductor device 1, for example, the first conductivity type can be set to N type, the second conductivity type can be set to P type, the first source region 14, the second source region 24, the semiconductor substrate 32, and the low-concentration impurity layer 33 can be N type semiconductors, and the first bulk region 18, the first connecting portion 18a, the second bulk region 28, and the second connecting portion 28a can be P type semiconductors.

[0117] Further, in the semiconductor device 1, for example, the first conductivity type can be set to P type, the second conductivity type can be set to N type, the first source region 14, the second source region 24, the semiconductor substrate 32, and the low-concentration impurity layer 33 can be P type semiconductors, and the first bulk region 18, the first connecting portion 18a, the second bulk region 28, and the second connecting portion 28a can be N type semiconductors.

[0118] In the following description, it is assumed that the transistor 10 and the transistor 20 are so-called N channel type transistors in which the first conductivity type is set to N type and the second conductivity type is set to P type, and a bidirectional conduction path of the semiconductor device 1 is described.

[0119] In the semiconductor device 1, if a high voltage is applied to the first source electrode 11 and a low voltage is applied to the second source electrode 21, and a voltage of the threshold value or more is applied to the second gate electrode 29 (the second gate conductor 25) with the second source electrode 21 as a reference, a conduction channel is formed in the vicinity of the second gate insulating film 26 in the second bulk region 28. As a result, a current flows in a path of the first source electrode 11 - the first connecting portion 18a - the first bulk region 18 - the low-concentration impurity layer 33 - the semiconductor substrate 32 - the metal layer 30 - the semiconductor substrate 32 - the low-concentration impurity layer 33 - the conduction channel formed in the second bulk region 28 - the second source region 24 - the second source electrode 21, and the semiconductor device 1 becomes a conduction state. A PN junction exists at a contact surface between the first bulk region 18 and the low-concentration impurity layer 33 in the conduction path, and functions as a body diode.

[0120] Also, in the semiconductor device 1, if a high voltage is applied to the second source electrode 21 and a low voltage is applied to the first source electrode 11, and a voltage exceeding the threshold value is applied to the first gate electrode 19 (the first gate conductor 15) with the first source electrode 11 as a reference, a conduction channel is formed in the vicinity of the first gate insulating film 16 in the first body region 18. As a result, current flows in a path of the second source electrode 21 - the second connection portion 28a - the second body region 28 - the low-concentration impurity layer 33 - the semiconductor substrate 32 - the metal layer 30 - the semiconductor substrate 32 - the low-concentration impurity layer 33 - the conduction channel formed in the first body region 18 - the first source region 14 - the first source electrode 11, and the semiconductor device 1 becomes in an on state. A PN junction exists at a contact surface between the second body region 28 and the low-concentration impurity layer 33 in the on path, and functions as a body diode.

[0121] Further, in the semiconductor device 1, a voltage exceeding the threshold value can be applied to the first gate electrode 19 to form a conduction channel in the vicinity of the first gate insulating film 16 in the first body region 18, and a voltage exceeding the threshold value can be applied to the second gate electrode 29 to form a conduction channel in the vicinity of the second gate insulating film 26 in the second body region 28. As a result, the semiconductor device 1 can be turned on by current flowing in a path of the first source electrode 11 - the first source region 14 - the conduction channel formed in the first body region 18 - the low-concentration impurity layer 33 - the semiconductor substrate 32 - the metal layer 30 - the semiconductor substrate 32 - the low-concentration impurity layer 33 - the conduction channel formed in the second body region 28 - the second source region 24 - the second source electrode 21 or a reverse path thereof.

[0122] Figure 2 is a plan view showing an example of the shape and arrangement of the first body region 18 and the second body region 28 and the first active region 112 and the second active region 122 in the semiconductor device 1. In Figure 3 In, in order to easily understand the configuration of the upper surface of the semiconductor layer 40 which cannot actually be recognized, the passivation layer 35, the first source electrode 11, the first gate electrode 19, the second source electrode 21, the second gate electrode 29, and the interlayer insulating layer 34 are omitted as if they are transparent and illustrated. Further, the first source region 14 and the second source region 24 are also omitted. Each pad shown by a dashed line is illustrated in order to easily understand the correspondence with Figure 6 and Figure 6 are illustrated in order to easily understand the correspondence.

[0123] The first active region 112 refers to the smallest range in which the entire portion that forms an on-conduction channel when a voltage above a threshold value is applied to the first gate electrode 19 (first gate conductor 15) of the transistor 10 is contained inside. The portion that forms an on-conduction channel is the portion in which the plurality of first gate trenches 17 respectively abut the first source region 14. As shown in FIG. 1, in a plan view of the semiconductor layer 40, the first active region 112 is contained inside the first bulk region 18. Figure 3

[0124] The second active region 122 refers to the smallest range in which the entire portion that forms an on-conduction channel when a voltage above a threshold value is applied to the second gate electrode 29 (second gate conductor 25) of the transistor 20 is contained inside. The portion that forms an on-conduction channel is the portion in which the plurality of second gate trenches 27 respectively abut the second source region 24. As shown in FIG. 1, in a plan view of the semiconductor layer 40, the second active region 122 is contained inside the second bulk region 28. Figure 8

[0125] In order to reduce the on-resistance of the semiconductor device 1, it is required to secure the first active region 112 and the second active region 122 as large as possible. If the area of the first active region 112 and the area of the second active region 122 are large, the on-conduction path of the semiconductor device 1 is expanded, and thus the on-resistance of the semiconductor device 1 is reduced.

[0126] Figure 10 The first control region C1 and the second control region C2 as shown in FIG. 1 are regions in which the first active region 112 and the second active region 122 are not formed, and are regions that do not contribute to the on-conduction of the semiconductor device 1. That is, the first control region C1 and the second control region C2 are regions that are necessary for the semiconductor device 1 to function, and on the other hand, the first control region C1 and the second control region C2 are regions that are desired to be reduced as small as possible in the limited device area in order to reduce the on-resistance of the semiconductor device 1.

[0127] [3. Investigation]

[0128] The features of the semiconductor device 1 in the present disclosure described above are as follows.

[0129] ​​A semiconductor device 1 according to one aspect of the present disclosure is a flip chip mounted chip size package type semiconductor device 1 including: a semiconductor layer 40 including a semiconductor substrate 32; a first vertical MOS transistor 10 formed entirely in a first region Al of the semiconductor layer 40 on a top surface side of the semiconductor layer 40; a second vertical MOS transistor 20 formed entirely in a second region A2 adjacent to the first region Al in a plan view of the semiconductor layer 40; and a metal layer 30 formed on a bottom surface side of the semiconductor layer 40 in contact with the semiconductor substrate 32. The semiconductor substrate 32 is a common drain region of the first vertical MOS transistor 10 and the second vertical MOS transistor 20. The semiconductor layer 40 is a square in the plan view. The first region Al and the second region A2 are arranged in a first direction in the plan view. A boundary line 90 between the first region Al and the second region A2 is orthogonal to the first direction in the plan view and is a straight line that bisects the semiconductor layer 40 in area and passes through a center of the semiconductor layer 40. In the plan view, a pad included in the first region Al is only one first source pad 111 connected to a first source electrode 11 of the first vertical MOS transistor 10 and one first gate pad 119 connected to a first gate electrode 19 of the first vertical MOS transistor 10. The first vertical MOS transistor 10 includes: a first gate resistance element 41 connected to the first gate electrode 19; a first gate electrode region Gl that is a rectangular region including the first gate pad 119 inside in the plan view and is a region having the largest area in a range that does not include the first source electrode 11 or the first gate resistance element 41; and a first resistance element region Rl that is a rectangular region including the first gate resistance element 41 inside in the plan view and is a region having the largest area in a range that does not include the first source electrode 11 or the first gate electrode region Gl. In the plan view, a total length of one side of an outer periphery of the first gate electrode region Gl and a total length of one side of an outer periphery of the first resistance element region Rl coincide with a portion of a side of an outer periphery of the semiconductor layer 40 that is orthogonal to the boundary line 90 and has the shortest distance from the first gate pad 119. In the plan view, only one corner portion (first corner portion P1) of the outer periphery of the first resistance element region Rl that has the shortest distance from the boundary line 90 and the shortest distance from a side of the outer periphery of the semiconductor layer 40 that is orthogonal to the boundary line 90 is included in the outer periphery of the first resistance element region Rl.

[0130] Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 8 , Figure 10is a plan view that shows the shape and arrangement of the constituent elements of the semiconductor device 1 of the present embodiment that satisfy the above conditions.

[0131] Figure 11 Figure 12 Figure 13 Figure 14 Figure 8 Figure 7A In the drawing, the passivation layer 35 and the interlayer insulating layer 34 are omitted as if they are transparent in order to easily understand the configuration of the upper surface of the semiconductor layer 40 that cannot actually be recognized. The pads shown by the broken lines would be invisible if the passivation layer 35 is omitted, but are shown as remaining for easy understanding.

[0132] Before explaining the features and effects of the shape and arrangement of the constituent elements shown later, Figure 7B Figure 7A Figure 7A The semiconductor device 2 of Comparative Example 1 of the present embodiment will be described. As for the semiconductor device 2 of Comparative Example 1, the same reference numerals are assigned to the same constituent elements as those of the semiconductor device 1 of the present embodiment, which are considered to have been described, and detailed description thereof is omitted, and the description will be made focusing on the points of difference from the semiconductor device 1.

[0133] It has been described that the ESD resistance of the semiconductor device is improved by providing the gate resistance element in the semiconductor device, but in the plan view of the semiconductor layer, depending on the positions where the gate electrode and the gate resistance element are arranged, there is a case where, in the active region, there is a place where, although it is the active region, a contribution to conduction is low, and this will be described using the semiconductor device 2 of Comparative Example 1.

[0134] Figure 7B is a plan view that shows the shape and arrangement of the constituent elements of the semiconductor device 2 in the plan view of the semiconductor layer 40. Figure 7B In the drawing, the passivation layer 35 and the interlayer insulating layer 34 are omitted as if they are transparent in order to easily understand the configuration of the upper surface of the semiconductor layer 40 that cannot actually be recognized. The pads shown by the broken lines would be invisible if the passivation layer 35 is omitted, but are shown as remaining for easy understanding.

[0135] Figure 7A is a plan view that shows the shape and arrangement of the first body region 18 and the second body region 28 and the first active region 112 and the second active region 122 in the plan view of the constituent elements of the semiconductor device 2. Figure 7A In the drawing, the passivation layer 35 and the interlayer insulating layer 34 are omitted as if they are transparent in order to easily understand the configuration of the upper surface of the semiconductor layer 40 that cannot actually be recognized. The pads shown by the broken lines would be invisible if the passivation layer 35 is omitted, but are shown as remaining for easy understanding. Figure 3 ​​​​​​​Except for omissions in the diagram, the first source electrode 11, the first gate electrode 19, the second source electrode 21, and the second gate electrode 29 are omitted from the illustration. Furthermore, the illustrations of the first source region 14 and the second source region 24 are also omitted.

[0136] In a plan view, the semiconductor layer 40 of the semiconductor device 2 of Comparative Example 1 has the same shape and the same area as the semiconductor layer 40 of the semiconductor device 1 of Embodiment 1.

[0137] like Figure 7A As shown in the plan view, in the first region A1 of the semiconductor device 2, a first control region C1 is formed, which combines the first gate electrode region G1 and the first resistive element region R1. Furthermore, in the second region A2, a second control region C2 is formed, which combines the second gate electrode region G2 and the second resistive element region R2. In the plan view, the areas of the first control region C1 and the second control region C2 are the same for the semiconductor device 1 of the embodiment and the semiconductor device 2 of Comparative Example 1 (see reference). Figure 7B ).

[0138] like Figure 6 As shown, in the plan view, one side of the outer periphery of the first resistive element region R1 coincides with a portion of the third side S3 of the semiconductor layer 40. However, the outer periphery of the first gate electrode region G1 does not have a portion that coincides with the outer periphery of the semiconductor layer 40. Furthermore, the outer periphery of the first resistive element region R1 does not include the first corner P1 among the four corners of the outer periphery of the first gate electrode region G1. In addition, the so-called first corner P1, as defined in the semiconductor device 1 of the embodiment, is the corner among the four corners of the outer periphery of the first gate electrode region G1 in the plan view that has the shortest distance to the boundary line 90 and the shortest distance to the side of the outer periphery of the semiconductor layer 40 that is orthogonal to the boundary line 90.

[0139] Similarly, in the plan view, one side of the outer periphery of the second resistive element region R2 coincides with a portion of the third side S3 of the semiconductor layer 40. However, the outer periphery of the second gate electrode region G2 does not have a portion that coincides with the outer periphery of the semiconductor layer 40. Furthermore, the outer periphery of the second resistive element region R2 does not include the second corner P2 among the four corners of the outer periphery of the second gate electrode region G2. In addition, the so-called second corner P2, as defined in the semiconductor device 1 of the embodiment, is the corner among the four corners of the outer periphery of the second gate electrode region G2 in the plan view that has the shortest distance to the boundary line 90 and the shortest distance to the side of the outer periphery of the semiconductor layer 40 that is orthogonal to the boundary line 90.

[0140] Figure 7BThe areas of the first active region 112 and the second active region 122 in the plan view of the semiconductor device 2 shown are the same as the areas of the first active region 112 and the second active region 122 in the plan view of the semiconductor device 1 of the embodiment (see reference). Figure 7B ).

[0141] However, as Figure 3 As shown in the plan view, in the first active region 112 of the semiconductor device 2, a relatively narrow region is formed in the region between the first gate electrode region G1 and the boundary line 90, or in the region between the first gate electrode region G1 and the first side S1 of the semiconductor layer 40. This relatively narrow region between the first gate electrode region G1 and the boundary line 90, or between the first gate electrode region G1 and the first side S1 of the semiconductor layer 40, is referred to as the first narrow (narrow path) region N1.

[0142] Similarly, in a plan view, in the second active region 122 of the semiconductor device 2, a relatively narrow region is formed in the region between the second gate electrode region G2 and the boundary line 90, or in the region between the second gate electrode region G2 and the second side S2 of the semiconductor layer 40. This relatively narrow region between the second gate electrode region G2 and the boundary line 90, or between the second gate electrode region G2 and the second side S2 of the semiconductor layer 40, is referred to as the second narrow (narrow path) region N2.

[0143] In addition, such as Figure 8 As shown in the plan view, in the first active region 112 of the semiconductor device 2, there is a region that cannot be reached without passing through the first narrow region N1. This is referred to as the first non-path (dead-end) region D1.

[0144] Similarly, in a plan view, in the second active region 122 of the semiconductor device 2, viewed from the second source pad 121, there is a region that cannot be reached without passing through the second narrow region N2. This is referred to as the second non-path (dead-end) region D2.

[0145] When current flows into the first source pad 111, the portion of the first source electrode 11 formed near the first source pad 111 is large enough to have low on-resistance, making it an area that can be effectively utilized for conduction.

[0146] From the perspective of the first source pad 111, current cannot reach the portion of the first source electrode 11 formed in the first non-passage region D1 without passing through the first narrow region N1. However, the portion of the first source electrode 11 formed in the first narrow region N1 has a relatively high on-resistance due to its narrow width in the plan view. Therefore, current does not easily flow in the portion of the first source electrode 11 formed in the first narrow region N1, and consequently, current also does not easily reach the portion of the first source electrode 11 formed in the first non-passage region D1 in front of the first narrow region N1.

[0147] That is, although both the first narrow region N1 and the first non-circuit region D1 have mechanisms that contribute to conduction as part of the first active region 112, the current density does not increase, and they are only regions that are relatively difficult to contribute to conduction. The same applies to the second narrow region N2 and the second non-circuit region D2.

[0148] Therefore, the semiconductor device 2 of Comparative Example 1 cannot be said to be a configuration that, in a plan view, can make full and efficient use of the remaining limited area after the first control region C1 and the second control region C2 are provided, in order to reduce the on-resistance. In order to reduce the on-resistance, it is preferable to configure it to minimize the generation of the first narrow region N1 and the second narrow region N2, as well as the first non-path region D1 and the second non-path region D2, which relatively reduce the contribution to conduction.

[0149] like Figure 8 As shown, in the semiconductor device 1 of this disclosure, in a plan view, the first gate electrode region G1 and the first resistor element region R1 are respectively configured such that the entire length of one side of the outer periphery of the first gate electrode region G1 and the first resistor element region R1 is consistent with a portion of the third side S3 of the semiconductor layer 40, so that the first non-passage region D1 is not generated.

[0150] Similarly, in the semiconductor device 1 of this disclosure, in a plan view, the second gate electrode region G2 and the second resistor element region R2 are respectively configured such that the entire length of one side of the outer periphery of the second gate electrode region G2 and the second resistor element region R2 is consistent with a portion of the third side S3 of the semiconductor layer 40, so that the second non-passage region D2 is not generated.

[0151] Therefore, in semiconductor device 1, although it has the same area of ​​active region, compared with semiconductor device 2 of Comparative Example 1, it is possible to expand the area with a relatively high contribution to conduction. That is, it is a configuration that can effectively utilize the limited area of ​​semiconductor device 1 and reduce on-resistance.

[0152] Furthermore, when the semiconductor device 1 is mounted face down onto the mounting substrate, if the distance between the pads of the semiconductor device 1 is short in a plan view, the solder that bonds the semiconductor device 1 to the mounting substrate may come into contact with each other. Therefore, the distance between the pads of the semiconductor device 1 needs to be maintained at a certain level. As a non-limiting example, a certain distance is the same as the diameter of the pads of the semiconductor device 1.

[0153] Given the above reasons, such as Figure 8 As shown, in a plan view of the semiconductor layer 40, the semiconductor device 1 preferably has the first resistive element region R1 positioned between the edge of the outer periphery of the first gate electrode region G1 that has the shortest distance to the boundary line 90 and the boundary line 90. More preferably, the entire length of one side of the outer periphery of the first resistive element region R1 coincides with a portion of the edge of the outer periphery of the first gate electrode region G1 that has the shortest distance to the boundary line 90.

[0154] Similarly, preferably, the second resistive element region R2 is disposed between the side of the outer periphery of the second gate electrode region G2 that has the shortest distance from the boundary line 90 and the boundary line 90. More preferably, the entire length of one side of the outer periphery of the second resistive element region R2 coincides with a portion of the side of the outer periphery of the second gate electrode region G2 that has the shortest distance from the boundary line 90.

[0155] By configuring it in this way, the area between the first gate pad 119 and the second gate pad 129, which is provided to prevent poor installation caused by solder contact with each other, can be flexibly utilized as an area for configuring the first gate resistor element 41 and the second gate resistor element 51 without any waste.

[0156] The advantages mentioned above will be described in more detail.

[0157] exist Figure 8 In the semiconductor device 1 shown, areas with reduced area are indicated on both sides in the X direction. These are areas where the area can be appropriately reduced under the assumption of further miniaturization of the semiconductor device 1. As explained above, regarding the area between the first gate pad 119 and the second gate pad 129, a certain distance must be ensured to prevent the solder from contacting each other, and excessive reduction is not a good practice.

[0158] Therefore, in Figure 9A-9EIn the plan view, the end of the semiconductor device 1 in the X direction of the first active region 112 (or the first source electrode 11) becomes a place where the area can be easily reduced. In the plan view, the first region A1 is a strip-shaped region in the Y direction between the side with the shortest distance between the outer periphery of the first gate electrode region G1 and the first side S1 of the semiconductor layer 40 and the first side S1 of the semiconductor layer 40.

[0159] Similarly, in the plan view, the end of the semiconductor device 1 in the X direction of the second active region 122 (or the second source electrode 21) becomes a place where the area can be easily reduced. In the plan view, the second region A2 is a strip-shaped region in the Y direction between the side with the shortest distance between the outer periphery of the second gate electrode region G2 and the second side S2 of the semiconductor layer 40 and the second side S2 of the semiconductor layer 40.

[0160] Right now, Figure 9A-9E In the semiconductor device 1 of this embodiment shown, the first resistive element region R1 and the second resistive element region R2 are arranged in a manner that is sandwiched between the first gate electrode region G1 and the second gate electrode region G2, thereby meeting the requirements for reducing the area of ​​the semiconductor layer 40, i.e. miniaturization of the semiconductor device 1.

[0161] Next, use Figure 9A-9E The semiconductor devices 3 to 7 of Comparative Examples 2 to 6 of this embodiment will be described. Regarding the semiconductor devices 3 to 7 of Comparative Examples 2 to 6, for the same constituent elements as those of semiconductor device 1, it is assumed that they have been described and the same reference numerals are added to describe them in detail, and the description will focus on the differences from semiconductor device 1.

[0162] By representation Figure 9A-9E In Comparative Examples 2 to 6, in the semiconductor device 1 of this embodiment, the advantages of the outer periphery of the first resistive element region R1 and the outer periphery of the second resistive element region R2 respectively including only the first corner P1 of the outer periphery of the first gate electrode region G1 and the second corner P2 of the outer periphery of the second gate electrode region G2 will be described.

[0163] Figure 9A-9E This is a planar schematic diagram showing the shape and arrangement of the constituent elements of semiconductor devices 3 to 7 in a plan view of semiconductor layer 40. Furthermore, Figure 9AFor ease of understanding, only the first region A1 of the semiconductor layer 40 is extracted from the constituent elements of semiconductor devices 3 to 7. Therefore, only the first source electrode 11, the first source pad 111, the first gate pad 119, the first gate electrode region G1, and the first resistive element region R1 are shown, omitting other constituent elements in the illustration. Regarding the shape and arrangement of each constituent element in the second region A2 of the semiconductor layer 40 in the plan view, it can be understood that the shape and arrangement of each constituent element corresponding to it in the first region A1 at a 1:1 ratio are linearly symmetrical about the boundary line 90 as the axis of symmetry.

[0164] In the semiconductor devices 3 to 7 of Comparative Examples 2 to 6, the first region A1 of the semiconductor layer 40 has the same shape and area in plan view as the first region A1 of the semiconductor layer 40 of the semiconductor device 1 of the embodiment. Furthermore, the first gate electrode region G1, the first resistive element region R1, the first active region 112, the first source pad 111, etc., also have the same area.

[0165] like Figure 9A As shown, in the semiconductor devices 3 to 7 of Comparative Examples 2 to 6, the commonality is that the full length of one side of the outer periphery of the first gate electrode region G1 is consistent with a part of the third side S3 of the semiconductor layer 40.

[0166] Figure 8 This is a plan view of the semiconductor device 3 of Comparative Example 2. In the plan view, in the semiconductor device 3, the outer periphery of the first resistive element region R1 includes only one corner among the four corners of the outer periphery of the first gate electrode region G1, which has the shortest distance to the boundary line 90, but is not the shortest distance to the third side S3 of the semiconductor layer 40 (i.e., the shortest distance to the fourth side S4 of the semiconductor layer 40). Furthermore, in the semiconductor device 3, in the plan view, the first resistive element region R1 is disposed in the region between the first gate electrode region G1 and the boundary line 90.

[0167] Therefore, in Figure 9B In the configuration shown, a first non-path region D1 is generated in the semiconductor device 3. Therefore, it can be said that this is related to the semiconductor device 1 of the embodiment ( Figure 9C In contrast, even if the area of ​​the first active region 112 is the same, it is difficult to reduce the on-resistance configuration.

[0168] Figure 9Bis a plan view of the semiconductor device 4 of Comparative Example 3. In the plan view, in the semiconductor device 4, the outer periphery of the first resistance element region Rl includes only one of the four corners of the outer periphery of the first gate electrode region Gl, which is closest to the first side S l of the semiconductor layer 40 and is closest to the fourth side S4 of the semiconductor layer 40.

[0169] Further, Figure 9C is a plan view of the semiconductor device 5 of Comparative Example 4. In the plan view, in the semiconductor device 5, the outer periphery of the first resistance element region Rl includes only one of the four corners of the outer periphery of the first gate electrode region Gl, which is closest to the first side S l of the semiconductor layer 40 and is closest to the fourth side S4 of the semiconductor layer 40.

[0170] Further, in the semiconductor device 4 and the semiconductor device 5, in the plan view, the first resistance element region Rl is disposed in a region between the first gate electrode region Gl and the first source pad 111.

[0171] Thus, in the configuration of the semiconductor device 4 shown in Figure 8 and the configuration of the semiconductor device 5 shown in Figure 9D a region in the vicinity of the first source pad 111, which contributes relatively greatly to the on-resistance, is intentionally replaced with the first resistance element region Rl, which does not contribute to the on-resistance. Therefore, compared with the semiconductor device 1 of the embodiment ( Figure 9E ), it can be said that the configuration is not easy to reduce the on-resistance even if the area of the first active region 112 is the same.

[0172] Figure 9D is a plan view of the semiconductor device 6 of Comparative Example 5. In the plan view, in the semiconductor device 6, the outer periphery of the first resistance element region Rl includes only one of the four corners of the outer periphery of the first gate electrode region Gl, which is closest to the first side S l of the semiconductor layer 40 and is closest to the fourth side S4 of the semiconductor layer 40.

[0173] Further, Figure 9E is a plan view of the semiconductor device 7 of Comparative Example 6. In the plan view, in the semiconductor device 7, the outer periphery of the first resistance element region Rl includes only one of the four corners of the outer periphery of the first gate electrode region Gl, which is closest to the third side S3 of the semiconductor layer 40 but is not closest to the boundary line 90 (i.e., is closest to the first side S l of the semiconductor layer 40).

[0174] Further, in the semiconductor device 6 and the semiconductor device 7, in a plan view, the first resistance element region R1 is disposed in a region between the first gate electrode region G1 and the first side S1 of the semiconductor layer 40.

[0175] Thus, in Figure 8 the configuration of the semiconductor device 6 and Figure 9D the configuration of the semiconductor device 7 illustrated in FIG. 1, in a plan view, the first resistance element region R1 is disposed in a region between the first gate electrode region G1 and the first side S1 of the semiconductor layer 40. Figure 8 As described above, in the case where the area of the semiconductor layer 40 is required to be reduced (miniaturization of the semiconductor device 1), it is not possible to cope with.

[0176] Further, in Figure 3 the configuration illustrated in FIG. 1, the first non-via region D1 is generated in the semiconductor device 6. Thus, it can be said that, compared with the semiconductor device 1 of the embodiment (FIG. 1), it is a configuration in which the on-resistance is not easily reduced even if the area of the first active region 112 is the same. Figure 8

[0177] As described above, most preferably, as illustrated in Figure 8 or Figure 10 in a plan view, in the outer periphery of the first resistance element region R1, only one corner (first corner P1) of four corners of the outer periphery of the first gate electrode region G1, which is the shortest distance from the boundary line 90 and the shortest distance from the third side S3 of the semiconductor layer 40, is included.

[0178] Likewise, most preferably, in a plan view, in the outer periphery of the second resistance element region R2, only one corner (second corner P2) of four corners of the outer periphery of the second gate electrode region G2, which is the shortest distance from the boundary line 90 and the shortest distance from the third side S3 of the semiconductor layer 40, is included.

[0179] By being configured as described above, in the semiconductor device 1 of the embodiment, by having the gate resistance element, ESD resistance is ensured, and the proportion in which the active region of the limited area is maximally effectively utilized is improved, and the on-resistance can be reduced. Further, it is possible to have room to cope with the requirement for miniaturization of the semiconductor device 1.

[0180] Further, as illustrated in Figure 7A the semiconductor device 1 of the embodiment, in a plan view of the semiconductor layer 40, the transistor 10 and the transistor 20 are formed in a line-symmetrical configuration with the boundary line 90 as the axis of symmetry. Thus, there is almost no case where the electrical characteristics in bidirectional conduction and the heat dissipation between the transistor 10 and the transistor 20 are biased.

[0181] ​Therefore, in semiconductor device 1, it is preferable that transistors 10 and 20 are arranged in a linearly symmetrical configuration about the boundary line 90 as the axis of symmetry, as described above. This reduces the likelihood of electrical characteristics and heat dissipation biases arising from different current directions. For example, in lithium-ion battery packs for smartphones, tablets, etc., if a protection circuit utilizing semiconductor device 1 is constructed, then regardless of charging or discharging, there is no need to specifically address differences in the conduction direction of semiconductor device 1.

[0182] That is, in the plan view, the pads provided in the second region A2 are only one second source pad 121 connected to the second source electrode 21 of the second vertical MOS transistor 20 and one second gate pad 129 connected to the second gate electrode 29 of the second vertical MOS transistor 20. The second vertical MOS transistor 20 has a second gate resistor element 51 connected to the second gate electrode 29, a second gate electrode region G2 that is the largest rectangle in the plan view containing the second gate pad 129 and excluding both the second source electrode 21 and the second gate resistor element 51, and a second resistor element region R2 that is the largest rectangle in the plan view containing the second gate resistor element 51 and excluding both the second source electrode 21 and the second gate electrode region G2. In the plan view, the outer surface of the second gate electrode region G2... The total length of one side of the periphery of the second resistive element region R2 and the total length of one side of the outer periphery of the second resistive element region R2 are consistent with a portion of the side of the outer periphery of the semiconductor layer 40 that is orthogonal to the boundary line 90 and has the shortest distance to the second gate pad 129. In the plan view, the outer periphery of the second resistive element region R2 includes only one corner (second corner P2) among the four corners of the outer periphery of the second gate electrode region G2 that has the shortest distance to the boundary line 90 and the shortest distance to the side of the outer periphery of the semiconductor layer 40 that is orthogonal to the boundary line 90. In the plan view, it is preferable that the second source pad 121, the second gate pad 129, the second gate electrode region G2 and the second resistive element region R2 are respectively configured to be in a linear symmetric relationship with the first source pad 111, the first gate pad 119, the first gate electrode region G1 and the first resistive element region R1 about the boundary line 90 as the axis of symmetry.

[0183] It can also be like Figure 11 As shown, in a plan view of semiconductor layer 40, the full length of one side of the outer periphery of the first resistive element region R1 is configured to coincide with a portion of the boundary line 90, and the full length of one side of the outer periphery of the second resistive element region R2 is configured to coincide with a portion of the boundary line 90.

[0184] Based on the above structure, and Figure 7AThe semiconductor device 1 does not generate the first non-passing region D1 and the second non-passing region D2, and can reduce the area of the first narrow region N1 and the area of the second narrow region N2, compared with the semiconductor device 2 of Comparative Example 1. Therefore, the region contributing to the conduction of the semiconductor device 1 can be effectively enlarged, and thus the conduction resistance of the semiconductor device 1 can be reduced.

[0185] Further, as Figure 11 indicated, in a plan view of the semiconductor layer 40, the entire length of one side in the outer periphery of the first gate electrode region G1 is configured to coincide with a portion of the first side S1 in the outer periphery of the semiconductor layer 40 parallel to the boundary line 90, and the entire length of one side in the outer periphery of the second gate electrode region G2 is configured to coincide with a portion of the second side S2 in the outer periphery of the semiconductor layer 40 parallel to the boundary line 90.

[0186] According to the above-described structure, compared with Figure 10 the semiconductor device 2 of Comparative Example 1, the semiconductor device 1 does not generate the first non-passing region D1 and the second non-passing region D2, and can reduce the area of the first narrow region N1 and the area of the second narrow region N2. Therefore, the region contributing to the conduction of the semiconductor device 1 can be effectively enlarged, and thus the conduction resistance of the semiconductor device 1 can be reduced.

[0187] Further, the configuration indicated in Figure 11 is compared with the configuration indicated in Figure 11 In a plan view, in Figure 3 the first active region 112 (or the first source electrode 11) and the second active region 122 (or the second source electrode 21) are enlarged in the X-direction on the side close to the boundary line 90. Further, the first active region 112 (or the first source electrode 11) and the second active region 122 (or the second source electrode 21) occupy the entire length of the boundary line 90 in the Y-direction, except for a margin.

[0188] The opposing regions of the first region A1 and the second region A2, which are opposed across the boundary line 90, can use the entire length in the Y-direction for conduction because the current density is the highest. That is, it is preferable that the opposing regions be occupied by the first active region 112 (or the first source electrode 11) and the second active region 122 (or the second source electrode 21). In Figure 11 the configuration indicated, the entire length of the opposing regions in the Y-direction can be effectively used for conduction, and thus the effect of reducing the conduction resistance can be particularly obtained.

[0189] It is preferable that even if not the entire length along the Y direction, as long a region of the opposing region along the Y direction as possible is effectively utilized. Therefore, it is preferable that in a plan view, the outer periphery of the first source electrode 11 is longest in a portion closest to the boundary line 90. It is preferable that in a plan view, at least the length of the portion of the outer periphery of the first source electrode 11 closest to the boundary line 90 is longer than the length of the portion of the outer periphery of the first source electrode 11 closest to the first side S1 of the semiconductor layer 40.

[0190] Likewise, it is preferable that in a plan view, the outer periphery of the second source electrode 21 is longest in a portion closest to the boundary line 90. It is preferable that in a plan view, at least the length of the portion of the outer periphery of the second source electrode 21 closest to the boundary line 90 is longer than the length of the portion of the outer periphery of the second source electrode 21 closest to the second side S2 of the semiconductor layer 40.

[0191] The above-described structure can be achieved by Figure 11 or Figure 3 such a configuration. In particular, in the configuration shown in Figure 7A , in addition to providing a margin, the first source electrode 11 and the second source electrode 21 each occupy the entire length along the Y direction of the boundary line 90, so the effect of being able to reduce the on-resistance can be obtained in particular.

[0192] Further, it is also possible to configure as shown in Figure 7B , the entire length of one side of the outer periphery of the first control region C1 coincides with half of the third side S3 of the semiconductor layer 40, and the entire length of one side of the outer periphery of the second control region C2 coincides with half of the third side S3 of the semiconductor layer 40.

[0193] In other words, the above-described structure is that the length of the portion of the outer periphery of the first control region C1 coinciding with a portion of the third side S3 of the semiconductor layer 40 and the length of the portion of the outer periphery of the second control region C2 coinciding with a portion of the third side S3 of the semiconductor layer 40 are the same as the length of one side of the outer periphery of the semiconductor layer 40 (the length of the third side S3).

[0194] Further, in a plan view, with respect to the length of the portion of the outer periphery of the first control region C1 coinciding with the outer periphery of the semiconductor layer 40, the length of the portion of the outer periphery of the first control region C1 coinciding with the third side S3 of the semiconductor layer 40 is the longest, and with respect to the length of the portion of the outer periphery of the second control region C2 coinciding with the outer periphery of the semiconductor layer 40, the length of the portion of the outer periphery of the second control region C2 coinciding with the third side S3 of the semiconductor layer 40 is the longest.

[0195] According to the above-described structure, as compared with Figure 8 ,Figure 10 Compared to the semiconductor device 2 of Comparative Example 1, the semiconductor device 1 does not form the first non-passage region D1 and the second non-passage region D2, and, compared to... Figure 12 , Figure 13 Compared to the previous embodiment, the area of ​​the first narrow region N1 and the area of ​​the second narrow region N2 can be minimized to the greatest extent. Therefore, the region that contributes most to the conduction of the semiconductor device 1 is maximized, and the on-resistance of the semiconductor device 1 can be significantly reduced.

[0196] In addition, Figure 14 , Figure 12 , Figure 13 In the semiconductor device 1 shown, a portion of the first gate trench 17 and a portion of the second gate trench 27 are schematically represented by straight lines and circles at their ends. The straight lines represent the gate trenches, and the direction in which the straight lines extend is the direction in which the gate trenches extend. The circles at both ends are used to indicate the locations where the gate conductors embedded inside each trench are connected to the gate wiring.

[0197] In addition, Figure 13 In the semiconductor device 1 shown, in a plan view, the first gate trench 17 and the second gate trench 27 extend in a direction orthogonal to the boundary line 90. In this case, the first gate wiring 42 and the second gate wiring 52 can be configured to surround the first source electrode 11 and the second source electrode 21 respectively, except for the portion closest to the fourth side S4 of the semiconductor layer 40.

[0198] In a plan view, to connect the first gate electrode 19 and the first gate conductor 15, a first gate wiring 42 is provided on the extension line of the first gate trench 17. Similarly, to connect the second gate electrode 29 and the second gate conductor 25, a second gate wiring 52 is provided on the extension line of the second gate trench 27. Therefore, when the first gate trench 17 and the second gate trench 27 extend in a direction orthogonal to the boundary line 90, no adverse conditions will occur even if the first gate wiring 42 and the second gate wiring 52 are not provided at the portion closest to the fourth side S4 of the semiconductor layer 40.

[0199] According to the above structure, the first gate wiring 42 and the second gate wiring 52 are not located in the part closest to the fourth side S4 of the semiconductor layer 40, which can correspondingly expand the first active region 112 and the second active region 122, thereby reducing the on-resistance of the semiconductor device 1.

[0200] exist Figure 14In the illustrated semiconductor device 1, in a plan view, the first gate trench 17 extends in a direction parallel to the boundary line 90. In this case, the first gate wiring 42 can be arranged so as to surround the first source electrode 11 except for a portion closest to the first side S1 of the semiconductor layer 40. Similarly, in ​ In the illustrated configuration, in a plan view, the second gate trench 27 extends in a direction parallel to the boundary line 90. In this case, the second gate wiring 52 can be arranged so as to surround the second source electrode 21 except for a portion closest to the second side S2 of the semiconductor layer 40.

[0201] According to the above-described structure, the first gate wiring 42 and the second gate wiring 52 are not arranged in the portion closest to the first side S1 of the semiconductor layer 40 and the portion closest to the second side S2 of the semiconductor layer 40, respectively, and accordingly the first active region 112 and the second active region 122 can be enlarged, so that the on-resistance of the semiconductor device 1 can be reduced.

[0202] Further, the semiconductor device 1 can also be arranged so as to have, in a plan view, the first connection region connecting the first Zener diode 43 and the first source electrode 11 has a portion overlapping only a side of the outer periphery of the first gate electrode region G1 in a direction in which the first gate electrode region G1 opposes the first source electrode 11 and extends in parallel to the first gate trench 17, as illustrated. ​

[0203] Similarly, it can also be arranged so as to have, in a plan view, the second connection region connecting the second Zener diode 53 and the second source electrode 21 has a portion overlapping only a side of the outer periphery of the second gate electrode region G2 in a direction in which the second gate electrode region G2 opposes the second source electrode 21 and extends in parallel to the second gate trench 27.

[0204] According to the above-described structure, in a plan view of the semiconductor layer 40, the first Zener diode 43 and the first source electrode 11 can be connected without interfering with a region in which the first gate wiring 42 and the first gate conductor 15 are connected. Similarly, the second Zener diode 53 and the second source electrode 21 can be connected without interfering with a region in which the second gate wiring 52 and the second gate conductor 25 are connected.

[0205] Accordingly, in a plan view, it is possible to prevent the area of the first active region 112 and the area of the second active region 122 from being reduced, so that the on-resistance of the semiconductor device 1 can be reduced.

[0206] ​The above describes a semiconductor device according to the embodiment of the present disclosure, but the present disclosure is not limited to the embodiment. As long as the gist of the present disclosure is not deviated from, a configuration obtained by applying various modifications conceivable by those skilled in the art to the embodiment, a configuration constructed by combining components in different embodiments and modification examples can also be included in the scope of one or more configurations of the present disclosure.

[0207] Industrial applicability

[0208] A semiconductor device provided with the vertical MOS transistor of the present application can be widely used as a device that controls the on state of a current path.

[0209] Explanation of reference numerals

[0210] 1, 2, 3, 4, 5, 6, 7 semiconductor device

[0211] 10 transistor (first vertical MOS transistor)

[0212] 11 first source electrode

[0213] 12, 13, 22, 23 portion

[0214] 14 first source region

[0215] 15 first gate conductor

[0216] 16 first gate insulating film

[0217] 17 first gate trench

[0218] 18 first body region

[0219] 18a first connection portion

[0220] 19 first gate electrode

[0221] 20 transistor (second vertical MOS transistor)

[0222] 21 second source electrode

[0223] 24 second source region

[0224] 25 second gate conductor

[0225] 26 second gate insulating film

[0226] 27 second gate trench

[0227] 28 second body region

[0228] 28a second connection portion

[0229] 29 second gate electrode

[0230] 30 metal layer

[0231] 32 semiconductor substrate

[0232] 33 low-concentration impurity layer

[0233] 34 interlayer insulating layer

[0234] 35 passivation layer

[0235] 40 semiconductor layer

[0236] 41 first gate resistor element

[0237] 42 first gate wiring

[0238] 43 first Zener diode

[0239] 44 first EQR

[0240] 51 second gate resistor element

[0241] 52 second gate wiring

[0242] 53 second Zener diode

[0243] 54 second EQR

[0244] 90 boundary line

[0245] 111 first source pad

[0246] 112 first active region

[0247] 119 first gate pad

[0248] 121 second source pad

[0249] 122 second active region

[0250] 129 second gate pad

[0251] A1 first region

[0252] A2 second region

[0253] C1 first control region

[0254] C2 second control region

[0255] G1 first gate electrode region

[0256] G2 second gate electrode region

[0257] R1 first resistor element region

[0258] R2 second resistance element region

[0259] P1 first corner

[0260] P2 second corner

[0261] N1 first narrow region

[0262] N2 second narrow region

[0263] D1 first non-via region

[0264] D2 second non-via region

[0265] S1 first side

[0266] S2 second side

[0267] S3 third side

[0268] S4 fourth side

Claims

1. A chip-size packaged semiconductor device capable of being mounted face-down, characterized in that, have: Semiconductor layer, including semiconductor substrate; The first vertical MOS transistor is integrally formed on the upper surface side of the semiconductor layer in the first region of the semiconductor layer; The second vertical MOS transistor is integrally formed in a second region adjacent to the first region in a plan view of the aforementioned semiconductor layer; and A metal layer is formed on the lower surface of the semiconductor layer and is in contact with the semiconductor substrate. The aforementioned semiconductor substrate is the common drain region of the aforementioned first vertical MOS transistor and the aforementioned second vertical MOS transistor; In the plan view above, the semiconductor layer is square; In the above plan view, the first region and the second region are arranged in the first direction; In the above plan view, the boundary line between the first region and the second region is orthogonal to the first direction, and is a straight line that divides the semiconductor layer into two equal parts in area and passes through the center of the semiconductor layer; In the above plan view, the pads provided in the first region are only one first source pad connected to the first source electrode of the first vertical MOS transistor and one first gate pad connected to the first gate electrode of the first vertical MOS transistor. The aforementioned first vertical MOS transistor has: The first gate resistor element is connected to the first gate electrode; The first gate electrode region is a rectangular region in the plan view that includes the first gate pad, and is the region with the largest area in the area that does not include the first source electrode or the first gate resistor element; and The first resistive element region is a rectangular region that includes the first gate resistive element in the above plan view, and is the region with the largest area in the range that does not include the first source electrode or the first gate electrode region. In the above plan view, the total length of one side of the outer periphery of the first gate electrode region and the total length of one side of the outer periphery of the first resistive element region coincide with a portion of the side of the outer periphery of the semiconductor layer that is orthogonal to the boundary line and has the shortest distance to the first gate pad. In the above plan view, the outer periphery of the first resistive element region includes only one of the four corners of the outer periphery of the first gate electrode region, which has the shortest distance to the boundary line and the shortest distance to the side of the outer periphery of the semiconductor layer that is orthogonal to the boundary line.

2. The semiconductor device as claimed in claim 1, characterized in that, In the above plan view, the pads provided in the second region are only one second source pad connected to the second source electrode of the second vertical MOS transistor and one second gate pad connected to the second gate electrode of the second vertical MOS transistor. The aforementioned second vertical MOS transistor has: The second gate resistor element is connected to the second gate electrode mentioned above; The second gate electrode region is a rectangular region that includes the second gate pad in the above plan view, and is the region with the largest area in the range that does not include the second source electrode or the second gate resistor element. as well as The second resistive element region is a rectangular region that includes the second gate resistive element in the above plan view, and is the region with the largest area in the range that does not include the second source electrode or the second gate electrode region. In the above plan view, the total length of one side of the outer periphery of the second gate electrode region and the total length of one side of the outer periphery of the second resistive element region coincide with a portion of the side of the outer periphery of the semiconductor layer that is orthogonal to the boundary line and has the shortest distance to the second gate pad. In the above plan view, the outer periphery of the second resistive element region includes only one of the four corners of the outer periphery of the second gate electrode region, which has the shortest distance to the boundary line and the shortest distance to the side of the outer periphery of the semiconductor layer that is orthogonal to the boundary line. In the above plan view, the second source pad, the second gate pad, the second gate electrode region, and the second resistor element region are configured to be linearly symmetrical with respect to the first source pad, the first gate pad, the first gate electrode region, and the first resistor element region, respectively, with the boundary line as the axis of symmetry.

3. The semiconductor device as claimed in claim 2, characterized in that, In the above plan view, the full length of one side of the outer periphery of the first resistive element region coincides with a portion of the boundary line.

4. The semiconductor device as claimed in claim 2, characterized in that, In the above plan view, the full length of one side of the outer periphery of the first gate electrode region coincides with a portion of the side of the outer periphery of the semiconductor layer that is parallel to the boundary line.

5. The semiconductor device as claimed in claim 3 or 4, characterized in that, In the above plan view, the first gate electrode region and the first resistor element region are combined to form the first control region; In the above plan view, among the two sides parallel to the boundary line in the outer periphery of the semiconductor layer, the side with the shortest distance to the first gate pad is designated as the first side, and the other side opposite to the first side is designated as the second side. In the above plan view, among the two sides of the outer periphery of the semiconductor layer that are orthogonal to the boundary line, the side with the shortest distance to the first gate pad is designated as the third side, and the other side opposite to the third side is designated as the fourth side. In the above plan view, the length of the portion of the outer periphery of the first control area that coincides with the third side is half the length of the third side; In the above plan view, the portion of the outer periphery of the first control region that coincides with the outer periphery of the semiconductor layer has the longest length.

6. The semiconductor device as claimed in claim 4, characterized in that, In the above plan view, the outer periphery of the first source electrode is the longest in the part closest to the boundary line.

7. The semiconductor device as claimed in claim 5, characterized in that, In the above plan view, in the first region, a first gate trench and a first gate wiring connected to the first gate electrode are formed at a depth from the upper surface of the semiconductor layer to a portion of the semiconductor layer. In the above plan view, the first gate trench extends in a direction orthogonal to the boundary line; In the above plan view, the first gate wiring is configured to surround the first source electrode except for the portion closest to the fourth side.

8. The semiconductor device as claimed in claim 5, characterized in that, In the above plan view, in the first region, a first gate trench and a first gate wiring connected to the first gate electrode are formed at a depth from the upper surface of the semiconductor layer to a portion of the semiconductor layer. In the above plan view, the first gate trench extends in a direction parallel to the boundary line. In the above plan view, the first gate wiring is configured to surround the first source electrode except for the portion closest to the first side.

9. The semiconductor device as claimed in claim 5, characterized in that, In the above plan view, in the first region, a first gate trench is formed at a depth from the upper surface of the semiconductor layer to a portion of the semiconductor layer, and a first Zener diode is connected to the first gate electrode and the first source electrode. In the above plan view, the first connection region connecting the first Zener diode and the first source electrode overlaps only with the edge of the outer periphery of the first gate electrode region that is opposite to the first source electrode and extends parallel to the direction of the first gate trench.

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