Comprehensive energy management circuit of charging integrated system

Abstract

The invention belongs to the technical field of charging management, and particularly relates to a comprehensive energy management circuit of a charging integrated system. The invention provides a hardware foundation of an integrated energy management circuit of a charging integrated system. The system comprises a charging power supply and communication part, an electric vehicle communication part, a communication ID setting part, a full-bridge driving part, an input voltage detection part, a power supply part, a relay driving part, an ADC conversion part and a master control FPGA part. The system is characterized in that an information transmission port of the master control FPGA part is respectively connected with an information transmission port of the charging power supply and communication part, an information transmission port of the electric vehicle communication part, an information transmission port of the communication ID setting part and an information transmission port of the full-bridge driving part; through combined control of the charging piles and flexible power distribution, the problem that in the prior art, the use condition of the charging piles can only be met by increasing the number of the charging piles is insufficient is solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of charging management, and in particular relates to a comprehensive energy management circuit of an integrated charging system. Background Art

[0002] During the peak period of electric vehicle charging, the use of charging piles is tight. If the number of charging piles is simply increased, the cost and floor space will increase significantly, and the power requirements for inbound power will also increase significantly. In addition, the existing electric vehicle charging stations do not have the function of working together between the charging piles, so the flexibility of use needs to be further improved.

[0003] In the prior art, for example, Chinese invention patent publication number CN114784837A discloses a charging station energy management system and a management method thereof, wherein the energy management system includes an AC-DC module, a DC bus, a DC-DC module, and a controller connected in sequence, wherein the output end of the DC-DC module is connected to the charging vehicle, and also includes an energy storage device, and the controller controls whether the energy storage device charges the charging vehicle according to the output power requirement of the DC-DC module and the distribution power of the AC-DC module; this patent can reduce the infrastructure construction of the DC bus of the charging station, greatly reduce the construction cost of the charging station, realize rapid overcharging of electric vehicles, reasonably utilize peak, flat and valley electricity prices, and avoid waste of resources caused by excess power design margin of the charging station. For example, a utility model with announcement number CN220457128U discloses a power management controller for an electric vehicle charging pile, including a main control board, a civil power end, an industrial power end, a charging output end, a tram power supply end, a power output end, and an intelligent switch controlled by the main control board, wherein the intelligent switch has three control bits, namely a first control bit, a second control bit, and a third control bit; the civil power end connected to the civil power grid and the power output end form a first line through a wire through the first control bit, and the power output end is connected to a local power grid outside the local power grid to output power to the local power grid.

[0004] If the charging piles do not have the function of working together, the following situations will occur: The utilization rate of charging power is low. Electric vehicle charging is not continuous maximum power charging. Some electric vehicles require 20KW charging, and some electric vehicles require 60WK charging. The charging power is also related to the temperature. The lower the temperature, the lower the maximum power. Therefore, the maximum power of the charging pile cannot be 100% utilized.

[0005] Table 1 is an example of the power and time percentage used in each stage of charging an electric vehicle battery from 0% to 100%: Charging stage Power range Power ratio (%) Time proportion (%) 0%-20% 0%-20% 70% 10% 20%-50% 20%-50% 50% 20% 50%-80% 50%-80% 30% 30% 80%-100% 80%-100% 20% 40% Table 1 0%-20% stage: At the beginning of charging, the battery receives a higher power (70%). Because the battery can be charged quickly, this stage accounts for 10% of the total charging time.

[0006] 20%-50% stage: Charging power is reduced to 50%, and the charging time accounts for 20%.

[0007] 50%-80% stage: Charging power is further reduced to 30%, and the time consumed accounts for 30%.

[0008] 80%-100% stage: The final charging stage, with the lowest power at 20% and taking 40% of the time.

[0009] The above charging power and total charging time are at an ideal temperature of 25 degrees Celsius. In low temperature conditions, the lower the temperature, the smaller the maximum power value and the longer the charging time. This causes a great waste of efficiency for conventional charging piles, because the conventional charging power source monomer is 120KW or 60KW, and the power cannot be maximized when the charging power is low. Summary of the invention

[0010] The present invention is aimed at the above-mentioned problems and provides a hardware foundation of a comprehensive energy management circuit of an integrated charging system.

[0011] To achieve the above-mentioned purpose, the present invention adopts the following technical scheme, which includes a charging power supply and communication part, an electric vehicle communication part, a communication ID setting part, a full-bridge driving part, an input voltage detection part, a power supply part, a relay driving part, an ADC conversion part and a main control FPGA part, characterized in that the information transmission port of the main control FPGA part is respectively connected with the information transmission port of the charging power supply and communication part, the information transmission port of the electric vehicle communication part, the information transmission port of the communication ID setting part, the information transmission port of the full-bridge driving part, the information transmission port of the input voltage detection part, the information transmission port of the relay driving part, and the information transmission port of the ADC conversion part; The power output port of the power supply part is respectively connected to the power port of the charging power supply and communication part, the power port of the electric vehicle communication part, the power port of the communication ID setting part, the power port of the full-bridge drive part, the power port of the input voltage detection part, the power port of the relay drive part, the power port of the ADC conversion part, and the power port of the main control FPGA part; The driving signal output port of the full-bridge driving part is connected to the driving signal input port of the charging power supply and the communication part; The detection signal input port of the input voltage detection part is connected to the detection signal output port of the charging power supply and the communication part; The driving signal output port of the relay driving part is connected to the relay driving signal input port of the charging power supply and the communication part; The signal input port of the ADC conversion part is connected to the output voltage and current acquisition signal output port of the charging power supply and communication part and the switch tube working current acquisition signal output port.

[0012] As a preferred solution, the charging power supply and communication part of the present invention includes a YK818C relay K100, the control end of K100 is connected to U2-OB and U2-OA respectively, and the 1st, 3rd, 4th and 6th pins of the SH8023 chip U2 are connected to U2-OB, P30, U2-OA and P28 respectively; VIN+1 is connected to the 1st pin of the common mode inductor U4, VIN-1 is connected to the 3rd pin of U4, the 2nd pin of U4 is connected to one end of the K100 controlled switch and one end of the resistor R9 respectively, the other end of R9 is connected to the other end of the K100 controlled switch and VBUS respectively, the 4th pin of U4 is connected to GND-P and the 1st pin of the HSTS08L module U46 respectively; The gate of IXFN50N120SiC tube Q1 is connected to A-PWM through resistor R11, the drain of Q1 is connected to VBUS, and the source of Q1 is connected to the first terminal of the primary side of transformer T1; The gate of IXFN50N120SiC tube Q2 is connected to A-PWM through resistor R12, the drain of Q2 is connected to VBUS, and the source of Q2 is connected to the first terminal of the primary side of transformer T1; The gate of IXFN50N120SiC tube Q5 is connected to B-PWM through resistor R22, the drain of Q5 is connected to the first terminal of the primary side of transformer T1, and the source of Q5 is connected to pin 2 of U46; The gate of IXFN50N120SiC tube Q6 is connected to B-PWM through resistor R23, the drain of Q6 is connected to the first terminal of the primary side of transformer T1, and the source of Q6 is connected to pin 2 of U46; The gate of IXFN50N120SiC tube Q3 is connected to C-PWM through resistor R13, the drain of Q3 is connected to VBUS, and the source of Q3 is connected to the second terminal of the primary side of transformer T1; The gate of IXFN50N120SiC tube Q4 is connected to C-PWM through resistor R14, the drain of Q4 is connected to VBUS, and the source of Q4 is connected to the second terminal of the primary side of transformer T1; The gate of IXFN50N120SiC tube Q7 is connected to D-PWM through resistor R24, the drain of Q7 is connected to the second terminal of the primary side of transformer T1, and the source of Q7 is connected to pin 2 of U46; The gate of IXFN50N120SiC tube Q8 is connected to D-PWM through resistor R25, the drain of Q8 is connected to the second terminal of the primary side of transformer T1, and the source of Q8 is connected to pin 2 of U46; The sources of Q1 to Q8 are connected to AS, AS, CS, CS, BS, BS, DS, and DS respectively; The OUT port of U46 is connected to the 3rd pin of LMP7731MF chip U6 through inductor L1, inductor L2, resistor R35 and resistor R36 in sequence, and the 1st and 4th pins of U6 are connected to AD-0; One end of the first secondary side T1B of T1 is connected to VOUT and the controlled switches of relays K101 to K106 through diode BD1 and inductor L15 respectively, and the other end of T1B is connected to pin 1 of HSTS08L module U45; One end of the second secondary side T1C of T1 is connected to the inductor L15 through the diode BD2, and the other end of T1C is connected to the pin 1 of U45; The OUT port of U45 is connected to the 3rd pin of LMP7731MF chip U5 through resistors R32 and R33, and the 1st and 4th pins of U5 are connected to AD-1; Pin 1 of HBV-A3.3 module VP1 is connected to VOUT through resistor R34, pin 2 of VP1 is connected to GOUT through resistor R37, pin 4 of VP1 is connected to pin 3 of LMP7731MF chip U7 through resistor R38, and pins 1 and 4 of U7 are connected to AD-2; Pins 1 and 4 of the CAN / TJA1050T / CM chip U8 are connected to P10 and P7 respectively, pin 7 of U8 is connected to pin 2 of the connector CH1 through inductor L3, and pin 6 of U8 is connected to pin 1 of CH1 through inductor L4.

[0013] As another preferred solution, the electric vehicle communication part of the present invention includes a CAN / TJA1050T / CM chip U10, wherein the 1st and 4th pins of U10 are respectively connected to TXD and RXD, and the 7th pin of U10 is connected to the 3rd pin of the ACT45B-510-2P-TL003 common mode filter L7, and the 2nd pin of L7 is respectively connected to the 2nd pin of the connector P1 and one end of the inductor L5 through the fuse F1, and the other end of L5 is connected to the 2nd pin of the connector CH3; Pin 6 of U10 is connected to pin 4 of L7, and pin 1 of L7 is connected to one end of resistor R43 and one end of inductor L8 through fuse F2. The other end of L8 is connected to pin 2 of connector CH3, and the other end of R43 is connected to pin 1 of P1. The 1~4 pins of the B0505S-1W module U11 are connected to GND, +5V, +5V2, and GND2 respectively; The 2, 3, 6, and 7 pins of the ADUM1201CRZ chip U12 are connected to P85, P86, RXD, and TXD respectively.

[0014] As another preferred solution, the communication ID setting part of the present invention adopts a dip switch U9, pins 5 to 8 of U9 are respectively connected to P72, P71, P69, and P11, pins 1 to 4 of U9 are respectively connected to one end of resistors R39 to R42, and the other end of R39 to R42 is connected to +3.3V.

[0015] As another preferred solution, the full-bridge driving part of the present invention adopts the BTD3011 chip U40, the IN+ port of U40 is connected to CHA1 through R45 and R44 in sequence, the OUTL port of U40 is connected to A-PWM, the VISO port of U40 is connected to VCCA, the OUTH port of U40 is connected to A-PWM, and the VEE port of U40 is connected to AS.

[0016] As another preferred solution, the input voltage detection part of the present invention includes an LM224D chip U20, wherein the 5th pin of U20 is respectively connected to one end of a resistor R71 and one end of a resistor R78, the other end of R71 is connected to VBUS, the other end of R78 is connected to GND-P, and the 6th pin of U20 is respectively connected to one end of the resistor R70 and the cathode of a voltage regulator tube D31, the anode of D31 is connected to GND-P, and the other end of R70 is connected to VBUS; Pin 7 of U20 is connected to the anode of the OP1 input terminal of the EL357 chip, and the cathode of the OP1 input terminal is connected to GND-P through resistor R80 and light-emitting diode E1 in sequence; the emitter of the OP1 output terminal is connected to P110.

[0017] As another preferred solution, the power supply part of the present invention includes an LM1085-3.3 module U24, pin 3 of U24 is connected to +5V, and pin 2 of U24 is connected to +3.3V; The Vout port of the AMS1117-1.2 module U28 is connected to +3.3V, and the Vin port of U28 is connected to +1.2V; Pin 1 of LM2576-5.0 module U18 is connected to +24V, and pin 2 of U18 is connected to pin 4 of U18 and +5V respectively through inductor L6; Pin 1 of UC1844 module U19 is connected to FB, pin 4 of U19 is connected to RT / CT, pin 5 of U19 is connected to the gate of 12N170K5 tube Q1 through resistor R75, source of Q1 is connected to GND-P through resistor R81, drain of Q1 is connected to one end of the primary side of transformer T2, and the other end of the primary side of T2 is connected to VBUS; pin 7 of U19 is connected to one end of the secondary side T2B of T2 through resistor R66 and diode D27 in sequence, and the other end of T2B is connected to GND-P; One end of the secondary side T2C of T2 is connected to +24V through diode D23 and inductor L10, and the other end of T2C is connected to GND; One end of the secondary side T2D of T2 is connected to the 1st pin of the K7815M-1000R3 module U15 through the diode D25 and the inductor L11, the 3rd pin of U15 is connected to +15VP, and the other end of T2D is connected to GND-P; One end of the secondary side T2E of T2 is connected to VCCA through diode D28 and inductor L12, and the other end of T2E is connected to GNDA; One end of the secondary side T2F of T2 is connected to VCCB through diode D30 and inductor L13, and the other end of T2F is connected to GNDB; One end of the secondary side T2G of T2 is connected to VCCC through diode D32 and inductor L14, and the other end of T2G is connected to GNDC; One end of the secondary side T2H of T2 is connected to VCCD through diode D33 and inductor L16, and the other end of T2H is connected to GNDD; Pin 4 of PC817 chip U33 is connected to FB, pin 3 of U33 is connected to GND-P, pin 1 of U33 is connected to VCCD through resistor R89, pin 2 of U33 is connected to pin 2 of TL431 chip U35, pin 3 of U35 is connected to GNDD, pin 1 of U35 is respectively connected to one end of resistor R93 and one end of resistor R95, the other end of R95 is connected to GNDD, and the other end of R93 is connected to VCCD through resistor R90.

[0018] As another preferred solution, the relay driving part of the present invention adopts SH8023 chip U13, and the 1st, 3rd, 4th and 6th pins of U13 are respectively connected to U13-OB, P32, U13-OA and P31, and the control terminals of YK818C relay K101 are connected to U13-OB and U13-OA.

[0019] Secondly, the ADC conversion part of the present invention adopts AD7788 chip U22, and pins 1, 2, 3, 9, and 10 of U22 are respectively connected to P119, P113, AD-2, P121, and P120; Pin 4 of the LT1790 module U32 is connected to +3.3V through resistor R94 and magnetic bead L9, and pin 6 of U32 is connected to +2.5V2.

[0020] In addition, the main control FPGA part of the present invention adopts the EP4CE15E22I7 chip U1, and the 28, 30, 31, 32, and 33 pins of U1 are respectively connected to P28, P30, P31, P32, and P33; Pins 1, 2, 5, and 6 of the EPCS4SI8N chip U3 are connected to FPGA-nCSO, FPGA-DATA0, FPGA-ASDO, and FPGA-DCLK respectively; Pins 58-61, 64-69, 71, and 72 of U1 are connected to P58-P61, P64-P69, P71, and P72 respectively; Pin 13 of U1 is connected to FPGA-DATA0 through resistor R31, and pins 11, 10, 8, 7, and 6 of U1 are connected to P11, P10, FPGA-nCSO, P7, and FPGA-ASDO respectively; Pins 76, 77, 80, 83, 85, and 86 of U1 are connected to CHA1, CHA4, P85, and P86 respectively; Pins 110~115 and 119~121 of U1 are connected to P110~P115 and P119~P121 respectively.

[0021] Beneficial effects of the present invention: The charging power supply and communication part of the present invention can communicate between various DC-DC high-power charging piles (i.e. charging piles), and can jointly control various charging piles and flexibly distribute power.

[0022] The switch tube control signal of the main control FPGA part of the present invention controls the switch tubes of the charging power supply and the communication part after passing through the full-bridge driving part.

[0023] The main control FPGA part of the present invention communicates with the controller of the charged electric vehicle through the electric vehicle communication part to obtain the charging information of the electric vehicle.

[0024] The communication ID setting part of the present invention sets the ID of each charging pile to distinguish each charging pile.

[0025] The input voltage detection part of the present invention is used to detect the input voltage value of the charging power supply and the communication part.

[0026] The power supply part of the present invention provides appropriate power supply voltage for each part of the system.

[0027] The main control FPGA part of the present invention controls the state of the power output of the charging power supply and the communication part through the relay driving part.

[0028] The ADC conversion part of the present invention converts the detected analog detection value into a digital value and sends it to the main control FPGA part.

[0029] From the above, it can be seen that the present invention solves the problem in the prior art that the tight usage of charging piles can only be met by increasing the number of charging piles, and the problems of no mutual coordination between the charging piles, poor flexibility and low charging power utilization rate through joint control of the charging piles and flexible power allocation. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The present invention is further described below in conjunction with the accompanying drawings and specific implementation methods. The protection scope of the present invention is not limited to the following description.

[0031] Figure 1 to Figure 4 It is a schematic diagram of the charging power supply and communication circuit of the present invention.

[0032] Figure 5 It is a circuit schematic diagram of the communication part of the electric vehicle of the present invention.

[0033] Figure 6 It is a circuit schematic diagram of the communication ID setting part of the present invention.

[0034] Figure 7 It is a circuit schematic diagram of the full-bridge driving part of the present invention.

[0035] Figure 8 It is a circuit schematic diagram of the input voltage detection part of the present invention.

[0036] Figures 9 to 12 It is a circuit schematic diagram of the power supply part of the present invention.

[0037] Fig.13 It is the circuit principle diagram of the relay driving part of the present invention.

[0038] Fig.14 It is a schematic diagram of the circuit principle of the ADC conversion part of the present invention.

[0039] Figure 15 to Figure 17 It is a schematic diagram of the main control FPGA circuit of the present invention.

[0040] Fig.18 It is a connection circuit diagram of multiple charging piles of the present invention. DETAILED DESCRIPTION

[0041] The present invention comprises a charging power supply and communication part, an electric vehicle communication part, a communication ID setting part, a full-bridge driving part, an input voltage detection part, a power supply part, a relay driving part, an ADC conversion part and a main control FPGA part, wherein the information transmission port of the main control FPGA part is respectively connected with the information transmission port of the charging power supply and communication part, the information transmission port of the electric vehicle communication part, the information transmission port of the communication ID setting part, the information transmission port of the full-bridge driving part, the information transmission port of the input voltage detection part, the information transmission port of the relay driving part and the information transmission port of the ADC conversion part; The power output port of the power supply part is respectively connected to the power port of the charging power supply and communication part, the power port of the electric vehicle communication part, the power port of the communication ID setting part, the power port of the full-bridge drive part, the power port of the input voltage detection part, the power port of the relay drive part, the power port of the ADC conversion part, and the power port of the main control FPGA part; The driving signal output port of the full-bridge driving part is connected to the driving signal input port of the charging power supply and the communication part; The detection signal input port of the input voltage detection part is connected to the detection signal output port of the charging power supply and the communication part; The driving signal output port of the relay driving part is connected to the relay driving signal input port of the charging power supply and the communication part; The signal input port of the ADC conversion part is connected to the output voltage and current acquisition signal output port of the charging power supply and communication part and the switch tube working current acquisition signal output port.

[0042] The charging power supply and communication part includes a YK818C relay K100, the control end of K100 is connected to U2-OB and U2-OA respectively, and the 1st, 3rd, 4th and 6th pins of the SH8023 chip U2 are connected to U2-OB, P30, U2-OA and P28 respectively; VIN+1 is connected to the 1st pin of the common mode inductor U4, VIN-1 is connected to the 3rd pin of U4, the 2nd pin of U4 is connected to one end of the K100 controlled switch and one end of the resistor R9 respectively, the other end of R9 is connected to the other end of the K100 controlled switch and VBUS respectively, the 4th pin of U4 is connected to GND-P and the 1st pin of the HSTS08L module U46 respectively; The gate of IXFN50N120SiC tube Q1 is connected to A-PWM through resistor R11, the drain of Q1 is connected to VBUS, and the source of Q1 is connected to the first terminal of the primary side of transformer T1; The gate of IXFN50N120SiC tube Q2 is connected to A-PWM through resistor R12, the drain of Q2 is connected to VBUS, and the source of Q2 is connected to the first terminal of the primary side of transformer T1; The gate of IXFN50N120SiC tube Q5 is connected to B-PWM through resistor R22, the drain of Q5 is connected to the first terminal of the primary side of transformer T1, and the source of Q5 is connected to pin 2 of U46; The gate of IXFN50N120SiC tube Q6 is connected to B-PWM through resistor R23, the drain of Q6 is connected to the first terminal of the primary side of transformer T1, and the source of Q6 is connected to pin 2 of U46; The gate of IXFN50N120SiC tube Q3 is connected to C-PWM through resistor R13, the drain of Q3 is connected to VBUS, and the source of Q3 is connected to the second terminal of the primary side of transformer T1; The gate of IXFN50N120SiC tube Q4 is connected to C-PWM through resistor R14, the drain of Q4 is connected to VBUS, and the source of Q4 is connected to the second terminal of the primary side of transformer T1; The gate of IXFN50N120SiC tube Q7 is connected to D-PWM through resistor R24, the drain of Q7 is connected to the second terminal of the primary side of transformer T1, and the source of Q7 is connected to pin 2 of U46; The gate of IXFN50N120SiC tube Q8 is connected to D-PWM through resistor R25, the drain of Q8 is connected to the second terminal of the primary side of transformer T1, and the source of Q8 is connected to pin 2 of U46; The sources of Q1 to Q8 are connected to AS, AS, CS, CS, BS, BS, DS, and DS respectively; The OUT port of U46 is connected to the 3rd pin of LMP7731MF chip U6 through inductor L1, inductor L2, resistor R35 and resistor R36 in sequence, and the 1st and 4th pins of U6 are connected to AD-0; One end of the first secondary side T1B of T1 is connected to VOUT and the controlled switches of relays K101 to K106 through diode BD1 and inductor L15 respectively, and the other end of T1B is connected to pin 1 of HSTS08L module U45; One end of the second secondary side T1C of T1 is connected to the inductor L15 through the diode BD2, and the other end of T1C is connected to the pin 1 of U45; The OUT port of U45 is connected to the 3rd pin of LMP7731MF chip U5 through resistors R32 and R33, and the 1st and 4th pins of U5 are connected to AD-1; Pin 1 of HBV-A3.3 module VP1 is connected to VOUT through resistor R34, pin 2 of VP1 is connected to GOUT through resistor R37, pin 4 of VP1 is connected to pin 3 of LMP7731MF chip U7 through resistor R38, and pins 1 and 4 of U7 are connected to AD-2; Pins 1 and 4 of the CAN / TJA1050T / CM chip U8 are connected to P10 and P7 respectively, pin 7 of U8 is connected to pin 2 of the connector CH1 through inductor L3, and pin 6 of U8 is connected to pin 1 of CH1 through inductor L4.

[0043] like Figure 3 As shown, R38 and C46 form a Hz level low-pass filter, R38 uses 27R, and C46 uses 0.1uF50V, which greatly improves the suppression of high-frequency interference.

[0044] Figure 1 to Figure 17 It is just a circuit diagram of a DC-DC high-power charging pile (charging pile). CH1 is used to communicate with other charging piles, query the idle information on the CAN bus, which charging pile is in the idle state, and request to be connected in parallel with this charging pile to charge the electric vehicle. When the charging power of this charging pile is sufficient, disconnect other charging piles in parallel with this charging pile.

[0045] VIN+ is connected to 750VDC.

[0046] Q1~Q8 form an H-bridge topology structure, using two switching tubes in parallel (for example, Q1 and Q2 in parallel, A-PWM controls Q1 and Q2 at the same time) to increase the current and avoid the situation where the rated current of one switching tube is not enough.

[0047] Q1~Q8 use IXFN50N120SiC tubes. IXFN50N120SiC tubes are silicon carbide MOS tubes with low heat generation and high efficiency.

[0048] Q1 and Q2 are turned on and off at the same time; Q7 and Q8 are turned on and off at the same time; Q5 and Q6 are turned on and off at the same time; Q3 and Q4 are turned on and off at the same time; forming a full-bridge topology. When Q1, Q2 and Q7, Q8 are turned on, the current of the primary side T1A of the transformer flows forward. When Q5, Q6 and Q3, Q4 are turned on, the current flows through T1A in the reverse direction, forming an alternating magnetic flux in T1A. The secondary side T1B and T1C of the transformer generate secondary power due to the induced electromotive force, providing power to the secondary side load.

[0049] R9 and K100 controlled switch (K100A) form a surge discharge circuit. When the voltage between VBUS and GND-P is lower than 500V (the voltage between VBUS and GND-P is detected by the circuit composed of R84, R83, R86, D34, U20, and OP2), K100A is disconnected; when the circuit voltage is higher than 500V, K100A is closed to reduce the current impact of the charging of the rear-end energy storage capacitor on the front-end.

[0050] like Figure 2 As shown, there are filter capacitors C11, C12, C20, and C21 with large capacitance at the input end of the circuit. When the circuit is connected to the power supply line (750V), due to the characteristics of the capacitor, the capacitor voltage quickly rises from 0V to the power supply voltage of 750V, and the initial internal resistance of the capacitor is approximately 0. At this moment, the charging current is approximately infinite, which is similar to a transient short-circuit in the power grid, which will instantly lower the grid voltage and cause interference to other equipment on the power grid. In order to reduce this interference, R9 is connected in series with the capacitor in the circuit to limit the charging current and reduce the impact on the power grid. When the capacitor charging voltage rises to 600V, K100 is controlled to conduct and short-circuit R9 to avoid energy loss on R9.

[0051] U46 is used for switch tube current detection. U6 performs overcurrent protection by collecting switch tube detection current. Anti-magnetic bias is used to prevent the positive and negative half axes of transformer T1 from being unbalanced during operation, causing unilateral saturation of the transformer and burning of the switch tube.

[0052] like Figure 2As shown, the main transformer T1 of the H-bridge topology works on the positive and negative half axes of the hysteresis loop. When Q1, Q2, Q7, and Q8 are turned on, they work in the positive half cycle; when Q3, Q4, Q5, and Q6 are turned on, they work in the secondary half cycle. The working condition without deviation is: each time a cycle of work is completed, it will return to the 0-point position of the hysteresis loop. When bias magnetization occurs, the hysteresis loop will not return to the 0-point position, but will be above or below 0-point, which will cause the current flowing through Q1, Q2, Q7, and Q8 tubes to be greater than or less than Q3, Q4, Q5, and Q6 at the same power. The currents of the switch tubes in the two situations are different. After multiple accumulation and superposition, one group of tubes will be overcurrent and burnt. When each group of switch tubes of the present invention is working, the maximum current of the group of switch tubes is detected. When it reaches 50% of the rated current, the group of switch tubes is forced to close and the other group of switch tubes is turned on. This will avoid the occurrence of bias magnetization and protect the switch tubes from burning due to bias magnetization overcurrent.

[0053] like Figure 2 As shown, L1, L2, C41-C43 form a 58KHz low-pass filter circuit, L1 and L2 use 0.45mH inductors, C41 uses a 16nF25V capacitor, C42 uses a 54nF25V capacitor, and C43 uses a 17nF25V capacitor; the two-time low-pass filter structure has a better filtering effect and ensures that the source signal is not lost. The operating frequency of the full-bridge circuit selected by the present invention is 40KHz. In order to ensure the integrity of current collection, the collection frequency is greater than the working frequency and is as low as possible.

[0054] DEBUG1 is used for debugging.

[0055] The electric vehicle communication part includes a CAN / TJA1050T / CM chip U10, wherein the 1st and 4th pins of U10 are respectively connected to TXD and RXD, and the 7th pin of U10 is connected to the 3rd pin of the ACT45B-510-2P-TL003 common mode filter L7, and the 2nd pin of L7 is respectively connected to the 2nd pin of the connector P1 and one end of the inductor L5 through the fuse F1, and the other end of L5 is connected to the 2nd pin of the connector CH3; Pin 6 of U10 is connected to pin 4 of L7, and pin 1 of L7 is connected to one end of resistor R43 and one end of inductor L8 through fuse F2. The other end of L8 is connected to pin 2 of connector CH3, and the other end of R43 is connected to pin 1 of P1. The 1~4 pins of the B0505S-1W module U11 are connected to GND, +5V, +5V2, and GND2 respectively; The 2, 3, 6, and 7 pins of the ADUM1201CRZ chip U12 are connected to P85, P86, RXD, and TXD respectively.

[0056] U12 isolates U1 from U10. Its function is that this CAN interface is connected to the charging gun (CH3 is connected to the charging gun, and conventional charging guns all have a CAN bus for communicating with electric vehicles). The charging gun is connected to the outside. When the outside is damaged or interfered with by the CAN bus, the U1 circuit will not be damaged.

[0057] When the charging gun is inserted into the electric vehicle for charging, the electric vehicle controller communicates with U10 to obtain the electric vehicle charging information. U1 adjusts the duty cycle according to the information to charge the electric vehicle. When the electric vehicle charging seat is connected to the charging gun, the electric vehicle controller communicates with the charging pile through the CAN bus, and sends the electric vehicle's current battery information, charging voltage, charging current, temperature and other data to the charging pile. The charging pile charges the electric vehicle based on this information, which is a conventional technology.

[0058] When the required power increases (the power is determined based on communication with the electric vehicle, for example, the electric vehicle will send the required charging voltage and charging current to the charging pile), U1 sends it to the bus through the internal CAN, requesting other charging piles to be connected in parallel with it.

[0059] The electric vehicle battery is charged and the charging information is sent to the requesting party. As the battery is fully charged (the charging status of the battery is known by receiving information from the electric vehicle controller through CH3), the required charging power decreases, and U1 requests to remove the requested power source through the internal CAN and break away from the parallel relationship. The above power source coordination achieves optimized charging.

[0060] like Figure 3 As shown, among Channel-1 to Channel-6, one port is connected to the charging gun, and the other five ports are used for parallel control with other charging piles.

[0061] The present invention can charge multiple electric vehicles with one DC-DC high-power charging pile, thereby improving the utilization rate of a single DC-DC high-power charging pile. At the same time, it communicates with other DC-DC high-power charging piles through U8. When the output power of a certain DC-DC high-power charging pile needs to be increased, the DC-DC high-power charging pile can be controlled to be connected in parallel with other DC-DC high-power charging piles.

[0062] The output power of a single DC-DC high-power charging stack can be designed to be 10KW. Six DC-DC high-power charging stacks can be used to form an array. Each DC-DC high-power charging stack can be freely connected in parallel to form a maximum of 60KW charging. The power can be flexibly distributed through parallel control of the power supply. Multiple cars can be charged at the same time, and the remaining power of each car can be switched out and distributed to other charging cars.

[0063] like Figure 5As shown, P1 is used to quickly select whether to connect a 120-ohm resistor to the communication bus through a pin. The 120-ohm resistor is used to filter out interference in communication. Under normal circumstances, a 120-ohm resistor is connected to the very beginning and the farthest position of the communication bus, and the bus resistor is a 60-ohm resistor. The entire system includes multiple charging piles. Before the equipment is put into use, it is not certain which device is the first, which device is the last, and which device is the middle device (the middle device does not need to be connected to a 120-ohm resistor). Therefore, P1 is used to select whether to connect a 120-ohm resistor.

[0064] U11 is used to isolate the +5V input power supply and the +5V2 output power supply. The primary side of U11 is connected to +5V, and the secondary side of U11 is connected to +5V2. This avoids mutual interference between the primary and secondary circuits and improves the circuit's voltage resistance.

[0065] The communication ID setting part adopts the dip switch U9, and the 5th to 8th pins of U9 are respectively connected to P72, P71, P69, and P11, and the 1st to 4th pins of U9 are respectively connected to one end of the resistors R39 to R42, and the other end of R39 to R42 is connected to +3.3V.

[0066] The full-bridge driving part adopts BTD3011 chip U40, the IN+ port of U40 is connected to CHA1 through R45 and R44 in sequence, the OUTL port of U40 is connected to A-PWM, the VISO port of U40 is connected to VCCA, the OUTH port of U40 is connected to A-PWM, and the VEE port of U40 is connected to AS.

[0067] like Figure 2 As shown, AS is a unique pin of the IXFN50N120SiC silicon carbide MOS tube. This pin is used to drive the MOS. Like the source of the traditional MOS, the advantage is that this pin is not directly involved in the power part and is not affected by the large current on the control electrode.

[0068] like Figure 7 As shown, R44, R45, D17, D18, and C80 form an anti-interference circuit, which clamps the interference level on CHA1 to 3.3V and will not exceed 3.3V (exceeding 3.3V will damage U1).

[0069] Both OUTL and OUTH are connected to A-PWM, OUTH is used to turn on the high level, and OUTL is pulled down to a low level.

[0070] The input voltage detection part includes an LM224D chip U20, wherein the 5th pin of U20 is respectively connected to one end of a resistor R71 and one end of a resistor R78, the other end of R71 is connected to VBUS, the other end of R78 is connected to GND-P, the 6th pin of U20 is respectively connected to one end of the resistor R70 and the cathode of the voltage regulator D31, the anode of D31 is connected to GND-P, and the other end of R70 is connected to VBUS; Pin 7 of U20 is connected to the anode of the OP1 input terminal of the EL357 chip, and the cathode of the OP1 input terminal is connected to GND-P through resistor R80 and light-emitting diode E1 in sequence; the emitter of the OP1 output terminal is connected to P110.

[0071] like Figure 8 As shown, LM224D (U20) is used to design a voltage comparator. Pin 6 of U20 is clamped to 12V. When the voltage of pin 5 of U20 exceeds 12V, pin 7 of U20 outputs a high level. When pin 5 of U20 is lower than 12V, pin 7 of U20 has no output. Using the resistor voltage divider of R71 and R78, it is calculated that when the voltage reaches 600V, the voltage of pin 5 of U20 is 12.6V. At this moment, pin 7 of U20 outputs a high level, OP1 is turned on, P110 is a high level, and U1 detects that the input voltage exceeds 600V.

[0072] U20A is used to detect the indication that the VBUS voltage exceeds 600V (turn off the surge protection K100), U20C is used to detect the indication that the VBUS voltage is lower than 500V (undervoltage), and U20D is used to detect the indication that the VBUS voltage exceeds 900V (overvoltage). Undervoltage or overvoltage, U1 controls the switch tube to turn off the switch tube through the full-bridge drive part. Overvoltage will damage the switch tube. Undervoltage, under the same power condition, the current flowing through the switch tube is large, which will damage the switch tube.

[0073] The power supply part includes an LM1085-3.3 module U24, pin 3 of U24 is connected to +5V, and pin 2 of U24 is connected to +3.3V; The Vout port of the AMS1117-1.2 module U28 is connected to +3.3V, and the Vin port of U28 is connected to +1.2V; Pin 1 of LM2576-5.0 module U18 is connected to +24V, and pin 2 of U18 is connected to pin 4 of U18 and +5V respectively through inductor L6; Pin 1 of UC1844 module U19 is connected to FB, pin 4 of U19 is connected to RT / CT, pin 5 of U19 is connected to the gate of 12N170K5 tube Q1 through resistor R75, source of Q1 is connected to GND-P through resistor R81, drain of Q1 is connected to one end of the primary side of transformer T2, and the other end of the primary side of T2 is connected to VBUS; pin 7 of U19 is connected to one end of the secondary side T2B of T2 through resistor R66 and diode D27 in sequence, and the other end of T2B is connected to GND-P; One end of the secondary side T2C of T2 is connected to +24V through diode D23 and inductor L10, and the other end of T2C is connected to GND; One end of the secondary side T2D of T2 is connected to the 1st pin of the K7815M-1000R3 module U15 through the diode D25 and the inductor L11, the 3rd pin of U15 is connected to +15VP, and the other end of T2D is connected to GND-P; One end of the secondary side T2E of T2 is connected to VCCA through diode D28 and inductor L12, and the other end of T2E is connected to GNDA; One end of the secondary side T2F of T2 is connected to VCCB through diode D30 and inductor L13, and the other end of T2F is connected to GNDB; One end of the secondary side T2G of T2 is connected to VCCC through diode D32 and inductor L14, and the other end of T2G is connected to GNDC; One end of the secondary side T2H of T2 is connected to VCCD through diode D33 and inductor L16, and the other end of T2H is connected to GNDD; Pin 4 of PC817 chip U33 is connected to FB, pin 3 of U33 is connected to GND-P, pin 1 of U33 is connected to VCCD through resistor R89, pin 2 of U33 is connected to pin 2 of TL431 chip U35, pin 3 of U35 is connected to GNDD, pin 1 of U35 is respectively connected to one end of resistor R93 and one end of resistor R95, the other end of R95 is connected to GNDD, and the other end of R93 is connected to VCCD through resistor R90.

[0074] T2 and the primary and secondary connection circuits of T2 form an auxiliary power supply circuit.

[0075] Pin 7 of U19 charges capacitor C119 through R64 and R65. When charged to about 16V, U19 starts, magnetic flux is generated in the core of T2 transformer, and the induced electromotive force of T2B continues to supply current to pin 7 of U19.

[0076] Pin 3 of U19 is the switch current over-current detection pin. When the current passing through Q1 is too large, the voltage on resistor R81 increases, and the voltage at pin 3 of U19 increases. When it reaches its shutdown threshold, pin 6 of U19 becomes a low level, turning off Q1 to protect Q1 from over-current.

[0077] Pin 4 of U19 is the switching frequency setting pin of U19, which is determined by R68 and C122.

[0078] Pin 6 of U19 is the switch tube drive pin.

[0079] Pin 8 of U19 is the chip reference voltage output.

[0080] Pin 1 of U19 is the feedback collection pin.

[0081] T2H, U33 and U35 form a feedback sampling circuit, which collects voltage from the output terminal T2H and compares it with the reference voltage. When it is lower than the reference voltage, U19 increases the duty cycle, and when it is higher than the reference voltage, U19 reduces the duty cycle.

[0082] U35 is the reference source. Changes in the voltage at pin 1 of U35 will change the current value from pin 2 to pin 3 of U35, thereby changing the brightness of the light-emitting tube on the primary side of U33, thereby changing the conduction condition of the phototransistor on the secondary side of U33. The secondary side of U33 is connected to the feedback pin FB of U19, so that U19 uses the feedback signal to adjust the duty cycle and control the stability of the secondary voltage of T2.

[0083] The relay driving part adopts SH8023 chip U13, and the 1st, 3rd, 4th and 6th pins of U13 are respectively connected to U13-OB, P32, U13-OA and P31, and the control terminal of YK818C relay K101 is connected to U13-OB and U13-OA.

[0084] The main control FPGA part is used to control which channel-1 to Channel-6 outputs power through U13, U14, U16, U17, U23, and U25 according to the request of each channel (through CH3 communication).

[0085] The circuit usage principle of the present invention is as follows: Fig.18 As shown, suppose there are six charging piles, each of which has an electric vehicle connected, and each charging pile charges its own connected electric vehicle. When an electric vehicle connected to a charging pile requires more power (determined by the main control FPGA part of the charging pile), the charging pile sends a request on the bus through CH1, and the charging piles that are idle or have not fully released their power respond. The priority of the response can be confirmed according to the ID (from low to high). When the charging pile is connected to a charging pile and still fails to meet the demand, the charging pile can send a request again to reconnect other charging piles that are idle or have not fully released their power. This is explained by the KA~KF switch (taking KA as an example. Fig.18 KA1~KA6 is equivalent to Figure 3 The control of K101B~K106B in the control module selects which charging pile or piles to connect to. When the power demand of the charging pile is reduced and it is no longer necessary to connect to other charging piles, a disconnection request is sent, and the priority level is from high to low.

[0086] YK818C is a magnetic latching relay, which is power-saving, has stable performance, small size and large carrying capacity.

[0087] The SH8023 chip is a magnetic latching relay driver chip.

[0088] The ADC conversion part adopts AD7788 chip U22, and pins 1, 2, 3, 9, and 10 of U22 are respectively connected to P119, P113, AD-2, P121, and P120; Pin 4 of the LT1790 module U32 is connected to +3.3V through resistor R94 and magnetic bead L9, and pin 6 of U32 is connected to +2.5V2.

[0089] like Fig.14 As shown, three AD7788 chips are set, corresponding to the output voltage acquisition signal (AD-2) of the charging power supply and communication part, the output current acquisition signal (AD-1) and the switch tube working current acquisition signal (AD-0).

[0090] AD-0: Used to detect the current signal of Q1~Q8 for overcurrent / short circuit / bias magnetic protection.

[0091] AD-1: Used to detect the size and direction of the output current. The main control FPGA part controls the size of the output current through the full-bridge drive part to make the current size meet the requirements of charging electric vehicles.

[0092] AD-2: Used to detect the output voltage. The main control FPGA part controls the output voltage through the full-bridge drive part to make the voltage meet the requirements of charging electric vehicles.

[0093] The output voltage and current are detected and used to adjust the duty cycle of Q1 to Q8 tubes to control the output voltage and current to meet the requirements of charging electric vehicles.

[0094] The main control FPGA part adopts EP4CE15E22I7 chip U1, and pins 28, 30, 31, 32, and 33 of U1 are connected to P28, P30, P31, P32, and P33 respectively; Pins 1, 2, 5, and 6 of the EPCS4SI8N chip U3 are connected to FPGA-nCSO, FPGA-DATA0, FPGA-ASDO, and FPGA-DCLK respectively; Pins 58-61, 64-69, 71, and 72 of U1 are connected to P58-P61, P64-P69, P71, and P72 respectively; Pin 13 of U1 is connected to FPGA-DATA0 through resistor R31, and pins 11, 10, 8, 7, and 6 of U1 are connected to P11, P10, FPGA-nCSO, P7, and FPGA-ASDO respectively; Pins 76, 77, 80, 83, 85, and 86 of U1 are connected to CHA1, CHA4, P85, and P86 respectively; Pins 110~115 and 119~121 of U1 are connected to P110~P115 and P119~P121 respectively.

[0095] It can be understood that the above specific description of the present invention is only used to illustrate the present invention and is not limited to the technical solutions described in the embodiments of the present invention. Those skilled in the art should understand that the present invention can still be modified or replaced by equivalents to achieve the same technical effects; as long as the use requirements are met, they are within the protection scope of the present invention.

Claims

1. A comprehensive energy management circuit for an integrated charging system, comprising a charging power supply and communication part, an electric vehicle communication part, a communication ID setting part, a full-bridge driving part, an input voltage detection part, a power supply part, a relay driving part, an ADC conversion part and a main control FPGA part, characterized in that The information transmission port of the main control FPGA part is respectively connected with the information transmission port of the charging power supply and communication part, the information transmission port of the electric vehicle communication part, the information transmission port of the communication ID setting part, the information transmission port of the full-bridge driving part, the information transmission port of the input voltage detection part, the information transmission port of the relay driving part, and the information transmission port of the ADC conversion part; The power output port of the power supply part is respectively connected to the power port of the charging power supply and communication part, the power port of the electric vehicle communication part, the power port of the communication ID setting part, the power port of the full-bridge drive part, the power port of the input voltage detection part, the power port of the relay drive part, the power port of the ADC conversion part, and the power port of the main control FPGA part; The driving signal output port of the full-bridge driving part is connected to the driving signal input port of the charging power supply and the communication part; The detection signal input port of the input voltage detection part is connected to the detection signal output port of the charging power supply and the communication part; The driving signal output port of the relay driving part is connected to the relay driving signal input port of the charging power supply and the communication part; The signal input port of the ADC conversion part is connected to the output voltage and current acquisition signal output port of the charging power supply and communication part and the switch tube working current acquisition signal output port.

2. According to claim 1, the integrated energy management circuit of the charging integrated system is characterized in that The charging power supply and communication part includes a YK818C relay K100, the control end of K100 is connected to U2-OB and U2-OA respectively, and the 1st, 3rd, 4th and 6th pins of the SH8023 chip U2 are connected to U2-OB, P30, U2-OA and P28 respectively; VIN+1 is connected to the 1st pin of the common mode inductor U4, VIN-1 is connected to the 3rd pin of U4, the 2nd pin of U4 is connected to one end of the K100 controlled switch and one end of the resistor R9 respectively, the other end of R9 is connected to the other end of the K100 controlled switch and VBUS respectively, the 4th pin of U4 is connected to GND-P and the 1st pin of the HSTS08L module U46 respectively; The gate of IXFN50N120SiC tube Q1 is connected to A-PWM through resistor R11, the drain of Q1 is connected to VBUS, and the source of Q1 is connected to the first terminal of the primary side of transformer T1; The gate of IXFN50N120SiC tube Q2 is connected to A-PWM through resistor R12, the drain of Q2 is connected to VBUS, and the source of Q2 is connected to the first terminal of the primary side of transformer T1; The gate of IXFN50N120SiC tube Q5 is connected to B-PWM through resistor R22, the drain of Q5 is connected to the first terminal of the primary side of transformer T1, and the source of Q5 is connected to pin 2 of U46; The gate of IXFN50N120SiC tube Q6 is connected to B-PWM through resistor R23, the drain of Q6 is connected to the first terminal of the primary side of transformer T1, and the source of Q6 is connected to pin 2 of U46; The gate of IXFN50N120SiC tube Q3 is connected to C-PWM through resistor R13, the drain of Q3 is connected to VBUS, and the source of Q3 is connected to the second terminal of the primary side of transformer T1; The gate of IXFN50N120SiC tube Q4 is connected to C-PWM through resistor R14, the drain of Q4 is connected to VBUS, and the source of Q4 is connected to the second terminal of the primary side of transformer T1; The gate of IXFN50N120SiC tube Q7 is connected to D-PWM through resistor R24, the drain of Q7 is connected to the second terminal of the primary side of transformer T1, and the source of Q7 is connected to pin 2 of U46; The gate of IXFN50N120SiC tube Q8 is connected to D-PWM through resistor R25, the drain of Q8 is connected to the second terminal of the primary side of transformer T1, and the source of Q8 is connected to pin 2 of U46; The sources of Q1 to Q8 are connected to AS, AS, CS, CS, BS, BS, DS, and DS respectively; The OUT port of U46 is connected to the 3rd pin of LMP7731MF chip U6 through inductor L1, inductor L2, resistor R35 and resistor R36 in sequence, and the 1st and 4th pins of U6 are connected to AD-0; One end of the first secondary side T1B of T1 is connected to VOUT and the controlled switches of relays K101 to K106 through diode BD1 and inductor L15 respectively, and the other end of T1B is connected to pin 1 of HSTS08L module U45; One end of the second secondary side T1C of T1 is connected to the inductor L15 through the diode BD2, and the other end of T1C is connected to the pin 1 of U45; The OUT port of U45 is connected to the 3rd pin of LMP7731MF chip U5 through resistors R32 and R33, and the 1st and 4th pins of U5 are connected to AD-1; Pin 1 of HBV-A3.3 module VP1 is connected to VOUT through resistor R34, pin 2 of VP1 is connected to GOUT through resistor R37, pin 4 of VP1 is connected to pin 3 of LMP7731MF chip U7 through resistor R38, and pins 1 and 4 of U7 are connected to AD-2; Pins 1 and 4 of the CAN / TJA1050T / CM chip U8 are connected to P10 and P7 respectively, pin 7 of U8 is connected to pin 2 of the connector CH1 through inductor L3, and pin 6 of U8 is connected to pin 1 of CH1 through inductor L4.

3. The integrated energy management circuit of the charging integrated system according to claim 1, characterized in that The electric vehicle communication part includes a CAN / TJA1050T / CM chip U10, wherein the 1st and 4th pins of U10 are respectively connected to TXD and RXD, and the 7th pin of U10 is connected to the 3rd pin of the ACT45B-510-2P-TL003 common mode filter L7, and the 2nd pin of L7 is respectively connected to the 2nd pin of the connector P1 and one end of the inductor L5 through the fuse F1, and the other end of L5 is connected to the 2nd pin of the connector CH3; Pin 6 of U10 is connected to pin 4 of L7, and pin 1 of L7 is connected to one end of resistor R43 and one end of inductor L8 through fuse F2. The other end of L8 is connected to pin 2 of connector CH3, and the other end of R43 is connected to pin 1 of P1. The 1~4 pins of the B0505S-1W module U11 are connected to GND, +5V, +5V2, and GND2 respectively; The 2, 3, 6, and 7 pins of the ADUM1201CRZ chip U12 are connected to P85, P86, RXD, and TXD respectively.

4. The integrated energy management circuit of the charging integrated system according to claim 1, characterized in that The communication ID setting part adopts the dip switch U9, and the 5th to 8th pins of U9 are respectively connected to P72, P71, P69, and P11, and the 1st to 4th pins of U9 are respectively connected to one end of the resistors R39 to R42, and the other end of R39 to R42 is connected to +3.3V.

5. The integrated energy management circuit of the charging integrated system according to claim 1, characterized in that The full-bridge driving part adopts BTD3011 chip U40, the IN+ port of U40 is connected to CHA1 through R45 and R44 in sequence, the OUTL port of U40 is connected to A-PWM, the VISO port of U40 is connected to VCCA, the OUTH port of U40 is connected to A-PWM, and the VEE port of U40 is connected to AS.

6. The integrated energy management circuit of the charging integrated system according to claim 1, characterized in that The input voltage detection part includes an LM224D chip U20, wherein the 5th pin of U20 is respectively connected to one end of a resistor R71 and one end of a resistor R78, the other end of R71 is connected to VBUS, the other end of R78 is connected to GND-P, the 6th pin of U20 is respectively connected to one end of the resistor R70 and the cathode of the voltage regulator D31, the anode of D31 is connected to GND-P, and the other end of R70 is connected to VBUS; Pin 7 of U20 is connected to the anode of the OP1 input terminal of the EL357 chip, and the cathode of the OP1 input terminal is connected to GND-P through resistor R80 and light-emitting diode E1 in sequence; the emitter of the OP1 output terminal is connected to P110.

7. The integrated energy management circuit of the charging integrated system according to claim 1, characterized in that The power supply part includes an LM1085-3.3 module U24, pin 3 of U24 is connected to +5V, and pin 2 of U24 is connected to +3.3V; The Vout port of the AMS1117-1.2 module U28 is connected to +3.3V, and the Vin port of U28 is connected to +1.2V; Pin 1 of LM2576-5.0 module U18 is connected to +24V, and pin 2 of U18 is connected to pin 4 of U18 and +5V respectively through inductor L6; Pin 1 of UC1844 module U19 is connected to FB, pin 4 of U19 is connected to RT / CT, pin 5 of U19 is connected to the gate of 12N170K5 tube Q1 through resistor R75, source of Q1 is connected to GND-P through resistor R81, drain of Q1 is connected to one end of the primary side of transformer T2, and the other end of the primary side of T2 is connected to VBUS; pin 7 of U19 is connected to one end of the secondary side T2B of T2 through resistor R66 and diode D27 in sequence, and the other end of T2B is connected to GND-P; One end of the secondary side T2C of T2 is connected to +24V through diode D23 and inductor L10, and the other end of T2C is connected to GND; One end of the secondary side T2D of T2 is connected to the 1st pin of the K7815M-1000R3 module U15 through the diode D25 and the inductor L11, the 3rd pin of U15 is connected to +15VP, and the other end of T2D is connected to GND-P; One end of the secondary side T2E of T2 is connected to VCCA through diode D28 and inductor L12, and the other end of T2E is connected to GNDA; One end of the secondary side T2F of T2 is connected to VCCB through diode D30 and inductor L13, and the other end of T2F is connected to GNDB; One end of the secondary side T2G of T2 is connected to VCCC through diode D32 and inductor L14, and the other end of T2G is connected to GNDC; One end of the secondary side T2H of T2 is connected to VCCD through diode D33 and inductor L16, and the other end of T2H is connected to GNDD; Pin 4 of PC817 chip U33 is connected to FB, pin 3 of U33 is connected to GND-P, pin 1 of U33 is connected to VCCD through resistor R89, pin 2 of U33 is connected to pin 2 of TL431 chip U35, pin 3 of U35 is connected to GNDD, pin 1 of U35 is respectively connected to one end of resistor R93 and one end of resistor R95, the other end of R95 is connected to GNDD, and the other end of R93 is connected to VCCD through resistor R90.

8. The integrated energy management circuit of the charging integrated system according to claim 1, characterized in that The relay driving part adopts SH8023 chip U13, and the 1st, 3rd, 4th and 6th pins of U13 are respectively connected to U13-OB, P32, U13-OA and P31, and the control terminal of YK818C relay K101 is connected to U13-OB and U13-OA.

9. The integrated energy management circuit of the charging integrated system according to claim 1, characterized in that The ADC conversion part adopts AD7788 chip U22, and pins 1, 2, 3, 9, and 10 of U22 are respectively connected to P119, P113, AD-2, P121, and P120; Pin 4 of the LT1790 module U32 is connected to +3.3V through resistor R94 and magnetic bead L9, and pin 6 of U32 is connected to +2.5V2.

10. The integrated energy management circuit of the charging integrated system according to claim 1, characterized in that The main control FPGA part adopts EP4CE15E22I7 chip U1, and pins 28, 30, 31, 32, and 33 of U1 are connected to P28, P30, P31, P32, and P33 respectively; Pins 1, 2, 5, and 6 of the EPCS4SI8N chip U3 are connected to FPGA-nCSO, FPGA-DATA0, FPGA-ASDO, and FPGA-DCLK respectively; Pins 58-61, 64-69, 71, and 72 of U1 are connected to P58-P61, P64-P69, P71, and P72 respectively; Pin 13 of U1 is connected to FPGA-DATA0 through resistor R31, and pins 11, 10, 8, 7, and 6 of U1 are connected to P11, P10, FPGA-nCSO, P7, and FPGA-ASDO respectively; Pins 76, 77, 80, 83, 85, and 86 of U1 are connected to CHA1, CHA4, P85, and P86 respectively; Pins 110~115 and 119~121 of U1 are connected to P110~P115 and P119~P121 respectively.

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