Array circuit based on inverted counting type TDC

Abstract

The invention discloses an array circuit based on an inverted counting type TDC. The array circuit comprises a pixel array composed of pixel units, a data output module, a synchronous signal generation module, a time sequence control circuit and an initial and final phase detection module. Each pixel unit comprises an active quenching interface circuit AQC, a low-error-code inverted counting type time-to-digital converter TDC and a data transmission path switching module; and the initial and final phase detection module comprises an initial phase detection module contained in each TDC and a common final phase quantization module shared by the array. The initial phase detection module contained in each TDC can finely distinguish the initial phase error at the rising edge of the STOP signal, and the common end phase module can quantify the common end error at the falling edge of the EN signal, so that the resolution of the TDC is improved. The system imaging distance can be expanded, the system power consumption can be reduced, the TDC bit error rate can be reduced, the precision can be improved, and the time synchronization problem can be solved on the premise of not violating the working optical constraint of the system in the application scene of weak light and long-distance transmission.

Description

Technical Field

[0001] The invention belongs to the field of photoelectric detection technology, and in particular relates to an array circuit based on an inverted counting type TDC. Background Art

[0002] Single Photon Avalanche Diode (SPAD) array circuits are developing in the direction of large-scale, low power consumption, and high precision. In low-light application scenarios, most pixels (Time-to-Digital Converter, TDC) in the classic array will work at full scale. This is because the time when each pixel receives light is inconsistent, resulting in each pixel needing to be configured with a TDC circuit one by one to record the arrival time of the photon, resulting in a lot of useless power consumption. At the same time, since the timing start time of the time data converter needs to be synchronized with the laser emission time point, that is, the time data converter starts timing at the same time as the laser emission, a large transient current will be generated. As the array scale expands, the transient current will also increase, resulting in excessive transient voltage drop inside the array. Therefore, for larger-scale SPAD arrays, the power consumption generated by the TDC in the pixel is accumulated, which will have a very adverse effect on the function and performance of the entire circuit. At the same time, as the array scale expands, the requirements for the number of TDC bits increase. The traditional two-stage TDC is prone to inter-segment mismatch and low-segment TDC latch errors, resulting in bit errors. In addition, the TDC initial and final phase quantization errors caused by quantization timing problems will also have an adverse effect on the accuracy of measuring photon flight time. Summary of the invention

[0003] Technical problem: According to the requirements of LiDAR imaging technology for low power consumption and high precision, and targeting the power consumption sources and codeless reasons of the array circuit system in specific application scenarios, an array circuit based on an inverted counting TDC is designed. Based on the characteristics of the application scenario being weak light, a data transmission scheme that only outputs valid quantized data is used. By compressing the amount of transmitted data, the overall power consumption of the system is reduced.

[0004] Technical solution: An array circuit based on an inverted counting type TDC of the present invention comprises a pixel array composed of pixel units, a data output module, a synchronization signal generation module, a timing control circuit, and an initial and final phase detection module; each pixel unit comprises an active quenching interface circuit AQC (Active Quenching Circuit), a low error inverted counting type time-to-digital converter TDC (Time-to-Digital Converter), data transmission path switching module; the output of the active quenching interface circuit AQC in the pixel unit is connected to the low error inversion counting type digital converter TDC, and the data output of the low error inversion type TDC is connected to the data transmission path switching module to generate pixel unit output data; the data input of the pixel unit in each row is connected to the data output of another pixel unit, thereby forming a 128×128 pixel array; each data output module receives 4 rows×64 columns of pixel unit output data, and converts the data from serial to parallel output; the synchronization signal generation module is shared by the pixel array, and the output of the synchronization signal generation module is connected to each pixel unit through an H-Tree network to provide a synchronization signal for the pixel unit; the initial phase detection in the initial and final phase detection module is the low-segment phase interpolation type TDC in the low error inversion counting type time digital converter TDC, and the initial phase detection output is connected to the input of the high-segment 11-bit linear shift register LFSR (Linear Feedback Shift Register) type TDC in the low error inversion counting type time digital converter TDC, and the common final phase quantization module detects the clock signal and generates the final phase output.

[0005] Under the control of the timing control circuit, when the pixel unit arrives at the detection window, the active quenching interface circuit AQC converts the avalanche current generated when the single photon avalanche diode SPAD (Single Photon Avalanche Diode) detects a photon into a digital pulse signal STOP recognized by the time to digital converter TDC, which is used to start the time to digital converter TDC quantization of the corresponding pixel in the array; if the SPAD does not detect a photon within the detection window, the active quenching interface circuit AQC interface circuit actively quenches the single photon avalanche diode SPAD through internal feedback control, so that the single photon avalanche diode SPAD repeatedly detects photons according to the set timing.

[0006] The low error inverted counting time-to-digital converter TDC module in the pixel unit adopts an inverted counting quantization timing to quantize the time complementary to the photon flight time and latch the data, and controls the switching of the data transmission path through the data transmission path. Finally, the data transmitted through the data output port is assisted by the frame, word, and bit flag signals generated by the synchronization signal generation module to determine the type of current data and the row where the data is located, thereby completing the data transmission work.

[0007] The active quenching interface circuit AQC includes a gate tube, a quenching tube, a reset tube and a level conversion circuit. The active quenching interface circuit AQC is responsible for converting the avalanche current signal generated by the single-photon avalanche diode SPAD detector into a STOP pulse signal; after the single-photon avalanche diode SPAD detects a photon event, the active quenching interface circuit AQC is responsible for converting the avalanche photocurrent signal generated by it into a voltage pulse signal. Since the single-photon avalanche diode SPAD will remain in an avalanche state after being triggered, it will continuously generate an avalanche current; in order to prevent permanent damage to the device, the active quenching interface circuit AQC quickly reduces the reverse bias voltage to below the breakdown voltage and cuts off the avalanche current; the quenching tube is a process of restoring the single-photon avalanche diode SPAD from an avalanche state to a test state, and then when the next photoelectric detection is performed, the single-photon avalanche diode SPAD is reverse biased to restore it to the Geiger mode, clearing the accumulated charge, so that the single-photon avalanche diode SPAD is ready for the next round of photon detection.

[0008] The low error inversion counting type time digital converter TDC in the pixel unit adopts a two-stage TDC architecture combining a linear feedback shift register and a phase interpolation type; the high-stage linear shift register LFSR (Linear Feedback Shift Register) type time digital converter TDC is used to expand the time digital converter TDC range; the low-stage phase interpolation type time digital converter TDC is used as an initial phase detection module to achieve fine resolution of time quantization; the photon flight time finally obtained is

[0009] T tof =T EN -T TDC

[0010] Get, where T tof represents the photon flight time, T EN Represents the effective time of the gate signal EN, T TDC Represents the time quantized by the reverse counting TDC.

[0011] The data transmission path switching module controls the enabling / disabling of the intra-pixel time-to-digital converter TDC and controls the data transmission path switching.

[0012] The data output module realizes parallel-to-serial output of 4 rows of data through a NOR gate, and the data output port outputs quantized data of 4 rows×64 columns of pixels.

[0013] The initial and final phase detection module includes an initial phase detection module and a common final phase quantization module. The initial phase detection module performs time fine resolution on the initial phase error at the rising edge of the STOP signal; the common final phase quantization module is used to latch the phase states of the two high-frequency clock signals HCK1 and HCK at the arrival of the EN falling edge to achieve time subdivision; since all pixels in the array use the same TDC architecture, all pixel TDCs stop quantization at the EN falling edge, and the final phase states of each pixel are the same when the EN falling edge arrives, so only one common final phase quantization module is configured outside the pixel array.

[0014] The low-error inverted counting TDC module optimizes the transmission paths of the STOP signal and the HCK signal, adjusts the positions of the separation nodes of the two transmission paths of the above signals, tries to ensure the delay matching of the signals on the high-segment and low-segment transmission paths, improves the synchronization between the high-segment TDC counting clock switching moment and the low-segment TDC phase locking moment, reduces the inter-segment error time interval, and thus reduces the bit error rate.

[0015] Beneficial effects: Compared with the prior art, the present invention has the following significant advantages:

[0016] 1. The present invention is applied to direct time-of-flight measurement lidar SPAD arrays, especially to time-of-flight measurement lidar SPAD arrays in low-light scenarios. The present invention utilizes an inverted counting TDC. Compared with the traditional solution in which TDC works in the entire detection window, the TDC of the present invention only works after each SPAD trigger, which can greatly reduce the average power consumption of the system.

[0017] 2. The present invention proposes a new type of low-error inverted counting TDC structure, which optimizes the signal transmission path to ensure the delay matching of the high and low segments of the signal, shortens the miscounting time interval to about 1ps, and reduces the miscounting probability to 0.05%, solving the TDC miscounting problem caused by delay time mismatch.

[0018] 3. The array circuit proposed in the present invention can be used in a larger-scale SPAD array, and by reducing the number of TDC operations in the circuit and the number of bits of the TDC driven by a high-frequency clock, the quantization power consumption of the system is reduced while ensuring the resolution.

[0019] 4. The array proposed in the present invention adopts a new timing quantization scheme for quantizing the error problem of the initial phase and the final phase, which greatly solves the time synchronization problem caused by the initial and final phase quantization errors, and is conducive to improving the TDC resolution. The initial phase error of each TDC in the pixel is quantized separately, and the initial phase error of the STOP rising edge is finely distinguished; at the same time, through theoretical analysis, it is found that the final phase quantization error of the TDC latch clock of each pixel is consistent under ideal conditions, so a common final term quantization module is used, and the final phase information of one pixel is used to represent the final phase information of all pixels, which greatly saves circuit area. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a structural schematic diagram of an array circuit based on an inverted counting type TDC of the present invention;

[0021] Figure 2 It is the schematic diagram of the AQC interface circuit structure;

[0022] Figure 3 It is a schematic diagram of the TDC module structure;

[0023] Figure 4 This is a schematic diagram of a data transmission path switching module;

[0024] Figure 5 This is a schematic diagram of the data output module;

[0025] Figure 6 This is a key signal timing diagram of the array circuit based on the inverted counting TDC of the present invention. DETAILED DESCRIPTION

[0026] The array circuit based on the inverted counting type TDC of the present invention mainly includes a pixel array composed of pixel units, a data output module DATA_OUT, a synchronization signal generation module, a timing control circuit Timing_Control, and an initial and final phase detection module. Each single pixel unit includes an AQC interface circuit, a low error inverted counting type TDC module, and a data transmission path switching module.

[0027] The working logic of an array circuit based on an inverted counting TDC of the present invention is as follows: under the control of a timing control circuit, when the pixel circuit arrives at the detection window, the AQC interface circuit can convert the avalanche current generated when the SPAD detects a photon into a digital pulse signal STOP that can be recognized by the TDC, which is used to start the TDC quantization of the corresponding pixel in the array; if the SPAD does not detect a photon in the detection window, the AQC interface circuit can actively quench the SPAD through internal feedback control, so that the SPAD can repeatedly detect the photon according to the set timing. The single-pixel TDC circuit adopts an inverted counting quantization timing, quantizes the time complementary to the photon flight time and latches the data, controls the switching of the data transmission path through the data transmission path, and finally the data transmitted through the data output port is assisted by the frame (FRAME), word (WORD), and bit (BIT) flag signals generated by the synchronization signal generation module to determine the type of the current data and the row where the data is located, thereby completing the data transmission work.

[0028] Furthermore, the AQC interface includes at least a gate control tube, a quenching tube, a reset tube and a level conversion circuit. The AQC interface circuit is responsible for converting the avalanche current signal generated by the SPAD detector into a STOP pulse signal. After the SPAD detects a photon event, the AQC interface circuit is responsible for converting the avalanche photocurrent signal it generates into a voltage pulse signal. Since the SPAD will remain in an avalanche state after being triggered and continuously generate an avalanche current, in order to prevent permanent damage to the device, the AQC interface circuit can quickly reduce the reverse bias voltage to below the breakdown voltage and cut off the avalanche current. Quenching is the process of restoring the SPAD from the avalanche state to the state to be tested. Then, when the next photoelectric detection is performed, the APD is reverse biased to restore it to the Geiger mode, clearing the accumulated charge and making the SPAD ready for the next round of photon detection.

[0029] Furthermore, the single-pixel TDC adopts a two-stage TDC architecture combining a linear feedback shift register (LFSR) type register and a phase interpolation type. The high-stage LFSR type TDC is used to expand the TDC range; the low-stage phase interpolation type TDC is used as an initial phase detection module to achieve fine resolution of time quantization. The final photon flight time T tof Can be

[0030] T tof =T EN -T TDC

[0031] get.

[0032] Furthermore, the data transmission path switching module can control the enabling / disabling of the TDC module in the pixel and control the switching of the data transmission path at the same time.

[0033] Furthermore, the data output module realizes parallel-to-serial output of 4 rows of data through a NOR gate, and the data output port outputs quantized data of 4 rows×64 columns of pixels.

[0034] Furthermore, the initial and final phase detection module includes an initial phase detection module included in each pixel TDC, and a common final phase quantization module. The initial phase detection module performs time fine resolution on the initial phase error at the rising edge of the STOP signal. The common final phase quantization module is used to latch the phase states of the two high-frequency clock signals HCK1 and HCK at the time when the EN falling edge arrives, so as to achieve time subdivision. Since all pixels in the array use the same TDC architecture, all pixel TDCs theoretically stop quantization at the EN falling edge. Theoretically, the final phase states of each pixel are the same when the EN falling edge arrives, so only one common final phase quantization module is configured outside the pixel array.

[0035] The technical solution of the present invention is further described below in conjunction with the accompanying drawings.

[0036] Figure 1 It is a structural schematic diagram of an array circuit based on an inverted counting type TDC provided by the present invention. The overall circuit is composed of a pixel array composed of pixel units and data transmission related modules. Each pixel unit includes an AQC interface circuit, a low error inverted counting type TDC module and a data transmission path switching module. When a SPAD detects a photon, the corresponding AQC interface circuit is responsible for converting the avalanche current signal generated by the SPAD detector into a STOP pulse signal and actively quenching the SPAD. The inverted counting type TDC responds to the first arriving STOP signal and starts time quantization, generates time quantization counting data, and waits for data transmission. The timing control module Timing_Control generates data transmission start and end signals and connects to the readout synchronization signal generation module to generate frame (FRAME), word (WORD), and bit (BIT) timing control signals when the data is read out, and finally controls the data output module to complete the transmission of binary coded data. The global signals include an enable signal EN, a global reset signal RESET, and an AQC interface circuit reset signal REC. The clock signals HCK1 and HCK2 are connected to the entire array through a symmetrical H-Tree distribution network to improve the consistency of each pixel signal.

[0037] Figure 2The figure is a schematic diagram of the AQC interface structure. The operation of the circuit is divided into three stages: (1) Cut-off stage: According to the timing constraint, when the gate signal EN = 0 and REC = 0, the gate tube M1 is turned on, the voltage at the IN point increases, the STOPb voltage decreases, and the quenching tube M2 is gradually turned on to accelerate the voltage increase rate at the IN point until the voltage at the IN point is approximately 5V. At this time, the voltage across the SPAD is lower than the avalanche breakdown voltage. Even if a photon arrives, no avalanche current will be generated. The interface circuit output signal STOP = 1. (2) Reset stage: When the gate signal EN = 1 and the reset signal REC = 1, the reset tube M4 is turned on, the voltage at the IN point decreases, and the STOPb voltage increases. At this time, the quenching tube M2 is gradually turned off, which accelerates the voltage drop rate at the IN point until the voltage at the IN point is approximately 0V. At this time, the output signal of the interface circuit is STOP = 0; when the reset signal REC = 0 and no echo photons are detected, ideally, there is no charging and discharging action in the circuit at this time, and the output voltage of the interface circuit is maintained at a low level. At this time, the voltage across the SPAD is higher than the avalanche breakdown voltage, and it enters the waiting state to wait for the arrival of photons. (3) Avalanche stage: After the circuit completes the reset and enters the waiting state, if the echo photon is detected within the detection window of the gate signal EN (EN = 1), the avalanche current output by the SPAD quickly charges the IN point, the IN point voltage continues to rise, and STOPb continues to fall. At this time, the quenching tube M2 gradually opens, causing the IN point voltage to rise faster, until the IN point voltage is greater than the comparator flip voltage, STOPb = 0, the interface circuit outputs STOP = 1, and finally the rising edge of the 1.8V STOP signal generated by the level conversion circuit indicates that a photon event has been detected; if no photon is detected during the period when the gate signal EN = 1, the interface circuit outputs STOP = 0, until EN = 0, the circuit enters the cutoff stage, waiting for the next frame to start.

[0038] Figure 3Schematic diagram of the TDC module structure in the pixel, where the high-end 11-bit LFSR TDC is used to expand the range of the array TDC. When the rising edge of the STOP signal arrives, the high-frequency counting clock HCK1 drives the high-end TDC to generate pseudo-random numbers; the low-end phase interpolation TDC is used as an initial phase detection module to latch the phase states of the two high-frequency clock signals HCK1 and HCK2 when the rising edge of the STOP signal arrives. Before the arrival of STOP, the OR gate is blocked and its output signal always remains at a high level; when the rising edge of STOP arrives, the phase relationship between HCK and HCK2 is used to wait for the rising edge of HCK2 to arrive, the OR gate is released, and then the driving clock of the high-end TDC is switched to HCK1, so that the clock that first enters the high-end TDC counter is a complete cycle of HCK1, thereby avoiding the situation of missed counts in the high-end TDC. In order to improve the bit error rate, the transmission paths of the STOP signal and the HCK signal were optimized, and the positions of the separation nodes of the two transmission paths of the above signals were adjusted to ensure the delay matching of the signals on the high-segment and low-segment transmission paths as much as possible, improve the synchronization between the high-segment TDC counting clock switching moment and the low-segment TDC phase locking moment, reduce the inter-segment bit error time interval, and thus reduce the bit error rate.

[0039] Figure 4 This is a schematic diagram of the data transmission path switching module. The CONTROL signal controls the enable / disable of the TDC module in the pixel and also controls the data transmission path switching. The functions implemented by the two circuits are: when the CONTROL signal is configured to "1", the TDC of the current pixel is enabled and the quantized data of the TDC can be read out; when the CONTROL signal is configured to "0", the TDC is disabled and the current pixel is shielded from the data path during the data transmission stage.

[0040] Figure 5 This is a schematic diagram of the data output module. The specific circuit function is: when RC1 is "1", RC_LCK1 is a valid low-frequency clock, and other RC_LCKi are all "0". At this time, the data output port transmits the first row of pixel data, represented by D1 in the figure; when RC2 is "1", RC_LCK2 is a valid low-frequency clock, and the output port transmits the quantized data of the second row of pixels; similarly, RC3 and RC4 control the transmission of the address data and TDC quantized data of the third and fourth rows of pixels respectively. After transmitting all the data of the current row, the DFF of the row in the DATA_OUT module is reset to "0", thereby avoiding the problem of blocking data transmission, and finally realizing the parallel-to-serial output of 4 rows of data through the NOR gate.

[0041] Figure 6This is the key signal timing diagram of the array circuit based on the inverted counting type TDC of the present invention, which is divided into four stages: (1) Array initialization: After the system is powered on, the global reset signal RESET resets the entire array except the active quenching interface circuit, waiting for the detection window to arrive. (2) Quantization stage: When EN changes from 0→1, the laser pulse is synchronously emitted to irradiate the object to be detected, and the interface circuit reset signal REC is valid, resetting the SPAD array to the Geiger detection mode, and the output signal STOP generated by the interface circuit changes from 1→0; at this time, all circuit modules in the system have completed the reset work and are waiting for the event of detecting photons. In the detection window of the gate signal EN=1, when the SPAD array detects the echo photon, the SPAD generates a large avalanche current so that the STOP signal output by the interface circuit changes from 0→1, and at the same time, the TDC inside the corresponding pixel unit is activated to start the time quantization work. When the gate signal EN changes from 1→0, the TDC stops working and latches the quantization data. (3) Transmission preparation stage: According to the CONTROL signal, it is determined whether the TDC is disabled and whether it is excluded from the data transmission path. When the judgment is completed, all data in the system are ready, all data are latched and remain unchanged, waiting for the arrival of a valid data transmission signal (4) Transmission phase: According to the control signal generated by the timing control circuit Timing_Control, the array system performs data transmission. The FINAL signal is the output data of the common end phase detection module, that is, the high-frequency clock phase latched by the low-segment TDC of the module at the falling edge of the EN signal. In this stage, SYNC generates BIT, WORD, and FRAME signals for auxiliary reading and judging the nature and position of the current pixel output data. When the data transmission is completed, the FRAME signal changes from 1 to 0, and the time quantization and data transmission of this frame are all completed, waiting for the global reset signal RESET to arrive to start the next frame.

[0042] Compared with the traditional scheme, the array circuit based on TDC of the present invention has the following advantages: (1) It utilizes an inverted counting TDC. Compared with the traditional scheme in which TDC works in the entire detection window, the inverted counting TDC of the present invention only works after each SPAD trigger. The TDC working time is short, which can greatly reduce the average power consumption of the system and realize low-power application on a large-scale SPAD array. (2) It proposes a reasonable low-error inverted counting TDC architecture, which effectively improves the miscounting and missed counting problems caused by two-segment TDC. While having good time resolution and linearity, it reduces the time interval of inter-segment errors and significantly reduces the bit error rate. (3) It proposes an initial and final phase detection module applied to the circuit. The initial phase detection module is in each pixel TDC, and a common final phase detection module is configured outside the pixel array. It has a good effect on solving the timing synchronization problem, improving the TDC resolution and reducing the circuit area.

[0043] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be within the scope of protection of the present invention.

Claims

1. An array circuit based on an inverted counting type TDC, characterized in that The circuit includes a pixel array composed of pixel units, a data output module, a synchronization signal generation module, a timing control circuit, and an initial and final phase detection module; each pixel unit includes an active quenching interface circuit AQC, a low-error inverted counting type time-to-digital converter TDC, and a data transmission path switching module; the output of the active quenching interface circuit AQC in the pixel unit is connected to the low-error inverted counting type digital converter TDC, and the data output of the low-error inverted type TDC is connected to the data transmission path switching module to generate pixel unit output data; the data input of the pixel unit in each row is connected to the data output of another pixel unit, thereby forming a pixel array of 128×128 scale; Each data output module receives output data of 4 rows×64 columns of pixel units, and converts the data from serial to parallel output; the synchronization signal generation module is common to the pixel array, and the output of the synchronization signal generation module is connected to each pixel unit through an H-Tree network to provide a synchronization signal for the pixel unit; the initial phase detection in the initial and final phase detection module is the low-segment phase interpolation type TDC in the low-error inversion counting type time-to-digital converter TDC, and the initial phase detection output is connected to the input of the high-segment 11-bit linear shift register LFSR type TDC in the low-error inversion counting type time-to-digital converter TDC, and the common final phase quantization module detects the clock signal and generates the final phase output.

2. The array circuit based on the inverted counting type TDC according to claim 1, characterized in that Under the control of the timing control circuit, when the pixel unit arrives at the detection window, the active quenching interface circuit AQC converts the avalanche current generated when the single photon avalanche diode SPAD detects the photon into a digital pulse signal STOP recognized by the time digital converter TDC, which is used to start the time digital converter TDC quantization of the corresponding pixel in the array; If the SPAD does not detect photons within the detection window, the active quenching interface circuit AQC interface circuit actively quenches the single photon avalanche diode SPAD through internal feedback control, so that the single photon avalanche diode SPAD repeatedly detects photons according to the set timing.

3. The array circuit based on the inverted counting type TDC according to claim 1, characterized in that The low error inverted counting time-to-digital converter TDC module in the pixel unit adopts an inverted counting quantization timing to quantize the time complementary to the photon flight time and latch the data, and controls the switching of the data transmission path through the data transmission path. Finally, the data transmitted through the data output port is assisted by the frame, word, and bit flag signals generated by the synchronization signal generation module to determine the type of current data and the row where the data is located, thereby completing the data transmission work.

4. The array circuit based on the inverted counting type TDC according to claim 1, characterized in that: The active quenching interface circuit AQC includes a gate tube, a quenching tube, a reset tube and a level conversion circuit. The active quenching interface circuit AQC is responsible for converting the avalanche current signal generated by the single-photon avalanche diode SPAD detector into a STOP pulse signal; after the single-photon avalanche diode SPAD detects a photon event, the active quenching interface circuit AQC is responsible for converting the avalanche photocurrent signal generated by it into a voltage pulse signal. Since the single-photon avalanche diode SPAD will remain in an avalanche state after being triggered, it will continuously generate an avalanche current; in order to prevent permanent damage to the device, the active quenching interface circuit AQC quickly reduces the reverse bias voltage to below the breakdown voltage and cuts off the avalanche current; the quenching tube is a process of restoring the single-photon avalanche diode SPAD from an avalanche state to a test state, and then when the next photoelectric detection is performed, the single-photon avalanche diode SPAD is reverse biased to restore it to the Geiger mode, clearing the accumulated charge, so that the single-photon avalanche diode SPAD is ready for the next round of photon detection.

5. The array circuit based on the inverted counting type TDC according to claim 1, characterized in that: The low error inversion counting type time digital converter TDC in the pixel unit adopts a two-stage TDC architecture combining a linear feedback shift register and a phase interpolation type; the high-stage linear shift register LFSR type time digital converter TDC is used to expand the time digital converter TDC range; the low-stage phase interpolation type time digital converter TDC is used as an initial phase detection module to achieve fine resolution of time quantization; the photon flight time finally obtained is T tof =T EN -T TDC Get, where T tof represents the photon flight time, T EN Represents the effective time of the gate signal EN, T TDC Represents the time quantized by the reverse counting TDC.

6. The array circuit based on the inverted counting type TDC according to claim 1, characterized in that: The data transmission path switching module controls the enabling / disabling of the intra-pixel time-to-digital converter TDC and controls the data transmission path switching.

7. The array circuit based on the inverted counting type TDC according to claim 1, characterized in that: The data output module realizes parallel-to-serial output of 4 rows of data through a NOR gate, and the data output port outputs quantized data of 4 rows×64 columns of pixels.

8. The array circuit based on the inverted counting type TDC according to claim 1, characterized in that: The initial and final phase detection module includes an initial phase detection module and a common final phase quantization module. The initial phase detection module performs time fine resolution on the initial phase error at the rising edge of the STOP signal; the common final phase quantization module is used to latch the phase states of the two high-frequency clock signals HCK1 and HCK at the arrival of the EN falling edge to achieve time subdivision; since all pixels in the array use the same TDC architecture, all pixel TDCs stop quantization at the EN falling edge, and the final phase states of each pixel are the same when the EN falling edge arrives, so only one common final phase quantization module is configured outside the pixel array.

9. The array circuit based on the inverted counting type TDC according to claim 1, characterized in that: The low-error inverted counting TDC module optimizes the transmission paths of the STOP signal and the HCK signal, adjusts the positions of the separation nodes of the two transmission paths of the above signals, tries to ensure the delay matching of the signals on the high-segment and low-segment transmission paths, improves the synchronization between the high-segment TDC counting clock switching moment and the low-segment TDC phase locking moment, reduces the inter-segment error time interval, and thus reduces the bit error rate.

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