Multi-path power on / off timing control circuit and method

Abstract

The application provides a multi-path power supply power-on and power-off timing control circuit and method. The circuit comprises a multi-path power supply loop, a system power supply voltage detection loop, a reset loop, a power-on and power-off state selection loop and a multi-path power supply timing control loop. In the multi-path power supply power-on and power-off timing control circuit, the power supply state of the system power supply of the processor device can be obtained through the system power supply voltage detection loop, and the restart state of the processor device can be obtained through the reset loop. Combined with the power supply state of the system power supply and the restart state of the processor device, the actual power-on and power-off state of the processor device can be determined. Based on the actual power-on and power-off state of the processor device, the power-on and power-off timing of the processor device can be more accurately controlled, which helps to ensure the normal work of the processor device and improve the reliability of the processor device.

Description

Technical Field

[0001] This application relates to the field of electronic circuit design, and in particular to a multi-power supply power-on / off timing control circuit and method. Background Technology

[0002] With the rapid development of semiconductor manufacturing processes and electronic technology, various industries have increasingly higher requirements for chip processors such as central processing units (CPUs) and field-programmable gate arrays (FPGAs). These devices have strict requirements for power-on and power-off timing. If the power-on and power-off timing does not meet the requirements, it will shorten the normal operating life of these devices, and in severe cases, it will lead to direct chip failure, restricting the application development of these devices. Typically, the power-on and power-off timing of these devices can be controlled by complex programmable logic devices (CPLDs). However, CPLDs cannot always ensure that the power-on and power-off timing meets the requirements. Furthermore, CPLD devices involve CPLD software programming, which increases the complexity of the entire system architecture. Summary of the Invention

[0003] This application provides a multi-channel power-on / off timing control circuit and method.

[0004] In a first aspect, embodiments of this application provide a multi-power supply power-on / off timing control circuit, including a multi-power supply loop, a system power supply voltage detection loop, a reset loop, a power-on / off state selection loop, and a multi-power supply timing control loop.

[0005] Multiple power supply loops are used to enable processor devices;

[0006] The system power supply voltage detection circuit is used to determine whether the voltage of the system power supply of the processor device is greater than the first threshold. The input terminal of the system power supply voltage detection circuit is connected to the system power supply, and the output terminal of the system power supply voltage detection circuit is connected to the first input terminal of the power-on / off state selection circuit.

[0007] The reset circuit is used to control the restart of the processor device. The input terminal of the reset circuit is connected to the output terminal of the processor device, and the output terminal of the reset circuit is connected to the second input terminal of the power-on / off state selection circuit.

[0008] The power-on / off state selection circuit is used to determine the power-on / off state of the processor device. When the voltage is greater than the first threshold and the reset circuit does not control the processor device to restart, the processor device is in the power-on state. When the voltage is not greater than the first threshold or the reset circuit controls the processor device to restart, the processor device is in the power-off state. The output terminal of the power-on / off state selection circuit is connected to the input terminal of the multi-power supply timing control circuit.

[0009] The multi-power supply timing control loop is used to control the power-on and power-off sequence of the multi-power supply circuits according to the power-on and power-off states. When the circuit is powered on, the multi-power supply timing control loop controls the multi-power supply circuits to power on in a predetermined order. Conversely, when the circuit is powered off, the multi-power supply timing control loop controls the multi-power supply circuits to power off in a predetermined order. The output terminal of the multi-power supply timing control loop is connected to the input terminal of the multi-power supply circuit.

[0010] Optionally, the system power supply voltage detection circuit includes a comparator and a reference voltage circuit. The first input terminal of the comparator is connected to the reference voltage circuit, the second input terminal of the comparator is connected to the system power supply, and the output terminal of the comparator is connected to the first input terminal of the power-on / off state selection circuit. The first threshold is determined based on the reference voltage of the reference voltage circuit. The comparator outputs a high level when the voltage of the system power supply is greater than the first threshold, and outputs a low level otherwise.

[0011] Optionally, the comparator's hysteresis is less than the second threshold, the comparator's operating voltage is less than the third threshold, and the reference voltage circuit's operating voltage is less than the fourth threshold.

[0012] Optionally, the reset circuit includes a watchdog circuit that outputs a low level when controlling the processor device to restart and a high level when not controlling the processor device to restart.

[0013] Optionally, the power-on / off state selection circuit includes an AND gate circuit, which outputs a high level when both the comparator and the watchdog circuit output a high level, and outputs a low level otherwise.

[0014] Optionally, the multi-power supply timing control loop includes a bidirectional buffer. When the AND gate outputs a high level, the bidirectional buffer outputs an enable signal to control the multi-power supply loop to power on in a predetermined sequence. Conversely, when the AND gate outputs a low level, the bidirectional buffer outputs an enable signal to control the multi-power supply loop to power off in a predetermined sequence.

[0015] Optionally, the multi-power supply timing control loop includes a bidirectional buffer.

[0016] Optionally, the multi-power supply timing control loop includes two bidirectional buffers, and the power-on and power-off timings of the two bidirectional buffers are independent of each other.

[0017] Alternatively, the time required to enable the processor device via the multiple power loop is less than the time it takes for the multiple power loop to function normally during system power-off.

[0018] Secondly, embodiments of this application provide a power supply system, which includes a multi-channel power-on / off timing control circuit as described in any one of the first aspects.

[0019] Thirdly, embodiments of this application provide a multi-power supply power-on / off timing control method, which controls the power-on / off timing of the processor device through a multi-power supply power-on / off timing control circuit as described in any one of the first aspects.

[0020] Fourthly, an electronic device is provided, which may include at least one unit or module that can be used to perform the method as described in any of the third aspects above.

[0021] Fifthly, an electronic device is provided, which may include at least one processor coupled to at least one memory, the at least one memory being used to store computer programs or instructions, which, when executed by the at least one processor, cause the electronic device to perform the methods as described in any of the third aspects above.

[0022] In a sixth aspect, a computer-readable storage medium is provided that stores a computer program or instructions which, when executed on a computer, cause the method of any of the third aspects described above to be performed.

[0023] In the multi-power-on / off timing control circuit of this application, the power supply status of the processor device's system power supply can be obtained through the system power supply voltage detection loop, and the restart status of the processor device can be obtained through the reset loop. Combining the power supply status of the system power supply and the restart status of the processor device, the actual power-on / off status of the processor device can be determined. Based on the actual power-on / off status of the processor device, the power-on / off timing of the processor device can be controlled more accurately, which helps to ensure the normal operation of the processor device and improve its reliability. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below.

[0025] Figure 1 This is a schematic diagram of the multi-power supply power-on / off timing control circuit provided in the embodiments of this application.

[0026] Figure 2 This is an example diagram of a multi-power supply power-on / off timing control circuit provided in an embodiment of this application.

[0027] Figure 3 This is an example diagram of another multi-channel power-on / off timing control circuit provided in the embodiments of this application.

[0028] Figure 4 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0029] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings.

[0030] With the rapid development of semiconductor manufacturing processes and electronic technologies, various industries are placing increasingly higher demands on chip processors such as CPUs and FPGAs. For example, in the industrial, automotive, and consumer electronics industries, the complexity of CPUs and FPGAs is increasing.

[0031] These devices have strict requirements for power-on and power-off timing. If the power-on and power-off timing does not meet the requirements, the normal operating life of these devices will be shortened, and in severe cases, the chips will fail directly, restricting the application development of these devices. For example, failure to meet the power-on and power-off timing requirements may cause the electronic fuse (EFUSE) of devices such as CPUs and FPGAs to malfunction or the input / output (I / O) state of power-on and power-off control to be uncertain. This may lead to the risk of false triggering or direct damage to devices such as CPUs and FPGAs.

[0032] Typically, the power-on and power-off timing of these devices can be controlled by a CPLD. However, CPLDs cannot always ensure that the power-on and power-off timing meets the requirements. For example, when the chip system powers down, the CPLD's supply voltage also begins to drop, which may result in the CPLD ceasing operation while the power supplies to devices such as the CPU and FPGA are not yet fully powered down. Furthermore, if the CPLD's I / O fails, the power supplies to devices such as the CPU or FPGA will not be able to supply power normally, causing problems such as the CPU or FPGA failing to start normally or never starting. In addition, CPLD devices involve CPLD software programming, which increases the complexity of the entire system architecture.

[0033] Based on this Figure 1 The diagram shows a multi-channel power-on / off timing control circuit provided in this application embodiment. This circuit can be used for power-on / off timing control of processor devices such as CPUs and FPGAs.

[0034] like Figure 1As shown, circuit 100 may include a multi-power supply circuit 110, a system power supply voltage detection circuit 120, a reset circuit 130, a power-on / off state selection circuit 140, and a multi-power supply timing control circuit 150.

[0035] The multiple power supply loop 110 can be used to enable the processor device. The multiple power supply loop 110 can include multiple power supply loops, each of which can be used to enable different modules within the processor device. Each of the multiple power supply loops can include a direct current-to-direct current converter (DCDC) or a low dropout voltage regulator (LDO), and the type of DCDC or LDO is not limited.

[0036] The system power supply voltage detection circuit 120 can be used to determine whether the voltage of the system power supply of the processor device is greater than a first threshold. The input terminal of the system power supply voltage detection circuit 120 is connected to the system power supply, and the output terminal of the system power supply voltage detection circuit 120 is connected to the first input terminal of the power-on / off state selection circuit 140.

[0037] The first threshold can be used to determine whether the system power supply can supply power normally. When the voltage of the system power supply is greater than the first threshold, it means that the system power supply can supply power normally, and it can be determined that circuit 100 is in the powered-on state. Otherwise, when the voltage of the system power supply is less than or equal to the first threshold, it means that the system power supply cannot supply power normally, and it can be determined that circuit 100 is in the powered-off state.

[0038] It should be noted that determining that circuit 100 is powered on does not necessarily mean that the processor is also powered on. For example, when the processor restarts, circuit 100 may be powered on, but the processor may be powered off. However, determining that circuit 100 is powered off confirms that the processor is also powered off.

[0039] The system power supply voltage detection circuit 120 can compare the voltage of the system power supply with a first threshold and determine the output result based on the comparison result. For example, when the voltage of the system power supply is greater than the first threshold, the system power supply voltage detection circuit 120 can output a high level; otherwise, the system power supply voltage detection circuit 120 can output a low level.

[0040] The reset circuit 130 can be used to control the restart of the processor device. The input terminal of the reset circuit 130 is connected to the output terminal of the processor device, and the output terminal of the reset circuit 130 is connected to the second input terminal of the power-on / off state selection circuit 140. For example, the reset circuit 130 can control the restart of the processor device when the processor device crashes or when the processor device needs to be remotely upgraded.

[0041] In this application, restarting the processor device refers to restarting the enable power supply of the processor device. When the reset circuit 130 controls the processor device to restart, the processor device needs to be powered down, that is, the processor device is in a powered-down state. When the reset circuit 130 controls the processor device to restart, the system power supply is usually still providing power normally, that is, the circuit 100 is in a powered-on state.

[0042] The reset circuit 130 can determine the output result based on whether it controls the processor device to restart. For example, when the reset circuit 130 controls the processor device to restart, it can output a low level; otherwise, it can output a high level.

[0043] The power-on / off state selection circuit 140 can be used to determine the power-on / off state of the processor device. When the voltage of the system power supply is greater than the first threshold and the reset circuit 130 does not control the processor device to restart, the processor device is in the power-on state. When the voltage of the system power supply is not greater than the first threshold or the reset circuit 130 controls the processor device to restart, the processor device is in the power-off state. The output terminal of the power-on / off state selection circuit 140 is connected to the input terminal of the multi-channel power supply timing control circuit 150.

[0044] When the system power supply voltage is greater than the first threshold and the reset circuit 130 does not control the processor device to restart, the circuit 100 is in the power-on state, and the processor does not need to be powered down; therefore, the processor device is in the power-on state. When the system power supply voltage is less than or equal to the first threshold, the circuit 100 is in the power-off state, and therefore, the processor device is in the power-off state. When the reset circuit 130 controls the processor device to restart, the circuit 100 is in the power-on state, but the processor needs to be powered down; therefore, the processor device is in the power-off state.

[0045] The power-on / off state selection circuit 140 can determine the output result based on the power-on / off state of the processor device. For example, when the processor device is powered on, the power-on / off state selection circuit 140 can output a high level; otherwise, it can output a low level.

[0046] The multi-power supply timing control loop 150 can be used to control the power-on and power-off sequence of the multi-power supply loop 110 according to the power-on and power-off states. When the power-on state is on, the multi-power supply timing control loop 150 controls the multi-power supply loop 110 to power on in a predetermined order. Conversely, the multi-power supply timing control loop 150 controls the multi-power supply loop 110 to power off in a predetermined order. The output terminal of the multi-power supply timing control loop 150 is connected to the input terminal of the multi-power supply loop 110.

[0047] The multi-power supply timing control loop 150 can control the power-on / off sequence of multiple power supply loops in the multi-power supply loop 110 according to the power-on / off status. The power-on / off sequence of the multiple power supply loops determines the power-on / off sequence of different modules in the processor device. The power-on / off sequence of different modules in the processor device may be opposite or independent of each other. Correspondingly, the power-on / off sequence of multiple power supply loops can be opposite or independent of each other.

[0048] In the multi-power-on / off timing control circuit of this application, the power supply status of the processor device's system power supply can be obtained through the system power supply voltage detection loop, and the restart status of the processor device can be obtained through the reset loop. Combining the power supply status of the system power supply and the restart status of the processor device, the actual power-on / off status of the processor device can be determined. Based on the actual power-on / off status of the processor device, the power-on / off timing of the processor device can be controlled more accurately, which helps to ensure the normal operation of the processor device and improve its reliability.

[0049] Optionally, the system power supply voltage detection circuit 120 may include a comparator and a reference voltage circuit. The first input terminal of the comparator is connected to the reference voltage circuit, the second input terminal of the comparator is connected to the system power supply, and the output terminal of the comparator is connected to the first input terminal of the power-on / off state selection circuit 140. The first threshold can be determined based on the reference voltage of the reference voltage circuit. The comparator can output a high level when the voltage of the system power supply is greater than the first threshold, and output a low level otherwise. Based on the comparator and the reference voltage circuit, the comparison between the voltage of the system power supply and the first threshold can be easily realized.

[0050] The comparator model is not limited. Optionally, the comparator's hysteresis can be less than a second threshold. For example, the second threshold can be 0.05, meaning the comparator's hysteresis can be less than 0.05. A comparator with a smaller hysteresis is more sensitive. Optionally, the comparator's operating voltage can be less than a third threshold. For example, the third threshold can be 2V, meaning the comparator's operating voltage can be less than 2V. A lower operating voltage ensures that the comparator can operate for a longer time when the system power supply is off, eliminating the need for a separate power supply. For example, the comparator model could be TLV3691.

[0051] The model of the reference voltage circuit is not limited. Optionally, the operating voltage of the reference voltage circuit can be lower than the fourth threshold. For example, the fourth threshold can be 2V, meaning the operating voltage of the reference voltage circuit can be lower than 2V. A lower operating voltage ensures that the reference voltage circuit can operate for a longer period when the system power supply is off, eliminating the need for a separate power supply. For example, the model of the reference voltage circuit could be TPR3312.

[0052] Alternatively, the system power supply voltage detection loop 120 may also include a power monitoring circuit with a reference. The power monitoring circuit with a reference can also compare the voltage of the system power supply with a first threshold, and the model of the power monitoring circuit with a reference is not limited.

[0053] Optionally, the reset circuit 130 may include a watchdog (WD) circuit. The watchdog circuit outputs a low level when controlling the processor device to restart, and a high level when not controlling the processor device to restart. The watchdog circuit can control the processor device to restart when the processor device crashes or requires remote upgrade. The model of the watchdog circuit is not limited; for example, the watchdog circuit could be an SGM706.

[0054] Optionally, the power-on / off state selection loop 140 may include an AND gate circuit. The AND gate circuit outputs a high level when both the comparator and watchdog circuit output high levels, and a low level otherwise. When both the comparator and watchdog circuit output high levels, the processor device is in the power-on state. When either the comparator or watchdog circuit outputs a low level, the processor device is in the power-off state. In other words, the AND gate circuit can output a high level when the processor device is in the power-on state and a low level when the processor device is in the power-off state. The type of AND gate circuit is not limited; for example, it could be an SN74LVC1G08. Based on the AND gate circuit, the power-on / off state of the processor device can be determined simultaneously based on the outputs of the comparator and watchdog circuit.

[0055] Optionally, the multi-power supply timing control loop 150 may include a bidirectional buffer, and the output of the watchdog circuit can be used as the input of the bidirectional buffer. When the AND gate output is high, the bidirectional buffer outputs an enable signal to control the multi-power supply loop 110 to power on in a predetermined sequence; conversely, when the AND gate output is low, the bidirectional buffer outputs an enable signal to control the multi-power supply loop 110 to power off in a predetermined sequence. The bidirectional buffer can control the direction of current transmission between two circuits; when the inputs of the bidirectional buffer are high and low, respectively, the current transmission directions controlled by the bidirectional buffer are opposite.

[0056] As mentioned above, the power-on and power-off sequence of multiple power supply circuits in the system power supply voltage detection circuit 120 can be reversed, so the multi-power supply timing control circuit 150 can include a bidirectional buffer.

[0057] Alternatively, the power-on and power-off sequences of multiple power supply circuits in the system power supply voltage detection circuit 120 can be independent of each other. Therefore, the multi-power supply timing control circuit 150 can also include two bidirectional buffers. The power-on and power-off sequences of the two bidirectional buffers are independent of each other, with one used to control power-on and the other used to control power-off.

[0058] The model of the bidirectional buffer is not limited; for example, the model of the bidirectional buffer can be SN74LVCR2245A.

[0059] Based on the bidirectional buffer, the power-on and power-off sequence of the multi-power circuit 110 can be easily controlled, thereby controlling the power-on and power-off sequence of the processor devices.

[0060] Optionally, the time required for the multiple power supply loop to enable the processor device is less than the time the multiple power supply loop can operate normally during system power-down. In other words, the multiple power supply loop can enable the processor device during system power-down. This helps avoid situations where the processor device has not yet completed power-down, but the multiple power supply loop is already inoperable.

[0061] Optionally, the multiplexed power supply loop 110 may include an enable pin, and the enable signal output by the multiplexed power supply timing control loop 150 can be input to the multiplexed power supply loop 110 through the enable pin.

[0062] The following is combined Figure 2 The following is an example of the power-on / off timing control circuit for the multiple power supplies in this application.

[0063] For example, Figure 2 In the circuit shown, the processor device is a CPU / FPGA. The system power supply voltage detection circuit includes a TLV3691 comparator and a TPR3312 reference voltage circuit. The reset circuit includes an SGM706 watchdog circuit. The power-on / off state selection circuit includes an SN74LVC1G08 AND gate circuit. The multi-power supply timing control circuit includes an SN74LVCR2245A bidirectional buffer. The multi-power supply circuit includes 6 power supply circuits (controlled by DC-DC1, DC-DC2, DC-DC3, LDO1, LDO2, and LDO3 respectively).

[0064] exist Figure 2In the circuit shown, the watchdog circuit is connected to the general-purpose input / output (GPIO) pins of the CPU / FPGA via the watchdog input (WDI) pin to determine whether to control the CPU / FPGA restart. The watchdog circuit outputs a low level when controlling the CPU / FPGA restart, and a high level otherwise. The output of the watchdog circuit is connected to the second input of the AND gate circuit through the reset (RESET, RST) pin.

[0065] The first input terminal of the comparator is connected to the reference voltage (V) output by the reference voltage circuit. ref The second input terminal is connected to the voltage of the system power supply. The voltage threshold of the system power supply (i.e., the first threshold) can be calculated using a reference voltage and resistors R1 and R2. The comparator outputs a high level when the voltage of the system power supply is greater than the first threshold, and outputs a low level otherwise. The output of the comparator is connected to the first input terminal of the AND gate circuit through the power fail output (PFO) pin.

[0066] When both the first and second input terminals of the AND gate are high, the output is high, indicating that the power supply of the multiple power supply loop is turned on (i.e., PWP-UP). Otherwise, the output is low, indicating that the power supply of the multiple power supply loop is turned off (i.e., PWP-DOWN). The output of the AND gate is connected to the input terminal of the bidirectional buffer. The output of the bidirectional buffer includes 6 enable (EN) terminals (EN[1:6]), which enable the 6 power supply loops respectively. The output voltage (VOUT)[1:6] of the 6 power supply loops enables different modules in the CPU / FPGA respectively.

[0067] When the AND gate outputs a high level (i.e., PWP-UP), the bidirectional buffer controls the direction of B by passing A (not shown in the figure), which is the power-on control timing. When the AND gate outputs a low level (i.e., PWP-DOWN), the bidirectional buffer controls the direction of A by passing B (not shown in the figure), which is the power-down control timing. This enables LDOs or DC-DC converters of different voltage levels, meeting the power-on and power-off timing requirements of the CPU / FPGA.

[0068] Figure 2 The circuit shown can be operated as follows: After the circuit is powered on, the system power supply starts to work. When the voltage of the system power supply reaches the preset threshold, the AND gate loop determines that the CPU / FPGA is powered on. The bidirectional buffer outputs the enable control signal to enable multiple DC-DC or LDOs in sequence according to the timing requirements, so that multiple DC-DC or LDOs can be powered on according to the timing requirements.

[0069] When the system power supply starts to lose power, causing the voltage to be less than or equal to a preset threshold, or when the reset circuit starts to reset (i.e., controlling the CPU / FPGA to restart), the AND gate circuit determines that the CPU / FPGA is in a power-down state. The bidirectional buffer outputs an enable control signal to sequentially disable the enable of multiple DC-DC or LDOs according to the timing requirements, so that the multiple DC-DC or LDOs can be powered down according to the timing requirements.

[0070] After the reset circuit completes the reset, since the system power supply is always working, the AND gate circuit determines that the CPU / FPGA is in the power-on state. The bidirectional buffer outputs the enable control signal to enable the multiple power supplies DC-DC or LDO in sequence according to the timing requirements, so that the DC-DC or LDO can be powered on according to the timing requirements.

[0071] The following is combined Figure 3 The circuit design of the multi-power supply power-on / off timing control circuit of this application is illustrated with an example.

[0072] like Figure 3 As shown, U1 is an AND gate circuit, U2 is a watchdog circuit, U3 is a bidirectional buffer, U4A is a comparator circuit, and U5 is a reference voltage circuit.

[0073] Figure 3 The meanings of some terms in the code are as follows: Vcc represents the power supply voltage pin of the AND gate circuit, PFI represents the input terminal of the threshold detector of the watchdog circuit, IN represents the input terminal of the reference voltage circuit, OUT represents the output terminal of the reference voltage circuit, DIR represents the direction control pin of the bidirectional buffer, OE represents the enable control pin of the bidirectional buffer, and VCC represents the power supply voltage pin of the bidirectional buffer. Figure 3 The meanings of the other terms in the text are explained in the context and will not be repeated here.

[0074] In this configuration, pins 1 and 8 of U2 are shorted and connected to pull-up resistor R1, which is connected to the system power supply (VDD can be used to represent the system power supply voltage). Pin 2 is connected to VDD, pin 3 is grounded (GND), and pins 4 and 5 are floating (normally closed, NC). Pin 6 of U2 is connected to the GPIO pin of the FPGA or CPU for dog feeding and has a pull-up resistor. Pin 7 is the reset pin and has a pull-up resistor. Pin 7 is also connected to pin 1 of U1.

[0075] Pin 1 of U5 is connected to VDD, pin 3 to GND, and pin 2 to the load capacitor, providing voltage regulation for the reference voltage (VREF). Pin 2 is also connected to pin 2 of U4A. Pin 3 of U4A is connected to resistors R5 and R16, and pin 1 is connected to U1. The system power supply voltage threshold (i.e., the first threshold) is calculated using the formula: VT = (R5 + R16) / R16 * VREF. When VDD voltage > VT, pin 1 of U4A outputs a high level, indicating that the power supply is powered on; when VDD voltage ≤ VT, pin 1 of U4A outputs a low level, indicating that the power supply is powered off.

[0076] Pin 1 of U1 is connected to pin 7 of U2, pin 2 of U1 is connected to pin 1 of U4A, pin 3 is the GND pin, pin 5 is the VDD power supply pin, and pin 4 is the PWR_STAUS power status pin, which requires a pull-down resistor R2. When pin 4 outputs a high level, it indicates that the power supply is on; when pin 4 outputs a low level, it indicates that the power supply is off.

[0077] Pin 1 of U3 is the direction control pin. When the input is high, the control data moves from A to B; when the input is low, the control data moves from B to A. Pins 2 to 9 of U3 are for A-direction data signals, pins 11 to 18 are for B-direction data signals, pin 10 is the GND pin, pin 20 is the power supply VDD pin, and pin 19 is the enable pin, which is directly shorted to ground and operates normally. EN[1:6] enables the LDO or DC-DC converter, causing its output voltage to be VOUT[1:6] supplied to the FPGA or CPU.

[0078] When the PWR_STAUS signal is high, the CPU / FPGA is in power-on mode. U3 is used for data transfer from A to B. R7 and C12 form a resistor-capacitance circuit (RC) charging loop. By controlling the resistance value of R7 and the capacitance value of C12, after U3 is enabled, EN1 starts with a delay. The delay time (time constant) of EN1 is: R7*C12 (one time constant is 0.663*VDD, which is high level at this time). Similarly, the delay time of EN2 is: R10*C10, the delay time of EN3 is: R13*C8, the delay time of EN4 is: R17*C6, the delay time of EN5 is: R20*C4, and the delay time of EN6 is: R23*C2.

[0079] When the PWR_STAUS signal is low, the CPU / FPGA is in power-down mode, and U3 performs data transfer from B to A. Therefore, the capacitance of capacitor C3 needs to be very small, and C3 is discharged through R24 and R25. When the PWR_STAUS signal is low, EN6 is delayed in power-down. The power-down delay time of EN6 is: 2.3*(R24+R25)*C3 (2.3 time constants equal 0.9*VDD, which is low at this time). Using pF level C3 allows for fast power-down. The power-down delay time of EN5 is: 2.3*(R21+R23)*C5. This is because resistors R9, R12, R15, R19, and R22 provide power for EN6. With a defined voltage level, the resistance values ​​are in the 10K range. Resistors R7, R8, R10, R11, R13, R14, R17, R18, R20, R21, R23, and R24 act as series resistors with resistance values ​​in the 100Ω range. When capacitor C3 is at a low level, pin 7 of U3 outputs a low level. At this time, the discharge circuit of C5 passes through R21 and is connected in parallel with R23 and R22. Since the resistance value of R23 is much smaller than that of R22, the discharge time of resistor R22 can be ignored. Similarly, the delay between EN4 and EN5 power-off times is: 2.3*(R18+R20)*C7; the delay between EN3 and EN4 power-off times is: 2.3*(R14+R17)*C9; the delay between EN2 and EN3 power-off times is: 2.3*(R11+R13)*C11; and the delay between EN1 and EN2 power-off times is: 2.3*(R8+R10)*C13. It is important to note that the sum of all EN signal intervals must be less than the time U3 can operate normally during the VDD power-off process.

[0080] Figure 3 The circuit shown is a pure hardware design and does not involve programmable devices such as CPLDs. Therefore, this circuit has low cost, high reliability, and flexible configuration parameters, making it suitable for all complex devices with timing requirements, such as CPUs and FPGAs.

[0081] This application also provides a power supply system, which may include a multi-power supply power-on / off timing control circuit as described in any of the preceding descriptions.

[0082] This application also provides a method for controlling the power-on and power-off timing of multiple power supplies, which can control the power-on and power-off timing of the processor device through a multi-power supply power-on and power-off timing control circuit as described in any of the preceding descriptions.

[0083] This application also provides an electronic device that may include at least one unit or module that can be used to perform the multi-power supply power-on / off timing control method described above.

[0084] This application also provides an electronic device. For example... Figure 4As shown, the electronic device 400 includes: at least one processor 401, a memory 402, and a computer program 403 stored in the memory 402 and executable on the at least one processor 401. When the processor 401 executes the computer program 403, it implements the method provided in this application.

[0085] For example, computer program 403 may be divided into one or more modules / units, one or more of which are stored in memory 402 and executed by processor 401 to complete this application. One or more modules / units may be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of the computer program in electronic device 400.

[0086] Those skilled in the art will understand that Figure 4 This is merely an example of electronic device 400 and does not constitute a limitation on electronic devices. It may include more or fewer components than shown, or combine certain components, or different components. For example, electronic device 400 may also include input / output devices, network access devices, buses, etc.

[0087] Processor 401 can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor.

[0088] The memory 402 can be an internal storage unit of the electronic device 400, such as a hard disk or RAM of the electronic device 400. The memory 402 can also be an external storage device of the electronic device 400, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., equipped on the electronic device 400. Furthermore, the memory 402 can include both internal storage units and external storage devices of the electronic device 400. The memory 402 is used to store computer programs and other programs and data required by the electronic device 400. The memory 402 can also be used to temporarily store data that has been output or will be output.

[0089] The electronic device 400 provided in this embodiment can execute the above method embodiment, and its implementation principle and technical effect are similar, so it will not be described again here.

[0090] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, can implement the steps in the above-described multi-power supply power-on / off timing control method.

[0091] This application also provides a computer program product that, when run on an electronic device, enables the electronic device to perform the steps in the above-described multi-power supply power-on / off timing control method.

[0092] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the above method embodiments of this application can be implemented by a computer program instructing related hardware. This computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or some intermediate form. The computer-readable medium can include at least: any entity or device capable of carrying the computer program code to a photographic device / electronic device, a recording medium, a computer memory, ROM (read-only memory), RAM (random access memory), CD-ROM (compact disc read-only memory), magnetic tape, floppy disk, and optical data storage devices. The computer-readable storage medium mentioned in this application can be a non-volatile storage medium; in other words, it can be a non-transient storage medium.

[0093] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0094] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0095] In the embodiments provided in this application, it should be understood that the disclosed apparatus / device and method can be implemented in other ways. For example, the apparatus / device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0096] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0097] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0098] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0099] Furthermore, in the description of this application and the appended claims, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0100] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A multi-channel power-on / off timing control circuit, characterized in that, This includes a multi-power supply circuit, a system power supply voltage detection circuit, a reset circuit, a power-on / off state selection circuit, and a multi-power supply timing control circuit; The multiple power supply loop is used to enable the processor device; The system power supply voltage detection circuit is used to determine whether the voltage of the system power supply of the processor device is greater than a first threshold. The input terminal of the system power supply voltage detection circuit is connected to the system power supply, and the output terminal of the system power supply voltage detection circuit is connected to the first input terminal of the power-on / off state selection circuit. The system power supply voltage detection circuit includes a comparator and a reference voltage circuit. The first input terminal of the comparator is connected to the reference voltage circuit, the second input terminal of the comparator is connected to the system power supply, and the output terminal of the comparator is connected to the first input terminal of the power-on / off state selection circuit. The first threshold is determined based on the reference voltage of the reference voltage circuit. The comparator outputs a high level when the voltage of the system power supply is greater than the first threshold, and outputs a low level otherwise. The reset circuit is used to control the restart of the processor device. The input terminal of the reset circuit is connected to the output terminal of the processor device, and the output terminal of the reset circuit is connected to the second input terminal of the power-on / off state selection circuit. The power-on / off state selection circuit is used to determine the power-on / off state of the processor device. When the voltage is greater than the first threshold and the reset circuit does not control the processor device to restart, the processor device is in the power-on state. When the voltage is not greater than the first threshold or the reset circuit controls the processor device to restart, the processor device is in the power-off state. The output terminal of the power-on / off state selection circuit is connected to the input terminal of the multi-channel power supply timing control circuit. The multi-power supply timing control loop is used to control the power-on and power-off sequence of the multi-power supply loop according to the power-on and power-off states. In the power-on state, the multi-power supply timing control loop controls the multi-power supply loop to power on in a predetermined order, and conversely, the multi-power supply timing control loop controls the multi-power supply loop to power off in a predetermined order. The output terminal of the multi-power supply timing control loop is connected to the input terminal of the multi-power supply loop.

2. The circuit according to claim 1, characterized in that, The hysteresis of the comparator is less than the second threshold, the operating voltage of the comparator is less than the third threshold, and the operating voltage of the reference voltage circuit is less than the fourth threshold.

3. The circuit according to claim 2, characterized in that, The reset circuit includes a watchdog circuit, which outputs a low level when controlling the processor device to restart, and outputs a high level when not controlling the processor device to restart.

4. The circuit according to claim 3, characterized in that, The power-on / off state selection circuit includes an AND gate circuit, which outputs a high level when both the comparator and the watchdog circuit output a high level, and outputs a low level otherwise.

5. The circuit according to claim 4, characterized in that, The multi-power supply timing control loop includes a bidirectional buffer. When the AND gate outputs a high level, the bidirectional buffer outputs an enable signal to control the multi-power supply loop to power on in a predetermined sequence. Conversely, when the AND gate outputs a low level, the bidirectional buffer outputs an enable signal to control the multi-power supply loop to power off in a predetermined sequence.

6. The circuit according to claim 5, characterized in that, The multi-power supply timing control loop includes a bidirectional buffer.

7. The circuit according to claim 5, characterized in that, The multi-power supply timing control loop includes two bidirectional buffers, and the power-on and power-off timings of the two bidirectional buffers are independent of each other.

8. The circuit according to claim 6 or 7, characterized in that, The time required for the multiple power supply loop to enable the processor device is less than the time it takes for the multiple power supply loop to operate normally during the power-off process of the system power supply.

9. A method for controlling the power-on / off sequence of multiple power supplies, characterized in that, The power-on / off timing of the processor device is controlled by the multi-power supply power-on / off timing control circuit as described in any one of claims 1-8.

Images