Reconfigurable double-layer analog in-memory computing architecture and analog part accumulation summation circuit

Abstract

The invention discloses a reconfigurable double-layer simulation in-memory computing architecture and a simulation part accumulation summation circuit. The reconfigurable double-layer analog in-memory computing architecture is simultaneously suitable for single-layer product accumulation computation and double-layer product accumulation computation through the design of a double-layer structure, in the double-layer product accumulation computation, a first CIM layer and a second CIM layer are communicated through an analog line mode, analog-to-digital conversion, external storage access and digital-to-analog conversion between the two layers are reduced, and the computing efficiency is improved. And the method has relatively good calculation efficiency and energy efficiency performance. The analog part accumulation and summation circuit performs sampling and summation on data by using the reset time of the analog-to-digital converter, so that the in-memory calculation efficiency is effectively improved, and meanwhile, the use area of a chip and the energy consumption of the circuit are reduced. On the whole, the calculation efficiency and the area efficiency of the in-memory calculation system are improved, and the requirements of large-scale data processing and complex model calculation can be better met; and meanwhile, the energy consumption demand is also reduced, and an energy-saving and environment-friendly calculation mode can be realized.

Description

Technical Field

[0001] The present invention relates to the field of in-memory computing technology, and in particular to a reconfigurable double-layer analog in-memory computing architecture and an analog partial cumulative summation circuit. Background Art

[0002] With the rapid advancement of computer technology, computing power and energy efficiency have become important indicators for measuring the performance of computing systems. Modern applications such as machine learning, big data processing, and high-performance computing require processing massive amounts of data and running complex models, which places higher demands on the efficiency and energy consumption of computing systems. When traditional computing systems handle such tasks, performance bottlenecks are becoming increasingly significant due to their inherent limitations, such as high energy consumption, low computing and readout efficiency, and frequent external storage access. Therefore, in order to meet these challenges, Computing In-Memory (CIM) has gradually gained attention as an innovative technical path and has become a hot topic in current research.

[0003] In-memory computing reduces the distance and frequency of data transmission by integrating computing units inside or near the memory, thereby improving computing efficiency and reducing energy consumption. However, the traditional single-layer fixed-length memory computing structure has many shortcomings, especially in terms of computing unit utilization and readout circuit efficiency. This structure limits the ability of parallel computing and increases dependence on external storage, further affecting overall performance.

[0004] In addition, the analog to digital converter (ADC) in the readout circuit has a long reset time, which not only increases the delay but also greatly reduces the efficiency in high-speed, high-precision data processing scenarios, limiting the potential of in-memory computing. Summary of the invention

[0005] In order to improve the efficiency of in-memory computing, an embodiment of the present invention provides a reconfigurable double-layer analog in-memory computing architecture and an analog partial accumulation and summation circuit.

[0006] A first aspect of the present invention provides a reconfigurable double-layer analog in-memory computing architecture, comprising a first CIM layer and a second CIM layer; wherein the first CIM layer is provided with a plurality of computing cores, each computing core comprising a first SRAM weight memory and a plurality of programmable capacitive digital-to-analog converters, and the second CIM layer is provided with a plurality of computing cores, each computing core comprising a second SRAM weight memory and a plurality of computing units; The in-memory computing architecture has a single-layer computing mode and a double-layer computing mode; In the single-layer computing mode, the first CIM layer is used to perform input activation based on a capacitive digital-to-analog converter, and the second CIM layer is used to perform multiplication and accumulation calculations; In the dual-layer calculation mode, the first CIM layer is used to perform depth-level multiplication-addition calculations, and the second CIM layer is used to perform point-level multiplication-addition calculations.

[0007] Furthermore, in a single-layer computing mode, the multiple programmable capacitive digital-to-analog converters of all computing cores of the first CIM layer act as capacitive digital-to-analog converters, and by adjusting the on and off of each programmable capacitive digital-to-analog converter, the input signal is converted from a digital signal to an analog signal and output to the second CIM layer; the computing unit of the second CIM layer performs multiplication and addition calculations according to the weights of the second SRAM weight memory to obtain the analog part accumulation and summation result output.

[0008] Furthermore, the analog signal output by the first CIM layer is transmitted to the second CIM layer through an analog line; and the analog line is controlled by a ReLU decision unit.

[0009] Further, in the dual-layer calculation mode, the depth multiplication and accumulation calculation of the first CIM layer specifically includes the following steps: Allocate computational weights to the programmable capacitive digital-to-analog converter of each computational core of the first CIM layer through a first SRAM weight memory; The calculation cores of the first CIM layer are combined into an n×n form, and the input signals are multiplied and accumulated to obtain analog signals; After the depth multiplication and accumulation calculation of the first CIM layer is completed, the analog layer activation start signal is sent to the analog line through the ReLU decision unit to transmit the analog signal of the first CIM layer to the second CIM layer; The point-level multiplication accumulation calculation for the second CIM layer specifically includes the following steps: Allocate computational weights to the programmable capacitive digital-to-analog converter of each computational core of the second CIM layer through a second SRAM weight memory; In the second CIM layer, a 1×1 calculation core is used to perform multiplication and accumulation calculations on the analog signal to obtain an analog partial accumulation and summation result output.

[0010] Furthermore, the SRAM weight memory of the first CIM layer and the SRAM weight memory of the second CIM layer have the same weight allocation strategy; the first CIM layer and the second CIM layer use a global bit line decoder and a global word line decoder to perform decoding operations.

[0011] The second aspect of the present invention provides an analog partial cumulative summation circuit, which is used to process the analog partial cumulative summation results output by a reconfigurable double-layer analog in-memory computing architecture described in the first aspect, and includes a first capacitor sampling array, a second capacitor sampling array and an on-chip clock generator; wherein the on-chip clock generator is used to control the working timing of the first capacitor sampling array and the second capacitor sampling array, the first capacitor sampling array is used to sample the analog partial cumulative summation results, and the second capacitor sampling array is used to sum the sampling results of the first capacitor sampling array and output them to the analog-to-digital converter for reading.

[0012] Furthermore, the first capacitor sampling array and the second capacitor sampling array are respectively composed of a plurality of sampling capacitors, and the number of the sampling capacitors corresponds to the number of output channels of the accumulated summation result of the analog part.

[0013] Furthermore, the sampling capacitor is an analog part accumulating summing capacitor.

[0014] Furthermore, the first capacitor sampling array and the second capacitor sampling array do not stop sampling and summing during the reset of the analog-to-digital converter; after the reset of the analog-to-digital converter is completed, the summation result of the second capacitor sampling array is output to the analog-to-digital converter for reading.

[0015] Furthermore, the on-chip clock generator controls the working timing of the first capacitor sampling array and the second capacitor sampling array according to the working timing of the reconfigurable double-layer analog in-memory computing architecture.

[0016] The embodiments of the present invention have the following beneficial effects: the reconfigurable double-layer analog in-memory computing architecture provided by the present invention is suitable for both single-layer multiplication and accumulation calculations and double-layer multiplication and accumulation calculations through the design of a two-layer structure. In the double-layer multiplication and accumulation calculations, the first CIM layer and the second CIM layer are connected by analog lines, which reduces the analog-to-digital conversion, external storage access and digital-to-analog conversion between the two layers, and has good computing efficiency and energy efficiency. The analog partial accumulation and summation circuit provided by the present invention utilizes the reset time of the analog-to-digital converter to sample and sum the data, effectively improving the in-memory computing efficiency, while reducing the chip usage area and circuit energy consumption. Overall, the present invention improves the computing efficiency and area efficiency of the in-memory computing system, and can better meet the needs of large-scale data processing and complex model calculations; at the same time, it also reduces energy consumption requirements, which helps to achieve an energy-saving and environmentally friendly computing mode.

[0017] Additional aspects and advantages of the present invention will be given in part in the following description, and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 It is a schematic diagram of the overall implementation of the reconfigurable double-layer analog memory computing architecture and the analog part accumulation and summation circuit of the present invention.

[0020] Figure 2 It is a schematic diagram of the internal circuit of the weight calculation module in the reconfigurable double-layer analog in-memory computing architecture of the present invention.

[0021] Figure 3 It is a schematic diagram of the internal circuit structure of the first CIM layer in the reconfigurable double-layer analog in-memory computing architecture of the present invention.

[0022] Figure 4 It is a schematic diagram of the logic operation of the first CIM layer in the reconfigurable double-layer analog in-memory computing architecture of the present invention.

[0023] Figure 5 It is a schematic diagram of the output timing of the first CIM layer in the reconfigurable double-layer analog in-memory computing architecture of the present invention.

[0024] Figure 6 It is a schematic diagram of the digital-to-analog conversion effect of the first CIM layer in the reconfigurable double-layer analog in-memory computing architecture of the present invention.

[0025] Figure 7 It is a schematic diagram of the internal circuit structure of the second CIM layer in the reconfigurable double-layer analog in-memory computing architecture of the present invention.

[0026] Figure 8 It is a schematic diagram of the internal circuit structure of the second CIM layer computing unit in the reconfigurable double-layer analog in-memory computing architecture of the present invention.

[0027] Fig. 9 It is a schematic diagram of the computing effect of the reconfigurable double-layer analog in-memory computing architecture in the double-layer computing mode of the present invention.

[0028] Fig.10 It is a schematic diagram of the computing efficiency of the reconfigurable double-layer analog in-memory computing architecture in the double-layer computing mode of the present invention.

[0029] Fig.11 It is a schematic diagram of EMA consumption of the first CIM layer in the double-layer computing mode of the reconfigurable double-layer analog in-memory computing architecture of the present invention.

[0030] Fig.12It is a schematic diagram of EMA consumption of the second CIM layer in the double-layer computing mode of the reconfigurable double-layer analog in-memory computing architecture of the present invention.

[0031] Fig.13 It is a circuit structure schematic diagram of the analog partial cumulative summing circuit of the present invention.

[0032] Fig.14 It is a schematic diagram of the effect of configuring the sampling memory of the analog part accumulative summation circuit of the present invention according to the number of channels of the reconfigurable double-layer analog memory computing architecture.

[0033] Fig.15 It is a schematic diagram of the working timing of the analog partial cumulative summing circuit of the present invention. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0035] like Figure 1 As shown, the present invention aims to provide a reconfigurable double-layer analog in-memory computing architecture and an analog partial accumulation and summation circuit, which receives a digital signal from a reading bit line driver (Reading Bit Line Driver) through the reconfigurable double-layer analog in-memory computing architecture to perform MAC (Multiply Accumulate); the calculation result is input into the analog partial accumulation and summation (Analog Partial Sum, APS) circuit for processing and then read out through ADC.

[0036] The reconfigurable double-layer analog in-memory computing architecture and the analog partial accumulation and summation circuit of the embodiment of the present invention are respectively described below.

[0037] Reconfigurable double-layer analog in-memory computing architecture: The reconfigurable double-layer analog in-memory computing architecture in an embodiment of the present invention includes a first CIM layer and a second CIM layer; wherein the first CIM layer is provided with multiple computing cores, each computing core includes a first SRAM weight memory and multiple programmable capacitive digital-to-analog converters, and the second CIM layer is provided with multiple computing cores, each computing core includes a second SRAM weight memory and multiple computing units.

[0038] The SRAM weight memory used in the present invention is 9 groups of local 4-bit weight memory, and the internal structure is as follows: Figure 2As shown. The storage unit is an SRAM unit (Static Random-Access Memory), and the SRAM units in the same group have their own local word lines (Local Word Line, LWL), and share the global bit line (Global Bit Line, GWL) with the SRAM units in other groups. In the embodiment of the present invention, the SRAM weight memories of the first CIM layer and the second CIM layer are set to have the same weight allocation logic, that is, double-layer weight stationary, to reduce the EMR (External Memory Access) consumption of the weight parameters.

[0039] In the embodiment of the present invention, the first CIM layer is configured to have 32 computing cores, and the internal circuit structure of each computing core is as follows: Figure 3 It includes a digital logic unit and a programmable CDACs (Capacitive Digital-to-Analog Converters). The digital logic unit performs weight distribution in the double-layer calculation and is not used in the single-layer calculation. The specific schematic diagram is shown in Figure 4 As shown. The capacitive digital-to-analog converter plays a role in digital-to-analog conversion in single-layer calculations, and outputs high-precision analog voltage signals to the second CIM layer. Specifically, the CDACs are arranged in an array in the first CIM layer, and each CDAC is connected to a different reference voltage or ground through weight distribution. The charges stored in the CDAC array are proportionally superimposed to form an analog signal output. The timing of the analog signal output is shown in Figure 5 As shown, the digital-to-analog conversion effect is as follows Figure 6 As shown, it can be seen that the digital-to-analog conversion effect of the first CIM layer in the embodiment of the present invention can save 15.56% of the chip usage area compared to setting up an additional digital-to-analog conversion circuit.

[0040] The first CIM layer and the second CIM layer are directly connected using analog lines, so AD data conversion, EMA and DA data conversion between the two layers are possible. The specific communication timing is achieved by the on-chip clock generator controlling the ReLU decision unit, so that the calculation results of the two layers are synchronously communicated with the analog part of the cumulative summation circuit. Specifically, in the two-layer calculation mode, after the first CIM layer completes the calculation, the analog inter-layer activation is performed, and the in-memory calculation of the second CIM layer is started. The two-layer calculation and the analog inter-layer activation are completed in the same clock cycle.

[0041] The internal circuit structure of the second CIM layer is as follows Figure 7 As shown, it includes multiple computing units, and the internal structure of each computing unit is as follows Figure 8In single-layer computing, the second CIM layer is used to perform conventional MAC operations, and an appropriate number of computing units are configured to participate in the operation according to the number of input channels.

[0042] In the embodiment of the present invention, the first CIM layer and the second CIM layer share the global bit line and global word line decoders to improve resource utilization.

[0043] In the dual-layer computing mode, the first CIM layer is configured as a depth computing layer, and the second CIM layer is configured as a point computing layer, so that the in-memory computing architecture of the embodiment of the present invention can implement a depthwise separable convolution operation (Depthwise Separable Convolution), and the effect is as follows: Fig. 9 shown.

[0044] In the deep computing layer, each input channel is processed using a 3×3 computing core. Each computing core performs a MAC operation with the element at the corresponding position of the input channel to generate a single-channel output feature map. The output feature maps of all computing cores are stacked to form a multi-channel output, which is converted into analog line voltage through CDAC and transmitted to the point layer computing layer.

[0045] In the point-level computation layer, a convolution operation is performed on all channels using a 1×1 computation kernel. For each position in the multi-channel output, the values ​​of all input channels are MAC-ed with the 1×1 convolution kernel to produce a new channel value.

[0046] The effect of the two-layer computing model is as follows Fig.10 , 11 As shown in Figure 12, taking the in-memory computing of the MobileNet-V2 neural network as an example, the reconfigurable double-layer analog in-memory computing architecture of the embodiment of the present invention has higher energy efficiency (2569.3TOPS / W) and area efficiency (471.7TOPS / mm²) in the double-layer mode, while the EMA of the depth computing layer and the point computing layer are reduced, especially the EMA of the point computing layer is reduced to 36.84%. On the other hand, the reconfigurable double-layer analog in-memory computing architecture of the embodiment of the present invention can still maintain high energy efficiency (2222.9TOPS / W) and area efficiency (196.1TOPS / mm²) in the single-layer mode.

[0047] The reconfigurable two-layer analog in-memory computing architecture of the embodiment of the present invention can be configured as a single-layer computing mode based on the two-layer computing mode to meet the conventional MAC computing requirements of the non-separable layer and realize any MAC-related network architecture requirements, while improving input accuracy and reducing chip area occupancy in the single-layer mode.

[0048] Analog partial cumulative summation circuit: The analog partial cumulative summation circuit of the embodiment of the present invention is used to process the output of the reconfigurable double-layer analog in-memory computing architecture before the analog-to-digital converter (ADC). Compared with the high-speed in-memory computing architecture, the ADC needs a period of time to reset after performing an analog-to-digital conversion, so the readout speed of the ADC is slow. The embodiment of the present invention samples and accumulates the output of the in-memory computing architecture through the analog partial cumulative summation circuit, thereby avoiding the existence of the idle state of the in-memory computing architecture and the ADC, and improving the working efficiency of the in-memory computing architecture and the ADC through pipeline.

[0049] The circuit structure of the analog partial accumulation and summation circuit is as follows Fig.13 As shown, it includes 2 groups of capacitor sampling arrays, each group of arrays includes 9 sampling capacitors, which work together to achieve the function of accurate sampling / accumulation and summation of the MAC partial results of high-speed calculation. Specifically, one group of capacitor sampling arrays performs data sampling of the timing partial MAC results, obtains multiple VMAC (analog voltage signal output by the in-memory computing architecture) samples, and stores them in the APS capacitor to ensure the stability and accuracy of the signal. Another group of capacitor sampling arrays is used for accumulation and summation and sent to the ADC for reading. Through the on-chip clock generator and the 9 groups of memories stored in the first CIM layer and the second CIM layer in the in-memory computing architecture and other computing auxiliary circuits, the utilization rate and area efficiency of the CIM chip are jointly improved.

[0050] like Fig.14 As shown, each capacitor sampling array in the embodiment of the present invention can store up to 9 VMAC samples, effectively supporting the reconfigurable core size from 1×32 to 9×32, and improving the versatility and adaptability of the circuit. The working timing of the circuit is shown in FIG. Fig.15 As shown, during the ADC reset period, the embodiment of the present invention can control the capacitor sampling array to perform multiple sampling calculations, so the unit area efficiency is improved by up to 9 times compared with the traditional design.

[0051] In summary, the reconfigurable double-layer analog in-memory computing architecture and the analog partial accumulation and summation circuit of the present invention improve the computing efficiency and area efficiency of the storage and computing system, can better meet the needs of large-scale data processing and complex model calculations, and have important practical value and broad application prospects.

[0052] Those skilled in the art will appreciate that the modules in the devices in the embodiments of the present invention may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments of the present invention may be combined into one module or unit or component, and in addition they may be divided into a plurality of submodules or subunits or subcomponents. Except that at least some of such features and / or processes or units are mutually exclusive, all features disclosed in this specification (including the corresponding claims, abstracts and drawings) and all processes or units of any method or device disclosed in this manner may be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the corresponding claims, abstracts and drawings) may be replaced by an alternative feature providing the same, equivalent or similar purpose.

[0053] Through the description of the above implementation methods, technical personnel in the relevant field can understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0054] In addition, each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other. In particular, for embodiments such as devices and equipment, since they are basically similar to method embodiments, the relevant parts can refer to the partial description of the method embodiments. The embodiments of the devices and equipment described above are merely schematic, wherein the modules, units, etc. described as separate components may or may not be physically separated, that is, they may be located in one place, or they may be distributed in multiple places, such as nodes of a system network. Specifically, some or all of the modules and units may be selected according to actual needs to achieve the purpose of the above-mentioned embodiment scheme. Those skilled in the art can understand and implement it without paying creative labor.

[0055] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0056] In addition, the terms "first", "second", etc. used in the embodiments of the present invention are only used for descriptive purposes and should not be understood as indicating or implying relative importance, or implicitly indicating the number of technical features indicated in the present embodiment. Therefore, the features defined by the terms "first", "second", etc. in the embodiments of the present invention can explicitly or implicitly indicate that the embodiment includes at least one of the features. In the description of the present invention, the word "multiple" means at least two or two or more, such as two, three, four, etc., unless otherwise clearly and specifically defined in the embodiments.

[0057] In the embodiments of the present invention, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element. In addition, components, features, and elements with the same name in different embodiments of the present invention may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context in the specific embodiment.

[0058] Although embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and cannot be construed as limitations of the present invention, and those of ordinary skill in the art may change, modify, replace and modify the above embodiments within the scope of the present invention. Those skilled in the art will readily come to think of other embodiments of the present invention after considering the specification and practicing the present invention. This application is intended to cover any variations, uses or adaptations of the present invention, which follow the general principles of the present invention and include common knowledge or customary technical means in the art that are not disclosed in the present invention. The specification and embodiments are intended to be exemplary only, and the true scope and spirit of the present invention are indicated by the following claims.

Claims

1. A reconfigurable two-layer analog in-memory computing architecture, characterized in that: It includes a first CIM layer and a second CIM layer; wherein the first CIM layer is provided with a plurality of computing cores, each computing core includes a first SRAM weight memory and a plurality of programmable capacitive digital-to-analog converters, and the second CIM layer is provided with a plurality of computing cores, each computing core includes a second SRAM weight memory and a plurality of computing units; The in-memory computing architecture has a single-layer computing mode and a double-layer computing mode; In the single-layer computing mode, the first CIM layer is used to perform input activation based on a capacitive digital-to-analog converter, and the second CIM layer is used to perform multiplication and accumulation calculations; In the dual-layer calculation mode, the first CIM layer is used to perform depth-level multiplication-addition calculations, and the second CIM layer is used to perform point-level multiplication-addition calculations.

2. A reconfigurable two-layer analog in-memory computing architecture according to claim 1, characterized in that: In the single-layer computing mode, the multiple programmable capacitive digital-to-analog converters of all computing cores of the first CIM layer act as capacitive digital-to-analog converters, and the input signal is converted from a digital signal to an analog signal and output to the second CIM layer by adjusting the on and off of each programmable capacitive digital-to-analog converter; the computing unit of the second CIM layer performs multiplication and addition calculations according to the weights of the second SRAM weight memory to obtain the analog part cumulative summation result output.

3. The reconfigurable two-layer analog in-memory computing architecture according to claim 1, characterized in that: The analog signal output by the first CIM layer is transmitted to the second CIM layer through an analog line; and the analog line is controlled by a ReLU decision unit.

4. The reconfigurable two-layer analog in-memory computing architecture according to claim 3, characterized in that: In the dual-layer calculation mode, the depth multiplication and accumulation calculation of the first CIM layer specifically includes the following steps: Allocate computational weights to the programmable capacitive digital-to-analog converter of each computational core of the first CIM layer through a first SRAM weight memory; The calculation cores of the first CIM layer are combined into an n×n form, and the input signals are multiplied and accumulated to obtain analog signals; After the depth multiplication and accumulation calculation of the first CIM layer is completed, the analog layer activation start signal is sent to the analog line through the ReLU decision unit to transmit the analog signal of the first CIM layer to the second CIM layer; The point-level multiplication accumulation calculation for the second CIM layer specifically includes the following steps: Allocate computational weights to the programmable capacitive digital-to-analog converter of each computational core of the second CIM layer through a second SRAM weight memory; In the second CIM layer, a 1×1 calculation core is used to perform multiplication and accumulation calculations on the analog signal to obtain an analog partial accumulation and summation result output.

5. The reconfigurable two-layer analog in-memory computing architecture according to claim 4, characterized in that: The SRAM weight memory of the first CIM layer and the SRAM weight memory of the second CIM layer have the same weight allocation strategy; the first CIM layer and the second CIM layer use a global bit line decoder and a global word line decoder to perform decoding operations.

6. An analog partial cumulative summation circuit for processing analog partial cumulative summation results output by a reconfigurable double-layer analog in-memory computing architecture as claimed in any one of claims 1 to 5, characterized in that: It includes a first capacitor sampling array, a second capacitor sampling array and an on-chip clock generator; wherein the on-chip clock generator is used to control the working timing of the first capacitor sampling array and the second capacitor sampling array, the first capacitor sampling array is used to sample the accumulated summation result of the analog part, and the second capacitor sampling array is used to sum the sampling results of the first capacitor sampling array and output them to the analog-to-digital converter for reading.

7. The analog partial cumulative summation circuit according to claim 6, characterized in that: The first capacitor sampling array and the second capacitor sampling array are respectively composed of a plurality of sampling capacitors, and the number of the sampling capacitors corresponds to the number of output channels of the accumulated summation result of the analog part.

8. The analog partial cumulative summation circuit according to claim 7, characterized in that: The sampling capacitor is an analog part accumulating summing capacitor.

9. The analog partial cumulative summation circuit according to claim 6, characterized in that: The first capacitor sampling array and the second capacitor sampling array do not stop sampling and summing during the reset of the analog-to-digital converter; after the reset of the analog-to-digital converter is completed, the summation result of the second capacitor sampling array is output to the analog-to-digital converter for reading.

10. The analog partial cumulative summation circuit according to claim 6, characterized in that: The on-chip clock generator controls the working timing of the first capacitor sampling array and the second capacitor sampling array according to the working timing of the reconfigurable double-layer analog in-memory computing architecture.

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