Instruction compiling method and device, compiler and computing equipment

Abstract

The invention discloses an instruction compiling method and device, a compiler and computing equipment. The method comprises the steps that a to-be-compiled object containing multiple instructions is obtained, the multiple instructions comprise labeled target variables and labeled target branch instructions, and the target branch instructions comprise target variables; the to-be-compiled object is compiled to obtain an executable program, the executable program comprises an assignment instruction of the target variable, a self-modification instruction, a target branch instruction and other compiling instructions, and the self-modification instruction is used for reducing the complexity of the target branch instruction based on assignment of the target variable. The technical problem that performance loss is caused when branch instructions are executed for multiple times in the prior art is solved.

Description

Technical Field

[0001] The present application relates to the field of processors, and in particular, to an instruction compilation method, apparatus, compiler and computing device. Background Art

[0002] During program execution, a large number of operating parameters are specified by the user and written into variables. When variables are referenced by conditional judgments in branch instructions, for hot branch instructions, the branch instructions need to be executed multiple times, resulting in a large performance loss.

[0003] To address the above-mentioned problems, no effective solution has been proposed yet. Summary of the invention

[0004] The embodiments of the present application provide an instruction compilation method, apparatus, compiler and computing device to at least solve the technical problem in the related art of performance loss caused by multiple executions of branch instructions.

[0005] According to one aspect of an embodiment of the present application, an instruction compilation method is provided, comprising: obtaining an object to be compiled comprising multiple instructions, wherein the multiple instructions include a marked target variable and a marked target branch instruction, wherein the target branch instruction includes the target variable; compiling the object to be compiled to obtain an executable program, wherein the executable program includes: an assignment instruction of the target variable, a self-modification instruction, a target branch instruction and other compilation instructions, the self-modification instruction being used to reduce the complexity of the target branch instruction based on the assignment of the target variable.

[0006] Optionally, the target branch instruction is a hot branch instruction that is executed more than a predetermined number of times in the source program.

[0007] Optionally, reducing the complexity of the target branch instruction includes: modifying the target branch instruction.

[0008] Optionally, modifying the target branch instruction includes: replacing the target branch instruction with a no-operation instruction.

[0009] Optionally, reducing the complexity of the target branch instruction includes: replacing the target variable in the target branch instruction with a constant, wherein the constant is the assignment.

[0010] Optionally, the target variable includes at least one of the following: the length of a vector in a predetermined vector instruction set, whether the simulator generates instruction tracing, and whether the simulator generates data tracing.

[0011] According to another aspect of an embodiment of the present application, an instruction compilation device is also provided, including: an acquisition module, used to acquire an object to be compiled containing multiple instructions, wherein the multiple instructions include a marked target variable and a marked target branch instruction, wherein the target branch instruction includes the target variable; a compilation module, used to compile the object to be compiled to obtain an executable program, wherein the executable program includes: assignment instructions of the target variable, self-modification instructions, target branch instructions and other compilation instructions, and the self-modification instructions are used to reduce the complexity of the target branch instructions based on the assignment of the target variable.

[0012] According to another aspect of an embodiment of the present application, a compiler is also provided, including: a compilation unit, used to convert a source file into an intermediate file, the intermediate file including the object to be compiled; optimizing the intermediate file; converting the optimized intermediate file into an assembly file; converting the assembly file into a binary file; and merging multiple binary files into a program; the compilation unit is also used to convert the object to be compiled into the executable program based on the instruction compilation method.

[0013] According to another aspect of an embodiment of the present application, a computing device is further provided, including: a memory storing an executable program; and a processor for running the program, wherein the instruction compilation method in each embodiment of the present application is executed when the program is running.

[0014] According to another aspect of an embodiment of the present application, a computer-readable storage medium is further provided, the computer-readable storage medium including a stored executable program, wherein when the executable program is executed by a processor, the instruction compilation method in each embodiment of the present application is implemented.

[0015] In an embodiment of the present application, a method of marking target variables and marking target branch instructions is adopted. By adopting self-modifying instructions, the complexity of the target branch instructions is reduced based on the assignment of target variables, thereby effectively achieving the technical effect of reducing performance loss when the target branch instructions are executed multiple times, thereby solving the technical problem in the related technology that performance loss is caused when the branch instructions are executed multiple times.

[0016] It is easy to notice that the above general description and the following detailed description are only for the purpose of exemplifying and explaining the present application, and do not constitute a limitation of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0018] Figure 1 It is a hardware structure block diagram of a RISC-V system for implementing an instruction compilation method according to an embodiment of the present application;

[0019] Figure 2 According to an embodiment of the present application, the above Figure 1 Schematic diagram of the RISC-V architecture system on chip (System On Chip, SOC);

[0020] Figure 3 is a flow chart of an instruction compiling method according to an embodiment of the present application;

[0021] Figure 4 is a schematic diagram of an optional annotated code structure according to an implementation manner of the present application;

[0022] Figure 5 is a schematic diagram of the code generated by the compiler when writing variable A after an optional annotation according to an implementation manner of the present application;

[0023] Figure 6 It is a schematic diagram of code generated by the compiler of branch 1 before and after an optional annotation of envcfg according to an embodiment of the present application;

[0024] Figure 7 is a structural block diagram of an instruction compiling device according to an embodiment of the present invention;

[0025] Figure 8 It is a structural block diagram of a computing device according to an embodiment of the present application. DETAILED DESCRIPTION

[0026] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0027] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0028] First, some nouns or terms that appear in the description of the embodiments of the present application are subject to the following explanations:

[0029] Variable: A method of identifying memory units in high-level languages. Variables can be further described by type, life cycle, variability, attributes, and other dimensions.

[0030] Variable attributes: specify special properties of variables, such as memory alignment.

[0031] Hot Instructions: refers to instructions that are frequently accessed or executed during program execution. In a computer program, although there may be a large number of instructions, the execution time is often concentrated on a small number of instructions. These instructions are called hot instructions because of their high execution frequency. When a branch instruction is frequently accessed or executed, it is called a hot branch instruction.

[0032] Self-modifying instructions: refers to machine code instructions that can modify other instructions in the executable program. Self-modifying instructions can be simple data write instructions or complex conditional branch instructions, which are used to dynamically modify the instruction stream according to specific conditions. When a program is run once, the representation of its instructions in memory will be modified, so that the next time the instructions in the same position are run, different behaviors will be exhibited.

[0033] Branch prediction: It is an optimization technology of the processor (Central Processing Unit, CPU). The CPU executes instructions according to the pipeline, and divides the instructions into stages such as instruction fetching, decoding, execution, memory access, and write back. When fetching instructions and encountering a branch, it will not wait for the branch instruction to be executed before executing the next instruction, but will directly fetch the next instruction. However, the branch has two targets, and the specific target needs to be predicted. Whether the prediction is correct can only be known after the branch instruction is executed. If the prediction is correct, you can prepare for the execution of the instruction in advance and let the pipeline continue to work.

[0034] In response to the technical problem of performance loss caused by multiple executions of branch instructions, the relevant technology proposes to solve it through function pointers, that is, by parsing parameters, registering different function pointers to execute different processing logic, and then using this method to avoid branch judgment. However, the method of avoiding branch judgment through function pointers has two disadvantages. First, the cost of function calls itself is relatively high, and converting branches into function processing is usually not worth the cost; second, function pointers bring a large number of indirect function calls, and the prediction rate of indirect function calls is difficult to achieve 100%, and this method does not eliminate data loading instructions. The relevant technology also proposes to use conditional branch processing, but this method will result in redundant data loading instructions and comparison jump instructions, and branch prediction is also difficult to achieve 100%.

[0035] In view of the above-mentioned problems in the related art, an instruction compilation method is provided in an embodiment of the present application. Variables in a program have the typical characteristics of being written only once and referenced in multiple places. Therefore, according to the characteristics that the variable referenced by the branch instruction has the behavior of being written only once, and the writing behavior occurs before the branch reference, the performance loss is reduced by eliminating the branch. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that here.

[0036] It should be noted that the entire life cycle of a program can include three main stages: writing source code, compiling source code to generate an executable program, and executing the executable program. Among them, writing source code is the starting point of software development. Developers use specific programming languages ​​(such as C, C++, Java, Python, etc.) to write source code to implement specific functions or algorithms. The source code may include variables that are written only once and referenced multiple times (i.e., initial variables), and hot branch instructions that reference the variables for conditional judgment (i.e., initial branch instructions). Compiling source code to generate an executable program is performed by a compiler or interpreter. The compiler or interpreter can follow the grammatical rules and semantics of the language to analyze, convert and optimize the source code to generate an executable program or executable file. For the initial variables, compile to generate target variables and storage instructions for the target variables. For the initial branch instructions, compile to generate target branch instructions for conditional judgment and load instructions for assigning values ​​to load target variables for the target branch instructions. The executable program can be executed by the CPU, which completes operations such as reading instructions, decoding, and executing calculations or data flows. When executing the target branch instruction, since the target branch instruction is a hot branch instruction, it will be executed multiple times. Therefore, the target branch instruction and the corresponding load instruction will also be executed multiple times, resulting in performance waste.

[0037] In response to the above problems, the implementation method of the present invention improves the above process. In the source code writing stage, developers can determine which variables are variables that are written only once and referenced multiple times, and are referenced by hot branch instructions as conditional judgments, and determine which branch instructions are hot branch instructions that reference variables and need to be executed multiple times, and mark the determined variables and the determined hot branch instructions. In the stage of compiling source code to generate an executable program, the compiler or interpreter not only compiles the initial variables to generate target variables and assignment instructions for the target variables, compiles the initial branch instructions to generate target branch instructions, but also generates corresponding self-modification instructions after the assignment instructions of the target variables. In the stage of executing the target program, when the above self-modification instructions are executed, the above target branch instructions are modified based on the assignment of the target variables, reducing the complexity of the target branch instructions, thereby reducing the performance loss of executing the above target branch instructions. The following is a detailed explanation.

[0038] The method embodiment provided in Embodiment 1 of the present application can be executed in a RISC-V system, a RISC-V chip or a similar device. Figure 1 FIG. 4 shows a hardware structure block diagram of a RISC-V system for implementing an instruction compilation method. Figure 1 As shown, the RISC-V system can be divided from the bottom layer to the upper layer into a reduced instruction set architecture 101 (including a basic instruction set 101-1 and an extended instruction set 101-2), a hardware layer 102 (including a processor 102-1, a peripheral hardware circuit 102-2, etc.), an interface layer 103, an operating system layer 104 (supporting multiple operating systems 104-1, 104-2, ..., 104-n, such as Linux, FreeSBD, RT-Tread, etc.), a middleware and library layer 105 (including a system library 105-1, an API 105-2 and a middleware service 105-3) and an application layer 106 (including multiple user programs and services 106-1, 106-2, ..., 106-n). The RISC-V system also includes a tool chain 107 from the underlying hardware to the application layer. The tool chain may include a compiler and assembler 107-1, a linker 107-2, a debugger 107-3, a simulator and emulator 107-4, an integrated development environment 107-5, a hardware description language tool 107-6, a performance analysis tool 107-7, and a version control system 107-8, etc.

[0039] The instruction set architecture 101 defines the basic operations and instruction sets supported by the processor 102-1, including a basic instruction set and an extended instruction set, wherein the basic instruction set represents a basic integer instruction set, such as RV32I and RV64I, and the extended instruction set can be floating point, atomic operations, compressed instructions, etc.

[0040] The interface layer 103 includes the specific design of the processor, such as pipeline design, cache structure, execution unit, branch prediction, etc. This layer is the process of mapping abstract instructions to physical hardware.

[0041] The operating system layer 104 is located above the hardware and provides a hardware abstraction layer and management mechanism, so that applications can interact with the hardware through system calls. The operating system is responsible for managing processor resources, memory, device drivers, task scheduling, etc.

[0042] The middleware and library layer 105 provides a rich set of services and interfaces to help applications run more efficiently. For example, the standard library provides functions such as file operations and mathematical calculations, while the middleware can provide complex services such as network communications and graphical user interfaces.

[0043] The application layer 106 uses the functions and services provided by the lower layer to implement specific application logic. These applications can be command line tools, graphical interface applications, server-side services, etc.

[0044] The tool chain 107 is a key component that connects the underlying hardware to the upper-level software. Various tools in the tool chain 107 function at different levels to support the entire process from hardware design to software development, ensuring the consistency and effectiveness of the entire system design.

[0045] It should be noted that the layered design of the RISC-V architecture allows decoupling between different layers, so that each layer can be developed and optimized independently.

[0046] In an optional embodiment, Figure 2 Shown using the above Figure 1 The schematic diagram of the RISC-V architecture system on chip (System On Chip, SOC) is shown in FIG. Figure 2 As shown, the SOC includes at least one RISC-V core 202 (only one is shown in the figure), and the RISC-V core 202 is connected to peripheral devices through a bus 204, including but not limited to ROM 206, RAM 208, timer 210, UART (Universal Asynchronous Receiver / Transmitter) 212, GPIO (General Purpose Input / Output) 214, SPI (Serial Peripheral Interface Bus) 216, etc.

[0047] Under the above operating environment, this application provides Figure 3 The instruction compilation method shown. Figure 31 is a flow chart of an instruction compilation method according to an embodiment of the present application. Figure 3 As shown, the method comprises the following steps:

[0048] S302, obtaining a to-be-compiled object including a plurality of instructions, wherein the plurality of instructions include marked target variables and marked target branch instructions, wherein the target branch instructions include target variables.

[0049] As an optional embodiment, the execution subject of the method of this embodiment can be multiple subjects, including an instruction compilation device that can be used for instruction compilation, a compiler or interpreter that can be used for instruction compilation, etc.

[0050] As an optional embodiment, when obtaining an object to be compiled containing multiple instructions, the obtained object to be compiled containing multiple instructions includes a marked target variable and a marked target branch instruction, wherein the target branch instruction includes the target variable, that is, the target branch instruction references the target variable. There are many ways to mark the target variable, for example, it can be marked as "write_only_once" based on the special attribute that the target variable is only written once. There are also many ways to mark the target branch instruction, for example, it can be marked as "envcfg".

[0051] As an optional embodiment, the target branch instruction is a hot branch instruction that is executed more than a predetermined number of times in the object to be compiled. Branch instructions that need to be executed multiple times in the object to be compiled can be regarded as hot branch instructions. By taking the hot branch instruction as the target branch instruction and performing subsequent processing, the program execution path can be optimized more accurately, avoiding the optimization of non-hot branch instructions, thereby ensuring the program execution efficiency while reducing the waste of resources in the optimization process.

[0052] S304, compile the object to be compiled to obtain an executable program, wherein the executable program includes: assignment instructions of target variables, self-modification instructions, target branch instructions and other compilation instructions, and the self-modification instructions are used to reduce the complexity of the target branch instructions based on the assignment of the target variables.

[0053] As an optional embodiment, in the process of compiling the object to be compiled, compared with the unmarked compilation process in the related art, the compilation process in the embodiment of the present invention generates not only the compiled assignment instruction but also the self-modification instruction when compiling the assignment instruction of the target variable, generates the compiled target branch instruction when compiling the target branch instruction, and generates other compilation instructions normally when compiling other instructions of the object to be compiled. That is, this compilation process can not only generate a more efficient machine-recognized executable program, but also generate self-modification instructions according to the characteristics of the target variable and the target branch instruction in the object to be compiled, so that the compiled executable program can be optimized according to the actual assignment of the target variable during execution, which can improve the adaptability and execution efficiency of the executable program.

[0054] As an optional embodiment, reducing the complexity of the target branch instruction includes: modifying the target branch instruction. By modifying the target branch instruction based on the assignment of the target variable, the target branch instruction can be modified in a direction of reducing its complexity. The assignment of the target variable can be determined in a variety of ways, for example, based on user input or based on a computer environment in which the program is executed.

[0055] As an optional embodiment, when modifying the target branch instruction, multiple methods can be used. For example, when modifying the target branch instruction, the target branch instruction can be replaced with a no-operation instruction. Since the target variable has been assigned when the self-modification instruction is executed, the execution instruction matching the assignment can be directly executed according to the assignment of the target variable in the target branch instruction that needs to use the target variable for conditional judgment, without executing the target branch instruction. For example, when the above-mentioned target branch instruction is judged only according to the assignment of the target variable, such as a is the marked target variable, if (a == 0) is the marked target branch instruction, and a is assigned to 0, the above-mentioned self-modification instruction modifies the compiled instruction from "Load rega; Beqz reg, Zero_condition" to "Nop; Nop", so that the target branch instruction is replaced with a no-operation instruction, which can avoid executing a branch instruction and a corresponding load instruction every time the target branch instruction is executed, so that the execution instruction matching the assignment can be directly executed according to the assignment of the target variable, which greatly reduces the execution burden of the CPU and improves the execution speed of the program.

[0056] As an optional embodiment, when reducing the complexity of the target branch instruction, multiple methods can be used, for example, the target variable of the target branch instruction can be replaced with a constant, and the constant is an assignment. Since the target variable has been assigned when the self-modifying instruction is executed, in the target branch instruction that needs to use the target variable for conditional judgment, the target variable can be regarded as a constant for judgment based on the assignment of the target variable. For example, when the target branch instruction is judged not only based on the assignment of the target variable, but also based on the assignment of other variables, such as a is the marked target variable, b is the other unmarked variable, if(a+b>5) is the marked target branch instruction, when a is assigned 1, a can be regarded as the constant 1, and if(a+b>5) can be regarded as if(b>4), that is, the self-modifying instruction changes the compiled instruction from "add reg_d,a,b; bgt reg_d,5,great_than_5" to "bgt b,4,great_than_5", thus changing the two instructions of the target branch instruction to one. By replacing the target variable with a constant, the frequent reading and calculation of the assignment of the target variable can be avoided, further improving the efficiency of program execution.

[0057] As an optional embodiment, the target variable is different based on the application scenario of program execution. For example, the target variable may include at least one of the following: the length of the vector in the predetermined vector instruction set, whether the simulator generates instruction tracing, and whether the simulator generates data tracing. In architectures such as RISC-V and ARM, variable-length vector instruction set extensions are introduced. The vector length is a crucial parameter in these variable-length vector instruction sets, which determines the number of elements of vector operations. When developing programs for these architectures, the vector length usually needs to be dynamically determined through host environment detection, for example, through CPUID instructions or preprocessor macro definitions during compilation. This detection result will be written into a variable, namely the length of the vector in the predetermined vector instruction set. This variable will not be changed again during the entire program execution, but will be referenced by multiple functions or program fragments to select the correct vector instruction for processing. By taking the length of the vector in the predetermined vector instruction set as the target variable, the self-modifying instruction can optimize the branch instruction according to the assignment of the target variable during execution, eliminate unnecessary data loading and branch prediction, and thus improve performance.

[0058] In addition, when executing a program, the simulator may need to generate trace records for debugging or analysis. Instruction tracing involves recording the execution of each instruction, while data tracing records the access and modification of data. Due to the large amount of trace data, frequent tracing judgments (i.e., whether to generate a trace) will result in significant performance losses. By using the tracing judgment as the target variable, subsequent program execution can directly determine whether to perform instruction or data tracing records based on the assignment of the target variable. Optimizing branch instructions related to this variable can avoid unnecessary tracing judgments and reduce performance losses.

[0059] Through the above steps, self-modifying instructions are used to process the marked target variables and the marked target branch instructions, so that the self-modifying instructions can reduce the complexity of the target branch instructions when they are executed, thereby significantly reducing the performance loss during program execution and improving the program's operating efficiency. This optimization effect is more obvious, especially in hot branch instructions.

[0060] In combination with the above embodiment and the optional embodiment, an optional implementation is provided. In this optional implementation, a branch instruction compilation optimization method based on variable attribute annotation is proposed, and the method includes the following processing.

[0061] S1, specially mark the variables that store command line parameters / host environment and specify _attribute_(write_only_once).

[0062] S2, for branches that reference variables with the write_only_once attribute, specify the envcfg branch prompt.

[0063] S3, when compiling and linking, for variables with the write_only_once attribute, not only store instructions are generated, but also self-modifying instructions are generated to process the branch instructions in S2 according to the value of the variable. For branches that match the value, the corresponding load instructions and branch instructions will be rewritten as nop instructions (no operation instructions).

[0064] in, Figure 4 is a schematic diagram of an optional annotated code structure according to an implementation method of the present application, such as Figure 4 As shown, variable A is marked with the write_only_once attribute, and branch 1 that references variable A is marked with the envcfg branch prompt as a hotspot branch among multiple branches.

[0065] Figure 5 is a schematic diagram of the code generated by the compiler when writing variable A after an optional annotation according to an implementation mode of the present application, such as Figure 5 As shown, the value of variable A is stored, and conditional judgment is performed based on the value of variable A. Different branch instructions correspond to whether the value of variable A is equal to 0.

[0066] Figure 6 is a schematic diagram of the code generated by the compiler of branch 1 before and after an optional annotation of envcfg according to an embodiment of the present application, such as Figure 6 As shown, before envcfg is marked, for branch 1, the compiler generates a load instruction for loading the value of variable A, a branch instruction for conditional judgment based on the value of variable A, and a branch corresponding to when the value of variable A is not equal to 0 and a branch corresponding to when the value of variable A is equal to 0. After envcfg is marked, for branch 1, the compiler combines the self-modification instruction and no longer generates branch instructions, but generates no-operation instructions. According to the value of variable A, it directly enters the branch corresponding to when the value of variable A is not equal to 0 and the branch corresponding to when the value of variable A is equal to 0.

[0067] The above method can be used for two-branch instructions, where the branch with wrong conditions is no longer executed, and the other branch with correct conditions does not generate branch instructions. It can also be used for multi-branch instructions, as long as the condition judgment of each branch can be calculated through the write_only_once variable or other constant expressions. It can also be used for condition resolution. Even if the condition judgment of the branch cannot be completely solved, only the part that uses the write_only_once variable can be solved to reduce the calculation instructions.

[0068] The above method uses the variable attribute annotation write_only_once and the branch prediction annotation envcfg, and implements write_only_once through self-modifying instructions, which can eliminate specific types of conditional branches, avoid redundant instructions and branch prediction errors caused by branches, and improve the running efficiency of the program. By modifying instructions in situ, avoiding the use of function pointers and function call mechanisms, thereby avoiding on-site save and restore processing such as stack push or stack pop, reducing the cost of program execution; it can also reduce the performance loss caused by host operating environment detection, and in the development of acceleration libraries that pursue better efficiency, it can also achieve one program and multiple runs. In summary, this optional implementation method can improve the efficiency of program execution and reduce performance losses by reducing the complexity of conditional judgment when branch instructions are executed.

[0069] According to an embodiment of the present invention, an instruction compiling device is provided. Figure 7 is a structural block diagram of an instruction compiling device according to an embodiment of the present invention. Figure 7 As shown, the device includes: an acquisition module 702 and a compilation module 704. The device is described below.

[0070] An acquisition module 702 is used to acquire an object to be compiled that includes multiple instructions, wherein the multiple instructions include a marked target variable and a marked target branch instruction, wherein the target branch instruction includes a target variable; a compilation module 704 is connected to the acquisition module 702, and is used to compile the object to be compiled to obtain an executable program, wherein the executable program includes: assignment instructions for target variables, self-modification instructions, target branch instructions and other compilation instructions, and the self-modification instructions are used to reduce the complexity of the target branch instructions based on the assignment of the target variable.

[0071] It should be noted here that the above-mentioned acquisition module 702 and compilation module 704 correspond to steps S302 to S304 in the embodiment, and the instances and application scenarios implemented by multiple modules and corresponding steps are the same, but are not limited to the contents disclosed in the above-mentioned embodiment.

[0072] As an optional embodiment, the above instruction compiling device further includes: the target branch instruction is a hot branch instruction that has been executed more than a predetermined number of times in the object to be compiled.

[0073] As an optional embodiment, the compiling module 704 includes: a modification unit. The modification unit is used to modify the target branch instruction.

[0074] As an optional embodiment, the modification unit includes: a replacement subunit. The replacement subunit is used to replace the target branch instruction with a no-operation instruction.

[0075] As an optional embodiment, the compiling module 704 includes: a replacement unit. The replacement unit is used to replace the target variable of the target branch instruction with a constant, where the constant is an assignment.

[0076] As an optional embodiment, the instruction compilation device further includes: the target variable includes at least one of the following: the length of a vector in a predetermined vector instruction set, whether the simulator generates instruction tracing, and whether the simulator generates data tracing.

[0077] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0078] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0079] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, disk, CD), including a number of instructions for a processor to execute the methods described in each embodiment of the present application.

[0080] An embodiment of the present application may provide a computing device. Figure 8 is a structural block diagram of a computing device according to an embodiment of the present application. Figure 8 As shown, the computing device may include: one or more (only one is shown in the figure) processors 802 , a memory 804 and a peripheral interface 806 , wherein the processor 802 , the memory 804 and the peripheral interface 806 are interconnected via a bus 808 .

[0081] Among them, the memory can be used to store software programs and modules, such as program instructions / modules corresponding to the methods and devices in the embodiments of the present application, and the processor executes various functional applications and data processing by running the software programs and modules stored in the memory, that is, implementing the methods in the above embodiments. The memory may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory may further include a memory remotely arranged relative to the processor, and these remote memories may be connected to the terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0082] The processor can call the information and application programs stored in the memory through the transmission device to execute the methods in various embodiments of the present application.

[0083] A person of ordinary skill in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing the hardware related to the terminal device through a program, and the program can be stored in a computer-readable storage medium, and the storage medium may include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0084] The embodiment of the present application further provides a computer-readable storage medium. Optionally, in this embodiment, the computer-readable storage medium can be used to store the program code executed by the method provided in the above embodiment.

[0085] Optionally, in this embodiment, the above storage medium may be located in any computing device in the computing device group.

[0086] Optionally, in this embodiment, the computer-readable storage medium includes a stored executable program, wherein when the executable program is executed by a processor, the method in each embodiment of the present application is implemented.

[0087] The embodiment of the present application further provides a computer program product. Optionally, in this embodiment, the computer program product may include a computer program, and the computer program implements the method provided in the embodiment when executed by a processor.

[0088] The embodiments of the present application also provide a computer program product. Optionally, the computer program product may include a non-volatile computer-readable storage medium, which may be used to store a computer program, and when the computer program is executed by a processor, the method provided in the embodiments is implemented.

[0089] The embodiment of the present application further provides a computer program. Optionally, in this embodiment, when the computer program is executed by a processor, the method provided in the above embodiment is implemented.

[0090] In the above embodiments of the present application, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0091] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0092] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0093] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0094] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, disk or optical disk and other media that can store program codes.

[0095] The above is only a preferred implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A method for compiling instructions, characterized in that: include: Acquire a to-be-compiled object including a plurality of instructions, wherein the plurality of instructions include a marked target variable and a marked target branch instruction, wherein the target branch instruction includes the target variable; The object to be compiled is compiled to obtain an executable program, wherein the executable program includes: assignment instructions of the target variable, self-modification instructions, target branch instructions and other compilation instructions, and the self-modification instructions are used to reduce the complexity of the target branch instructions based on the assignment of the target variable.

2. The method according to claim 1, characterized in that The target branch instruction is a hot branch instruction that has been executed more than a predetermined number of times in the object to be compiled.

3. The method according to claim 1, characterized in that The reducing the complexity of the target branch instruction comprises: The target branch instruction is modified.

4. The method according to claim 3, characterized in that The modifying the target branch instruction comprises: The target branch instruction is replaced with a no-operation instruction.

5. The method according to claim 1, characterized in that: The reducing the complexity of the target branch instruction comprises: The target variable in the target branch instruction is replaced with a constant, wherein the constant is the assigned value.

6. The method according to any one of claims 1 to 5, characterized in that The target variable includes at least one of the following: the length of a vector in a predetermined vector instruction set, whether the simulator generates instruction tracing, and whether the simulator generates data tracing.

7. An instruction compiling device, characterized in that: include: An acquisition module, used for acquiring an object to be compiled including a plurality of instructions, wherein the plurality of instructions include a marked target variable and a marked target branch instruction, wherein the target branch instruction includes the target variable; A compilation module is used to compile the object to be compiled to obtain an executable program, wherein the executable program includes: assignment instructions of the target variable, self-modification instructions, target branch instructions and other compilation instructions, and the self-modification instructions are used to reduce the complexity of the target branch instructions based on the assignment of the target variable.

8. A compiler, characterized in that include: A compiling unit, used for converting a source file into an intermediate file, wherein the intermediate file includes the object to be compiled; Optimizing the intermediate file; converting the optimized intermediate file into an assembly file; converting the assembly file into a binary file; and merging multiple binary files into programs; The compiling unit is further configured to convert the object to be compiled into the executable program based on the method according to any one of claims 1 to 6.

9. A computing device, characterized in that include: A memory storing an executable program; A processor, used to run the program, wherein the instruction compilation method according to any one of claims 1 to 6 is executed when the program is run.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored executable program, wherein when the executable program is executed by a processor, the instruction compiling method according to any one of claims 1 to 6 is implemented.

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