A memory and a task processing method

Abstract

The present invention provides a memory and a task processing method. The memory includes: a main control module for receiving host tasks; a command queue module for storing and allocating the host tasks; a hardware acceleration module for executing the allocated host tasks. Among them, the command queue module is used to allocate some or all of the host tasks to the hardware acceleration module for execution according to the ability of the hardware acceleration module to execute host tasks, and allocate the remaining unallocated host tasks to the main control module for execution. Through the memory and the task processing method provided by the present invention, the task processing efficiency of the memory can be improved.

Description

Technical Field

[0001] The present invention relates to the field of storage, and particularly to a memory and a task processing method. Background Art

[0002] With the wide application of memories in consumer electronic devices such as smart TVs, set-top boxes, and mobile terminals, the data reliability and stability thereof have become core requirements. The memory consists of a main control module based on the ARM architecture and a NAND Flash memory module. The main control module realizes key functions such as bad block management, garbage collection (GC), performance optimization, and lifespan maintenance of the storage module by running firmware.

[0003] The execution, calculation, and query of various tasks of the existing memory are all processed by the main control module, resulting in an overloaded main control module and delays in some tasks, thereby affecting the performance of the memory. Therefore, there is room for improvement. Summary of the Invention

[0004] An object of the present invention is to provide a memory and a task processing method, which can improve the task processing efficiency of the memory.

[0005] To solve the above technical problems, the present invention is implemented through the following technical solutions:

[0006] The present invention provides a memory, including:

[0007] A main control module, configured to receive host tasks;

[0008] A command queue module, configured to store and allocate the host tasks;

[0009] A hardware acceleration module, configured to execute the allocated host tasks;

[0010] Wherein, the command queue module is further configured to allocate some or all of the host tasks to the hardware acceleration module for execution according to the ability of the hardware acceleration module to execute host tasks, and allocate the remaining unallocated host tasks to the main control module for execution.

[0011] In an embodiment of the present invention, the host tasks include at least one of logical operation tasks, data search tasks, and data migration tasks; the hardware acceleration module includes:

[0012] An acceleration control unit, configured to receive the allocated logical operation tasks, allocated data search tasks, and allocated data migration tasks;

[0013] A logical operation unit, configured to execute the allocated logical operation tasks;

[0014] A data search unit, configured to execute the allocated data search tasks;

[0015] A data transfer unit for performing the assigned data transfer task.

[0016] In an embodiment of the present invention, the main control module has one CPU core; the command queue module distributes host tasks according to the following steps:

[0017] Judge the type of the host task:

[0018] When the host task is one of a logical operation task, a data search task, and a data transfer task, split the host task into multiple subtasks, allocate some or all of the subtasks to the task queues of the corresponding logical operation unit, data search unit, and data transfer unit, and allocate the remaining unallocated subtasks to the task queue of the main control module;

[0019] When the host task is at least two of a logical operation task, a data search task, and a data transfer task, allocate all host tasks to the task queues of the corresponding logical operation unit, data search unit, and data transfer unit.

[0020] In an embodiment of the present invention, the command queue module distributes subtasks according to the following steps:

[0021] Obtain and judge the task queues of the logical operation unit, data search unit, and data transfer unit that match the subtask:

[0022] When the task queue is in an idle state, allocate the subtask to the task queues of the corresponding logical operation unit, data search unit, and data transfer unit until the task queue is in a full load state;

[0023] When the task queue is in a full load state, allocate the remaining unallocated subtasks to the task queue of the main control module.

[0024] In an embodiment of the present invention, the main control module has multiple CPU cores; the command queue module distributes host tasks according to the following steps:

[0025] Split each type of host task into multiple subtasks of the corresponding type, allocate some or all of the subtasks to the task queues of the corresponding logical operation unit, data search unit, and data transfer unit, and allocate the remaining unallocated subtasks to the task queue of the main control module.

[0026] In an embodiment of the present invention, the command queue module distributes subtasks according to the following steps:

[0027] Obtain and judge the task queues of the logical operation unit, the data search unit, and the data transfer unit that match the sub-task:

[0028] When the task queue is in an idle state, allocate the sub-task to the task queues of the logical operation unit, the data search unit, and the data transfer unit that match it until the task queue is in a full state;

[0029] When the task queue is in a full state, allocate the remaining unallocated sub-tasks to different task queues of the main control module; different task queues of the main control module correspond to different CPU cores.

[0030] In an embodiment of the present invention, the command queue module allocates the remaining unallocated sub-tasks according to the following steps:

[0031] Obtain the number of idle CPU cores in the main control module that are idle: create corresponding task queues according to the number of idle cores;

[0032] Allocate the remaining unallocated sub-tasks to the corresponding task queues according to their types.

[0033] In an embodiment of the present invention, the command queue module allocates the remaining unallocated sub-tasks to the corresponding task queues according to their types according to the following steps:

[0034] Judge the number of types of the remaining unallocated sub-tasks:

[0035] When the number of types is less than or equal to the number of task queues, allocate the remaining unallocated sub-tasks to different task queues according to their types;

[0036] When the number of types is greater than the number of task queues, evenly allocate the remaining unallocated sub-tasks to all task queues.

[0037] In an embodiment of the present invention, the main control module is used to generate and send an operation start instruction, a search start instruction, and a transfer start unit. The logical operation unit is used to start according to the operation start instruction, the data search unit is used to start according to the search start instruction, and the data transfer unit is used to start according to the transfer start unit.

[0038] The present invention also provides a task processing method for a memory. The memory includes a main control module and a hardware acceleration module. The task processing method includes:

[0039] Receive and allocate host tasks;

[0040] According to the capabilities of the hardware acceleration module for executing host tasks, part or all of the host tasks are allocated to the hardware acceleration module for execution, and the remaining unallocated host tasks are allocated to the main control module for execution.

[0041] As described above, the present invention provides a memory and a task processing method. By introducing a hardware acceleration module and adopting a fine-grained task division strategy, the system operation efficiency is significantly improved. The command queue module dynamically monitors the load condition of the hardware acceleration module and adopts different allocation strategies according to the task type and quantity: preferentially allocate subtasks to the hardware acceleration module to make full use of its high-efficiency processing capabilities. When the hardware acceleration module is overloaded, the remaining tasks are flexibly allocated to the main control module. By allocating tasks according to type, dynamically creating task queues, and evenly allocating unallocated tasks, efficient task allocation and load balancing are achieved.

[0042] Of course, it is not necessary for any product implementing the present invention to simultaneously achieve all the above-mentioned advantages. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for describing the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can also obtain other drawings based on these drawings without creative efforts.

[0044] Figure 1 Schematic diagram of a memory in an embodiment of the present invention;

[0045] Figure 2 Schematic diagram of a hardware acceleration module in an embodiment of the present invention.

[0046] In the figure: 10, power supply module; 20, interface module; 30, main control module; 40, read-only storage module; 50, random storage module; 60, command queue module; 70, read cache module; 80, write cache module; 90, mapping table module; 100, flash memory module; 110, hardware acceleration module; 111, bus interface unit; 112, input cache unit; 113, acceleration control unit; 114, logical operation unit; 115, data search unit; 116, data transfer unit; 117, output cache unit. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0047] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0048] Please refer to Figure 1 , the present invention provides a memory, which can be an Embedded MultiMedia Card (eMMC) or a Universal Flash Storage (UFS). The memory can communicate with the electronic device through the CMD line and the DATA0~7 lines, and execute operations such as reading, writing, and erasing by receiving instructions from the electronic device. The electronic device can send instructions through the CMD line and transmit data through the DATA0~7 lines. The communication protocol between the memory and the electronic device can follow the JEDEC protocol. The memory can include an interface module 20, a main control module 30, a read-only storage module 40, a random storage module 50, a command queue module 60, a read cache module 70, a write cache module 80, a mapping table module 90, a flash module 100, and a hardware acceleration module 110.

[0049] In some embodiments, the power supply module 10 can be the power supply of the electronic device, and the power supply module 10 can be used to provide the core power supply (VCC) and the interface power supply (VCCQ) for the memory.

[0050] In some embodiments, the interface module 20 (interface) can be the transmission interface and the power supply interface between the memory and the electronic device. The interface module 20 can receive instructions transmitted from the electronic device and return data or status information to the electronic device. The interface module 20 can receive instructions from the electronic device through the CMD line and the DATA line, and return the result data or the execution status to the electronic device through the DATA line. The interface module 20 can also be used to receive the core power supply (VCC) and the interface power supply (VCCQ) provided by the electronic device.

[0051] In some embodiments, the main control module 30 may be a microcontroller unit (MCU). The main control module 30 can be used to perform specific control tasks, such as reading data, processing instructions from electronic devices, etc. The CPU core of the main control module 30 can be designed based on the RISC-V architecture to execute various control and computing tasks. The main control module 30 may have one CPU core or multiple CPU cores. The CPU core is the basic unit in the main control module 30 that executes instructions and performs operations. Each CPU core can independently execute tasks and has its own registers, ALU (Arithmetic Logic Unit), and cache.

[0052] In some embodiments, the read-only storage module 40 may be a non-volatile memory (Read-Only Memory, ROM) for storing data in the long term. Programs, such as firmware, can be stored in the read-only storage module 40. The program can be a set of pre-written instructions that guide the main control module 30 on how to start and run. These instructions include device initialization, peripheral configuration, and possibly a bootloader. The bootloader can be used to load updated programs or operating systems, etc.

[0053] In some embodiments, the random storage module 50 may be a volatile memory (Random Access Memory, RAM) for temporarily storing data and program code. The random storage module 50 can be used to temporarily store data. When the control module 30 executes a program, the program code can be loaded from the read-only storage module 40 into the random storage module 50 for execution.

[0054] In some embodiments, the command queue module 60 (CMDQ) can be a buffer for temporarily storing memory access requests / host tasks from different hardware modules, sorting and scheduling these requests / host tasks according to certain rules (such as priority, order, or optimization strategy), and then sending them to other modules for execution.

[0055] In some embodiments, the read cache module 70 (ReadBuffer) and the write cache module 80 (WriteBuffer) can serve as a high-speed temporary storage area between the main control module 30 and the flash memory module 100, used to store data and instructions frequently accessed by the main control module 30 to achieve the function of accelerating data transmission. The read cache module 70 is mainly to improve the data reading speed and reduce the access to the flash memory module 100; while the write cache module 80 is mainly to improve the data writing efficiency and optimize the performance of the writing operation.

[0056] In some embodiments, the memory mapping table module 90 (MemoryMappingTableModule) can be used to manage the mapping relationship between virtual memory and physical memory. The memory mapping table module 90 converts virtual addresses (used by programs) into physical addresses (used by hardware) by maintaining a mapping table, thereby achieving efficient memory management and protection. The mapping table can be a hierarchical structure (such as a page table) for recording the correspondence between virtual addresses and physical addresses. For example, in the paging mechanism, a virtual address is divided into a page number (PageNumber) and an offset within the page. The mapping table looks up the corresponding physical page frame through the page number. When a program accesses a virtual address, the main control module 30 queries the mapping table to find the corresponding physical address. If there is no corresponding entry in the mapping table (i.e., a page fault occurs), a page fault exception will be triggered, and the main control module 30 is responsible for loading the required data from the disk into physical memory and updating the mapping table.

[0057] In some embodiments, the flash memory module 100 can be a physical unit (nand) in the memory for storing data. The flash memory module 100 can be composed of multiple storage blocks. Each storage block can contain multiple pages (Page). Each page is the minimum unit for read / write operations, while a block is the minimum unit for erase operations. Data is usually read and written in units of pages, while the entire block needs to be erased during erasure.

[0058] Please refer to Figure 1 and Figure 2 , in some embodiments, the hardware acceleration module 110 (Hardware Acceleration, HACC) can be a dedicated hardware circuit newly added inside the memory, which accelerates the processing of specific tasks through hardware-level optimization, thereby reducing the burden on the main control module 30 and improving the overall system performance. The hardware acceleration module 110 can include a bus interface unit 111, an input buffer unit 112, an acceleration control unit 113, a logical operation unit 114, a data search unit 115, a data transfer unit 116, an output buffer unit 117, etc.

[0059] In some embodiments, the bus interface unit 111 can be used to convert different bus protocols inside the memory. For example, it can convert and adapt protocols such as AXI (Advanced eXtensible Interface), AHB (Advanced High-performance Bus), and APB (Advanced Peripheral Bus), so as to achieve efficient communication between different modules. The bus interface unit 111 can be connected to different functional modules, such as the master control module 30, the random access memory module 50, the command queue module 60, the read cache module 70, the write cache module 80, the mapping table module 90, the flash memory module 100, etc., to be applicable to hardware acceleration in different scenarios.

[0060] In some embodiments, the input cache unit 112 can be used to temporarily cache the data in the master control module 30, the random access memory module 50, the command queue module 60, the read cache module 70, the write cache module 80, the mapping table module 90, the flash memory module 100, as well as to cache logical operation tasks and their subtasks, data search tasks and their subtasks, data transfer tasks and their subtasks, so as to be processed by the logical operation unit 114, the data search unit 115, the data transfer unit 116, etc.

[0061] In some embodiments, the acceleration control unit 113 can be used to receive various instructions from the master control module 30, such as operation start instructions, search start instructions, transfer start instructions, etc. When hardware acceleration needs to be achieved through the hardware acceleration module 110, the master control module 30 is used to generate and send operation start instructions, search start instructions, transfer start instructions. The acceleration control unit 113 can be used to send the operation start instruction to the logical operation unit 114, and the logical operation unit 114 can be started according to the operation start instruction. The acceleration control unit 113 can be used to send the search start instruction to the data search unit 115, and the data search unit 115 can be started according to the search start instruction. The acceleration control unit 113 can be used to send the transfer start instruction to the data transfer unit 116, and the data transfer unit 116 can be started according to the transfer start instruction.

[0062] In some embodiments, the logic operation unit 114 can be used to process logic operation tasks. The logic operation unit 114 can process a variety of arithmetic and logic operations, including arithmetic operations, logic operations, and data comparisons, etc. Arithmetic operations include addition, subtraction, multiplication, division, etc. Logic operations include AND, OR, NOT, XOR, XNOR, NAND, NOR, etc. Data comparisons include greater than, less than, equal to, etc. The logic operation unit 114 can replace the main control module 30 to perform logic operation operations on a large amount of data, such as AND / OR / NOT operations on batch data. By configuring the logic operation unit 114, the main control module 30 can send logic operation tasks to the logic operation unit 114 for processing, thus freeing up resources to process other tasks and achieving parallel multi-task processing.

[0063] In some embodiments, the data search unit 115 can be used to process data search tasks. The data search unit 115 can search for specified characters or any combination of characters and can achieve: maximum value (Max), minimum value (Min) search; specified data feature search: for example, the digital length ranges from 1 to n; specified range search: it can search within the specified Die, Plane, Block, Page ranges; support search queries for firmware running algorithms, including maximum value, minimum value, specified feature character query, any combination of feature character query; it can search within the specified NAND LBA (Logical Block Address) range. The data search unit 115 can execute data search tasks through hardware acceleration, reducing the burden on the main control module 30.

[0064] In some embodiments, the data transfer unit 116 can be used to process data transfer tasks. The data transfer unit 116 can perform data acceleration transfer between the read cache module 70, the write cache module 80, and the flash memory module 100. The data transfer unit 116 can implement the functions of data filling and data transfer. Data filling refers to specifying any starting LBA address + LBA length + fixed value or random value; specifying any internal LBA address + internal LBA length + fixed value or random value. Data transfer refers to from any LBA address + any LBA length, and it can transfer from the cache of the main control module 30 to the read cache module 70, the write cache module 80, or transfer from the read cache module 70, the write cache module 80 to the cache of the main control module 30. The data transfer unit 116 executes data transfer tasks through hardware acceleration, reducing the occupancy time of the main control module 30.

[0065] In some embodiments, the output buffer unit 117 can be used to send the data processed by the logic operation unit 114, the data search unit 115, and the data transfer unit 116, and can be sent to the main control module 30, the random access memory module 50, the command queue module 60, the read buffer module 70, the write buffer module 80, the mapping table module 90, the flash memory module 100, etc.

[0066] In some embodiments, taking the host tasks issued by the electronic device as an example, the host tasks can include at least one of the logic operation tasks, the data search tasks, and the data transfer tasks, and the number of each type of task can also be at least one. The logic operation tasks can include operations such as addition, subtraction, multiplication, division, AND, OR, and NOT. The data search tasks can include tasks such as finding the maximum value, the minimum value, or the specified characteristic data. The data transfer tasks can include tasks such as transferring data between the read buffer module 70 and the flash memory module 100, and between the write buffer module 80 and the flash memory module 100. The main control module 30 can receive the host tasks issued by the host. The command queue module 60 can be used to store the host tasks and allocate the tasks to the hardware acceleration module 110 and / or the main control module 30 for execution according to a certain strategy. For example, the command queue module 60 can allocate some or all of the host tasks to the task queue of the hardware acceleration module 110 according to the ability of the hardware acceleration module 110 to execute the host tasks, so as to wait for the hardware acceleration module 110 to execute; and allocate the remaining unallocated host tasks to the task queue of the main control module 30 to wait for the main control module 30 to execute. Among them, the task queue can be created in advance by the command queue module 60, and different task queues can be created for different modules or units.

[0067] In some embodiments, when the main control module 30 has one CPU core, the command queue module 60 can determine the type of the host task: when the host task is one of the logic operation tasks, the data search tasks, and the data transfer tasks, the command queue module 60 can split the host task into multiple subtasks, allocate some or all of the subtasks to the corresponding logic operation unit 114, data search unit 115, and data transfer unit 116 for execution, and allocate the remaining unallocated subtasks to the main control module 30 for execution; when the host task is at least two of the logic operation tasks, the data search tasks, and the data transfer tasks, the command queue module 60 allocates all the host tasks to the corresponding logic operation unit 114, data search unit 115, and data transfer unit 116 for execution.

[0068] In some embodiments, the command queue module 60 may adopt different allocation strategies according to the types of host tasks. When the host task is one of the logical operation tasks, data search tasks, or data transfer tasks, the command queue module 60 may split the host task into multiple subtasks. The command queue module 60 may allocate some or all of the subtasks to the corresponding hardware acceleration units for execution: the subtasks of the logical operation task may be processed by the logical operation unit 114; the subtasks of the data search task may be processed by the data search unit 115; the subtasks of the data transfer task may be processed by the data transfer unit 116; the remaining unallocated subtasks may be allocated to the main control module 30 for processing. By efficiently processing suitable tasks by the logical operation unit 114, data search unit 115, and data transfer unit 116, and at the same time using the main control module 30 to process the remaining tasks, load balancing is achieved.

[0069] In some embodiments, when the host task is at least two of the logical operation tasks, data search tasks, or data transfer tasks, there is no need to split the task, and all host tasks are directly allocated to the corresponding logical operation unit 114, data search unit 115, and data transfer unit 116 for execution according to the task type. By making full use of the parallel processing ability of the hardware acceleration module 110, the burden on the main control module 30 is avoided, and the overall efficiency is improved.

[0070] In some embodiments, when the command queue module 60 splits the host task into multiple subtasks, the command queue module may obtain and judge the status of the task queues of the logical operation unit 114, data search unit 115, and data transfer unit 116 that match the subtasks: when the task queue is in an idle state, the subtasks are allocated to the task queues of the logical operation unit 114, data search unit 115, and data transfer unit 116 that match them until the task queue is in a full-load state; when the task queue is in a full-load state, the remaining unallocated subtasks are allocated to the task queue of the main control module 30.

[0071] In some embodiments, the idle state of the task queue means that the number of tasks to be processed in the task queue does not exceed the task threshold. For example, the task threshold can be set to 100. When the number of tasks to be processed in the task queue is 30, it means that 70 more tasks can be added to this task queue. The full-load state of the task queue means that the number of tasks to be processed in the task queue reaches the task threshold. At this time, if new tasks are continuously allocated to this task queue, it may cause a long delay in task execution. Therefore, when the task queue is in a full-load state, no new tasks can be allocated to it. Among them, the size of the task threshold of different task queues is not limited.

[0072] In some embodiments, when the command queue module 60 allocates subtasks, it can dynamically monitor the load conditions of the hardware acceleration modules (logical operation unit 114, data search unit 115, data transfer unit 116), and determine how to allocate tasks based on the number of tasks to be executed and the task threshold. Specifically, the command queue module 60 can obtain the number of tasks to be executed of the hardware acceleration module 110 that matches the subtask: the number of tasks to be executed of the logical operation unit 114; the number of tasks to be executed of the data search unit 115; the number of tasks to be executed of the data transfer unit 116. The command queue module 60 compares the number of tasks to be executed with the task threshold. The task threshold is a preset value, indicating the maximum number of tasks that the logical operation unit 114, data search unit 115, and data transfer unit 116 in the hardware acceleration module 110 can efficiently process.

[0073] In some embodiments, according to the relationship between the number of tasks to be executed and the task threshold, the command queue module 60 can adopt different allocation strategies: when the number of tasks to be executed in the logical operation unit 114, data search unit 115, and data transfer unit 116 is less than the task threshold, the command queue module 60 preferentially allocates the subtasks to the corresponding logical operation unit 114, data search unit 115, and data transfer unit 116 that matches it, and the allocation process continues until the number of tasks to be executed in the logical operation unit 114, data search unit 115, and data transfer unit 116 is equal to the task threshold. When the number of tasks to be executed in the logical operation unit 114, data search unit 115, and data transfer unit 116 is greater than or equal to the task threshold, the command queue module 60 allocates the remaining unallocated subtasks to the main control module 30 for execution.

[0074] In some embodiments, when the main control module 30 has multiple CPU cores, the command queue module 60 can split each type of host task into multiple subtasks of the corresponding type, allocate some or all of the subtasks to the task queues of the corresponding logical operation unit 114, data search unit 115, and data transfer unit 116 to wait for execution; allocate the remaining unallocated subtasks to the task queue of the main control module 30 to wait for execution. Through such allocation, efficient task allocation and resource utilization can be achieved, the performance advantages of the hardware acceleration module 110 can be fully utilized, and at the same time, by processing the remaining tasks through the main control module 30, the load balance and task completion efficiency of the system can be ensured.

[0075] In some embodiments, when the command queue module 60 allocates subtasks, it dynamically monitors the status of the task queues of the hardware acceleration module (logical operation unit 114, data search unit 115, data transfer unit 116): when the task queue is in an idle state, the subtasks are allocated to the task queues of the corresponding logical operation unit 114, data search unit 115, and data transfer unit 116 until the task queue is in a full state; when the task queue is in a full state, the remaining unallocated subtasks are allocated to different task queues of the main control module 30; different task queues of the main control module 30 correspond to different CPU cores.

[0076] In some embodiments, the command queue module 60 can obtain and judge the number of tasks to be executed in the logical operation unit 114, data search unit 115, and data transfer unit 116 that match the subtasks: when the number of tasks to be executed is less than the task threshold, the subtasks are preferentially allocated to the corresponding logical operation unit 114, data search unit 115, and data transfer unit 116 until the number of tasks to be executed is equal to the task threshold; when the number of tasks to be executed is greater than or equal to the task threshold, the remaining unallocated subtasks are allocated to different CPU cores of the main control module 30 for execution. When the hardware acceleration module is not overloaded, the subtasks are preferentially allocated to the hardware acceleration module 110 to make full use of its high processing ability. When the hardware acceleration module 110 is overloaded, the remaining unallocated subtasks are allocated to different CPU cores of the main control module 30 to ensure that the tasks can be efficiently completed.

[0077] In some embodiments, when the command queue module 60 allocates the remaining unallocated subtasks, it dynamically monitors the number of idle CPU cores in the main control module 30, creates corresponding task queues based on these idle CPU cores, and then allocates the remaining unallocated subtasks to the corresponding task queues according to their types. By making full use of the multi-core processing ability of the main control module 30, efficient parallel processing and load balancing of tasks are achieved. Specifically, the command queue module 60 can obtain the number of idle CPU cores in the main control module 30: create corresponding task queues based on the number of cores; each idle CPU core is matched with a task queue; allocate the remaining unallocated subtasks to the corresponding task queues according to their types. Among them, an idle CPU core refers to a CPU core on which no task is currently being executed. By allocating subtasks to different task queues, parallel execution of tasks can be achieved, improving system efficiency.

[0078] In some embodiments, for example, the master control module has 3 idle CPU cores, and the remaining unallocated subtasks may include subtasks of 5 logical operation tasks, subtasks of 4 data search tasks, and subtasks of 3 data transfer tasks. The command queue module 60 obtains that the master control module has 3 idle CPU cores and creates 3 task queues, which are respectively matched with the 3 idle CPU cores. Subsequently, the remaining unallocated subtasks can be assigned to the corresponding task queues according to their types: the first task queue can process the subtasks of 5 logical operation tasks, the second task queue can process the subtasks of 4 data search tasks, and the third task queue can process the subtasks of 3 data transfer tasks.

[0079] In some embodiments, the command queue module 60 can determine the number of types of the remaining unallocated subtasks: when the number of types is less than or equal to the number of task queues, the remaining unallocated subtasks are assigned to different task queues according to their types; when the number of types is greater than the number of task queues, the number of tasks of each type of the remaining unallocated subtasks is counted, and the remaining unallocated subtasks are evenly assigned to the task queues. The command queue module 60 realizes the efficient assignment of tasks and load balancing by adopting different assignment strategies according to the number of types of the remaining unallocated subtasks and the number of task queues. When the number of types is less than or equal to the number of task queues, tasks are assigned according to their types and the idle task queues are deleted; when the number of types is greater than the number of task queues, the unallocated tasks are evenly assigned to all task queues. This design can make full use of the resources of the task queues, ensure that tasks can be executed efficiently, and avoid resource waste at the same time.

[0080] It can be seen that in the above solution, by introducing the hardware acceleration module and adopting the task fine-grained division strategy, the system operation efficiency is significantly improved. The command queue module dynamically monitors the load condition of the hardware acceleration module and adopts different assignment strategies according to the task type and quantity: the subtasks are preferentially assigned to the hardware acceleration module to make full use of its high-efficiency processing ability, and when the hardware acceleration module is overloaded, the remaining tasks are flexibly assigned to the master control module. By assigning tasks according to their types, dynamically creating task queues, and evenly assigning the unallocated tasks, the efficient assignment of tasks and load balancing are realized.

[0081] The present invention also provides a task processing method for a memory. The task processing method can be applied to the above-mentioned memory, and the task processing method includes:

[0082] Receiving and assigning host tasks; the host tasks include at least one of logical operation tasks, data search tasks, and data transfer tasks;

[0083] According to the capabilities of the hardware acceleration module to execute host tasks, part or all of the host tasks are allocated to the hardware acceleration module for execution, and the remaining unallocated host tasks are allocated to the main control module for execution.

[0084] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the content of this specification. These embodiments are selected and specifically described in this specification in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can well understand and utilize the present invention. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A memory, characterized in that, including: a main control module, configured to receive host tasks; the host tasks include at least one of a logical operation task, a data search task, and a data transfer task; a command queue module, configured to store and allocate the host tasks; a hardware acceleration module, configured to execute the allocated host tasks; wherein, the command queue module is further configured to allocate some or all of the host tasks to the hardware acceleration module for execution according to the capabilities of the hardware acceleration module to execute host tasks, and allocate the remaining unallocated host tasks to the main control module for execution; the hardware acceleration module includes: an acceleration control unit, configured to receive the allocated logical operation tasks, the allocated data search tasks, and the allocated data transfer tasks; a logical operation unit, configured to execute the allocated logical operation tasks; a data search unit, configured to execute the allocated data search tasks; and a data transfer unit, configured to execute the allocated data transfer tasks; judge the number of CPU cores of the main control module. When the main control module has one CPU core, the command queue module is further configured to: judge the types of the host tasks: when the host tasks are at least two of a logical operation task, a data search task, and a data transfer task, allocate all the host tasks to the task queues of the corresponding logical operation unit, data search unit, and data transfer unit; when the host task is one of a logical operation task, a data search task, and a data transfer task, split the host task into multiple subtasks, obtain and judge the task queues of the logical operation unit, data search unit, and data transfer unit that match the subtasks: when the task queue is in an idle state, allocate the subtasks to the task queues of the logical operation unit, data search unit, and data transfer unit that match them until the task queue is in a full state; when the task queue is in a full state, allocate the remaining unallocated subtasks to the task queue of the main control module.

2. The memory according to claim 1, wherein the main control module has multiple CPU cores; the command queue module allocates host tasks according to the following steps: split each type of the host tasks into multiple subtasks of the corresponding type, allocate some or all of the subtasks to the task queues of the corresponding logical operation unit, data search unit, and data transfer unit, and allocate the remaining unallocated subtasks to the task queue of the main control module.

3. The memory according to claim 2, wherein, the command queue module allocates subtasks according to the following steps: obtain and judge the task queues of the logical operation unit, data search unit, and data transfer unit that match the subtasks: when the task queue is in an idle state, allocate the subtasks to the task queues of the logical operation unit, data search unit, and data transfer unit that match them until the task queue is in a full state; when the task queue is in a full state, allocate the remaining unallocated subtasks to different task queues of the main control module; different task queues of the main control module correspond to different CPU cores.

4. The memory according to claim 3, wherein The command queue module allocates the remaining unallocated subtasks according to the following steps: Obtain the number of idle CPU cores in the main control module: create a corresponding task queue based on the number of idle cores; Allocate the remaining unallocated subtasks to the corresponding task queues according to their types.

5. The memory according to claim 4, wherein The command queue module allocates the remaining unallocated subtasks to the corresponding task queues according to their types according to the following steps: Judge the number of types of the remaining unallocated subtasks: When the number of types is less than or equal to the number of task queues, allocate the remaining unallocated subtasks to different task queues according to their types; When the number of types is greater than the number of task queues, evenly allocate the remaining unallocated subtasks to all task queues.

6. The memory according to claim 1, characterized in that, The main control module is used to generate and send an operation start instruction, a search start instruction, and a transfer start unit. The logic operation unit is used to start according to the operation start instruction, the data search unit is used to start according to the search start instruction, and the data transfer unit is used to start according to the transfer start unit.

7. A task processing method for a memory, characterized in that The memory includes a main control module and a hardware acceleration module. The task processing method is applied to the memory according to any one of claims 1 to 6. The task processing method includes: Receive and allocate host tasks; According to the ability of the hardware acceleration module to execute host tasks, allocate some or all of the host tasks to the hardware acceleration module for execution, and allocate the remaining unallocated host tasks to the main control module for execution.

Images