Method for directly accessing persistent memory on CXL bus

Abstract

The invention discloses a method for directly accessing a persistent memory on a CXL bus, which relates to the technical field of computers, and comprises the following steps: a system bus of a CXL host is connected with CXL equipment through a CXL switch; the CXL equipment comprises a persistent memory, and the driving module maps the persistent memory in the CXL equipment into a memory space of the CXL host. One or more CXL root ports are connected through a system bus of a host; the CXL root port is connected with one or more CXL devices through a CXL switch; the CXL equipment comprises a plurality of persistent memories; and the driving program is responsible for managing the underlying CXL equipment and exposing the HDM of the underlying CXL equipment in the memory space of the host. According to the method, the persistent memory is directly accessed on the CXL bus, like accessing a local memory, so that efficient memory expansion and low-delay memory access are realized, the access of remote memory resources is more efficient, and a user can experience the performance of the remote memory more truly.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and more particularly to a method for directly accessing a persistent memory on a CXL bus. Background Art

[0002] DRAM: Dynamic Random Access Memory, dynamic random access memory, that is, the memory widely used at this stage, its characteristic is that the information is lost after power failure, and the theoretical read and write life is unlimited. DIMM: Dual inline Memory Module, dual inline memory module, is the slot of DRAM on the motherboard. PM: Persistent Memory, non-volatile memory or persistent memory, STTRAM, PCM, RRAM are all PM, its characteristic is that the information is not lost after power failure, and byte search is possible; but the number of read and write times is limited, and the read and write are not balanced. Depending on the material, the PM write time is about 4 to 10 times the read time, and the PM read time is 1 to 4 times slower than DRAM. PCIe: Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard used to connect various components inside the computer, such as graphics cards, network cards, sound cards, etc., so that they can efficiently transmit data and work together. CXL: Compute Express Link, a high-speed interconnect technology that provides high-performance connections between multiple CXL host processors, hardware accelerators, and I / O devices. It is designed to provide higher data throughput and lower latency to meet the needs of modern computing and storage systems.

[0003] Persistent memory has developed rapidly in recent years. Due to its advantages of byte-seeking, non-volatility, low energy consumption, and high density, it has gradually become an important supplement or replacement for DRAM. However, there is currently no product or platform that truly integrates CXL for persistent memory de-aggregation.

[0004] Therefore, how to propose a method for directly accessing persistent memory on the CXL bus, directly accessing persistent memory through the CXL bus, making access to remote memory resources more efficient, and allowing users to more realistically experience the performance of remote memory is an issue that technical personnel in this field urgently need to solve. Summary of the invention

[0005] In view of this, the present invention provides a method for directly accessing persistent memory on a CXL bus, which directly accesses persistent memory through the CXL bus to solve the problems of low memory utilization and high latency, making access to remote memory resources more efficient, and allowing users to experience the performance of remote memory more realistically. In order to achieve the above purpose, the present invention adopts the following technical solutions:

[0006] A method for directly accessing persistent memory on a CXL bus comprises: a CXL host, a CXL switch, a CXL device and a driver module; the system bus of the CXL host is connected to the CXL device through the CXL switch; the CXL device includes persistent memory, and the driver module maps the persistent memory inside the CXL device to the memory space of the CXL host.

[0007] Optionally, the system bus of the CXL host is connected to the CXL device through the CXL switch, including: connecting one or more CXL root ports through the system bus of the CXL host; the CXL root port is connected to one or more CXL devices through the CXL switch; the CXL root port RP of the CXL host is connected to the CXL switch; and the CXL switch is connected to the CXL device port EP.

[0008] Optionally, the CXL switch includes: a CXL switch upstream port USP and a CXL switch downstream port DSP; the CXL switch upstream port USP is used to connect to a CXL root port RP of the CXL host; the CXL switch downstream port DSP is used to connect to another CXL switch upstream port USP or the CXL device port EP.

[0009] Optionally, the method further includes: the CXL switch includes multiple USPs and DSPs; and the CXL switch allows connecting multiple CXL hosts and multiple CXL devices.

[0010] Optionally, the CXL switch working steps are:

[0011] Step A1: Connect the CXL device

[0012] Connecting the CXL root port RP of the CXL host to the upstream port USP of the CXL switch or directly to the CXL device, and connecting the downstream port DSP of the CXL switch to another upstream port USP of the CXL switch or directly to the CXL device port EP;

[0013] Step A2: Configure the CXL switch

[0014] Using the fabric manager to set up an internal routing table, reconfigure the crossbar of the switch, and connect each of the USPs to a different DSP;

[0015] Step A3: Create CXL Virtual Hierarchy

[0016] Through reconfiguration of the crossbar switch, a virtual hierarchy is created from the CXL host to the CXL devices.

[0017] Optionally, the CXL device includes: a CXL device port EP, a base address register BAR, a CXL host-managed device memory HDM, a CXL controller, and a persistent memory;

[0018] The CXL device uses one or more of the CXL controllers and a plurality of persistent memories;

[0019] defining a plurality of logical devices, each logical device exposing its device memory HDM managed by the CXL host to the CXL host;

[0020] The CXL device port EP is used to connect to the CXL switch;

[0021] The CXL controller is used to map the persistent memory inside the CXL device to the memory space of the CXL host through CXL.

[0022] Optionally, the CXL controller operates as follows:

[0023] Step B1: Connect the CXL device

[0024] Ensure that the system bus of the CXL host is connected to one or more CXL root ports RP, and one or more CXL root ports RP are connected to the CXL device port EP;

[0025] Step B2: Query the CXL device information

[0026] The kernel driver of the CXL host queries the base address register BAR of the CXL device and the size of the device memory HDM managed by the CXL host through PCIe transactions;

[0027] Step B3: Mapping the BAR and HDM

[0028] Based on the retrieved size, the kernel driver maps the BAR and HDM of the CXL device in the system memory space reserved by the CXL host;

[0029] Step B4: Send device mapping location

[0030] Sending to the CXL device the mapping location of the BAR and HDM of the CXL device in the memory of the CXL host system;

[0031] Step B5: Access the HDM

[0032] The CXL host CPU accesses the mapped HDM system memory through load / store instructions, and the request is passed to the corresponding CXL root port RP;

[0033] Step B6: Conversion Request

[0034] The CXL root port RP converts the received request into a CXL flit;

[0035] Step B7: Convert the address

[0036] The CXL controller converts the incoming address to match the address space of the persistent memory inside the CXL device port EP by subtracting the base address of the HDM from the incoming address;

[0037] Step B8: Issue a request to persistent memory

[0038] The CXL controller sends a request after address translation to the underlying persistent memory controller;

[0039] Step B9: Return the result

[0040] The processed data is returned to the CXL host via the CXL switch and FlexBus.

[0041] Optionally, the driver module includes a software driver; the software driver is used to manage the underlying CXL device and expose its HDM in the memory space of the application; the software driver divides the address space of the HDM into multiple segments to obtain cxl-namespace; the software driver allows the CXL host application to access the cxl-namespace in the form of a memory mapped file mmap.

[0042] Optionally, the software driver working steps are:

[0043] Step C1: Detect CXL device

[0044] The CXL device is detected during PCIe enumeration;

[0045] Step C2: Create an entry device

[0046] The software driver creates an entry device after detecting the CXL device;

[0047] Step C3: Request the cxl-namespace

[0048] The user sends a request to the entry device to create a cxl-namespace;

[0049] Step C4: Check the address space

[0050] The driver checks for a contiguous address space on the HDM by referencing its HDM segment table;

[0051] Step C5: Allocate segments and create mapped devices

[0052] The driver allocates a segment according to the user request, creates a device for mmap, and updates the segment table;

[0053] Step C6: Mapping Virtual Memory

[0054] The CXL host application uses mmap and vm_area_struct to map the virtual memory space of its process into the cxl-namespace.

[0055] It can be seen from the above technical solutions that, compared with the prior art, the present invention discloses a method for directly accessing persistent memory on a CXL bus, which has the following beneficial effects:

[0056] The present invention proposes a method for directly accessing persistent memory on a CXL bus, comprising: a CXL host, a CXL switch, a CXL device and a driver module; the system bus of the CXL host is connected to the CXL device through the CXL switch; the CXL device contains persistent memory, and the driver module maps the persistent memory inside the CXL device to the memory space of the CXL host. The present invention connects one or more CXL root ports through the system bus of the host; the CXL root port is connected to one or more CXL devices through the CXL switch; the CXL device contains multiple persistent memories; the software system includes a driver; the driver is responsible for managing the underlying CXL device and exposing its HDM to the memory space of the host. Directly accessing persistent memory on the CXL bus is like accessing local memory, realizing efficient memory expansion and low-latency memory access, making the access to remote memory resources more efficient, and users can experience the performance of remote memory more realistically, which has good market prospects and application value. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0058] Figure 1 A schematic diagram of a network topology structure of a method for directly accessing persistent memory on a CXL bus provided by the present invention.

[0059] Figure 2 This is a schematic diagram of the structure of the CXL switch provided by the present invention.

[0060] Figure 3 A schematic diagram of the organizational structure of the CXL switch provided by the present invention.

[0061] Figure 4 This is a schematic diagram of the structure of the CXL controller provided by the present invention.

[0062] Figure 5 A schematic diagram of the structure of the software driver provided by the present invention. DETAILED DESCRIPTION

[0063] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0064] An embodiment of the present invention discloses a method for directly accessing persistent memory on a CXL bus, comprising: a CXL host, a CXL switch, a CXL device and a driver module; the system bus of the CXL host is connected to the CXL device through the CXL switch; the CXL device includes persistent memory, and the driver module maps the persistent memory inside the CXL device to the memory space of the CXL host.

[0065] In a specific implementation, a method for directly accessing persistent memory on a CXL bus includes: a hardware system and a software system.

[0066] Furthermore, the hardware system includes: a CXL host, a CXL switch, and a CXL device;

[0067] The CXL host and the CXL device are connected via a CXL switch;

[0068] The CXL root port RP of the CXL host is connected to the CXL switch;

[0069] The CXL switch is connected to the CXL equipment port EP.

[0070] Furthermore, the CXL switch includes:

[0071] USP on the upstream port of the CXL switch and DSP on the downstream port of the CXL switch;

[0072] The CXL switch upstream port USP is used to connect to the CXL root port RP of the CXL host;

[0073] The CXL switch downstream port DSP is used to connect to another CXL switch upstream port USP or the CXL equipment port EP;

[0074] The CXL switch uses multiple USPs and DSPs;

[0075] The CXL switch allows connecting a plurality of the CXL hosts and a plurality of the CXL devices.

[0076] Furthermore, the specific steps of the CXL switch are as follows:

[0077] Step A1: Connecting CXL devices: Connect the CXL root port RP of the CXL host to the upstream port USP of the CXL switch or directly to the CXL device, and connect the downstream port DSP of the CXL switch to another upstream port USP of the CXL switch or directly to the port EP of the CXL device;

[0078] Step A2: configuring the CXL switch: using a fabric manager (FM) to set up an internal routing table, reconfigure the crossbar switch of the switch, and connect each of the USPs to a different DSP;

[0079] Step A3: Create a CXL virtual hierarchy: Create a virtual hierarchy from the CXL host to the CXL devices through reconfiguration of the crossbar switch.

[0080] Further, the CXL device includes: a CXL device port EP, a base address register BAR, a CXL host-managed device memory HDM, a CXL controller, and a persistent memory;

[0081] The CXL device may use one or more of the CXL controllers and multiple persistent memories to define multiple logical devices, each logical device exposing its own CXL host-managed device memory HDM to the CXL host;

[0082] The CXL device port EP is used to connect to the CXL switch;

[0083] The CXL controller is used to map the persistent memory inside the CXL device to the memory space of the CXL host through CXL.

[0084] Furthermore, the specific steps of the CXL controller are as follows:

[0085] Step B1: Connecting the CXL device: ensuring that the system bus of the CXL host is connected to one or more of the CXL root ports RP, which are then connected to the CXL device ports EP;

[0086] Step B2: querying the CXL device information: the kernel driver of the CXL host queries the base address register BAR of the CXL device and the size of the device memory HDM managed by the CXL host through PCIe transactions;

[0087] Step B3: Mapping the BAR and the HDM: Based on the retrieved size, the kernel driver maps the BAR and the HDM of the CXL device in the system memory space reserved by the CXL host;

[0088] Step B4: Send device mapping location: Send the mapping location of the BAR and HDM of the CXL device in the memory of the CXL host system to the CXL device;

[0089] Step B5: Accessing the HDM: The CXL host CPU accesses the mapped HDM system memory through load / store instructions, and the request is passed to the corresponding CXL root port RP;

[0090] Step B6: Convert request: the CXL root port RP converts the received request into a CXL flit;

[0091] Step B7: Convert address: The CXL controller converts the incoming address to match the address space of the persistent memory inside the CXL device port EP by subtracting the HDM base address from the incoming address;

[0092] Step B8: Sending a request to the persistent memory: The CXL controller sends a request after address conversion to the underlying persistent memory controller;

[0093] Step B9: Returning results: The processed data is returned to the CXL host via the CXL switch and FlexBus.

[0094] Further, the software system includes: a software driver;

[0095] The software driver is used to manage the underlying CXL device and expose its HDM in the memory space of the application;

[0096] The software driver may simply divide the HDM address space into multiple segments, called cxl-namespaces;

[0097] The software driver allows CXL host applications to access the cxl-namespace in the form of a memory mapped file mmap.

[0098] Furthermore, the specific steps of the software driver working are as follows:

[0099] Step C1: Detecting a CXL device: Detecting the CXL device during the PCIe enumeration process;

[0100] Step C2: Creating an entry device: After detecting the CXL device, the software driver creates an entry device (e.g., / dev / cxl-pmem1) so that the user can manage the cxl-namespace through ioctl commands;

[0101] Step C3: Request the cxl-namespace: The user sends a request to / dev / cxl-pmem1 to request the creation of the cxl-namespace;

[0102] Step C4: Checking the address space: The driver checks a continuous address space on the HDM by referencing its HDM segment table, which records the offset, size and reference count of the segment (recording how many cxl-namespaces point to this segment). Multiple processes can access the segment table, and the table header contains spin locks, read-write locks, and summary information of the table entries;

[0103] Step C5: Allocate a segment and create a mapping device: The driver allocates a segment according to the user request, creates a device for mmap (e.g., / dev / cxl-ns0), and updates the segment table;

[0104] Step C6: Mapping virtual memory: The user application uses mmap and vm_area_struct to map the virtual memory space of its process to the cxl-namespace.

[0105] In a specific implementation, the network topology of the method for directly accessing persistent memory on a CXL bus is as follows: Figure 1 As shown:

[0106] There are n computing CXL hosts connected to m CXL devices through CXL switches;

[0107] Each CXL device prototype is built on an add-in card (AIC) CXL memory blade that uses a 16nm FPGA and eight different persistent memory modules. Within the FPGA, a CXL controller and eight persistent memory controllers are fabricated, each managing a CXL endpoint and an internal DRAM channel.

[0108] Since there is no processor architecture that supports CXL, this embodiment uses RISC-VISA to build an internal CXL host processor, which uses four out-of-order cores and its last-level cache LLC implements CXL RP. Each CXL-enabled host processor is implemented in a high-performance data center accelerator card, plays the role of a CXL host, and can run Linux 5.13 and software drivers independently.

[0109] This embodiment exposes four CXL devices to four CXL hosts through a PCIe backplane. The backplane is extended with an accelerator card of a CXL switch. The FM implemented by the CXL switch can create multiple virtual hierarchies, each of which connects a CXL host and a CXL device in a flexible way. The CXL host-side processor requires an Advanced Configuration and Power Interface (ACPI) to enumerate CXL 2.0 (such as RP location and RP reserved address space). Since the open source instruction set architecture RISC-V does not yet support ACPI, this embodiment implements CXL enumeration by adding such information in the device tree.

[0110] Specifically, this embodiment updates the MMIO register as a device tree node attribute to let the processor know where the CXLRP exists.

[0111] On the other hand, this embodiment adds a new field (cxl-reserved-area) in the node to indicate the location of the mappable HDM.

[0112] Specifically, the operating frequency of the internal soft core processor of this embodiment is 100 MHz, while the operating frequency of CXL and PCIe IP (RP, EP and Switch) is 250 MHz.

[0113] In a specific embodiment, the structure of the software driver is as follows: Figure 2 As shown, a CXL switch uses one or more CXL devices to disaggregate memory resources from a CXL host, including:

[0114] The CXL RP of a CXL host is directly connected to the upstream port USP of a CXL switch or a CXL device. The downstream port DSP of a CXL switch is also connected to the USP of another CXL switch or a CXL device.

[0115] It should be noted that the CXL switch of this embodiment uses multiple USPs and DSPs. Since a CXL device can use one or more controllers and multiple persistent memories, it can also define multiple logical devices, each of which opens its own HDM to the CXL host. Therefore, different CXL hosts can be connected to a CXL switch and a CXL device. It should be noted that each CXL virtual hierarchy only provides a path from one to another to ensure that no CXL hosts share HDMs.

[0116] In a specific embodiment, the CXL switch organization structure is as follows: Figure 3 As shown, by setting the internal routing table, the FM of the CXL switch of this embodiment reconfigures the crossbar of the switch to connect each USP to a different DSP, thereby creating a virtual hierarchical structure from the root (CXL host) to the terminal (CXL device).

[0117] In a specific embodiment, the structure of the CXL controller is as follows: Figure 4 As shown in the figure, the internal persistent memory of the CXL device is mapped to the CXL host memory space through CXL. The specific steps of the CXL controller are as follows:

[0118] (1) Connecting CXL devices: Ensure that the system bus of the CXL host is connected to one or more CXL root ports RP, which are then connected to CXL device ports EP;

[0119] (2) Query CXL device information: The kernel driver on the CXL host side queries the base address register BAR of the CXL device and the size of the device memory HDM managed by the CXL host through PCIe transactions;

[0120] (3) Mapping BARs and HDMs: Based on the retrieved sizes, the kernel driver maps the BARs and HDMs of the CXL device in the system memory space reserved by the CXL host;

[0121] (4) Send device mapping location: Send the mapping location of the BAR and HDM of the CXL device in the CXL host system memory to the CXL device;

[0122] (5) Accessing HDM: The CXL host CPU accesses the mapped HDM system memory through load / store instructions, and the request is passed to the corresponding CXL root port RP;

[0123] (6) Request conversion: The CXL root port RP converts the received request into a CXL flit;

[0124] (7) Address translation: The CXL controller translates the incoming address by subtracting the HDM base address from the incoming address to match the address space of the persistent memory inside the CXL device port EP;

[0125] (8) Issue a request to persistent memory: The CXL controller issues a request with the address translation to the underlying persistent memory controller;

[0126] (9) Return result: The processed data is returned to the CXL host through the CXL switch and FlexBus.

[0127] In a specific embodiment, the structure of the CXL controller is as follows: Figure 5 The figure shows the runtime software stack and the process of using decomposed memory through the CXL namespace by the application. The specific steps of the software driver are as follows:

[0128] (1) Detect CXL devices: CXL devices are detected during PCIe enumeration;

[0129] (2) Create an entry device: After detecting the CXL device, the software driver creates an entry device (for example, / dev / cxl-pmem1) so that users can manage the cxl-namespace through ioctl commands;

[0130] (3) Requesting cxl-namespace: The user sends a request to / dev / cxl-pmem1 to create a cxl-namespace;

[0131] (4) Check the address space: The driver checks a continuous address space on the HDM by referencing its HDM segment table. The table records the offset, size, and reference count of the segment (recording how many cxl-namespaces point to this segment). Multiple processes can access the segment table. The table header contains spin locks, read-write locks, and summary information of the table entries.

[0132] (5) Allocate a segment and create a mapping device: The driver allocates a segment according to the user request, creates a device for mmap (for example, / dev / cxl-ns0), and updates the segment table;

[0133] (6) Mapping virtual memory: The user application uses mmap and vm_area_struct to map the virtual memory space of its process to the cxl-namespace.

[0134] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0135] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for directly accessing persistent memory on a CXL bus, characterized in that: include: A CXL host, a CXL switch, a CXL device and a driver module; the system bus of the CXL host is connected to the CXL device through the CXL switch; the CXL device includes a persistent memory, and the driver module maps the persistent memory inside the CXL device to the memory space of the CXL host.

2. A method for directly accessing persistent memory on a CXL bus according to claim 1, characterized in that: The system bus of the CXL host connects the CXL device through the CXL switch, including: connecting one or more CXL root ports through the system bus of the CXL host; the CXL root port connects one or more CXL devices through the CXL switch; the CXL root port RP of the CXL host is connected to the CXL switch; and the CXL switch is connected to the CXL device port EP.

3. The method for directly accessing persistent memory on a CXL bus according to claim 1, characterized in that: The CXL switch comprises: a CXL switch upstream port USP and a CXL switch downstream port DSP; the CXL switch upstream port USP is used to connect to a CXL root port RP of the CXL host; the CXL switch downstream port DSP is used to connect to another CXL switch upstream port USP or the CXL device port EP.

4. A method for directly accessing persistent memory on a CXL bus according to claim 3, characterized in that: Also includes: The CXL switch includes multiple USPs and DSPs; The CXL switch allows connecting a plurality of the CXL hosts and a plurality of the CXL devices.

5. The method for directly accessing persistent memory on a CXL bus according to claim 3, characterized in that: The CXL switch working steps are: Step A1: Connect the CXL device Connecting the CXL root port RP of the CXL host to the upstream port USP of the CXL switch or directly to the CXL device, and connecting the downstream port DSP of the CXL switch to another upstream port USP of the CXL switch or directly to the CXL device port EP; Step A2: Configure the CXL switch Using the fabric manager to set up an internal routing table, reconfigure the crossbar of the switch, and connect each of the USPs to a different DSP; Step A3: Create CXL Virtual Hierarchy Through reconfiguration of the crossbar switch, a virtual hierarchy is created from the CXL host to the CXL devices.

6. The method for directly accessing persistent memory on a CXL bus according to claim 1, characterized in that: The CXL device includes: a CXL device port EP, a base address register BAR, a CXL host-managed device memory HDM, a CXL controller and a persistent memory; The CXL device uses one or more of the CXL controllers and a plurality of persistent memories; defining a plurality of logical devices, each logical device exposing its device memory HDM managed by the CXL host to the CXL host; The CXL device port EP is used to connect to the CXL switch; The CXL controller is used to map the persistent memory inside the CXL device to the memory space of the CXL host through CXL.

7. A method for directly accessing persistent memory on a CXL bus according to claim 6, characterized in that: The CXL controller works as follows: Step B1: Connect the CXL device Ensure that the system bus of the CXL host is connected to one or more CXL root ports RP, and one or more CXL root ports RP are connected to the CXL device port EP; Step B2: Query the CXL device information The kernel driver of the CXL host queries the base address register BAR of the CXL device and the size of the device memory HDM managed by the CXL host through PCIe transactions; Step B3: Mapping the BAR and HDM Based on the retrieved size, the kernel driver maps the BAR and HDM of the CXL device in the system memory space reserved by the CXL host; Step B4: Send device mapping location Sending to the CXL device the mapping location of the BAR and HDM of the CXL device in the memory of the CXL host system; Step B5: Access the HDM The CXL host CPU accesses the mapped HDM system memory through load / store instructions, and the request is passed to the corresponding CXL root port RP; Step B6: Conversion Request The CXL root port RP converts the received request into a CXL flit; Step B7: Convert the address The CXL controller converts the incoming address to match the address space of the persistent memory inside the CXL device port EP by subtracting the base address of the HDM from the incoming address; Step B8: Issue a request to persistent memory The CXL controller sends a request after address translation to the underlying persistent memory controller; Step B9: Return the result The processed data is returned to the CXL host via the CXL switch and FlexBus.

8. The method for directly accessing persistent memory on a CXL bus according to claim 1, characterized in that: The driver module includes a software driver, which is used to manage the underlying CXL device and expose its HDM in the memory space of the application; the software driver divides the address space of the HDM into multiple segments to obtain cxl-namespace; the software driver allows the CXL host application to access the cxl-namespace in the form of a memory mapped file mmap.

9. The method for directly accessing persistent memory on a CXL bus according to claim 8, characterized in that: The software driver working steps are: Step C1: Detect CXL device The CXL device is detected during PCIe enumeration; Step C2: Create an entry device The software driver creates an entry device after detecting the CXL device; Step C3: Request the cxl-namespace The user sends a request to the entry device to create a cxl-namespace; Step C4: Check the address space The driver checks for a contiguous address space on the HDM by referencing its HDM segment table; Step C5: Allocate segments and create mapped devices The driver allocates a segment according to the user request, creates a device for mmap, and updates the segment table; Step C6: Mapping Virtual Memory The CXL host application uses mmap and vm_area_struct to map the virtual memory space of its process into the cxl-namespace.

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