Bus relay device and interconnection system supporting simultaneous response to multi-instruction transmission

Abstract

The present invention provides a bus relay device and an interconnection system that support simultaneous response to multi-instruction transmission. The bus relay device is used to connect slave devices and an interconnection bus, and includes an instruction processing unit and a cache unit. The instruction processing unit is configured to separate and integrate multiple received instructions, and transmit the processed instructions to the cache unit. The cache unit is configured to determine to directly perform read and write operations in the cache unit according to the processed instructions, or send the processed instructions to the slave device for read and write operations. By separating and integrating read and write instructions, the present invention makes read and write operations independent of each other and processed in parallel, reduces the number of read and write access times with an equal relationship to one time, avoids repeated read and write, saves instruction processing time, and the cache unit supports multiple reads and writes. Read and write instructions from multiple master devices can be queried simultaneously, effectively reducing the access time to the slave device.

Description

Technical Field

[0001] This application relates to the field of computer technologies, and particularly to a bus relay device and an interconnection system that support simultaneous response to multiple instruction transmissions. Background Art

[0002] With the development of integrated circuit manufacturing technologies, there are usually many master and slave devices in a system on chip (SoC), and the devices are interconnected and communicate through an on-chip bus. When a master device such as a microprocessor or a microcontroller accesses a slave device such as a memory or a peripheral device, conflicts between instructions of multiple master devices often occur. For example, when multiple master devices access the same slave device simultaneously, since the slave device can only respond to one read / write instruction at a time, the remaining master devices that fail in the competition will enter a waiting state. Even when multiple master devices access the same address, the slave device needs to be accessed one by one, and the shared use of access resources cannot be achieved. The resulting competition for limited resources has become one of the important factors affecting system performance.

[0003] In a multi-master and multi-slave system, when multiple master devices issue instructions simultaneously, a common practice for the on-chip bus is to first classify the instructions of the master devices according to the access addresses, mask the instructions accessing the same slave device according to the priority (QoS) information of the master devices, and finally perform polling / fixed-priority arbitration on the instructions of the remaining master devices. The master device that succeeds in the competition sends the instruction to the slave device for reading and writing, and the remaining master devices need to wait for the slave device to be idle and repeat the above process until the competition is successful. With the increase in the number of master devices, limited by the response ability of the slave device, the waiting time of the master devices with lower priorities increases, and the following problems exist: the data required by the master device with a lower priority has already been read by the other master devices, but it still needs to wait; the master device with a higher priority has just written data to the same address, and the master device with a lower priority is still queuing to read from the slave device; two master devices write to the same address simultaneously, and two write operations are queued and sent, resulting in duplicate writes, etc. Ultimately, the above problems are due to the fact that the bus does not have the ability to process multiple instructions simultaneously, so the access is limited by the response ability of the slave device, resulting in low system working efficiency and high power consumption.

[0004] It should be noted that the above introduction to the technical background is only for the convenience of clearly and completely explaining the technical solutions of this application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art just because these solutions are described in the background art part of this application. Summary of the Invention

[0005] The object of the present invention is to provide a bus relay device, so that the on-chip bus has the ability to process multiple read and write instructions simultaneously, separate and integrate the read and write instructions from multiple hosts, minimize the number of accesses to slave devices, avoid access conflicts, and save access time.

[0006] To solve the above problems, in a first aspect, a bus relay device supporting simultaneous response to multi-instruction transmission is provided. The bus relay device is used to connect a slave device and an interconnect bus; the bus relay device includes an instruction processing unit and a cache unit.

[0007] The instruction processing unit is configured to separate and integrate the received multiple instructions, and transmit the processed instructions to the cache unit.

[0008] The cache unit is configured to determine to directly perform read and write operations in the cache unit according to the processed instructions, or send the processed instructions to the slave device for read and write operations.

[0009] The solution of the present invention separates and integrates read and write instructions through the instruction processing unit, makes the read and write operations independent of each other and processed in parallel, reduces the number of read and write accesses with an equal relationship to one time, avoids repeated reading and writing, and saves the instruction processing time; at the same time, since the cache unit supports multiple reads and writes, the read and write instructions from multiple master devices can be queried simultaneously. In the most ideal case, all read data is returned by the cache and all write data is stored, eliminating the competitive waiting time and reducing the access time to the slave device.

[0010] The instruction processing unit is configured to separately separate the received multiple instructions into read instructions and write instructions, and separately integrate the read instructions and the write instructions; the integration processing includes merging multiple read instructions with the same read address into one read instruction, and merging multiple write instructions with the same write address into one write instruction. The read and write instructions from multiple master devices are separated, and repeated accesses are merged, greatly reducing the number of accesses and shortening the waiting time of the master device.

[0011] The integration processing of the instruction processing unit further includes: merging the corresponding read instructions with consecutive read addresses in the merged read instructions into one read instruction, and merging the corresponding write instructions with consecutive write addresses in the merged write instructions into one write instruction. Further reduce the number of accesses and shorten the waiting time of the master device.

[0012] The instruction processing unit is used to separately correspond the received multiple instructions into read instructions and write instructions, and match the addresses of the read instructions and the write instructions. If the addresses are equal, the corresponding write data is directly returned as read data through the bus relay device. Only the write operation to the cache needs to be performed, and the read process is omitted, further improving the access efficiency of the master device to the bus.

[0013] The cache unit is used to retrieve in the cache unit according to the received read instructions, directly perform a read operation on the cache unit after a hit of the read instructions and then return, and send the read instructions that miss to the slave device for a read operation and then return; the cache unit is used to judge the category of the received write instructions, directly perform a write operation on the cache unit for the corresponding write instructions whose write data is cacheable write data and then return, and send the corresponding write instructions whose write data is non-cacheable write data to the slave device for a write operation and then return. With an additional cache unit, it allows read and write instructions not to be sent to the slave device, making it possible to integrate and release the read and write operations of the master device in advance, reducing the access time; the cache that supports multiple writes and reads enables the bus to have the ability to receive multiple read and write instructions.

[0014] The cache unit includes a cache table information unit, a cache maintenance unit, and a cache storage unit; the cache storage unit is used to store data, the cache maintenance unit is used to allocate cache addresses, and the cache table information unit is used to correspondingly record the physical address and the cache address of the data. It can perform temporary access to data and can achieve reasonable allocation of cache resources.

[0015] When the bus is idle or the cache storage unit is about to be full, the cache maintenance unit writes the valid data in the cache storage unit into the slave device. Wait for the slave device to be idle and then initiate the write, fully coordinating the bus resources and reducing the unnecessary queuing time.

[0016] It also includes an arbitration unit; the arbitration unit is used to perform arbitration according to the priority and then queue and send to the slave device before sending the processed instructions to the slave device for read and write operations.

[0017] Judge the category of the write instructions according to the special identification bit.

[0018] On the other hand, the present application also provides a bus interconnection system device, including a plurality of master devices and a plurality of slave devices connected through an interconnection bus;

[0019] On the slave device side of the interconnection bus, a bus relay device as described in any one of the first aspects is provided. The bus relay device corresponds to each of the slave devices one by one and is used to implement the access of each slave device to the multiple master devices. The bus relay device has a high degree of compatibility with the existing bus interconnection system, can be conveniently placed in the bus interconnection system, can fully coordinate bus resources, and improve the access efficiency of the master device to the bus.

[0020] Compared with the prior art, the beneficial effects of the present invention mainly include the following: 1) It can respond to multiple read and write instructions simultaneously, reducing the waiting time of the master device; 2) It has an instruction integration function, which can reduce the number of accesses for repeated accesses and reduce power consumption; 3) The device is equipped with a cache, allowing read and write instructions not to be sent to the slave device, reducing the access time, initiating writing when the slave device is idle, fully coordinating bus resources, and reducing unnecessary queuing time. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following described drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0022] Figure 1 It is a schematic diagram of a bus relay device provided by the present invention.

[0023] Figure 2 It is a flowchart of the operation of a bus relay device provided by the present invention.

[0024] Figure 3 It is a schematic diagram of the system architecture of a bus interconnection system provided by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] Regarding the foregoing and other technical contents, features and effects of the present invention, they will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The directional terms mentioned in the following embodiments, such as: up, down, left, right, front or back, etc., are only references to the directions of the attached drawings. Therefore, the directional terms used are for illustration and not for limiting the present invention.

[0026] The following will elaborate on each embodiment of the present application with reference to the drawings. However, those of ordinary skill in the art can understand that in each embodiment of the present application, many technical details are provided for the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions required to be protected by the present application can still be implemented.

[0027] The steps in the following embodiments do not correspond one by one to the content of the invention.

[0028] Embodiment 1:

[0029] Figure 1 This invention provides a schematic diagram of a bus relay device. Figure 2 This invention provides a flowchart of the operation of a bus relay device.

[0030] Refer to Figure 1-2 As shown, this invention first provides a bus relay device that supports simultaneous response to multiple instruction transmissions. The bus relay device is set on the slave device side of the bus and is used to connect the slave device and the interconnect bus. The bus relay device includes an instruction processing unit and a cache unit. The cache unit includes a cache table information unit, a cache maintenance unit, and a cache storage unit. The instruction processing unit is used to separate and integrate the multiple received instructions and transmit the processed instructions to the cache unit. The cache unit is used to determine whether to directly perform read and write operations in the cache unit according to the processed instructions, or send the processed instructions to the slave device for read and write operations.

[0031] It can be understood that in a multi-master and multi-slave bus interconnect system (i.e., a bus interconnect system with multiple master devices and multiple slave devices), one of the slave devices may be accessed simultaneously by multiple master devices, that is, receive multiple instructions simultaneously. Instructions can generally be divided into read instructions and write instructions. Among them, the read instruction carries the storage address of the data to be read (i.e., the read address), and the write instruction carries the data to be written and the storage address where the data to be written is to be stored (i.e., the write address).

[0032] Refer to Figure 1-2As shown, when the bus relay device receives multiple instructions (i.e., Instruction 1 to Instruction n, corresponding to Master Device 1 to Master Device n respectively), the instruction processing unit will separate and integrate the instructions. Specifically, the instruction processing unit will first separate the multiple instructions into two types: read instructions and write instructions, and then separately perform integration processing on the read instructions and write instructions. The integration process includes merging instructions with the same address (including read address and write address) into one. Taking the read instructions as an example, for the multiple separated read instructions, compare the read addresses of each read instruction and merge the corresponding read instructions with the same read address range into one, which can reduce the number of instructions. Similarly, for the multiple separated write instructions, compare the write addresses of each write instruction and merge the corresponding write instructions with the same write address range into one. Further, for the instructions after the above merging, instructions with consecutive addresses after merging can be merged into one again to further reduce the number of instructions. It can be understood that after the separation and integration by the instruction processing unit, the number of instructions can be effectively reduced. The addresses of all read instructions and write instructions can also be matched. For those with equal read address and write address, the corresponding write data can be directly returned as the required read data through the bus relay device; to improve the subsequent hit in the cache, the write data can be written into the cache for subsequent read instructions to query. Finally, referring to Figure 2 , it is possible to reduce n instructions to x read instructions and y write instructions (x + y < n).

[0033] The instruction processing unit transmits the processed instructions (x read instructions and y write instructions) to the cache unit. The cache unit specifically includes a cache table information unit, a cache maintenance unit, and a cache storage unit; among them, the cache storage unit is responsible for data storage, and the cache table information unit is used to record the physical address and cache address of the data, and the cache maintenance unit is responsible for maintenance.

[0034] This cache unit supports multiple reads and multiple writes. When the cache unit receives the processed instructions, for the read instructions, the cache unit first retrieves in the cache unit according to the received read instructions, directly performs a read operation on the cache unit after a hit of the read instruction and returns it, and sends the unhit read instructions to the slave device for a read operation and then returns. Specifically, the x read instructions simultaneously query the physical addresses stored in the cache table information unit to determine whether the access address generates a hit. If a hit occurs (as Figure 2 shown, j read instructions generate a hit), then query the cache storage unit according to the cache address corresponding to the physical address and return the data therein to the corresponding master device; if no hit occurs (as Figure 2As shown, if x - j read instructions miss, then slave device access is required. For the x - j missed read instructions, arbitration will be performed according to the priority, and finally they will be queued and sent to the slave device for reading operations and returned to the corresponding master device through the bus relay device. It can be understood that the situation of no hit usually occurs when the device is just used. As the usage frequency increases, the cache hit probability will also increase.

[0035] Considering that directly writing data into the slave device is inefficient, in order to reduce the data written to the slave device, the write data can be pre - classified into at least two categories. One is the data that can be written into the cache storage unit, called cacheable write data, and the other is the data that must be written to the slave device side (such as register configuration), called non - cacheable write data. The difference between cacheable write data and non - cacheable write data can be confirmed by using some preset rules or flags. For example, a special identification bit (such as the USER of AXI) can be used for identification.

[0036] Then, when the cache unit receives the processed write instruction, the cache unit can judge the category of the received write instruction, directly perform the write operation on the corresponding write instruction with cacheable write data in the cache unit and then return, and send the corresponding write instruction with non - cacheable write data to the slave device for write operation and then return. Refer to Figure 2 , the cacheable write data and non - cacheable write data in y write instructions can be judged first according to the special identification bit. For the cacheable write data, it can be directly stored in the cache storage unit. Specifically, refer to Figure 2 , the corresponding write instructions (k pieces) are allocated cache addresses by the cache maintenance unit, and the cache addresses and the actual physical addresses are stored in the cache table information unit together. The cacheable write data is also stored in the cache storage unit according to the cache address. For the non - cacheable write data, since it needs to be written to the slave device, the remaining write instructions (y - k pieces) are arbitrated according to the priority, and finally queued and sent to the slave device for write access.

[0037] After the above - mentioned processing by the bus relay device, the originally n instructions that need to be queued and arbitrated are finally simplified to only x - j read instructions and y - k write instructions queued and arbitrated at the slave end.

[0038] In this device, multiple read instructions with equal read addresses are merged into one, only triggering one cache read access or slave device read access; multiple write instructions with equal write addresses are merged into one, also only triggering one cache write access or slave device write access (under the same address, the write operation that must be written to the slave device will overwrite the cacheable write operation. Further, since the write instruction with the lowest priority is written last, only one write operation with the lowest priority is triggered); furthermore, the instructions with consecutive addresses after merging can be merged into one again to further reduce the read and write operations.

[0039] In this device, when the slave device is idle or the remaining cache space is small, a write operation can also be initiated to the slave device through the cache maintenance unit to truly write the data into the slave device. The data after the write operation is completed will be overwritten in the subsequent write operations initiated by the master device, realizing the allocation of cache resources.

[0040] Embodiment 2

[0041] Figure 3 FIG. [X] is a schematic diagram of the system architecture of a bus interconnection system provided by the present invention. The present invention also provides a bus interconnection system, including a plurality of master devices and a plurality of slave devices, where the master devices and the slave devices are connected through a bus; a bus relay device as described above is provided on the slave device side of the interconnection bus, and the bus relay devices and the slave devices are in one-to-one correspondence, and are used to implement the access of each of the slave devices and the plurality of master devices.

[0042] Based on the traditional bus distribution arbitration, this bus interconnection system adds a bus relay device. Through the instruction processing unit and the cache unit of the bus relay device, while ensuring the bus distribution instructions, it can support receiving multiple read / write instructions and responding, reducing the number of accesses to the slave devices and increasing the access efficiency of the master devices.

[0043] As Figure 3 shown, when multiple master devices (master device 1 to master device n) issue read / write instructions, after passing through their respective bus control devices, they are distributed to the bus relay devices at the corresponding slave device ends according to the address range, and the bus relay devices separate and integrate the received instructions and then process them respectively. When the data and the response are ready, they are returned to the master device by the bus relay device and the bus control device to complete the access.

[0044] Some common English nouns or letters used in the present invention for the convenience of clear description are only used for exemplary reference rather than restrictive interpretation or specific usage, and the protection scope of the present invention should not be limited by their possible Chinese translations or specific letters.

[0045] It should also be noted that in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

Claims

1. A bus relay device supporting simultaneous response to multi-instruction transmission, characterized in that The bus relay device is used to connect slave devices and an interconnect bus; the bus relay device includes an instruction processing unit and a cache unit; The instruction processing unit is used to separate and integrate multiple received instructions, and transmit the processed instructions to the cache unit; The cache unit is used to determine whether to directly perform read and write operations in the cache unit according to the processed instructions, or send the processed instructions to the slave device for read and write operations; The instruction processing unit is used to separately separate multiple received instructions into read instructions and write instructions, and separately integrate the read instructions and the write instructions; The integration processing includes merging multiple read instructions with the same read address into one read instruction, and merging multiple write instructions with the same write address into one write instruction; The integration processing of the instruction processing unit further includes: merging the corresponding read instructions with consecutive read addresses in the merged read instructions into one read instruction, and merging the corresponding write instructions with consecutive write addresses in the merged write instructions into one write instruction.

2. The bus relay device for supporting simultaneous response to multi-instruction transmission according to claim 1, characterized in that The instruction processing unit is used to separately separate multiple received instructions into read instructions and write instructions, and match the addresses of the read instructions and the write instructions. If the addresses are equal, the corresponding write data is directly returned as read data through the bus relay device.

3. The bus relay device supporting simultaneous response to multi-instruction transmission according to claim 1, characterized in that The cache unit is used to retrieve in the cache unit according to the received read instructions, directly perform a read operation on the cache unit after a hit of the read instructions and return, and send the unhit read instructions to the slave device for a read operation and then return; The cache unit is used to judge the category of the received write instructions, directly perform a write operation on the cache unit for the corresponding write instructions with cacheable write data and return, and send the corresponding write instructions with non-cacheable write data to the slave device for a write operation and then return.

4. The bus relay device supporting simultaneous response to multi-instruction transmission according to claim 3, characterized in that The cache unit includes a cache table information unit, a cache maintenance unit, and a cache storage unit; The cache storage unit is used to store data, the cache maintenance unit is used to allocate cache addresses, and the cache table information unit is used to correspondingly record the physical address and the cache address of the data.

5. The bus relay device supporting simultaneous response to multi-instruction transmission according to claim 4, characterized in that When the bus is idle or the cache storage unit is about to be full, the cache maintenance unit writes the valid data in the cache storage unit into the slave device.

6. The bus relay device for supporting simultaneous response to multi-instruction transmission according to claim 1, characterized in that It further includes an arbitration unit; The arbitration unit is used to perform arbitration according to the priority and queue and send to the slave device before sending the processed instructions to the slave device for read and write operations.

7. The bus relay device for supporting simultaneous response to multi-instruction transmission according to claim 3, characterized in that Judge the category of the write instructions according to a special identification bit.

8. A bus interconnection system device, characterized in that, It includes multiple master devices and multiple slave devices connected through an interconnect bus; On the slave device side of the interconnect bus, there is provided a bus relay device as described in any one of claims 1-7. The bus relay device corresponds to each slave device one by one and is used to realize the access of each slave device and the multiple master devices.

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