Data transmission method, chip and data transmission device
By using a ring bus structure in the switching chip to connect to multiple ports and transmit letters of credit on it, the exponential increase in the number of credit channels caused by the increase in the number of ports is solved, and the lossless forwarding of all ports is achieved and the overhead of trace area is reduced.
Patent Information
- Application Number
- CN202311440134.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-31
- Publication Date
- 2025-05-02
AI Technical Summary
When the current switching chip realizes internal credit channels, as the number of ports increases, the number of letters of credit channels that need to be established increases exponentially, resulting in significant trace area overhead, increased cost, power consumption and implementation difficulty.
The ring bus structure is used to connect to multiple ports, and the letter of credit is transmitted on the ring bus, so that each port can obtain the letter of credit, thereby realizing lossless forwarding of the full port and reducing the overhead of chip trace area.
While ensuring lossless forwarding of all ports, it reduces chip trace area overhead, reduces cost and power consumption, and simplifies implementation difficulty.
Smart Images
Figure CN119917445A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the technical field of data transmission, and in particular, to a data transmission method, a chip, and a data transmission device. Background Art
[0002] In recent years, with the rise of AI technologies that require large-scale computing power, such as chatbot programs, and the delay of Moore's Law, the computing power and memory capacity of a single chip can no longer meet the industry's growing demand for computing power. Cluster computing has become a hot topic, that is, interconnecting multiple processors through a high-performance network to achieve cluster parallel computing. Compared with the Ethernet lossy network that actively loses packets, high-performance networks usually use credit flow control technology to achieve lossless (no packet loss) transmission. At present, a switching switch chip usually has multiple ports. When the downstream chip sends a letter of credit to a port of the switching chip, the letter of credit received by this port will be used by the messages received by all the inbound ports of the switching chip. Therefore, the switching chip needs to implement a letter of credit channel between all ports to ensure that the messages received by each inbound port can use the letter of credit, thereby realizing full-port switching and forwarding.
[0003] The common practice for current switching chips to implement internal credit channels is to set up a full crossbar switch matrix, that is, each input port must establish a credit channel with all output ports, so that each message received by the input port can directly apply for / consume credit from the corresponding output port after routing. However, as the number of ports increases, the number of credit channels that need to be established in the full crossbar architecture will also increase exponentially. These channels will bring significant routing area overhead, increase cost, power consumption and implementation difficulty. Summary of the invention
[0004] The embodiments of the present application provide a data transmission method, a chip, and a data transmission device, which are used to reduce the chip routing area overhead when achieving lossless transmission.
[0005] In a first aspect, an embodiment of the present application provides a data transmission method, which is applied to a first chip. The first chip includes a plurality of ports and a ring bus, and the ring bus is connected to each of the plurality of ports. The method includes:
[0006] The first chip may receive a first letter of credit from a second chip through a first port, the first port being any port among a plurality of ports, and the second chip being a downstream chip of the first chip. The first chip may transmit the first letter of credit on a ring bus.
[0007] In this method, the first chip is connected to each of the multiple ports by deploying a ring bus, and the first letter of credit is transmitted on the ring bus, so that each of the multiple ports in the first chip can use the first letter of credit, thereby reducing the chip routing area overhead while ensuring lossless forwarding of all ports.
[0008] In a possible design, the first chip can also determine the first ring credit bus corresponding to the first port from the ring bus, and determine the first time slot corresponding to the first letter of credit. The first chip determines the first initial time slot of the first control signal transmitted on the first ring credit bus, and the first control signal is used to mark the starting point of the first ring credit bus transmitting the letter of credit information. When the first chip determines that the current time slot is the first time slot based on the first initial time slot, the first letter of credit is uploaded to the first ring credit bus, and the first quantity of the first letter of credit corresponding to the first port is updated.
[0009] Through this design, the first chip divides the letter of credit information carried on the first ring credit bus into different time slots according to the time granularity, and uses the first time slot to carry the first letter of credit, that is, the first chip uses different time slots to carry different types of letter of credit information. When the first chip determines that the current time slot is the first time slot, it can upload the first letter of credit to the first ring credit bus, so that each port can obtain the first letter of credit from the first time slot, thereby realizing full-port lossless forwarding efficiently and quickly.
[0010] In a possible design, the first control signal is a pulse signal, and the first chip can use the time slot when the first control signal is at a high level as the first initial time slot.
[0011] Through this design, the first chip can determine the starting point of the time slot for transmitting the letter of credit information on the ring credit bus according to the time slot where the first control signal is at a high level.
[0012] In a possible design, the first chip can also receive the message through the second port, and the second port is any port of the multiple ports. The first chip can determine a third port for outputting the message from the multiple ports, and forward the message using the second letter of credit corresponding to the third port.
[0013] Through this design, the first chip uses the second letter of credit corresponding to the third port to forward the message, which can achieve lossless forwarding of the message.
[0014] In one possible design, the first chip can also determine the second data of the second credit at the second port, and the third number of credits required to forward the message. When the second number is greater than or equal to the third number, the first chip can deduct the third number of second credits from the second credit at the second port, and use the third number of second credits to forward the message.
[0015] With this design, when forwarding a message, the first chip first determines whether there are enough second letters of credit stored locally to forward the message. When it is determined that there are enough second letters of credit locally, the first chip can directly deduct the third number of second letters of credit for forwarding the message, thereby realizing lossless forwarding efficiently and quickly.
[0016] In one possible design, when the second number is less than the third number, the first chip can also determine the second ring credit bus corresponding to the third port from the ring bus. The first chip determines the second time slot corresponding to the second letter of credit, and determines the second initial time slot of the second control signal transmitted on the second ring credit bus, the second control signal is used to mark the starting point of the second ring credit bus transmitting the letter of credit information. The first chip can also determine that the current time slot is the second time slot based on the second initial time slot.
[0017] With this design, when the second number is less than the third number, the first chip determines that the local second letter of credit cannot support the forwarding of the message, and the first chip can also obtain the third number of second letters of credit from the second ring credit bus. The first chip can determine whether the current time slot is the second time slot carrying the second letter of credit according to the second initial time slot of the second control signal transmitted on the second ring credit bus, so that the first chip can obtain the second letter of credit from the second ring credit bus, thereby realizing lossless forwarding efficiently and quickly.
[0018] In a possible design, when the first chip determines that the current time slot is the second time slot, it determines whether the fourth number of second credits on the second ring credit bus is greater than or equal to the third number. If so, the first chip deducts the third number of second credits from the second credits on the second ring credit bus, and uses the third number of second credits to forward the message. If not, the first chip continues to determine the number of second credits on the second ring credit bus until the number of second credits on the second ring credit bus is greater than or equal to the third number.
[0019] With this design, when the number of second credits on the second ring credit bus of the first chip meets the number of credits required for forwarding the message, the second credit corresponding to the number of credits is directly deducted, thereby realizing lossless forwarding efficiently and quickly. However, when the number of second credits on the second ring credit bus does not meet the number of credits required for the message, the second chip will continue to wait until the number of second credits on the second ring credit bus meets the number of credits required for forwarding the message.
[0020] In a possible design, the first chip may also update the quantity of the second letter of credit after using the second letter of credit corresponding to the third port to forward the message.
[0021] In one possible design, the ring bus includes multiple ring credit buses, and the multiple ring credit buses correspond one-to-one to the multiple ports.
[0022] Through this design, the ring bus connects each port in series, and the letter of credit information corresponding to each port can be transmitted on the corresponding ring credit bus, which can ensure that each port on the first chip can obtain the corresponding letter of credit and achieve efficient and fast lossless forwarding.
[0023] In one possible design, the first chip also includes multiple node control units, each of the multiple node control units includes at least two ports among the multiple ports, the ring bus includes multiple ring credit buses, and the multiple node control units correspond one-to-one to the multiple ring credit buses.
[0024] Through this design, multiple ports of the first chip form a node control unit, and multiple node control units correspond one-to-one to multiple ring credit buses. In this way, the ring credit bus connects each node control unit in series, and multiple ports share a ring credit bus to transmit letter of credit information, thereby reducing the chip routing area overhead and reducing the difficulty of chip implementation.
[0025] In a second aspect, the present application provides a chip, including a processor, a plurality of ports and a ring bus, wherein the ring bus is connected to each of the plurality of ports. Each of the plurality of ports is used to input and / or output data; the ring bus is used to transmit letter of credit information; and the processor is used to execute a computer program so that the method described in any one of the first aspects is executed.
[0026] In one possible design, the ring bus includes a plurality of ring-shaped credit buses.
[0027] In one possible design, multiple ring credit buses correspond one-to-one to multiple ports.
[0028] In one possible design, the chip further includes a plurality of node control units, each of the plurality of node control units includes at least two ports of the plurality of ports, and the plurality of node control units correspond one-to-one to the plurality of ring credit buses.
[0029] In a third aspect, the present application provides a data transmission device, applied to a first chip, wherein the first chip includes a plurality of ports and a ring bus, and the ring bus is connected to each of the plurality of ports. The data transmission device includes:
[0030] A communication unit, configured to receive a first letter of credit from a second chip through a first port; the first port is any port among the plurality of ports, and the second chip is a downstream chip of the first chip;
[0031] A processing unit for transmitting the first credit on the ring bus.
[0032] In a fourth aspect, the present application provides a computer-readable storage medium, in which a computer program or instructions are stored. When the computer program or instructions are executed by a computing device, the computing device executes any aspect of the above-mentioned first aspect, and any possible implementation of any aspect.
[0033] In a fifth aspect, the present application provides a computer program product, which includes a computer program or instructions. When the computer program or instructions are executed by a computing device, the computing device executes the method in any aspect of the above-mentioned first aspect and any possible implementation of any aspect. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] Figure 1 is a schematic diagram of the architecture of a data transmission system;
[0035] Figure 2 A schematic diagram of the hardware structure of a possible chip provided for this application;
[0036] Figure 3 A flowchart of a data transmission method provided by this application;
[0037] Figure 4 A schematic diagram of the structure of a port and a ring credit bus provided by the present application;
[0038] Figure 5 A schematic diagram of the structure of another port and ring credit bus provided by the present application;
[0039] Figure 6 A schematic diagram of the structure of a letter of credit information provided for this application;
[0040] Figure 7 A schematic diagram of the structure of another letter of credit information provided for this application;
[0041] Figure 8 A schematic diagram of a control signal transmission provided by the present application;
[0042] Fig. 9 A schematic diagram of the structure of a chip provided in this application;
[0043] Fig.10 A complete flow chart of a data transmission method provided by this application;
[0044] Fig.11 A schematic diagram of the structure of a data transmission device provided by the present application;
[0045] Fig.12A schematic diagram of the structure of a chip provided in this application. DETAILED DESCRIPTION
[0046] The technical solutions in the embodiments of the present application will be described in detail below in conjunction with the drawings in the following embodiments of the present application.
[0047] First, concepts related to the embodiments of the present application are explained.
[0048] Credit flow control technology refers to data transmission technology that achieves lossless transmission. Its principles are as follows:
[0049] The downstream chip converts its own receive buffer buffer into a number of credits and passes it to the upstream chip through the port connected to the upstream chip. After the upstream chip gets the credit (CRD), if there is a message to be sent to the port, it will first subtract the credit of the message size before sending the message. If the credit is 0, the upstream chip cannot continue to send packets. After the downstream chip receives the message sent by the upstream, it can directly store it in the receive buffer. When the downstream chip receives the buffer, the downstream chip can continue to convert the released space into a credit and send it to the upstream. Because the corresponding credit must be deducted in advance for each message sent, this mechanism can ensure that the downstream chip receive buffer will never be overcharged and cause packet loss. Thus, high-performance lossless transmission is achieved.
[0050] In the embodiments of the present application, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, a and b, a and c, b and c, or a and b and c, where a, b, c can be single or multiple.
[0051] Furthermore, unless otherwise specified, the ordinal numbers such as "first" and "second" mentioned in the embodiments of the present application are used to distinguish multiple objects, and are not used to limit the size, content, order, timing, priority or importance of multiple objects. For example, the second file and the second file are only used to distinguish different files, and do not indicate the difference in size, content, priority or importance of the two files.
[0052] At present, switching chips usually have multiple ports. When the downstream chip of the switching chip sends a letter of credit to a port of the switching chip, the letter of credit received by this port will be used by the messages received by all the input ports of this chip. Therefore, the chip needs to implement a letter of credit channel between all ports to ensure that the message received by each port can use the letter of credit, so as to realize full-port switching and forwarding. However, the common practice of current switching chips to implement internal credit channels is to set up a full crossbar switch matrix, that is, each input port must establish a credit channel with all output ports, so that the message received by each entrance can directly apply for / consume the letter of credit from the corresponding output port after routing. However, as the number of ports increases, the number of letter of credit channels that need to be established for the full crossbar architecture will also increase exponentially. These channels will bring significant routing area overhead, increase cost, power consumption and implementation difficulty.
[0053] Based on the above problems, an embodiment of the present application provides a data transmission method, a chip, and a data transmission device. The data transmission method is applied to a first chip, the first chip includes multiple ports and a ring bus, and the ring bus is connected to each of the multiple ports. The method includes: the first chip can receive a first letter of credit from the second chip through the first port, the first port is any port of the multiple ports, and the second chip is a downstream chip of the first chip. The first chip transmits the first letter of credit on the ring bus, so that each of the multiple ports can obtain the letter of credit from the ring bus, while ensuring efficient and fast full-port lossless transmission, reducing the area overhead of the chip routing.
[0054] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.
[0055] Figure 1 A schematic diagram of the architecture of a possible data transmission system applicable to the solution provided in the embodiment of the present application. Figure 1 As shown, the system includes a first chip and a second chip. The first chip is an upstream chip of the second chip. Exemplarily, the first chip and the second chip can be high-order lossless switching chips.
[0056] Figure 2 A possible hardware structure diagram of a chip provided in this application. Figure 2 As shown, the chip includes a plurality of ports and a ring bus, and the ring bus is connected to each of the plurality of ports. Figure 2 The chip shown can be Figure 1 The first chip shown may also be Figure 1 The second chip is shown.
[0057] like Figure 1As shown, the first chip and the second chip can be connected through a port. The second chip can send a letter of credit to the port in the first chip that is connected to it. The first chip receives the letter of credit through the port corresponding to the second chip and transmits the letter of credit on the ring bus. The letter of credit will pass through multiple ports on the ring bus in sequence. In this way, each port in the first chip can obtain the letter of credit on the ring bus to forward data, thereby realizing full-port lossless forwarding efficiently and quickly, and reducing the chip routing area overhead.
[0058] The solution provided in this application is introduced below in conjunction with specific embodiments.
[0059] Figure 3 A schematic diagram of a data transmission method provided in an embodiment of the present application is applied to a first chip. The first chip may be as follows Figure 2 The chip shown. Figure 3 As shown, the method includes:
[0060] S301: A first chip receives a first letter of credit from a second chip through a first port, wherein the first port is any port among a plurality of ports, and the second chip is a downstream chip of the first chip.
[0061] S302: The first chip transmits a first letter of credit on the ring bus.
[0062] In some embodiments, after receiving the first letter of credit from the second chip through the first port, the first chip can upload the first letter of credit to the ring bus for transmission.
[0063] The ring bus includes a plurality of ring credit buses. Exemplarily, the first chip can upload the first letter of credit to the ring credit bus corresponding to the first port for transmission. The first chip can upload the first letter of credit to the ring credit bus corresponding to the first port for transmission in the following manner.
[0064] A1: The first chip determines a first ring credit bus corresponding to a first port from the ring bus.
[0065] In some embodiments, multiple ring-shaped credit buses may correspond to multiple ports one by one. That is, one ring-shaped credit bus transmits the credit information corresponding to one port. For example, Figure 4As shown, the chip includes 8 ports, and the ring bus includes 8 ring credit buses R1, R2, ..., R8. Among them, the ring credit bus R1 is used to transmit the letter of credit information corresponding to port 1, the ring credit bus R2 is used to transmit the letter of credit information corresponding to port 2, the ring credit bus R3 is used to transmit the letter of credit information corresponding to port 3, the ring credit bus R4 is used to transmit the letter of credit information corresponding to port 4, the ring credit bus R5 is used to transmit the letter of credit information corresponding to port 5, the ring credit bus R6 is used to transmit the letter of credit information corresponding to port 6, the ring credit bus R7 is used to transmit the letter of credit information corresponding to port 7, and the ring credit bus R8 is used to transmit the letter of credit information corresponding to port 8.
[0066] In some other embodiments, the first chip may further include multiple network control units (NCUs), each NCU including at least two of the multiple ports, and the multiple NCUs correspond one to one with the multiple ring credit buses. For example, the first chip is a 48-port switching chip, and every 4 physical ports in the switching chip are divided into a group called an NCU, and a total of 12 NCUs can be obtained. Figure 6 As shown, the 12 NCUs are connected in series through 12 ring credit buses, and each ring credit bus corresponds to one NCU. Figure 5 As shown, NCU0 corresponds to the ring credit bus R1, NCU1 corresponds to the ring credit bus R2, ..., NCU11 corresponds to the ring credit bus R12. For example, NCU0 includes four ports P0, P1, P2 and P3, and the ring credit bus R1 can transmit the letter of credit information corresponding to P0, P1, P2 and P3.
[0067] based on Figure 4 and Figure 5 As shown, each port in the first chip has a corresponding ring credit bus to transmit its corresponding letter of credit information. Compared with the full cross credit channel between the NCU or ports, the number of connections between the physical ports in the first chip is greatly reduced, thereby reducing the routing area and routing power consumption.
[0068] When the first chip transmits the letter of credit information on the ring credit bus, the ring credit bus can be divided into different time slots (time slices) based on the time granularity, and different time slots transmit the letter of credit information of different virtual channels (virtuallane, VL) of different ports. In this way, when a port of the first chip has a message to send, the first chip can obtain the required letter of credit from the corresponding time slot on the ring credit bus and complete the forwarding of the credit. In addition, when a port of the first chip receives a letter of credit from the downstream chip it is connected to, the letter of credit can be uploaded to the ring credit bus for transmission when the ring credit bus is in the time slot corresponding to the port.
[0069] In some embodiments, the first chip can mark the starting point of the ring credit bus transmitting the letter of credit information through a control signal. In this way, the first chip can determine the starting point of the ring credit bus transmitting the letter of credit information through the control signal, and determine the time slot for transmitting the letter of credit on the ring credit bus according to the starting point.
[0070] Exemplarily, the first chip can use a 1-bit single control signal to mark the starting point of the ring credit bus transmitting the letter of credit information. The control signal is a pulse signal. The control signal and the letter of credit information are periodically transmitted on the ring credit bus. In one cycle, the control signal and the letter of credit information are transmitted on the ring credit bus for one cycle.
[0071] The first chip periodically transmits control signals on the ring credit bus. Each cycle control signal will be transmitted once among multiple ports of the first chip. Exemplarily, one cycle can be 96 cycles, or it can be set to other values. Each cycle is called a time slot. For example, the first chip includes 12 NCUs, and every 96 cycle control signals will circulate once among the 12 NCUs.
[0072] For example, Figure 6 As shown, each physical port can correspond to multiple private letters of credit and one public letter of credit. When the control signal is pulled up and is at a high level, it means that the current time slot is the starting point of the letter of credit information transmitted on the ring credit bus. From the starting point, the fifth time slot, the public letter of credit corresponding to the physical port P0 is transmitted on the ring credit bus, and the private letter of credit 0 corresponding to the physical port P0 is transmitted in the sixth time slot of the next beat, and so on.
[0073] For another example, the first chip includes multiple NCUs, each of which includes 4 physical ports. The NCU includes physical ports P0, P1, P2, and P3. Each physical port can correspond to 9 private letters of credit and one public letter of credit. Then, one NCU corresponds to 40 different letters of credit, and each ring credit bus needs to use 40 time slots to carry these letter of credit information. The structure of the letter of credit information transmitted on the ring credit bus corresponding to each NCU is as follows: Figure 7 As shown. Figure 7 As shown in the figure, when the control signal is pulled up to a high level, it indicates that the current time slot is the starting point of the letter of credit information transmitted on the ring credit bus. In the fifth time slot from the starting point, the public letter of credit corresponding to the physical port P0 is transmitted on the ring credit bus, and the private letter of credit 0 corresponding to the physical port P0 is transmitted in the sixth time slot of the next beat, and so on.
[0074] After receiving the first letter of credit through the first port, the first chip will upload the first letter of credit to the time slot of its corresponding ring credit bus.
[0075] A2: The first chip can determine the first initial time slot of the first control signal transmitted on the first ring-shaped credit bus, and the first control signal is used to mark the starting point of the first ring-shaped credit bus transmitting the letter of credit information.
[0076] In some embodiments, the first chip can transmit control credits on each ring credit bus to mark the starting point of the credit information transmitted on the ring credit bus.
[0077] In some other embodiments, the ring bus may further include a ring control bus, which is used to transmit control signals. Figure 8 As shown, the ring bus includes a ring control bus S and ring credit buses R0, R1, ..., R11. The ring control bus S transmits a control signal to mark the starting point of the letter of credit information transmitted on the 12 ring credit buses.
[0078] The first chip may use the time slot when the first control signal is at a high level as the first initial time slot.
[0079] A3: After determining the first initial time slot, the first chip determines whether the current time slot is the first time slot.
[0080] A4: When determining that the current time slot is the first time slot, the first chip can upload the first credit to the first ring credit bus.
[0081] After the first chip uploads the first credit to the first ring credit bus, the first credit will be transmitted between multiple ports along the first ring credit bus. In this way, each port of the first chip can obtain the first credit from the first ring credit bus for consumption.
[0082] A5: After the first chip uploads the first letter of credit to the first ring-shaped credit bus, the first chip can also update the first quantity of the first letter of credit corresponding to the first port.
[0083] In some embodiments, when a first letter of credit is uploaded to a first time slot corresponding to the first ring-shaped credit bus, a counter counter of the first time slot will increase the number of letters of credit corresponding to the first letter of credit.
[0084] After the first chip uploads the credit received by the port to the corresponding ring credit bus for transmission, the first chip can also receive messages through the second port and use the credit to forward the messages losslessly. The second port is any port among the multiple ports.
[0085] In some embodiments, after receiving the message, the first chip determines a third port from multiple ports to output the message. Exemplarily, after receiving the message, the first chip can determine that the message needs to be sent from the third port by searching a preset forwarding table.
[0086] The first chip can use the second letter of credit corresponding to the third port to forward the message. Exemplarily, the second letter of credit corresponding to the third port can be located locally at the port for use by the port, or can be located on the ring credit bus for use by all ports. Optionally, the letter of credit located locally at the port can be an unused letter of credit obtained by the port from the ring credit bus.
[0087] In some embodiments, the first chip may determine a second number of second credits at the second port and a third number of credits required to forward the message.
[0088] As an example, when the second quantity is greater than or equal to the third quantity, the first chip may deduct the third quantity of the second credit from the second credit located in the second port, and use the third quantity of the second credit to forward the message.
[0089] As another example, when the second number is less than the third number, the first chip can determine the second ring credit bus corresponding to the third port from the ring bus. The first chip can determine the second time slot corresponding to the second letter of credit, and determine the second initial time slot of the second control signal transmitted on the second ring credit bus. The second control signal is used to mark the starting point of the second ring credit bus transmitting the letter of credit information. Exemplarily, the second control signal is a pulse signal, and the time slot when the second control signal is at a high level is the second initial time slot.
[0090] When the first chip determines that the current time slot is the second time slot based on the second initial time slot, it can also determine whether the fourth number of second letters of credit on the second ring credit bus is greater than or equal to the third number.
[0091] If the fourth quantity is greater than or equal to the third quantity, the first chip can deduct the third quantity of second letters of credit from the second letter of credit on the second ring credit bus, and use the third quantity of second letters of credit to forward the message. Exemplarily, when the number of second letters of credit on the second ring credit bus is sufficient, the first chip can remove the third quantity of second letters of credit from the second ring credit bus to the local second port. The first chip deducts the third quantity of second letters of credit located locally at the second port to forward the message. For another example, the first chip can also remove a second letter of credit greater than the third quantity from the second ring credit bus to the local second port. In this way, the number of second letters of credit located locally at the second port can meet the message forwarding requirements. The first chip can deduct the third quantity of second letters of credit located locally at the second port to forward the message.
[0092] If the fourth number is less than the third number, the first chip continues to determine the number of second letters of credit on the second ring credit bus until the number of second letters of credit on the second ring credit bus is greater than or equal to the third number. Exemplarily, when determining that the fourth number is less than the third number, the first chip continues to wait for the second letter of credit in the second time slot to be transmitted on the second ring credit bus, and determines whether the number of the second letter of credit is greater than or equal to the third number at this time, so as to determine whether the number of the second letter of credit meets the message forwarding requirement.
[0093] After the first chip uses the second letter of credit to forward the message, the number of the second letter of credit can be updated. For example, when the first chip deducts the second letter of credit located locally at the second port, the number of the second letter of credit at the second port is updated. For another example, when the first chip deducts the second letter of credit located on the second ring credit bus, the number of the second letter of credit is updated using the counter corresponding to the second time slot.
[0094] Based on the contents of the above embodiment, after receiving the letter of credit, the first chip uploads the letter of credit to the ring bus connecting various ports for use by all ports of the first chip. In this way, efficient and fast full-port lossless forwarding can be achieved while reducing the area overhead of chip routing.
[0095] Fig. 9 A schematic diagram of the hardware structure of a chip provided in an embodiment of the present application. The chip may be a high-order lossless switching chip. The chip includes 48 physical ports, and each 4 physical ports P form an NCU. Each NCU includes a receive CRD (RX CRD) module, a virtual output queue (VOQ) module, and a CRD management (R_CRD) module.
[0096] like Fig. 9As shown, the R_CRD modules in the 12 NCUs are connected in series by a ring bus, which includes 12 ring credit buses, each of which corresponds to an NCU. The data transmission method described in the above embodiment can be deployed on a network-on-chip (NoC) credit interaction module inside this type of chip, and can achieve fast credit interaction between multiple ports with lower routing overhead and implementation difficulty.
[0097] The RX CRD module is used to receive the letter of credit returned by the opposite device and transmit the received letter of credit to the R_CRD module.
[0098] The R_CRD module is used to perform time slot judgment, upload the local credit and the credit received by the port to the corresponding ring credit bus for transmission, apply for credit from the ring credit bus, etc.
[0099] The VOQ module is used to obtain the letter of credit through the R_CRD module and forward the message using the letter of credit.
[0100] In some embodiments, after the downstream chip sends the letter of credit to a port of the chip, the port can send the received letter of credit to the R_CRD module of its corresponding NCU through the RX CRD module. The R_CRD module will wait for the corresponding ring credit bus to be in the time slot corresponding to the letter of credit, and then upload the letter of credit to the ring credit bus. At this time, the counter of the corresponding time slot on the ring credit bus will increase the corresponding number of letters of credit.
[0101] When the second port of the chip receives a message, it determines that the message needs to be sent from the third port. The second port will apply for the letter of credit corresponding to the third port from the R_CRD module of its corresponding NCU. After receiving the letter of credit application, the R_CRD module will first determine whether there are enough letters of credit locally to forward the message.
[0102] Optionally, if the R_CRD module determines that there are sufficient letters of credit locally, the R_CRD module can directly deduct the letters of credit and notify the VOQ module to forward the message.
[0103] Optionally, if the R_CRD module determines that there are not enough letters of credit locally, the R_CRD module determines whether there are enough letters of credit on the ring credit bus corresponding to the third port. When there are enough letters of credit on the ring credit bus, the R_CRD module removes enough letters of credit from the ring credit bus to the local. The R_CRD module can directly deduct the local letters of credit and notify the VOQ module to forward the message. When there are not enough letters of credit on the ring credit bus, the R_CRD module will continue to wait until there are enough letters of credit on the ring credit bus.
[0104] based on Fig. 9 As shown in the figure, the chip connects the R_CRD modules in series through a ring bus and transmits the letters of credit on the ring bus, which can realize fast credit interaction between multiple ports with lower routing overhead and implementation difficulty.
[0105] Fig.10 A complete flow chart of a data transmission method provided in an embodiment of the present application is applied to a first chip, the first chip includes multiple ports and a ring bus, the ring bus is connected to each of the multiple ports, and the ring bus includes multiple ring credit buses. Among them, the method can be applied to Figure 2 , Figure 4 , Figure 5 or Fig. 9 The chip shown. Fig.10 As shown, the method includes:
[0106] S1001: A first chip receives a first letter of credit from a second chip through a first port, wherein the first port is any port among a plurality of ports, and the second chip is a downstream chip of the first chip.
[0107] S1002: The first chip determines a first ring credit bus corresponding to a first port from the ring bus.
[0108] S1003: The first chip determines a first time slot corresponding to the first letter of credit.
[0109] S1004: The first chip uses the time slot when the first control signal is at a high level as the first initial time slot.
[0110] The first control signal is a pulse signal, and the first control signal is used to mark the starting point of the first ring credit bus transmitting the letter of credit information.
[0111] S1005: When the first chip determines that the current time slot is the first time slot according to the first initial time slot, it uploads the first letter of credit to the first ring credit bus and updates the first quantity of the first letter of credit corresponding to the first port.
[0112] S1006: The first chip receives a message through a second port, wherein the second port is any port among a plurality of ports.
[0113] There is no sequential execution order between the above steps S1001 - S1005 and step S1006.
[0114] S1007: The first chip determines a third port for outputting the message from the multiple ports.
[0115] S1008: The first chip determines the second quantity of the second letter of credit corresponding to the third port at the second port, and the third quantity of the letter of credit required to forward the message.
[0116] S1009: The first chip determines whether the second number is less than the third number; if so, execute step S1010; if not, execute step S1016.
[0117] S1010: The first chip determines a second ring credit bus corresponding to the third port from the ring bus.
[0118] S1011: The first chip determines a second time slot corresponding to the second letter of credit.
[0119] S1012: The first chip determines a second initial time slot of a second control signal transmitted on the second ring-shaped credit bus, wherein the second control signal is used to mark the starting point of the second ring-shaped credit bus transmitting the letter of credit information.
[0120] S1013: The first chip determines that the current time slot is the second time slot according to the second initial time slot.
[0121] S1014: The first chip determines whether the fourth quantity of the second letter of credit on the second ring credit bus is less than the third quantity; if so, execute step S1013; if not, execute step S1015.
[0122] S1015: The first chip deducts a third amount of second credits from the second credits on the second ring credit bus.
[0123] S1016: The first chip deducts a third amount of the second credit from the second credit in the second port.
[0124] S1017: The first chip forwards the message using the third number of second letters of credit.
[0125] S1018: The first chip updates the quantity of the second letter of credit.
[0126] based on Fig.10 As shown, the first chip can transmit the credit on the ring bus that connects all the ports of the first chip in series, and can realize fast credit interaction between multiple ports with lower routing overhead and implementation difficulty.
[0127] Based on the same technical concept, the embodiment of the present application also provides a data transmission device, which is applied to a first chip, wherein the first chip includes a plurality of ports and a ring bus, wherein the ring bus is connected to each of the plurality of ports, and the ring bus includes a plurality of ring credit buses. Fig.11 As shown, the data transmission device 1100 may include:
[0128] The communication unit 1101 is configured to receive a first letter of credit from a second chip through a first port; the first port is any port among the plurality of ports, and the second chip is a downstream chip of the first chip;
[0129] The processing unit 1102 is configured to transmit the first letter of credit on the ring bus.
[0130] In some optional implementations, the processing unit 1102 is specifically configured to:
[0131] Determine a first ring credit bus corresponding to the first port from the ring bus;
[0132] determining a first time slot corresponding to the first letter of credit;
[0133] Determining a first initial time slot of a first control signal transmitted on the first ring-shaped credit bus, the first control signal being used to mark a starting point for transmitting letter of credit information on the first ring-shaped credit bus;
[0134] When the current time slot is determined to be the first time slot according to the first initial time slot, the first letter of credit is uploaded to the first ring credit bus, and the first quantity of the first letter of credit corresponding to the first port is updated.
[0135] In some optional implementations, the first control signal is a pulse signal, and the processing unit 1102 is specifically configured to:
[0136] The time slot when the first control signal is at a high level is used as the first initial time slot.
[0137] In some optional implementations, the processing unit 1102 is further configured to:
[0138] receiving a message through a second port, where the second port is any port among the multiple ports;
[0139] Determining, from the multiple ports, a third port for outputting the message;
[0140] The message is forwarded using the second letter of credit corresponding to the third port.
[0141] In some optional implementations, the processing unit 1102 is specifically configured to:
[0142] determining a second number of the second credits at the second port and a third number of credits required to forward the message;
[0143] when the second amount is greater than or equal to the third amount, deducting the third amount of the second credit from the second credit located in the second port;
[0144] The message is forwarded using the third number of second letters of credit.
[0145] In some optional implementations, when the second number is less than the third number, the processing unit 1102 is further configured to:
[0146] Determine a second ring-shaped credit bus corresponding to the third port from the ring bus;
[0147] determining a second time slot corresponding to the second letter of credit;
[0148] Determining a second initial time slot of a second control signal transmitted on the second ring-shaped credit bus, the second control signal being used to mark a starting point for transmitting letter of credit information on the second ring-shaped credit bus;
[0149] The current time slot is determined as the second time slot according to the second initial time slot.
[0150] In some optional implementations, the processing unit 1102 is further configured to:
[0151] determining whether a fourth quantity of second credits on the second ring-shaped credit bus is greater than or equal to the third quantity;
[0152] If yes, deduct the third number of second credits from the second credits on the second ring credit bus; forward the message using the third number of second credits;
[0153] If not, continue to determine the number of second credits on the second ring-shaped credit bus until the number of second credits on the second ring-shaped credit bus is greater than or equal to the third number.
[0154] In some optional implementations, after forwarding the message using the second letter of credit corresponding to the third port, the processing unit 1102 is further configured to:
[0155] Update the amount of the second letter of credit.
[0156] In some optional implementations, the ring bus includes a plurality of ring credit buses, and the plurality of ring credit buses correspond one-to-one to the plurality of ports.
[0157] In some optional embodiments, the first chip further includes a plurality of node control units, each of the plurality of node control units includes at least two ports of the plurality of ports, the ring bus includes a plurality of ring credit buses, and the plurality of node control units correspond one-to-one to the plurality of ring credit buses.
[0158] Based on the same technical concept, the present application embodiment also provides a chip. Fig.12 As shown, the chip 1200 at least includes a plurality of ports 1201 , a ring bus 1202 , and a processor 1203 . The ring bus 1202 is connected to each of the plurality of ports 1201 .
[0159] Among them, port 1201 is used for inputting and / or outputting data;
[0160] Ring bus 1202, used to transmit letter of credit information;
[0161] The processor is used to execute a computer program so that the above embodiments and the data transmission methods provided by the embodiments are executed.
[0162] In some optional embodiments, the ring bus 1202 includes multiple ring credit buses.
[0163] In some optional implementations, a plurality of ring credit buses correspond one-to-one to a plurality of ports.
[0164] In some optional embodiments, the chip further includes a plurality of node control units, each of the plurality of node control units includes at least two of the plurality of ports, and the plurality of node control units correspond one-to-one to the plurality of ring credit buses. For example, when the chip includes a plurality of node control units, the architecture between the node control units and the plurality of ring credit buses is as follows: Figure 5 shown.
[0165] In the embodiment of the present application, the processor 1203 may be an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA), which may implement or execute the methods, steps and logic diagrams disclosed in the embodiment of the present application. The steps of the method disclosed in the embodiment of the present application may be directly embodied as being executed by a hardware processor, or may be executed by a combination of hardware and software modules in the processor.
[0166] In some embodiments, in addition to using a ring bus to transmit letters of credit, the chip provided in the embodiment of the present application can also use the ring bus architecture of the chip to transmit other information. Exemplarily, the chip provided in the embodiment of the present application can also use the ring bus architecture of the chip to transmit the depth of each queue inside each chip to achieve congestion control, as well as dynamic routing. Among them, during the implementation of congestion control, the chip needs to sense the total depth of the queue sent to each output port in the chip through the ring bus architecture to perform congestion marking. During the dynamic routing implementation process, the chip needs to sense the congestion level of each port through the ring bus architecture to select the appropriate line. The implementation process of the above scheme is the same as the process of transmitting letter of credit information in the data transmission method provided in the embodiment of the present application, and both are based on control signals and time slots to realize different time slots carrying different information. That is, the data transmission method provided in the embodiment of the present application essentially implements an ALL2ALL information broadcast interaction process.
[0167] In addition, the chip can also transmit the working status of each port through the ring bus architecture. For example, when a port fails or is disconnected, the chip can quickly transmit the link status of the port to each port through the ring bus architecture, thereby realizing hardware-level fast fault perception, active switching and other functions.
[0168] Based on the above embodiments, the present application also provides a computer program product, which includes: a computer program (also referred to as code, or instructions), which enables a computer to execute the data transmission method described in the embodiments of the present application when the computer program is executed.
[0169] Based on the above embodiments, the present application further provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a computer, the computer executes the data transmission method described in the embodiments of the present application.
[0170] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.
[0171] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0172] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.
[0173] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.
[0174] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.
Claims
1. A data transmission method, characterized in that: Applied to a first chip, the first chip includes a plurality of ports and a ring bus, the ring bus is connected to each of the plurality of ports; the method includes: receiving a first letter of credit from a second chip through a first port; the first port is any port among the plurality of ports, and the second chip is a downstream chip of the first chip; The first credit is transmitted on the ring bus.
2. The method according to claim 1, characterized in that: The transmitting the first letter of credit on the ring bus comprises: Determine a first ring credit bus corresponding to the first port from the ring bus; determining a first time slot corresponding to the first letter of credit; Determining a first initial time slot of a first control signal transmitted on the first ring-shaped credit bus, the first control signal being used to mark a starting point for transmitting letter of credit information on the first ring-shaped credit bus; When the current time slot is determined to be the first time slot according to the first initial time slot, the first letter of credit is uploaded to the first ring credit bus, and the first quantity of the first letter of credit corresponding to the first port is updated.
3. The method according to claim 2, characterized in that The first control signal is a pulse signal, and the step of determining a first initial time slot of the first control signal transmitted on the first ring credit bus comprises: The time slot when the first control signal is at a high level is used as the first initial time slot.
4. The method according to any one of claims 1 to 3, characterized in that: The method further comprises: receiving a message through a second port, where the second port is any port among the multiple ports; Determining, from the multiple ports, a third port for outputting the message; The message is forwarded using the second letter of credit corresponding to the third port.
5. The method according to claim 4, characterized in that The method of forwarding the message using the second letter of credit corresponding to the third port includes: determining a second number of the second credits at the second port and a third number of credits required to forward the message; when the second amount is greater than or equal to the third amount, deducting the third amount of the second credit from the second credit located in the second port; The message is forwarded using the third number of second letters of credit.
6. The method according to claim 5, characterized in that When the second number is less than the third number, the method further includes: Determine a second ring-shaped credit bus corresponding to the third port from the ring bus; determining a second time slot corresponding to the second letter of credit; Determining a second initial time slot of a second control signal transmitted on the second ring-shaped credit bus, the second control signal being used to mark a starting point for transmitting letter of credit information on the second ring-shaped credit bus; The current time slot is determined as the second time slot according to the second initial time slot.
7. The method according to claim 6, characterized in that The method further comprises: determining whether a fourth quantity of second credits on the second ring-shaped credit bus is greater than or equal to the third quantity; If yes, deduct the third number of second credits from the second credits on the second ring credit bus; forward the message using the third number of second credits; If not, continue to determine the number of second credits on the second ring-shaped credit bus until the number of second credits on the second ring-shaped credit bus is greater than or equal to the third number.
8. The method according to any one of claims 4 to 7, characterized in that: After forwarding the message using the second letter of credit corresponding to the third port, the method further includes: Update the amount of the second letter of credit.
9. The method according to any one of claims 1 to 8, characterized in that: The ring bus includes a plurality of ring credit buses, and the plurality of ring credit buses correspond one-to-one to the plurality of ports.
10. The method according to any one of claims 1 to 8, characterized in that: The first chip also includes a plurality of node control units, each of the plurality of node control units includes at least two ports of the plurality of ports, the ring bus includes a plurality of ring credit buses, and the plurality of node control units correspond one-to-one to the plurality of ring credit buses.
11. A chip, characterized in that: The chip includes a processor, a plurality of ports and a ring bus, wherein the ring bus is connected to each of the plurality of ports; wherein, Each port of the plurality of ports is used to input and / or output data; The ring bus is used to transmit letter of credit information; The processor is used to execute a computer program so that the method according to any one of claims 1 to 10 is performed.
12. The chip according to claim 11, characterized in that: The ring bus includes a plurality of ring-shaped credit buses.
13. The chip according to claim 12, characterized in that: The plurality of ring credit buses correspond one-to-one to the plurality of ports.
14. The chip according to claim 11 or 12, characterized in that: The chip further comprises a plurality of node control units, each of the plurality of node control units comprises at least two ports of the plurality of ports, and the plurality of node control units correspond one-to-one to the plurality of ring credit buses.
15. A data transmission device, characterized in that: Applied to a first chip, the first chip includes a plurality of ports and a ring bus, the ring bus is connected to each of the plurality of ports; the device includes: A communication unit, configured to receive a first letter of credit from a second chip through a first port; the first port is any port among the plurality of ports, and the second chip is a downstream chip of the first chip; A processing unit is used to transmit the first credit on the ring bus.
16. A computer storage medium, characterized in that: The computer-readable storage medium comprises a computer program, and when the computer program is run on a chip, the chip enables the method described in any one of claims 1 to 10 to be implemented.
17. A computer program product, characterized in that When the computer program product is run on a computer, the computer is caused to perform the method according to any one of claims 1 to 10.