Reconfigurable processor of 3D DRAM, computing method, device and medium

Abstract

The invention provides a reconfigurable processor based on a 3D DRAM, a computing method, equipment and a medium. The reconfigurable processor comprises the 3D DRAM, a logic circuit module and a reconfigurable module. The 3D DRAM comprises a plurality of 3D storage areas which are used for respectively storing reconfigurable operator configuration information and scheduling tasks of the reconfigurable processor; the logic circuit module is used for acquiring configuration data of the scheduling task from the 3D DRAM, analyzing the configuration data, determining a corresponding reconfigurable array according to an analysis result, configuring a reconfigurable operator in the reconfigurable array according to the scheduling task, and operating the scheduling task by adopting the configured reconfigurable operator; and the reconfigurable module comprises a plurality of reconfigurable operators and is used for reconfiguring the storage positions of the scheduling tasks in the plurality of 3D storage areas according to the task types of the scheduling tasks and the distances between the plurality of reconfigurable operators and the 3D storage areas so as to solve the problem of further improving the calculation amount and the storage amount of the reconfigurable processor.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a reconfigurable processor, a computing method, a device and a medium based on 3D DRAM. Background Art

[0002] At present, as the demand for high-speed, large-capacity, and low-latency memory in cloud computing, artificial intelligence, big data analysis, and other fields continues to rise, traditional DRAM is gradually unable to meet market demand in terms of bandwidth, capacity, and access speed. For example, in the process of artificial intelligence training and reasoning, a large amount of data storage and fast data access are required, which places extremely high demands on storage and computing power. The performance of traditional DRAM limits the efficiency and scale of artificial intelligence algorithms, so higher-performance storage technology is needed.

[0003] In the existing technology, the card memory capacity used to store data and configuration information on the reconfigurable processor is relatively small, which cannot meet the computing and storage requirements in fields such as artificial intelligence. The high capacity and high bandwidth characteristics of 3D DRAM can meet the data storage and access requirements of artificial intelligence and machine learning algorithms, providing powerful storage support for reconfigurable processors.

[0004] Therefore, there is an urgent need to propose a reconfigurable processor, computing method, device and medium based on 3D DRAM to solve the technical problem of further improving the computing power and storage capacity of the reconfigurable processor. Summary of the invention

[0005] In order to overcome the problems existing in the related art, the present disclosure provides a reconfigurable processor, a computing method, a device and a medium based on 3D DRAM to solve the technical problem of further improving the computing capacity and storage capacity of the reconfigurable processor in the related art.

[0006] One or more embodiments of this specification provide a reconfigurable processor based on 3D DRAM, including 3D DRAM, a logic circuit module and a reconfigurable module;

[0007] The 3D DRAM includes a plurality of 3D storage areas for respectively storing reconfigurable operator configuration information and scheduling tasks of the reconfigurable processor;

[0008] The logic circuit module is used to obtain and parse the configuration data of the scheduling task from the 3D DRAM, determine the corresponding reconfigurable array according to the parsing result, configure the reconfigurable operator in the reconfigurable array according to the scheduling task, and use the configured reconfigurable operator to calculate the scheduling task;

[0009] The reconfigurable module includes a plurality of reconfigurable operators, which are used to reconfigure the storage position of the scheduled task in the plurality of 3D storage areas according to the task type of the scheduled task and the distance between the plurality of reconfigurable operators and the three-dimensional storage area.

[0010] Preferably, the logic circuit module comprises a parsing unit for acquiring the configuration data of the scheduling task from the 3D DRAM;

[0011] converting the configuration data into a recognizable and processable format;

[0012] Parse the converted configuration data into structured data including the task type, task ID, task priority, time constraint and resource requirement of the scheduled task;

[0013] The scheduled tasks are sorted according to the parsed task priorities to form a priority task queue.

[0014] Preferably, the logic circuit module further comprises a monitoring unit for monitoring the task execution process of the reconfigurable processor, the priority task queue and the operating environment of the reconfigurable processor;

[0015] adjusting the task priority according to the real-time resources of the reconfigurable processor;

[0016] Re-evaluating and adjusting the scheduling order of the priority task queue according to the update of the scheduling task;

[0017] The reconfigurable operator is reconfigured according to the operating environment of the reconfigurable processor.

[0018] Preferably, the logic circuit module further comprises an operation unit, which is used to obtain the task data of the scheduled task from the 3D DRAM;

[0019] According to the topological structure of the reconfigurable array and the functional characteristics of the reconfigurable operator, the task data is divided into a plurality of subtask data, and the plurality of subtask data are mapped to each reconfigurable operator in the reconfigurable array;

[0020] The logic circuit module generates an operation control signal sequence according to the dependency relationship between the configuration data of the scheduling task and the reconfigurable operator, and controls the reconfigurable operator to process and operate the subtask data.

[0021] Preferably, the logic circuit module also includes a configuration unit, which is used to assign the function setting, connection method, and data processing mode of the reconfigurable operator of the scheduling task to the reconfigurable operator through a preset analysis algorithm and mapping rule, so as to configure the reconfigurable operator in the reconfigurable array.

[0022] One or more embodiments of the present specification provide a computing method of a reconfigurable processor based on 3D DRAM, including 3D DRAM, a logic circuit module and a reconfigurable module, including the following steps:

[0023] The 3D DRAM includes a plurality of 3D storage areas, respectively storing reconfigurable operator configuration information and scheduling tasks of the reconfigurable processor;

[0024] The reconfigurable module includes a plurality of reconfigurable operators;

[0025] The logic circuit module obtains and analyzes the configuration data of the scheduling task from the 3D DRAM, determines the corresponding reconfigurable array according to the analysis result, configures the reconfigurable operator in the reconfigurable array according to the scheduling task, and uses the configured reconfigurable operator to calculate the scheduling task;

[0026] The reconfigurable module reconfigures the storage position of the scheduled task in the multiple 3D storage areas according to the task type of the scheduled task and the distances between the multiple reconfigurable operators and the three-dimensional storage area.

[0027] Preferably, the logic circuit module obtains and parses the configuration data of the scheduling task from the 3D DRAM, specifically comprising the following steps:

[0028] Acquire configuration data of the scheduling task from the 3D DRAM;

[0029] converting the configuration data into a recognizable and processable format;

[0030] Parse the converted configuration data into structured data including the task type, task ID, task priority, time constraint and resource requirement of the scheduled task;

[0031] The scheduled tasks are sorted according to the parsed task priorities to form a priority task queue.

[0032] Preferably, the method further comprises the following steps:

[0033] The logic circuit module monitors the task execution process of the reconfigurable processor, the priority task queue and the operating environment of the reconfigurable processor;

[0034] adjusting the task priority according to the real-time resources of the reconfigurable processor;

[0035] Re-evaluating and adjusting the scheduling order of the priority task queue according to the update of the scheduling task;

[0036] The reconfigurable operator is reconfigured according to the operating environment of the reconfigurable processor.

[0037] One or more embodiments of the present specification provide a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the computing method of the reconfigurable processor based on 3D DRAM as described above when executing the computer program.

[0038] One or more embodiments of the present specification provide a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, the steps of the computing method of the reconfigurable processor based on 3D DRAM are implemented.

[0039] The present disclosure provides a reconfigurable processor, computing method, device and medium based on 3D DRAM, the advantage of which is that the 3D DRAM includes multiple 3D storage areas for respectively storing reconfigurable operator configuration information and scheduling tasks of the reconfigurable processor, and by means of the vertically stacked storage layers of the 3D DRAM, more storage units can be accommodated per unit area, greatly improving the storage capacity. In this way, a large amount of reconfigurable operator configuration information and scheduling task data can be easily stored; the logic circuit module is used to obtain and parse the configuration data of the scheduling task from the 3D DRAM, determine the corresponding reconfigurable array according to the parsing result, configure the reconfigurable operator in the reconfigurable array according to the scheduling task, and use the configured reconfigurable operator to calculate the scheduling task. The logic circuit module realizes effective processing of tasks through a series of operations such as obtaining data from the 3D DRAM, parsing, determining the array, configuring operators and calculating, thereby improving the adaptability of the system to diversified application scenarios, and can make full use of reconfigurable resources when executing scheduling tasks, reducing computing delays and resource waste; the reconfigurable module includes multiple reconfigurable operators, which are used to reconfigure the storage position of the scheduling task in the multiple 3D storage areas according to the task type of the scheduling task and the distance between the multiple reconfigurable operators and the three-dimensional storage area, and reconfigure the storage position by comprehensively considering the task type and distance factors to optimize the resource utilization of the storage system, thereby enhancing the flexibility of the system and the adaptability to complex and changeable application environments, which helps to improve the overall computing performance of the system and meet the application requirements with high computing efficiency requirements, such as real-time big data analysis, intelligent control systems and other fields. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate one or more embodiments of this specification or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0041] Figure 1 A schematic diagram of a reconfigurable processor based on 3D DRAM provided for one or more embodiments of this specification

[0042] Figure 2 A flowchart of a calculation method of a reconfigurable processor based on 3D DRAM provided for one or more embodiments of this specification;

[0043] Figure 3 A schematic diagram of the structure of a computer device provided for one or more embodiments of this specification. DETAILED DESCRIPTION

[0044] In order to enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the technical solutions in one or more embodiments of this specification will be clearly and completely described below in conjunction with the drawings in one or more embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on one or more embodiments of this specification, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the protection scope of the present invention.

[0045] The present invention is described in detail below in conjunction with specific implementation methods and the accompanying drawings.

[0046] Device Embodiment

[0047] According to an embodiment of the present invention, a reconfigurable processor based on 3D DRAM is provided, such as Figure 1 , which is a schematic diagram of the structure of a reconfigurable processor based on 3D DRAM provided in this embodiment. The reconfigurable processor based on 3D DRAM according to the embodiment of the present invention includes a 3D DRAM, a logic circuit module 12 and a reconfigurable module 13.

[0048] The 3D DRAM 11 includes a plurality of 3D storage areas for respectively storing reconfigurable operator configuration information and scheduling tasks of the reconfigurable processor.

[0049] The logic circuit module 12 is used to obtain and parse the configuration data of the scheduling task from the 3D DRAM. An efficient data reading channel is established between the logic circuit module and the 3D DRAM. The scheduling task information is quickly and accurately extracted from the 3D DRAM through a specific address mapping and access mechanism. The corresponding reconfigurable array is determined according to the parsing result. For example, if the configuration data indicates that the task has a high real-time requirement, it will be given a higher priority weight during scheduling; if the task has a large demand for specific resources (such as a specific type of reconfigurable operator), the relevant information of the resource is marked. The reconfigurable operator in the reconfigurable array is configured according to the scheduling task, and the configured reconfigurable operator is used to calculate the scheduling task.

[0050] The logic circuit module 12 undertakes the key scheduling and configuration operation functions in the entire system. It is specifically used to schedule the task from the 3D DRAM. As a storage unit for storing a large amount of task-related information, the 3D DRAM provides data support for task scheduling. The logic circuit module finely configures the reconfigurable operator based on the configuration data of the scheduled task. This process involves in-depth matching of task characteristics and operator functions.

[0051] The reconfigurable module 13 includes multiple reconfigurable operators. The reconfigurable module 13 is a key part for flexibly allocating resources in the entire system. The multiple reconfigurable operators it contains play a core role in optimizing the storage location of scheduling tasks. It is used to reconfigure the storage location of the scheduling task in the multiple 3D storage areas according to the task type of the scheduling task and the distance between the multiple reconfigurable operators and the three-dimensional storage area.

[0052] The reconfigurable module 13 has an advanced task type recognition function. When a scheduled task enters the system, it can accurately determine the task type by deeply analyzing the identification information, data features and related metadata carried by the task. For example, for image recognition tasks, its data usually has a specific image format (such as JPEG, PNG, etc.), and the related metadata may include information such as image resolution and color mode; for data encryption tasks, its data has a specific format and parameters related to the encryption algorithm.

[0053] According to different task types, the reconfigurable module 13 formulates corresponding storage location reconfiguration strategies. For computationally intensive tasks, such as complex scientific computing simulations, it is necessary to frequently access a large amount of data, so it is necessary to store it in a 3D storage area that can ensure fast data reading. For network communication tasks with frequent data transmission, it tends to be stored in a storage area close to the reconfigurable operator related to the data transmission interface to reduce data transmission delays. For real-time control tasks with extremely high real-time requirements, such as real-time monitoring and feedback adjustment tasks in industrial automation, the scheduling task data should be stored in a 3D storage area with high bandwidth and low access delay characteristics, and this area is close to the reconfigurable operator responsible for real-time processing.

[0054] Through this comprehensive consideration of the task type based on the scheduling task and the distance between the reconfigurable operator and the three-dimensional storage area, the reconfigurable module 13 can dynamically and intelligently reconfigure the storage location of the scheduling task in multiple 3D storage areas, thereby optimizing system performance, improving task processing efficiency, and better meeting diverse application needs.

[0055] The reconfigurable processor provided in this embodiment, the 3D DRAM 11 includes multiple 3D storage areas for respectively storing reconfigurable operator configuration information and scheduling tasks of the reconfigurable processor. By means of the vertically stacked storage layers of 3D DRAM, more storage units can be accommodated per unit area, greatly improving the storage capacity. In this way, a large amount of reconfigurable operator configuration information and scheduling task data can be easily stored; the logic circuit module 12 is used to obtain and parse the configuration data of the scheduling task from the 3D DRAM, determine the corresponding reconfigurable array according to the parsing result, configure the reconfigurable operator in the reconfigurable array according to the scheduling task, and use the configured reconfigurable operator to calculate the scheduling task. The logic circuit module 12 realizes effective processing of the task through a series of operations such as obtaining data from the 3D DRAM, parsing, determining the array, configuring the operator and calculating, thereby improving the adaptability of the system to diversified application scenarios, and can make full use of reconfigurable resources when executing scheduling tasks, reducing computing delays and resource waste; the reconfigurable module includes multiple reconfigurable operators, which are used to reconfigure the storage position of the scheduling task in the multiple 3D storage areas according to the task type of the scheduling task and the distance between the multiple reconfigurable operators and the three-dimensional storage area, and reconfigure the storage position by comprehensively considering the task type and distance factors to optimize the resource utilization of the storage system, thereby enhancing the flexibility of the system and the adaptability to complex and changeable application environments, which helps to improve the overall computing performance of the system and meet the application requirements with high computing efficiency requirements, such as real-time big data analysis, intelligent control systems and other fields.

[0056] In one embodiment, the logic circuit module 12 includes a parsing unit 121, which is used to obtain the configuration data of the scheduled task from the 3D DRAM, convert the configuration data into a recognizable and processable format, parse the converted configuration data into structured data including the task type, task ID, task priority, time constraint and resource requirement of the scheduled task, and sort the scheduled tasks according to the parsed task priority to form a priority task queue.

[0057] For example, for task scheduling data stored in a specific address space of 3D DRAM, the logic circuit module uses a built-in decoder to parse the binary data into structured data containing task ID, task priority level (expressed in numbers, such as 1-10, 10 being the highest priority), estimated execution time (in clock cycles), and a list of required resources (such as a specific number of registers, data transmission bandwidth, etc.).

[0058] Priority sorting and scheduling queue construction: Based on the parsed task priority information, the logic circuit module sorts the tasks. A priority queue data structure is used to store the tasks to be scheduled. High-priority tasks are placed at the front of the queue to ensure that they can get processing resources first. At the same time, for tasks with the same priority, they can be further sorted according to the task arrival time (first come first served principle) or other predefined secondary priority rules.

[0059] For example, if there are both a task A with a priority of 8 and a task B with a priority of 6, task A will be scheduled before task B. If there is another task C with a priority of 8 that arrives after task A, task A will be scheduled before task C according to the first-come-first-served principle, but they both take precedence over task B.

[0060] The reconfigurable processor provided in this embodiment can efficiently process and parse data, sort the scheduled tasks according to the parsed task priorities, and form a priority task queue. This is the core link to ensure the efficient operation of the system. The priority-based sorting method greatly improves the system's responsiveness and provides a clear basis for resource allocation.

[0061] In one embodiment, the logic circuit module 12 also includes a monitoring unit 122, which is used to monitor the task execution process of the reconfigurable processor, the priority task queue and the operating environment of the reconfigurable processor, adjust the task priority according to the real-time resources of the reconfigurable processor, re-evaluate and adjust the scheduling order of the priority task queue according to the update of the scheduled task, and reconfigure the reconfigurable operator according to the operating environment of the reconfigurable processor.

[0062] Dynamic adjustment mechanism: The monitoring unit 122 continuously monitors the system status and task execution status, and dynamically adjusts the scheduling queue. If a new high-priority task appears or an abnormal situation such as a blocking occurs in the task being executed, the scheduling order is re-evaluated and adjusted in time. In addition, the priority of the task is appropriately adjusted dynamically according to the real-time availability of system resources. If it is found that some tasks have delays or resource contention problems, the scheduling order is adjusted in time or the reconfigurable operator is reconfigured to optimize the overall task execution efficiency. For example, for tasks with high memory bandwidth requirements, if the current memory bandwidth resources are tight, their priority can be appropriately lowered to avoid affecting the execution of other tasks.

[0063] In one embodiment, the logic circuit module 12 further includes a computing unit 123, which is used to obtain the task data of the scheduled task from the 3D DRAM after determining the reconfigurable array.

[0064] According to the topological structure of the reconfigurable array and the functional characteristics of the reconfigurable operator (input data bandwidth and processing speed), the task data is divided into multiple sub-task data, and the data is loaded in batches reasonably to avoid data transmission bottlenecks, and the multiple sub-task data are mapped to each reconfigurable operator in the reconfigurable array. For example, for a large-scale matrix operation task, the data may be read out from the 3D DRAM in blocks and temporarily stored in a cache near the input port of the reconfigurable array, and then the data is loaded block by block according to the input requirements of the reconfigurable array, and the necessary format conversion and alignment operations are performed on the data.

[0065] The logic circuit module generates an operation control signal sequence according to the dependency relationship between the configuration data of the scheduling task and the reconfigurable operator, controls the reconfigurable operator to process and calculate the subtask data, ensures that the reconfigurable operator processes and calculates data in the correct order and time, and realizes efficient execution of the task.

[0066] For example, when executing a digital signal processing task, it may be necessary to first perform a filtering operation (implemented by a reconfigurable operator) and then perform a spectrum analysis operation (implemented by another reconfigurable operator). The logic circuit module will control the data to be correctly transmitted from the output port of the filtering operator to the input port of the spectrum analysis operator, and start the spectrum analysis operator operation at the appropriate time.

[0067] After the task operation is completed, the logic circuit module organizes and processes the result data output by the reconfigurable array. Depending on the requirements of the task, the result data may need to be further converted to a format, verified, and compressed. The result data is then stored in a specified storage location, such as a specific area of ​​3D DRAM or other external storage device, and a task completion signal is sent to the system. For example, for the result of a data encryption task, the logic circuit module will perform an integrity check on the encrypted ciphertext data, and then store it in a secure area of ​​3D DRAM specifically used to store encrypted data, and notify the relevant security management module that the task has been successfully completed.

[0068] In one embodiment, the logic circuit module 12 also includes a configuration unit 124, which is used to assign the function setting, connection method, and data processing mode of the reconfigurable operator of the scheduling task to the reconfigurable operator through a pre-set parsing algorithm and mapping rules, so as to configure the reconfigurable operator in the reconfigurable array.

[0069] Through the pre-set parsing algorithm and mapping rules, it is possible to deeply understand the reconfigurable operator related information contained in the scheduling task. For example, for complex computing tasks, its configuration data may exist in a specific encoding form, and the parsing algorithm can accurately extract the function setting parameters of the reconfigurable operator from it. It can identify different types of function setting information, whether it is arithmetic operation functions (such as addition, multiplication), logical operation functions (such as AND, OR, NOT), or more complex function operation functions (such as trigonometric functions and exponential function calculations). The parsing algorithm can also process the connection relationship information between reconfigurable operators. When faced with complex task logic, it can parse whether the operators are connected serially, in parallel, or have a more complex hierarchical connection structure. Moreover, the parsing algorithm can also accurately extract information related to the data processing mode, such as the flow direction of the data (is it a one-way flow or there is a feedback loop), the rules for splitting and merging the data, etc.

[0070] The configuration of the data processing mode can also enable the reconfigurable operator to adapt to different data characteristics. For different types of data (such as structured data and unstructured data), the configuration unit 124 can adjust the data processing mode of the reconfigurable operator. For example, for a structured database query task, the reconfigurable operator can be configured to perform data retrieval and processing according to the database table structure and query conditions; for an unstructured text data processing task, the reconfigurable operator can be configured to a mode suitable for text analysis, such as lexical analysis, syntax analysis and other related operations.

[0071] Method Embodiment

[0072] According to an embodiment of the present invention, a computing method for a reconfigurable processor based on 3D DRAM is provided, such as Figure 2 As shown, it is a flow chart of the calculation method of the reconfigurable processor based on 3D DRAM provided in this embodiment. The calculation method of the reconfigurable processor based on 3D DRAM according to the embodiment of the present invention includes 3D DRAM, a logic circuit module and a reconfigurable module, and includes the following steps:

[0073] S210. The 3D DRAM includes a plurality of 3D storage areas, which respectively store reconfigurable operator configuration information and scheduling tasks of the reconfigurable processor.

[0074] S220. The reconfigurable module includes a plurality of reconfigurable operators.

[0075] S230, the logic circuit module obtains the configuration data of the scheduling task from the 3D DRAM and parses it, determines the corresponding reconfigurable array according to the parsing result, configures the reconfigurable operator in the reconfigurable array according to the scheduling task, and uses the configured reconfigurable operator to calculate the scheduling task.

[0076] S240: The reconfigurable module reconfigures the storage position of the scheduled task in the multiple 3D storage areas according to the task type of the scheduled task and the distances between the multiple reconfigurable operators and the three-dimensional storage area.

[0077] In the method provided in this embodiment, the 3D DRAM includes multiple 3D storage areas for respectively storing reconfigurable operator configuration information and scheduling tasks of the reconfigurable processor. By means of the vertically stacked storage layers of the 3D DRAM, more storage units can be accommodated per unit area, greatly improving the storage capacity. In this way, a large amount of reconfigurable operator configuration information and scheduling task data can be easily stored; the configuration data of the scheduling task is obtained from the 3D DRAM and parsed, the corresponding reconfigurable array is determined according to the parsing result, the reconfigurable operator in the reconfigurable array is configured according to the scheduling task, and the configured reconfigurable operator is used to calculate the scheduling task. The logic circuit module realizes effective processing of the task through a series of operations such as obtaining data from the 3D DRAM, parsing, determining the array, configuring the operator and calculating, thereby improving the adaptability of the system to diversified application scenarios, and can make full use of reconfigurable resources when executing scheduling tasks, reducing computing delays and resource waste; the reconfigurable module includes a plurality of reconfigurable operators, which are used to reconfigure the storage position of the scheduling task in the plurality of 3D storage areas according to the task type of the scheduling task and the distance between the plurality of reconfigurable operators and the three-dimensional storage area, and comprehensively consider the task type and distance factors to reconfigure the storage position to optimize the resource utilization of the storage system, thereby enhancing the flexibility of the system and the adaptability to complex and changeable application environments, which helps to improve the overall computing performance of the system and meet the application requirements with high computing efficiency requirements, such as real-time big data analysis, intelligent control systems and other fields.

[0078] In one embodiment, the logic circuit module obtains and parses the configuration data of the scheduling task from the 3D DRAM, specifically including the following steps:

[0079] The configuration data of the scheduling task is obtained from the 3D DRAM.

[0080] The configuration data is converted into a format that can be recognized and processed.

[0081] The converted configuration data is parsed into structured data including the task type, task ID, task priority, time constraint and resource requirement of the scheduled task.

[0082] The scheduled tasks are sorted according to the parsed task priorities to form a priority task queue.

[0083] In one embodiment, the following steps are also included:

[0084] The logic circuit module monitors the task execution process of the reconfigurable processor, the priority task queue and the operating environment of the reconfigurable processor.

[0085] The task priority is adjusted according to the real-time resources of the reconfigurable processor.

[0086] The scheduling order of the priority task queue is re-evaluated and adjusted according to the update of the scheduling task.

[0087] The reconfigurable operator is reconfigured according to the operating environment of the reconfigurable processor.

[0088] The embodiment of the present invention is a method embodiment corresponding to the above-mentioned device embodiment. The specific operations of each processing step can be understood by referring to the description of the device embodiment, which will not be repeated here.

[0089] like Figure 3 As shown, the present invention also provides a computer-readable storage medium having a computer program stored thereon, which implements the calculation method of the reconfigurable processor based on 3D DRAM in the above-mentioned embodiment when the computer program is executed by a processor, or implements the calculation method of the reconfigurable processor based on 3D DRAM in the above-mentioned embodiment when the computer program is executed by a processor.

[0090] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0091] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device or system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment. The device and system embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0092] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein by equivalents. These modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention, and the contents not described in detail in the specification of the present invention belong to the common knowledge of those skilled in the art.

Claims

1. A reconfigurable processor based on 3D DRAM, characterized in that: Includes 3D DRAM, logic circuit modules and reconfigurable modules; The 3D DRAM includes a plurality of 3D storage areas for respectively storing reconfigurable operator configuration information and scheduling tasks of the reconfigurable processor; The logic circuit module is used to obtain and parse the configuration data of the scheduling task from the 3D DRAM, determine the corresponding reconfigurable array according to the parsing result, configure the reconfigurable operator in the reconfigurable array according to the scheduling task, and use the configured reconfigurable operator to calculate the scheduling task; The reconfigurable module includes a plurality of reconfigurable operators, which are used to reconfigure the storage position of the scheduled task in the plurality of 3D storage areas according to the task type of the scheduled task and the distance between the plurality of reconfigurable operators and the three-dimensional storage area.

2. The reconfigurable processor according to claim 1, wherein: The logic circuit module includes a parsing unit, which is used to obtain the configuration data of the scheduling task from the 3D DRAM; converting the configuration data into a recognizable and processable format; Parse the converted configuration data into structured data including the task type, task ID, task priority, time constraint and resource requirement of the scheduled task; The scheduled tasks are sorted according to the parsed task priorities to form a priority task queue.

3. The reconfigurable processor according to claim 1 or 2, characterized in that: The logic circuit module also includes a monitoring unit for monitoring the task execution process of the reconfigurable processor, the priority task queue and the operating environment of the reconfigurable processor; adjusting the task priority according to the real-time resources of the reconfigurable processor; Re-evaluating and adjusting the scheduling order of the priority task queue according to the update of the scheduling task; The reconfigurable operator is reconfigured according to the operating environment of the reconfigurable processor.

4. The reconfigurable processor according to claim 1, wherein: The logic circuit module further includes a computing unit, which is used to obtain the task data of the scheduling task from the 3D DRAM; According to the topological structure of the reconfigurable array and the functional characteristics of the reconfigurable operator, the task data is divided into a plurality of subtask data, and the plurality of subtask data are mapped to each reconfigurable operator in the reconfigurable array; The logic circuit module generates an operation control signal sequence according to the dependency relationship between the configuration data of the scheduling task and the reconfigurable operator, and controls the reconfigurable operator to process and operate the subtask data.

5. The reconfigurable processor according to claim 1, wherein: The logic circuit module also includes a configuration unit, which is used to assign the function setting, connection mode, and data processing mode of the reconfigurable operator of the scheduling task to the reconfigurable operator through a preset parsing algorithm and mapping rule, so as to configure the reconfigurable operator in the reconfigurable array.

6. A computing method for a reconfigurable processor based on 3D DRAM, characterized in that: The method comprises a 3D DRAM, a logic circuit module and a reconfigurable module, and includes the following steps: The 3D DRAM includes a plurality of 3D storage areas, respectively storing reconfigurable operator configuration information and scheduling tasks of the reconfigurable processor; The reconfigurable module includes a plurality of reconfigurable operators; The logic circuit module obtains and analyzes the configuration data of the scheduling task from the 3D DRAM, determines the corresponding reconfigurable array according to the analysis result, configures the reconfigurable operator in the reconfigurable array according to the scheduling task, and uses the configured reconfigurable operator to calculate the scheduling task; The reconfigurable module reconfigures the storage position of the scheduled task in the multiple 3D storage areas according to the task type of the scheduled task and the distances between the multiple reconfigurable operators and the three-dimensional storage area.

7. The computing method of the reconfigurable processor according to claim 6, characterized in that: The logic circuit module obtains and parses the configuration data of the scheduling task from the 3D DRAM, specifically including the following steps: Acquire configuration data of the scheduling task from the 3D DRAM; converting the configuration data into a recognizable and processable format; Parse the converted configuration data into structured data including the task type, task ID, task priority, time constraint and resource requirement of the scheduled task; The scheduled tasks are sorted according to the parsed task priorities to form a priority task queue.

8. The computing method of the reconfigurable processor according to claim 6 or 7, characterized in that: The following steps are also included: The logic circuit module monitors the task execution process of the reconfigurable processor, the priority task queue and the operating environment of the reconfigurable processor; adjusting the task priority according to the real-time resources of the reconfigurable processor; Re-evaluating and adjusting the scheduling order of the priority task queue according to the update of the scheduling task; The reconfigurable operator is reconfigured according to the operating environment of the reconfigurable processor.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the computing method of the reconfigurable processor based on 3D DRAM as claimed in any one of claims 6 to 7 is implemented.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the computing method of the reconfigurable processor based on 3D DRAM as claimed in any one of claims 6 to 8 are implemented.

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