Dynamic reconfigurable processing system for breadth-first search algorithm and application method

Abstract

The invention discloses a dynamic reconfigurable processing system for a breadth-first search algorithm and an application method.The system comprises a dynamic reconfigurable processing unit array PEA and a shared memory, the PEA comprises a plurality of algorithm configuration controllers and a plurality of processing units PE, and each PE corresponds to one algorithm configuration controller; the algorithm configuration controller is used for storing logic of a breadth-first search (BFS) algorithm needing to be executed by the corresponding PE, and the logic comprises a plurality of steps; the shared memory is used for storing an input variable and an output variable of a breadth-first search algorithm; and the PE is used for reading the logic of the corresponding algorithm configuration controller, sequentially executing the steps in the logic after reading the input variable from the shared memory, and storing the output variable into the shared memory after the execution is finished. The method is high in calculation efficiency and low in energy consumption.

Description

Technical Field

[0001] The present invention relates to the field of agile development technology, and in particular to a dynamic reconfigurable processing method and system for a breadth-first search algorithm. Background Art

[0002] This section is intended to provide a background or context to the embodiments of the invention recited in the claims. No admission is made that the description herein is prior art by inclusion in this section.

[0003] As the most basic graph traversal algorithm, the Breadth First Search (BFS) algorithm has very important research significance. On the one hand, the BFS algorithm is the implementation basis of algorithms such as the shortest path, adjacency query, and reachability query, and is widely used in fields such as graph segmentation and belief propagation statistics; on the other hand, as a typical data-intensive algorithm, the BFS algorithm is widely used in the data processing capability evaluation of large-scale parallel computing systems.

[0004] There are currently several ideas for hardware implementation of the breadth-first search algorithm:

[0005] (1) Method based on general-purpose processor

[0006] For example, the clock frequency of a general-purpose processor is 1.6 GHz. The execution time of the BFS algorithm on this platform is 4 us, and the corresponding machine cycle is 4×1.6×1000=6400 cycles, so its computational efficiency is low.

[0007] (2) GPU-based methods

[0008] Solution 1: Map the BFS algorithm to matrix operations, and each layer of expansion process is mapped to a matrix multiplication operation. In the worst case, the working complexity of this method is O(n+m×n), and the performance is better when the graph diameter is small and the BFS tree width is large.

[0009] Solution 2: Improve the node scanning-based BFS parallel algorithm. On the one hand, nodes are expanded by warps instead of single threads, thereby reducing thread branches within the warp and improving the GPU's memory access efficiency by increasing the continuity of memory access addresses. On the other hand, the concept of virtual warps is proposed, and the number of virtual warp threads that expand the same node is adjusted according to the computing load, thereby improving the utilization of computing resources.

[0010] However, both the above-mentioned scheme 1 and scheme 2 have the problem of excessively high energy consumption.

[0011] (3) FPGA-based method

[0012] In the hardware implementation of the breadth-first search algorithm, the typical solution is the FPGA-oriented BFS algorithm based on message passing. On a single FPGA, a hardware logic structure is used to implement a layer-by-layer synchronous parallel algorithm similar to node partitioning, storing local data structures in on-chip RAM and global data structures in off-chip DRAM. Since the on-chip RAM capacity of the FPGA is only a few MB, and the number and capacity of DRAM that can be connected are limited, the graph scale that can be processed by this single FPGA-implemented BFS algorithm is relatively small. In addition, the storage control and crossbar switches consume a lot of logic resources. Summary of the invention

[0013] The embodiment of the present invention provides a dynamically reconfigurable processing system for a breadth-first search algorithm, which has high computational efficiency and low energy consumption. The system includes:

[0014] A dynamically reconfigurable processing unit array PEA and a shared memory, wherein the PEA includes a plurality of algorithm configuration controllers and a plurality of processing units PE, each PE corresponding to an algorithm configuration controller;

[0015] An algorithm configuration controller, used to store the logic of a breadth-first search BFS algorithm to be executed by a corresponding PE, wherein the logic includes multiple steps;

[0016] Shared memory, used to store the input and output variables of the breadth-first search algorithm;

[0017] PE is used to read the logic of the corresponding algorithm configuration controller, and after reading the input variables from the shared memory, execute the steps in the logic in sequence, and store the output variables in the shared memory when the execution is completed.

[0018] The embodiment of the present invention also provides an application method of a dynamically reconfigurable processing system for a breadth-first search algorithm, which has high computational efficiency and low energy consumption of the system. The method comprises:

[0019] The computational requirements of the breadth-first search algorithm are used to obtain input variables;

[0020] Input variables are input into a dynamically reconfigurable processing system for a breadth-first search algorithm to obtain output variable values.

[0021] An embodiment of the present invention also provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the above-mentioned dynamically reconfigurable processing method for a breadth-first search algorithm when executing the computer program.

[0022] An embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the dynamic reconfigurable processing method for the breadth-first search algorithm is implemented.

[0023] An embodiment of the present invention further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the dynamic reconfigurable processing method for the breadth-first search algorithm is implemented.

[0024] In an embodiment of the present invention, a dynamically reconfigurable processing unit array PEA and a shared memory, wherein the PEA includes a plurality of algorithm configuration controllers and a plurality of processing units PE, each PE corresponding to an algorithm configuration controller; the algorithm configuration controller is used to store the logic of the breadth-first search BFS algorithm to be executed by the corresponding PE, and the logic includes a plurality of steps; the shared memory is used to store the input variables and output variables of the breadth-first search algorithm; the PE is used to read the logic of the corresponding algorithm configuration controller, and after reading the input variables from the shared memory, the steps in the logic are executed in sequence, and when the execution is completed, the output variables are stored in the shared memory. The above system is based on a dynamically reconfigurable processor architecture, and the PE in the system is jointly driven by the configuration of the algorithm configuration controller and the data flow in the shared memory to perform corresponding operations, and multiple parallel PEs greatly improve the efficiency of the breadth-first search, and the design based on the dynamically reconfigurable processor architecture greatly reduces the energy consumption of the breadth-first search process on the hardware; in addition. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the prior art descriptions. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0026] Figure 1 It is a structural schematic diagram of a dynamically reconfigurable processing system for a breadth-first search algorithm in an embodiment of the present invention;

[0027] Figure 2 An example of an input graph of the BFS algorithm in an embodiment of the present invention;

[0028] Figure 3 The calculation process of the BFS algorithm in the embodiment of the present invention;

[0029] Figure 4 A data flow diagram of a row pointer array, a column index array, and a layer number array in an embodiment of the present invention;

[0030] Figure 5 is a schematic diagram of a shared memory in an embodiment of the present invention;

[0031] Figure 6 is a flow chart of an application method of a dynamically reconfigurable processing system for a breadth-first search algorithm in this embodiment;

[0032] Figure 7 Schematic diagram of a computer device in an embodiment of the present invention. DETAILED DESCRIPTION

[0033] To make the purpose, technical solution and advantages of the embodiments of the present invention more clear, the embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings. Here, the exemplary embodiments of the present invention and their descriptions are used to explain the present invention, but are not intended to limit the present invention.

[0034] The present invention implements the BFS algorithm based on the dynamically reconfigurable processor architecture CGRA. The CGRA tool chain uses high-level languages ​​(such as C or C++) to shorten the development cycle. The reconfigurable unit provides CGRA with multi-level flexibility and parallelism, which can realize dynamic reconstruction of functions and interconnections. In addition, CGRA is superior to fine-grained FPGA in terms of energy and area efficiency.

[0035] Figure 1 The structure diagram of the dynamically reconfigurable processing system for the breadth-first search algorithm in an embodiment of the present invention includes:

[0036] A dynamically reconfigurable processing unit array PEA10 and a shared memory 20, wherein the PEA10 includes a plurality of algorithm configuration controllers 101 and a plurality of processing units PE102, each PE102 corresponds to an algorithm configuration controller 101;

[0037] The algorithm configuration controller 101 is used to store the logic of the breadth-first search BFS algorithm to be executed by the corresponding PE, and the logic includes multiple steps;

[0038] A shared memory 20, used for storing input variables and output variables of a breadth-first search algorithm;

[0039] PE102 is used to read the logic of the corresponding algorithm configuration controller, and after reading the input variables from the shared memory, execute the steps in the logic in sequence, and store the output variables in the shared memory after the execution is completed.

[0040] In an embodiment of the present invention, the system is based on a dynamically reconfigurable processor architecture, and the PEs in the system are jointly driven by the configuration memory of the algorithm configuration controller and the data flow in the shared memory to perform corresponding operations, and multiple parallel PEs greatly improve the efficiency of the breadth-first search, and the design based on the dynamically reconfigurable processor architecture greatly reduces the energy consumption of the breadth-first search process on the hardware; in addition.

[0041] In the BFS algorithm, for a graph G(V,E) and a selected root node r∈V, the BFS algorithm traverses all nodes reachable from r layer by layer in order of distance from the root node from near to far, and constructs a breadth-first tree T with r as the root. For any node w∈V, the path from r to w in the breadth-first tree T corresponds to the shortest path from r to w in the graph G.

[0042] Figure 2 This is an example of an input graph of the BFS algorithm in an embodiment of the present invention, see Figure 2 The input of the BFS algorithm includes the CSR representation of the graph and the starting node number. The BFS algorithm starts from the starting node and performs a breadth-first traversal of the graph, and finally generates a breadth-first tree T with the starting node as the root. Figure 1 Take the graph B in the figure as an example, and set the root node to 0. Figure 3 The calculation process of the BFS algorithm in the embodiment of the present invention, L[i] is the layer number of node i in the BFS tree, that is, the shortest distance between node i and the root node r. The top-level implementation of the BFS algorithm is as follows Figure 3 As shown, starting from the root node, traverse the nodes layer by layer, expand from the current layer node front curLevel to the next layer node front nxtLevel, and save the tree structure to the L array.

[0043] In order to improve the hardware execution efficiency of the BFS algorithm, the parallelism of the BFS algorithm is first analyzed. The BFS algorithm needs to traverse nodes layer by layer, and the idea of ​​layer-by-layer traversal is universal. The BFS algorithm includes while loops and indefinite-length for loops, so PE is abstracted as a thread. The input of PE includes the ptr[] and col[] arrays of the BFS algorithm, plus the current layer and the next layer. Then the input variables of the BFS algorithm include the current layer variable, the next layer variable, the row pointer array col[] of the BFS algorithm, and the column index array ptr[]. Each element in the column index array represents the total number of all non-zero elements up to the row corresponding to the order of the current element, for example Figure 2In the example, the column index array ptr[] = {2, 3, 4, 6, 8, 9} contains 2 non-zero elements up to the first row, 3 non-zero elements up to the second row, and 4 non-zero elements up to the third row; the row pointer array indicates the row number of each non-zero element in each row, and the rows start from 0; the output variables of the BFS algorithm include the layer number array L[], which is used to store the layer number of the BFS node in the BFS tree, that is, the layer number of the node i in the BFS tree, for example Figure 4 In the example, node 0 is on the second layer, so L[0]=1, and node 1 is on the third layer, so L[1]=2. Figure 4 This is a data flow diagram of a row pointer array, a column index array, and a layer number array in an embodiment of the present invention. Figure 4 Taking 4 PEs as an example, the input variables of each PE include col and ptr, and the output variables are all L.

[0044] In one embodiment, the column index array and layer number array of the BFS algorithm adopt a sparse matrix data structure.

[0045] In one embodiment, the shared memory includes a plurality of storage blocks, and each PE corresponds to a storage block;

[0046] The plurality of storage blocks include a first type storage block and a plurality of second type storage blocks;

[0047] The first type of storage block is used to store row pointer arrays, column index arrays, layer number arrays, and current layer variables and next layer variables required by a PE;

[0048] The second type of storage blocks are used to store current layer variables and next layer variables required by PEs other than the PEs corresponding to the first type of storage blocks.

[0049] Figure 5 is a schematic diagram of a shared memory in an embodiment of the present invention, Figure 5 Taking four storage blocks as an example, the embodiment of the present invention puts all the ptr[] array, col[] array and L[] array into one storage block (first type storage block, Figure 4 This is because during the execution of PE, the col[] and L[] arrays are read randomly. If these two arrays are evenly placed on four storage blocks, then the data reading needs to select the storage block to read, which increases the execution time.

[0050] In the embodiment of the present invention, multiple PEs are executed in parallel, reading the ptr[] array and the col[] array, and writing the results back to the L[] array.

[0051] In one embodiment, PE is specifically used for:

[0052] Read the logic of the corresponding algorithm configuration controller, read the row pointer array, column index array, and layer number array from the first-class storage block, read the current layer variables and the next layer variables from the first-class storage block or the second-class storage block corresponding to the PE, and then execute the steps in the logic in sequence. When the execution is completed, the output variables are stored in the first-class storage block, wherein the search task of one layer of the BFS algorithm is terminated after each PE is executed.

[0053] In an embodiment of the present invention, the algorithm configuration controller is used to store the logic of the breadth-first search BFS algorithm to be executed by the corresponding PE, and the logic includes multiple steps.

[0054] In one embodiment, the logic of the BFS algorithm is stored in a configuration table, and each row of the configuration table is used to store a step, wherein the first column of each row is used to store the step number, the second column is used to store the source of the first input variable, the third column is used to store the source of the second input variable, the fourth column is used to store the branch jump judgment operation, the fifth column is used to store the calculation operation, and the sixth column is used to store the destination of the output variable.

[0055] Each algorithm configuration controller corresponds to a PE, and the corresponding ones are the logic of the BFS algorithm, so the logic of each algorithm configuration controller is similar. The design of multiple algorithm configuration controllers can make each PE read the corresponding algorithm configuration controller separately, without multiple PEs preemptively reading one algorithm configuration controller, so that the PE execution efficiency is high. In another embodiment, only one algorithm configuration controller can be designed, and each PE needs to read the logic of the BFS algorithm from this algorithm configuration controller. The function can run normally, but the algorithm performance efficiency is low.

[0056] See also Figure 1 In one embodiment, the system further comprises a control distributor 30 for:

[0057] After obtaining the input variables of the breadth-first search algorithm, each storage block and each algorithm configuration controller are initialized;

[0058] Schedule idle PEs to start execution.

[0059] Specifically, the computing requirements include specific assignment of input variables, initialization of each storage block, and each algorithm configuration controller, that is, storing input variables in the storage block and storing the logic steps of the breadth-first search algorithm.

[0060] Since the dynamically reconfigurable processing system used for the breadth-first search algorithm improves execution efficiency through the parallelization of PEs, the control allocator schedules idle PEs to start execution according to actual needs.

[0061] In addition, by simply increasing the capacity of the shared memory, a larger search tree can be processed without changing other hardware modules. The reconfigurable processor can also be configured to perform other operations or functions, with strong scalability.

[0062] Figure 6 The flowchart of the application method of the dynamically reconfigurable processing system for the breadth-first search algorithm in this embodiment includes:

[0063] Step 601, obtaining input variables by computing requirements of a breadth-first search algorithm;

[0064] Step 602: Input the input variables to the dynamically reconfigurable processing system for the breadth-first search algorithm to obtain the output variable values.

[0065] In summary, in the system and application method proposed in the embodiment of the present invention, there are a dynamically reconfigurable processing unit array PEA and a shared memory, wherein the PEA includes a plurality of algorithm configuration controllers and a plurality of processing units PE, each PE corresponds to an algorithm configuration controller; the algorithm configuration controller is used to store the logic of the breadth-first search BFS algorithm to be executed by the corresponding PE, and the logic includes a plurality of steps; the shared memory is used to store the input variables and output variables of the breadth-first search algorithm; the PE is used to read the logic of the corresponding algorithm configuration controller, and after reading the input variables from the shared memory, the steps in the logic are executed in sequence, and when the execution is completed, the output variables are stored in the shared memory. The above system is based on a dynamically reconfigurable processor architecture, and the PE in the system is jointly driven by the configuration of the algorithm configuration controller and the data flow in the shared memory to perform corresponding operations, and multiple parallel PEs greatly improve the efficiency of the breadth-first search, and the design based on the dynamically reconfigurable processor architecture greatly reduces the energy consumption of the breadth-first search process on the hardware; in addition, the system can also be configured to complete other operations or functions, and has strong scalability.

[0066] An embodiment of the present invention further provides a computer device, Figure 7 Schematic diagram of a computer device in an embodiment of the present invention, the computer device 700 includes a memory 710, a processor 720, and a computer program 730 stored in the memory 710 and executable on the processor 720, and the processor 720 implements the above-mentioned dynamically reconfigurable processing method for the breadth-first search algorithm when executing the computer program 730.

[0067] An embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the dynamic reconfigurable processing method for the breadth-first search algorithm is implemented.

[0068] An embodiment of the present invention further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the dynamic reconfigurable processing method for the breadth-first search algorithm is implemented.

[0069] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0070] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0071] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0072] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0073] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A dynamically reconfigurable processing system for a breadth-first search algorithm, characterized in that: include: A dynamically reconfigurable processing unit array PEA and a shared memory, wherein the PEA includes a plurality of algorithm configuration controllers and a plurality of processing units PE, each PE corresponding to an algorithm configuration controller; An algorithm configuration controller, used to store the logic of a breadth-first search BFS algorithm to be executed by a corresponding PE, wherein the logic includes multiple steps; Shared memory, used to store the input and output variables of the breadth-first search algorithm; PE is used to read the logic of the corresponding algorithm configuration controller, and after reading the input variables from the shared memory, execute the steps in the logic in sequence, and store the output variables in the shared memory when the execution is completed.

2. The system according to claim 1, characterized in that The input variables include current layer variables, next layer variables, row pointer array and column index array of BFS algorithm, and the output variables include layer number array, which is used to store the layer numbers of BFS nodes in the BFS tree.

3. The system according to claim 1, characterized in that The column index array and layer number array of the BFS algorithm use sparse matrix data structures.

4. The system according to claim 2, characterized in that The shared memory includes multiple storage blocks, and each PE corresponds to a storage block; The plurality of storage blocks include a first type storage block and a plurality of second type storage blocks; The first type of storage block is used to store row pointer arrays, column index arrays, layer number arrays, and current layer variables and next layer variables required by a PE; The second type of storage blocks are used to store current layer variables and next layer variables required by PEs other than the PEs corresponding to the first type of storage blocks.

5. The system according to claim 4, characterized in that PE is specifically used for: Read the logic of the corresponding algorithm configuration controller, read the row pointer array, column index array, and layer number array from the first-class storage block, read the current layer variables and the next layer variables from the first-class storage block or the second-class storage block corresponding to the PE, and then execute the steps in the logic in sequence. When the execution is completed, the output variables are stored in the first-class storage block, wherein the search task of one layer of the BFS algorithm is terminated after each PE is executed.

6. The system according to claim 1, characterized in that The logic of the BFS algorithm is stored in a configuration table, where each row of the configuration table is used to store a step, wherein the first column of each row is used to store the step number, the second column is used to store the source of the first input variable, the third column is used to store the source of the second input variable, the fourth column is used to store the branch jump judgment operation, the fifth column is used to store the calculation operation, and the sixth column is used to store the destination of the output variable.

7. The system according to claim 4, characterized in that Also included are control distributors for: After obtaining the input variables of the breadth-first search algorithm, each storage block and each algorithm configuration controller are initialized; Schedule idle PEs to start execution.

8. An application method of a dynamically reconfigurable processing system for a breadth-first search algorithm according to any one of claims 1 to 7, characterized in that: include: The computational requirements of the breadth-first search algorithm are used to obtain input variables; Input variables are input into a dynamically reconfigurable processing system for a breadth-first search algorithm to obtain output variable values.

9. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the method of claim 8 is implemented.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method of claim 8 is implemented.

11. A computer program product, characterized in that The computer program product comprises a computer program, and when the computer program is executed by a processor, the method of claim 8 is implemented.

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