Gallium nitride transistor on-resistance identification method, device, electronic device and medium

Abstract

The present application belongs to the field of power electronics technology, and specifically discloses a method, device, electronic device and medium for identifying the on-resistance of a gallium nitride transistor. The method includes: obtaining multiple target electrical parameter information of the physical model of the buck converter at each sampling moment; determining the inductor current and load voltage corresponding to the output of the mathematical model of the buck converter based on the multiple target electrical parameter information of the physical model at each sampling moment; with the goal of minimizing the deviation between the corresponding output voltages of the mathematical model and the physical model at all sampling moments, iteratively solving the on-resistance of the gallium nitride transistor output by the mathematical model based on the inductor current and load voltage corresponding to the output of the mathematical model, and obtaining the on-resistance of the gallium nitride transistor to be measured. Through the present application, the online identification of the on-resistance of the gallium nitride switching device in the power electronics system can be realized conveniently and effectively, with high identification accuracy and fast identification speed.

Description

Technical Field

[0001] The present application belongs to the field of power electronics technology, and more specifically, relates to a method, device, electronic device, and medium for identifying the on-resistance of a gallium nitride transistor. Background Art

[0002] The on-resistance of GaN transistor switches is a critical parameter that directly impacts circuit functionality and efficiency. Lower on-resistance means current can flow more easily through the switch, improving circuit efficiency. Conversely, excessive on-resistance increases circuit power consumption and reduces efficiency. Furthermore, identifying on-resistance can help assess the quality of GaN transistor switches. High-quality switches typically have lower on-resistance, while low-quality ones may have higher on-resistance.

[0003] However, because the on-resistance of GaN transistors is typically a few milliohms, existing conventional identification methods often require complex test circuits and a cumbersome testing process. They also suffer from low accuracy and slow speed. Therefore, how to better identify the on-resistance of GaN transistors has become a pressing technical challenge in the industry. Summary of the Invention

[0004] In response to the shortcomings of the existing technology, the purpose of this application is to better realize the identification of the on-resistance of gallium nitride transistors, aiming to solve the problems of low identification accuracy and slow identification speed in the existing technology of the on-resistance of gallium nitride transistors.

[0005] To achieve the above objectives, in a first aspect, the present application provides a method for identifying the on-resistance of a gallium nitride transistor, comprising:

[0006] Acquiring multiple target electrical parameter information of a physical model of a buck converter at each sampling time; the buck converter is an electronic device in which the gallium nitride transistor to be tested is located;

[0007] Determining, based on a plurality of target electrical parameter information of the physical model at each sampling moment, an inductor current and a load voltage outputted by a mathematical model of the buck converter corresponding to the inductor current and the load voltage; wherein the mathematical model of the buck converter is obtained by discretely modeling the buck converter;

[0008] With the goal of minimizing the deviation between the output voltages corresponding to the mathematical model and the physical model at all sampling moments, the on-resistance of the gallium nitride transistor output by the mathematical model is iteratively solved based on the inductor current and load voltage corresponding to the output of the mathematical model to obtain the on-resistance of the gallium nitride transistor to be tested.

[0009] Optionally, minimizing the deviation between the output voltages corresponding to the mathematical model and the physical model at all sampling moments, iteratively solving the on-resistance of the gallium nitride transistor output by the mathematical model based on the inductor current and load voltage corresponding to the output of the mathematical model to obtain the on-resistance of the gallium nitride transistor to be tested includes:

[0010] Determining a first output voltage deviation based on the mathematical model and the gallium nitride transistor voltage output by the physical model at each sampling moment, and determining a second output voltage deviation based on the mathematical model and the load voltage output by the physical model at each sampling moment;

[0011] determining a target fitness function of a particle swarm optimization algorithm based on the first output voltage deviation and the second output voltage deviation;

[0012] With the goal of minimizing the fitness value of the target fitness function, the inductor current and load voltage corresponding to the output of the mathematical model are input into the particle swarm optimization algorithm, and the on-resistance of the gallium nitride transistor output by the mathematical model is iteratively solved to obtain the on-resistance of the gallium nitride transistor to be tested.

[0013] Optionally, minimizing the fitness value of the target fitness function, inputting the inductor current and load voltage corresponding to the output of the mathematical model into the particle swarm optimization algorithm, iteratively solving the on-resistance of the gallium nitride transistor output by the mathematical model, and obtaining the on-resistance of the gallium nitride transistor to be tested includes:

[0014] Step S101: initializing each particle of the particle swarm optimization algorithm, the local optimal position of each particle, and the current global optimal particle based on a preset value range of the on-resistance of the gallium nitride transistor to be tested;

[0015] Step S102: Substituting the GaN transistor voltage and load voltage output by the physical model at each sampling moment, the inductor current and load voltage output by the mathematical model, and the on-resistance corresponding to each particle into the target fitness function to determine the fitness value of each particle;

[0016] Step S103, with the goal of minimizing the fitness value, updating the local optimal position of each particle and the global optimal particle in the current iteration process;

[0017] Step S104, determining whether the current number of iterations has reached the maximum number of iterations or whether the fitness value of the current global optimal particle has converged; if not, updating the position and velocity of each particle and jumping to step S102; if so, executing step S105;

[0018] Step S105 : obtaining a global optimal particle of a particle swarm optimization algorithm, and determining the on-resistance of the gallium nitride transistor to be tested based on the global optimal particle.

[0019] Optionally, before updating the position and velocity of each particle and jumping to step S102, the method further includes:

[0020] The current inertia weight of the particle swarm optimization algorithm is updated using the current number of iterations, the maximum number of iterations, the initial inertia weight of the algorithm, and the inertia weight corresponding to the maximum number of iterations.

[0021] Optionally, before determining the inductor current and load voltage outputted by the mathematical model of the buck converter corresponding to the plurality of target electrical parameter information of the physical model at each sampling moment, the method further comprises:

[0022] Determining a target state-space transfer function of an equivalent circuit of the buck converter using an inductor current and a capacitor voltage within the buck converter as state variables;

[0023] The buck converter is discretely modeled based on the target state-space transfer function using the Runge-Kutta method to determine a mathematical model of the buck converter.

[0024] Optionally, determining a target state-space transfer function of an equivalent circuit of the buck converter using an inductor current and a capacitor voltage in the buck converter as state variables includes:

[0025] Determine a first state-space transfer function of the equivalent circuit when the gallium nitride transistor to be tested is in an on state, using the inductor current and the capacitor voltage in the buck converter as state variables;

[0026] Determine a second state-space transfer function of the equivalent circuit when the gallium nitride transistor to be tested is in an off state, using the inductor current and the capacitor voltage in the buck converter as state variables;

[0027] The first state-space transfer function and the second state-space transfer function are fused to determine a target state-space transfer function of the equivalent circuit.

[0028] Optionally, the equivalent circuit of the buck converter includes a first equivalent resistor and an equivalent constant voltage source corresponding to the freewheeling diode, a second equivalent resistor and an equivalent switch corresponding to the gallium nitride transistor to be tested, a DC voltage source, an energy storage inductor, a first parasitic resistance of the energy storage inductor, a filter capacitor, a second parasitic resistance of the filter capacitor, and a load resistor;

[0029] The positive electrode of the DC voltage source is connected to one end of the second equivalent resistor, the other end of the second equivalent resistor is connected to one end of the equivalent switch, and the other end of the equivalent switch, one end of the first parasitic resistor, and one end of the first equivalent resistor are connected in common;

[0030] The other end of the first equivalent resistor is connected to the negative electrode of the equivalent constant voltage source, the other end of the first parasitic resistor is connected to one end of the energy storage inductor, and the other end of the energy storage inductor, one end of the load resistor and the positive electrode of the filter capacitor are connected in common;

[0031] The negative electrode of the filter capacitor is connected to one end of the second parasitic resistor, and the negative electrode of the DC voltage source, the positive electrode of the equivalent constant voltage source, the other end of the second parasitic resistor and the other end of the load resistor are connected in common.

[0032] In a second aspect, the present application provides a device for identifying on-resistance of a gallium nitride transistor, comprising:

[0033] An acquisition module is configured to acquire a plurality of target electrical parameter information of a physical model of a buck converter at each sampling moment; the buck converter is an electronic device in which the gallium nitride transistor to be measured is located;

[0034] a processing module, configured to determine, based on a plurality of target electrical parameter information of the physical model at each sampling moment, an inductor current and a load voltage outputted by a mathematical model of the buck converter corresponding to the inductor current and the load voltage; the mathematical model of the buck converter being obtained by discretely modeling the buck converter;

[0035] An identification module is configured to iteratively solve the on-resistance of the gallium nitride transistor output by the mathematical model based on the inductor current and load voltage output by the mathematical model, with the goal of minimizing the deviation between the output voltages corresponding to the mathematical model and the physical model at all sampling moments, to obtain the on-resistance of the gallium nitride transistor to be tested.

[0036] In a third aspect, the present application provides an electronic device comprising: at least one memory for storing programs; and at least one processor for executing the programs stored in the memory. When the program stored in the memory is executed, the processor is used to execute the method described in the first aspect or any possible implementation of the first aspect.

[0037] In a fourth aspect, the present application provides a computer-readable storage medium, which stores a computer program. When the computer program runs on a processor, the processor executes the method described in the first aspect or any possible implementation of the first aspect.

[0038] In a fifth aspect, the present application provides a computer program product, which, when executed on a processor, enables the processor to execute the method described in the first aspect or any possible implementation of the first aspect.

[0039] In general, the above technical solutions conceived by this application have the following beneficial effects compared with the existing technologies:

[0040] The present application provides a method, apparatus, electronic device, and medium for identifying the on-resistance of a GaN transistor. By utilizing a digital twin approach, the method fully exploits the input-output characteristics associated between the physical model and the mathematical model of a buck converter in which a GaN transistor switching device resides. Multiple target electrical parameter information of the buck converter's physical model at each sampling moment is used to determine the inductor current and load voltage output by the mathematical model. Furthermore, with the goal of minimizing the deviation between the corresponding output voltages of the mathematical model and the physical model at all sampling moments, the on-resistance of the GaN transistor output by the mathematical model is iteratively solved. Feedback from the buck converter's physical system to its digital model is implemented, ultimately determining the on-resistance of the GaN transistor to be tested. This method facilitates the efficient and convenient online identification of the on-resistance of GaN switching devices in power electronics systems, with high accuracy and speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 1 is a flow chart of a method for identifying the on-resistance of a gallium nitride transistor provided in an embodiment of the present application;

[0042] Figure 2 1 is a schematic structural diagram of an equivalent circuit of a buck converter taking parasitic parameters into consideration provided by an embodiment of the present application;

[0043] Figure 3 1 is a schematic structural diagram of an equivalent circuit when the gallium nitride transistor to be tested in the buck converter provided by an embodiment of the present application is turned on;

[0044] Figure 4 1 is a schematic structural diagram of an equivalent circuit when the gallium nitride transistor to be tested in the buck converter provided by an embodiment of the present application is turned off;

[0045] Figure 5 This is a schematic diagram of the on-resistance identification process of a gallium nitride transistor based on the PSO algorithm provided in an embodiment of the present application;

[0046] Figure 6 Schematic diagram of the convergence curve of the particle swarm optimization algorithm based on variable inertia weight provided in an embodiment of the present application;

[0047] Figure 7(a) is a schematic diagram comparing the voltage waveform of the fourth-order Rung-Kutta method provided in an embodiment of the present application with the actual output; (b) is a schematic diagram comparing the inductor current waveform of the fourth-order Rung-Kutta method provided in an embodiment of the present application with the actual output; (c) is a schematic diagram showing the relative error curves of the output voltage and inductor current of the fourth-order Rung-Kutta method provided in an embodiment of the present application with the actual output;

[0048] Figure 8 2 is a schematic diagram of the on-resistance identification result of the gallium nitride transistor provided in an embodiment of the present application;

[0049] Figure 9 Schematic diagram of a clamping circuit structure for measuring the on-state voltage drop of a gallium nitride transistor provided in an embodiment of the present application;

[0050] Figure 10 1 is a schematic structural diagram of a device for identifying on-resistance of a gallium nitride transistor provided in an embodiment of the present application;

[0051] Figure 11 It is a structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0052] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0053] In the specification and claims of this application, the terms "first" and "second" are used to distinguish different objects, rather than to describe a specific order of objects. For example, "first output voltage deviation" and "second output voltage deviation" are used to distinguish different output voltage deviations, rather than to describe a specific order of output voltage deviations.

[0054] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0055] The embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application.

[0056] Figure 1 FIG. 1 is a flow chart of a method for identifying the on-resistance of a gallium nitride transistor according to an embodiment of the present application. Figure 1 Shown, including:

[0057] Step S1, obtaining multiple target electrical parameter information of a physical model of a buck converter at each sampling time; the buck converter is an electronic device in which the gallium nitride transistor to be tested is located;

[0058] Step S2: determining the output inductor current and load voltage corresponding to the mathematical model of the buck converter based on multiple target electrical parameter information of the physical model at each sampling moment; the mathematical model of the buck converter is obtained by discrete modeling of the buck converter;

[0059] In step S3, with the goal of minimizing the deviation between the output voltages corresponding to the mathematical model and the physical model at all sampling moments, the on-resistance of the GaN transistor output by the mathematical model is iteratively solved based on the inductor current and load voltage corresponding to the output of the mathematical model to obtain the on-resistance of the GaN transistor to be tested.

[0060] Specifically, the physical model of the buck converter described in the embodiments of this application refers to a circuit system consisting of physical components such as a gallium nitride transistor to be tested as a switch, a freewheeling diode, an energy storage inductor, a filter capacitor, and a load resistor. It is used to adjust the output voltage by adjusting the duty cycle of the switch. A buck converter is a non-isolated DC converter with an output voltage less than or equal to the input voltage; a gallium nitride transistor is also known as a gallium nitride high electron mobility transistor (GaN HEMT).

[0061] The mathematical model of the Buck converter described in the embodiment of the present application refers to a mathematical description of the dynamic characteristics of the Buck converter operating within a switching cycle, which can be obtained by discrete modeling of the equivalent circuit of the buck converter.

[0062] The target electrical parameter information described in the embodiments of the present application refers to the relevant electrical parameter information collected by the topological circuit of the Buck converter during actual operation at different sampling times. Specifically, it may include the power supply voltage, inductor current, the voltage across the GaN transistor to be measured, the load voltage, etc. This electrical parameter information can be used to calculate the inductor current and load voltage at the same sampling time based on the mathematical model of the Buck converter.

[0063] It can be understood that in the embodiments of the present application, the inductor current and load voltage described refer to the current flowing through the energy storage inductor and the voltage across the load resistor when the Buck converter is working, respectively.

[0064] In an embodiment of the present application, in step S1, a physical model of a Buck converter is first constructed using physical components such as a GaN transistor to be tested, a freewheeling diode, an energy storage inductor, a filter capacitor, and a load resistor, and a corresponding sampling circuit is constructed. Through the sampling circuit of the Buck converter, multiple target electrical parameter information of the Buck converter at each sampling moment can be obtained, including power supply voltage, inductor current, voltage across the GaN transistor to be tested, load voltage, etc.

[0065] Furthermore, in an embodiment of the present application, in step S2, first, a digital twin method can be used to obtain an equivalent circuit of the Buck converter based on the physical model of the Buck converter. Then, the equivalent circuit of the Buck converter can be discretely modeled by a differential equation solving method to obtain a mathematical model of the Buck converter. Then, the multiple target electrical parameter information obtained by the aforementioned physical model at each sampling moment can be substituted into the mathematical model of the Buck converter for solution to determine the inductor current and load voltage output by the mathematical model at each sampling moment.

[0066] Furthermore, in an embodiment of the present application, in step S3, an optimal solution search algorithm, such as a particle swarm optimization (PSO) algorithm, can be used to minimize the deviation between the output voltages corresponding to the mathematical model and the physical model of the Buck converter at all sampling times. The output of the mathematical model of the Buck converter is made as close as possible to the actual output of its physical model as an iteration condition. The inductor current and load voltage corresponding to the output of the mathematical model are substituted into the mathematical model to iteratively solve the on-resistance of the GaN transistor. The optimal solution for the on-resistance during the mathematical model solution process is found, and the on-resistance of the GaN transistor to be tested is ultimately obtained. This can achieve online identification of the on-resistance of the GaN transistor.

[0067] The GaN transistor on-resistance identification method of the present application fully exploits the input-output characteristics associated between the physical model and the mathematical model of the buck converter in which the GaN transistor switching device is located by utilizing a digital twin approach. The method utilizes multiple target electrical parameter information of the buck converter physical model at each sampling moment to determine the inductor current and load voltage output by the mathematical model. Furthermore, with the goal of minimizing the deviation between the corresponding output voltages of the mathematical model and the physical model at all sampling moments, the GaN transistor on-resistance output by the mathematical model is iteratively solved, enabling feedback from the buck converter physical system to its digital model. Ultimately, the on-resistance of the GaN transistor to be tested is solved. This method can conveniently and effectively implement online identification of the on-resistance of GaN switching devices in power electronics systems, with high accuracy and speed.

[0068] Based on the above embodiment, as an optional embodiment, before determining the output inductor current and load voltage corresponding to the mathematical model of the buck converter based on multiple target electrical parameter information of the physical model at each sampling moment, the method further includes:

[0069] Determine the target state space transfer function of the equivalent circuit of the buck converter using the inductor current and capacitor voltage in the buck converter as state variables;

[0070] The Runge-Kutta method is used to discretely model the buck converter based on the target state-space transfer function, and the mathematical model of the buck converter is determined.

[0071] Specifically, in the embodiments of the present application, before using the multiple target electrical parameter information of the Buck converter physical model at each sampling moment to determine the inductor current and load voltage output corresponding to the mathematical model, a mathematical model of the Buck converter must be pre-established. First, the parasitic parameters of the Buck converter during actual operation must be considered, and an equivalent circuit is established using the inductor current and capacitor voltage within the Buck converter as state variables, and the target state-space transfer function of the equivalent circuit is determined.

[0072] Figure 2 is a structural diagram of a buck converter equivalent circuit considering parasitic parameters provided in an embodiment of the present application, such as Figure 2 As shown, in the embodiment of the present application, the equivalent circuit of the Buck converter includes a first equivalent resistor corresponding to the freewheeling diode R D and equivalent constant voltage source v F , the second equivalent resistance corresponding to the GaN transistor to be tested R dson and equivalent switches S , DC voltage source v in , energy storage inductor L , energy storage inductor L The first parasitic resistance R L , filter capacitor C , filter capacitor C The second parasitic resistance R C and load resistance R ;

[0073] DC voltage source v in The positive electrode and the second equivalent resistance R dson One end of the second equivalent resistor is connectedR dson The other end of the equivalent switch S One end of the connection is equivalent to a switch S The other end of the first parasitic resistance R L One end and the first equivalent resistance R D One end is connected together;

[0074] The first equivalent resistance R D The other end of the equivalent constant voltage source v F The negative connection of the first parasitic resistance R L The other end of the energy storage inductor L One end of the energy storage inductor is connected L The other end of the load resistor R One end and the filter capacitor C The positive electrodes are connected in common;

[0075] filter capacitors C The negative electrode and the second parasitic resistance R C Connect one end of the DC voltage source v in Negative electrode, equivalent constant voltage source v F The positive electrode and the second parasitic resistance R C The other end and the load resistor R The other end is connected in common.

[0076] Specifically, if Figure 2 As shown, in practical applications, the Buck converter must consider parasitic parameters, such as the energy storage inductor L and filter capacitors C There are parasitic resistances R L and R C The GaN transistor switch tube to be tested can be equivalent to a conditional switch S Its on-resistance R dson Connected in series, the freewheeling diode can be equivalent to a forward conduction voltage of v F The constant voltage source and its on-resistance R D Series, v in The DC input voltage provided by the DC voltage source, v o is the DC output voltage, R is the load resistance,i L is the current flowing through the energy storage inductor, v c is the voltage across the filter capacitor.

[0077] The method of the embodiment of the present application, by considering the parasitic parameters in the Buck converter in actual applications to construct its equivalent circuit, can conveniently determine the state variables and state space of the Buck converter system, realize comprehensive mathematical description and analysis, and is conducive to improving the reliability and accuracy of the established Buck converter mathematical model.

[0078] Furthermore, in an embodiment of the present application, a target state-space transfer function of the above-mentioned Buck converter equivalent circuit is determined.

[0079] Based on the above embodiments, as an optional embodiment, determining a target state-space transfer function of an equivalent circuit of a buck converter using the inductor current and capacitor voltage in the buck converter as state variables includes:

[0080] Determine the first state-space transfer function of the equivalent circuit when the GaN transistor to be tested is in the on state, using the inductor current and capacitor voltage in the buck converter as state variables;

[0081] Using the inductor current and capacitor voltage in the buck converter as state variables, determine the second state-space transfer function of the equivalent circuit when the GaN transistor to be tested is in the off state;

[0082] The first state-space transfer function and the second state-space transfer function are fused to determine a target state-space transfer function of the equivalent circuit.

[0083] Specifically, the first state-space transfer function described in the embodiment of the present application refers to the state-space transfer function of the Buck converter equivalent circuit when the gallium nitride transistor to be tested is in the on state.

[0084] The second state-space transfer function described in the embodiment of the present application refers to the state-space transfer function of the Buck converter equivalent circuit when the GaN transistor to be tested is in the off state.

[0085] It's important to note that a circuit's state-space transfer function consists of state variables, input variables, and output variables. State variables describe the dynamic state within the circuit system, input variables are external signals acting on the system, such as an externally supplied DC input voltage, and output variables are the system's response to the input signal.

[0086] In the embodiment of the present application, the capacitor voltage v c and the inductor current iL A mathematical model of the Buck converter is established for the state variables, taking into account parasitic parameters. Here, the Buck converter is mainly discussed working in the continuous current mode, and the model is based on whether the GaN transistor to be tested is turned on.

[0087] like Figure 3 As shown in the figure, the circuit diagram is the equivalent circuit when the GaN transistor to be tested is turned on. Therefore, the first state space transfer function of the Buck converter equivalent circuit when the GaN transistor to be tested is in the turned-on state can be expressed as:

[0088] ;

[0089] Where, Indicates load resistance The voltage across the load is the output voltage of the entire circuit.

[0090] Further, if Figure 4 As shown in the figure, this circuit diagram is the equivalent circuit when the GaN transistor to be tested is turned off. Therefore, the second state space transfer function of the Buck converter equivalent circuit when the GaN transistor to be tested is in the off state can be expressed as:

[0091] ;

[0092] Furthermore, the first state-space transfer function and the second state-space transfer function can be fused and described in the form of a matrix to obtain the target state-space transfer function of the Buck converter equivalent circuit, which can be expressed as:

[0093] ;

[0094] in:

[0095] ;

[0096] Where, S =1 indicates that the GaN transistor to be tested is turned on; S =0 means the GaN transistor to be tested is turned off.

[0097] The method of the embodiment of the present application adopts a state-space representation method, uses the inductor current and capacitor voltage in the Buck converter as state variables, and the load voltage as the output variable, to accurately describe the input-output relationship and internal state changes of the entire Buck converter circuit system, which is conducive to further improving the reliability and accuracy of the established Buck converter mathematical model.

[0098] Furthermore, in the embodiment of the present application, the Rung-Kutta method can be used to discretely model the Buck converter based on the target state space transfer function obtained above to obtain a mathematical model of the Buck converter. Specifically, the fourth-order Rung-Kutta method can be used to complete high-precision modeling. The specific method is to use the interval [ x n , x n+1 ] by taking 2 different points in the interval, we can get the second-order Rung-Kutta expression. Similarly, by taking N different points in this interval, we can get the N-order Rung-Kutta expression.

[0099] Since the fourth-order Rung-Kutta method can achieve fourth-order accuracy, it has good numerical stability and is easy to program. In addition, this method only requires knowing the first-order derivative and inputting the initial conditions to automatically start the output. It is very suitable for fitting the output characteristics of power electronic systems containing components such as inductors and capacitors. Therefore, in the embodiments of this application, the fourth-order Rung-Kutta method can be applied, and its expression is:

[0100] ;

[0101] Furthermore, the fourth-order Rung-Kutta method can be combined with the target state space transfer function of the Buck converter to perform discrete modeling on the Buck converter and obtain its mathematical model. The specific process can be expressed as follows:

[0102] ; ;

[0103] in, The inductor current in the above target state space transfer function can be The time domain differential equation is obtained as follows: The inductor voltage in the above target state space transfer function can be The time domain differential equation is obtained.

[0104] The method of the embodiment of the present application uses the Rung-Kutta method combined with the state-space transfer function of the Buck converter to discretely model the Buck converter. By leveraging the advantages of the fourth-order Rung-Kutta method, such as fast convergence speed, high computational efficiency, and support for complex circuit analysis, the efficiency of circuit analysis can be greatly improved, thereby enhancing the efficiency of subsequent gallium nitride transistor on-resistance identification.

[0105] Based on the content of the above embodiment, as an optional embodiment, with the goal of minimizing the deviation between the corresponding output voltages of the mathematical model and the physical model at all sampling moments, the on-resistance of the gallium nitride transistor output by the mathematical model is iteratively solved based on the inductor current and load voltage corresponding to the output of the mathematical model to obtain the on-resistance of the gallium nitride transistor to be tested, including:

[0106] Determining a first output voltage deviation based on the GaN transistor voltage output by the mathematical model and the physical model at each sampling moment, and determining a second output voltage deviation based on the load voltage output by the mathematical model and the physical model at each sampling moment;

[0107] Determining a target fitness function of a PSO algorithm based on the first output voltage deviation and the second output voltage deviation;

[0108] With the goal of minimizing the fitness value of the target fitness function, the inductor current and load voltage corresponding to the output of the mathematical model are input into the PSO algorithm, and the on-resistance of the GaN transistor output by the mathematical model is iteratively solved to obtain the on-resistance of the GaN transistor to be tested.

[0109] Specifically, the first output voltage deviation described in the embodiment of the present application refers to the deviation between the voltage across the GaN transistor to be tested output by the mathematical model of the Buck converter and the voltage across the GaN transistor to be tested output by its physical model at each sampling moment.

[0110] The second output voltage deviation described in the embodiment of the present application refers to the deviation between the load voltage output by the mathematical model of the Buck converter and the load voltage output by its physical model at each sampling moment.

[0111] In the embodiment of the present application, the PSO algorithm is used to iteratively solve the on-resistance of the gallium nitride transistor output by the mathematical model. First, the target fitness function of the PSO algorithm is determined by using the first output voltage deviation and the second output voltage deviation. , the objective fitness function It can be expressed as:

[0112] ;

[0113] in, N Indicates the number of sampling moments within the preset sampling time period; The voltage across the GaN transistor under test output by the mathematical model of the Buck converter at each sampling moment; Indicates the voltage across the GaN transistor under test output by the physical model of the Buck converter at each sampling moment; Represents the load voltage output by the mathematical model of the Buck converter at each sampling moment; It represents the load voltage output by the physical model of the Buck converter at each sampling moment.

[0114] Furthermore, in the embodiment of the present application, the objective fitness function is minimized. The fitness value is the target, and the mathematical model corresponds to the inductor current output at each sampling moment and load voltage Input into the PSO algorithm, and at the same time, the voltage across the GaN transistor to be tested output at each sampling moment of the physical model is and load voltage , the on-resistance of the GaN transistor output by the mathematical model Perform iterative solution to obtain the on-resistance of the GaN transistor to be tested.

[0115] Specifically, after the discrete modeling of the closed-loop Buck converter is completed by the fourth-order Rung-Kutta method to obtain the digital model, the on-resistance value of the GaN device to be measured is R dson Complete initialization and determine the inductor current output by the mathematical model i L and capacitor voltage v C The initial value of the inductor current output by the mathematical model at the next moment can be calculated through the update iteration of the PSO algorithm model. i L and capacitor voltage v C Combine the output voltage corresponding to the mathematical model and the physical model at all sampling moments to calculate the target fitness function f obj The value of the target fitness function f obj Whether the value converges or the number of iterations reaches the maximum number of iterations.

[0116] If so, the control algorithm stops the identification process and outputs the final identification result R dson ; If not, complete a new round of values ​​to be identified R dson Initialization until the target fitness function f obj The value of satisfies the above-mentioned iterative termination condition, and finally the on-resistance of the GaN transistor to be tested is obtained.

[0117] The method of the embodiment of the present application utilizes the advantages of the PSO algorithm, such as fast convergence speed and strong global search capability, to iteratively solve the on-resistance of the GaN transistor output by the Buck switch mathematical model using the PSO algorithm, thereby improving the accuracy and convergence speed of the on-resistance identification of the GaN device.

[0118] Based on the content of the above embodiment, as an optional embodiment, with the goal of minimizing the fitness value of the target fitness function, the inductor current and load voltage corresponding to the output of the mathematical model are input into the PSO algorithm, and the on-resistance of the gallium nitride transistor output by the mathematical model is iteratively solved to obtain the on-resistance of the gallium nitride transistor to be tested, including:

[0119] Step S101 , initializing each particle of a particle swarm optimization algorithm, the local optimal position of each particle, and the current global optimal particle based on a preset value range of the on-resistance of the gallium nitride transistor to be tested;

[0120] Step S102: Substitute the GaN transistor voltage and load voltage output by the physical model at each sampling moment, the inductor current and load voltage output by the mathematical model, and the on-resistance corresponding to each particle into the target fitness function to determine the fitness value of each particle.

[0121] Step S103, with the goal of minimizing the fitness value, updating the local optimal position of each particle and the global optimal particle in the current iteration process;

[0122] Step S104: determine whether the current number of iterations has reached the maximum number of iterations or whether the fitness value of the current global optimal particle has converged; if not, update the position and velocity of each particle and jump to step S102; if so, execute step S105;

[0123] Step S105 : obtaining a global optimal particle of a particle swarm optimization algorithm, and determining the on-resistance of the gallium nitride transistor to be tested based on the global optimal particle.

[0124] Specifically, in the embodiment of the present application, a PSO algorithm is combined with a mathematical model of a Buck converter to introduce a specific implementation method for iteratively solving the on-resistance of a gallium nitride transistor.

[0125] Figure 5 : is a schematic diagram of the on-resistance identification process of a gallium nitride transistor based on the PSO algorithm provided in an embodiment of the present application, such as Figure 5As shown, in an embodiment of the present application, in step S101, parameter initialization is performed. Specifically, based on a preset value range of the on-resistance of the GaN transistor to be tested, each particle of the particle swarm optimization algorithm, the local optimal position of each particle, and the current global optimal particle are randomly initialized. The preset value range of the on-resistance of the GaN transistor to be tested can be set based on the model and physical properties of the GaN transistor to be tested.

[0126] It can be understood that each particle carries a randomly initialized on-resistance value of the GaN transistor to be tested.

[0127] Furthermore, in step S102, the fitness of each particle is calculated. Specifically, the GaN transistor voltage output by the physical model of the Buck converter at each sampling moment is converted into the GaN transistor voltage. and load voltage , the mathematical model corresponds to the output inductor current and load voltage , and the on-resistance value corresponding to each particle are substituted into the aforementioned target fitness function to calculate the fitness value of each particle.

[0128] Then, in step S103, the minimum fitness value is searched. The value is used to update the local best position value pBest of each particle and the fitness value gBest of the global best particle in the current iteration. Among them, the minimum fitness value among all fitness values ​​pBest is gBest.

[0129] Furthermore, in step S104, it is determined whether the current number of iterations has reached the maximum number of iterations or whether the fitness value gBest of the current global optimal particle has converged. If not, the particle state is estimated, the control algorithm parameters are adaptively controlled, and an elite learning strategy is executed to update the position and velocity of each particle. The process then jumps to step S102 to complete the initialization of the new round of on-resistance, reacquire the sampled data of the Buck converter physical model at different sampling times, and calculate the fitness value of each particle in the new round in combination with the output data corresponding to the mathematical model. Then, the aforementioned steps S103 and S104 are repeated.

[0130] Based on the content of the above embodiment, as an optional embodiment, before updating the position and velocity of each particle and jumping to step S102, the method further includes:

[0131] The current inertia weight of the particle swarm optimization algorithm is updated using the current number of iterations, the maximum number of iterations, the initial inertia weight of the algorithm, and the inertia weight corresponding to the maximum number of iterations.

[0132] Specifically, in the embodiment of the present application, in the aforementioned step S104, before updating the position and velocity of each particle and jumping to step S102, the PSO algorithm can be improved by using a variable inertia weight. The current inertia weight of the particle swarm optimization algorithm is dynamically updated using the current number of iterations, the maximum number of iterations, the initial inertia weight of the algorithm, and the inertia weight corresponding to the maximum number of iterations. This process can be expressed as:

[0133] ;

[0134] in, j Indicates the current iteration number, ger represents the maximum number of iterations, ω start and ω end They represent the initial inertia weight and the inertia weight corresponding to the maximum number of iterations, and their commonly used values ​​are 0.9 and 0.4 respectively.

[0135] The method of the embodiment of the present application improves the PSO algorithm by adopting a variable inertia weight, which can effectively accelerate the algorithm convergence speed, enhance global and local search capabilities, improve the robustness of the particle swarm optimization algorithm, and help further improve the efficiency of gallium nitride transistor on-resistance identification.

[0136] Figure 6 : is a schematic diagram of the convergence curve of the particle swarm optimization algorithm based on variable inertia weight provided in the embodiment of the present application, such as Figure 6 As shown in the figure, the variable inertia weight PSO evolution curve is obtained by running the simulation 10 times after collecting data (the fastest convergence among the 10 times is taken). The algorithm completes convergence after the 33rd iteration at the fastest, and the optimal fitness is 0.1016.

[0137] Furthermore, in step S104, it is determined whether the current number of iterations has reached the maximum number of iterations or whether the fitness value gBest of the current global optimal particle has converged. If so, the algorithm iteration termination condition is met, and step S105 is executed.

[0138] Furthermore, in step S105, the global optimal particle of the current PSO algorithm is obtained, and based on the fitness value gBest of the global optimal particle, the on-resistance value of the GaN transistor to be tested is determined. R dson , that is, the identification result of the on-resistance of the GaN transistor to be tested is finally obtained.

[0139] The method of the embodiment of the present application can further significantly improve the accuracy and efficiency of GaN device on-resistance identification by fully leveraging the advantages of the digital twin algorithm and combining it with the PSO algorithm to continuously iteratively optimize the identification results of the GaN transistor on-resistance.

[0140] Figure 7 (a) is a schematic diagram comparing the voltage waveform of the fourth-order Rung-Kutta method provided in the embodiment of the present application with the actual output; (b) is a schematic diagram comparing the inductor current waveform of the fourth-order Rung-Kutta method provided in the embodiment of the present application with the actual output; (c) is a schematic diagram showing the relative error curves of the output voltage and inductor current of the fourth-order Rung-Kutta method provided in the embodiment of the present application with the actual output. Figure 7 As shown, in the embodiment of the present application, after substituting the identification results, the relative error between the inductor current waveform output by the digital model based on the fourth-order Rung-Kutta method and the inductor current waveform output by the actual Buck converter circuit is within 0.17%, and after substituting the identification results, the relative error between the voltage waveform output by the digital model based on the fourth-order Rung-Kutta method and the voltage waveform output by the actual Buck converter circuit is within 0.025%. This shows that the output accuracy of the Buck converter mathematical model provided by the present application is high.

[0141] Figure 8 is a schematic diagram of the on-resistance identification result of the gallium nitride transistor provided in the embodiment of the present application, such as Figure 8 As shown, it is a statistical example of 10 times of the on-resistance of the gallium nitride transistor to be tested in a specific embodiment of the present application. R dson The identification value result of the on-resistance can be obtained by statistics. R dson The average relative error can reach 1.66%, which shows that the recognition method provided in the embodiment of the present application has a high recognition accuracy.

[0142] Figure 9 is a schematic diagram of a clamping circuit structure for measuring the on-state voltage drop of a gallium nitride transistor provided in an embodiment of the present application, such as Figure 9 As shown, in the embodiment of the present application, a clamping circuit is used to clamp and block the voltage of the gallium nitride transistor in the high off state. V dson , only measure the low open state V ds The voltage and low voltage measurement resolution will be improved, the results will be more accurate, and it will be convenient to measure the on-resistance online. R dson The true value is used to verify the accuracy of the identification results of this application.

[0143] It should be noted that in this clamping circuit D1 is a high-voltage SiC diode with relatively small parasitic capacitance. It blocks high voltage when the device under test is in the off state and conducts when it is in the on state. A Zener diode is required to attenuate the voltage spikes on the clamp circuit. Z 1, therefore, the measured voltage on the oscilloscope will not be overwritten and higher measurement resolution can be achieved. However, Zener diodes generally have relatively poor reverse recovery performance. During the turn-on transient, a relatively high voltage ramp d will be introduced due to the fast switching performance of the GaN HEMT. v / d t . Current can flow into the Zener diode Z 1. Its reverse recovery will affect the measured voltage V ds(m) , so the low voltage Schottky diode D 2 for d v / d t During this time, a path is provided for the current. R 1 and R 2 at the supply voltage Vcc A voltage divider is formed on the .

[0144] The GaN transistor on-resistance identification device provided in the present application is described below. The GaN transistor on-resistance identification device described below and the GaN transistor on-resistance identification method described above can be referenced to each other.

[0145] Figure 10 is a structural diagram of a gallium nitride transistor on-resistance identification device provided in an embodiment of the present application, such as Figure 10 Shown, including:

[0146] An acquisition module 100 is configured to acquire a plurality of target electrical parameter information of a physical model of a buck converter at each sampling time; the buck converter is an electronic device in which the gallium nitride transistor to be tested is located;

[0147] The processing module 200 is configured to determine, based on the multiple target electrical parameter information of the physical model at each sampling moment, the output inductor current and load voltage corresponding to the mathematical model of the buck converter; the mathematical model of the buck converter is obtained by discrete modeling of the buck converter;

[0148] The identification module 300 is configured to iteratively solve the on-resistance of the GaN transistor output by the mathematical model based on the inductor current and load voltage corresponding to the mathematical model, with the goal of minimizing the deviation between the corresponding output voltages of the mathematical model and the physical model at all sampling times, to obtain the on-resistance of the GaN transistor to be tested.

[0149] It is understandable that the detailed functional implementation of each of the above units / modules can be found in the introduction of the aforementioned method embodiment, and will not be repeated here.

[0150] It should be understood that the above-mentioned device is used to execute the method in the above-mentioned embodiment. The implementation principle and technical effect of the corresponding program module in the device are similar to those described in the above-mentioned method. The working process of the device can refer to the corresponding process in the above-mentioned method and will not be repeated here.

[0151] The GaN transistor on-resistance identification device of the present application utilizes a digital twin approach to fully exploit the input-output characteristics associated between the physical model and the mathematical model of the buck converter in which the GaN transistor switching device resides. It utilizes multiple target electrical parameter information of the buck converter physical model at each sampling moment to determine the inductor current and load voltage output by the mathematical model. Furthermore, with the goal of minimizing the deviation between the corresponding output voltages of the mathematical model and the physical model at all sampling moments, it iteratively solves the GaN transistor on-resistance output by the mathematical model, enabling feedback from the buck converter physical system to its digital model. Ultimately, the on-resistance of the GaN transistor to be tested is solved. This device can conveniently and effectively implement online identification of the on-resistance of GaN switching devices in power electronics systems, with high accuracy and speed.

[0152] Based on the method in the above embodiment, the embodiment of the present application provides an electronic device, such as Figure 11 As shown, the electronic device may include: a processor (Processor) 1110, a communication interface (Communications Interface) 1120, a memory (Memory) 1130 and a communication bus 1140, wherein the processor 1110, the communication interface 1120, and the memory 1130 communicate with each other via the communication bus 1140. The processor 1110 can call the logic instructions in the memory 1130 to execute the method in the above embodiment.

[0153] In addition, the logic instructions in the aforementioned memory 1130 can be implemented in the form of a software functional unit and, when sold or used as an independent product, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the portion that contributes to the prior art, or the portion of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application.

[0154] Based on the method in the above embodiment, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program runs on a processor, the processor executes the method in the above embodiment.

[0155] Based on the method in the above embodiment, an embodiment of the present application provides a computer program product. When the computer program product runs on a processor, the processor executes the method in the above embodiment.

[0156] It is understood that the processor in the embodiments of the present application may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA), other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. The general-purpose processor may be a microprocessor or any conventional processor.

[0157] The method steps in the embodiments of the present application can be implemented by hardware or by a processor executing software instructions. The software instructions can be composed of corresponding software modules, which can be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, mobile hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be an integral part of the processor. The processor and storage medium can be located in an ASIC.

[0158] The above embodiments can be implemented in whole or in part using software, hardware, firmware, or any combination thereof. When implemented using software, they can be implemented in whole or in part in the form of a computer program product. The computer program product comprises one or more computer instructions. When loaded and executed on a computer, the computer program instructions fully or partially produce the processes or functions described in the embodiments of this application. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted via the computer-readable storage medium. The computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible by a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium can be magnetic media (e.g., floppy disk, hard disk, tape), optical media (e.g., DVD), or semiconductor media (e.g., solid-state drive (SSD)).

[0159] It will be understood that the various numerical numbers involved in the embodiments of the present application are merely distinctions for the convenience of description and are not intended to limit the scope of the embodiments of the present application.

[0160] It is easy for those skilled in the art to understand that the above is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A method for identifying on-resistance of a gallium nitride transistor, characterized in that: include: Acquiring multiple target electrical parameter information of the physical model of the buck converter at each sampling moment; The buck converter is an electronic device in which the GaN transistor to be tested is located; Determining, based on a plurality of target electrical parameter information of the physical model at each sampling moment, an inductor current and a load voltage outputted by a mathematical model of the buck converter corresponding to the inductor current and the load voltage; wherein the mathematical model of the buck converter is obtained by discretely modeling the buck converter; With the goal of minimizing the deviation between the output voltages corresponding to the mathematical model and the physical model at all sampling moments, the on-resistance of the gallium nitride transistor output by the mathematical model is iteratively solved based on the inductor current and load voltage corresponding to the output of the mathematical model to obtain the on-resistance of the gallium nitride transistor to be tested; Before determining the inductor current and load voltage outputted by the mathematical model of the buck converter corresponding to the plurality of target electrical parameter information of the physical model at each sampling moment, the method further comprises: Determining a target state-space transfer function of an equivalent circuit of the buck converter using an inductor current and a capacitor voltage within the buck converter as state variables; Performing discrete modeling of the buck converter based on the target state-space transfer function using the Runge-Kutta method to determine a mathematical model of the buck converter; The method of minimizing the deviation between the output voltages corresponding to the mathematical model and the physical model at all sampling moments, iteratively solving the on-resistance of the gallium nitride transistor output by the mathematical model based on the inductor current and load voltage corresponding to the output of the mathematical model, and obtaining the on-resistance of the gallium nitride transistor to be tested, includes: Determining a first output voltage deviation based on the mathematical model and the gallium nitride transistor voltage output by the physical model at each sampling moment, and determining a second output voltage deviation based on the mathematical model and the load voltage output by the physical model at each sampling moment; determining a target fitness function of a particle swarm optimization algorithm based on the first output voltage deviation and the second output voltage deviation; With the goal of minimizing the fitness value of the target fitness function, the inductor current and load voltage corresponding to the output of the mathematical model are input into the particle swarm optimization algorithm, and the on-resistance of the gallium nitride transistor output by the mathematical model is iteratively solved to obtain the on-resistance of the gallium nitride transistor to be tested.

2. The gallium nitride transistor on-resistance identification method according to claim 1, characterized in that: The method aims to minimize the fitness value of the target fitness function, inputs the inductor current and the load voltage corresponding to the output of the mathematical model into the particle swarm optimization algorithm, iteratively solves the on-resistance of the gallium nitride transistor output by the mathematical model, and obtains the on-resistance of the gallium nitride transistor to be tested, including: Step S101: initializing each particle of the particle swarm optimization algorithm, the local optimal position of each particle, and the current global optimal particle based on a preset value range of the on-resistance of the gallium nitride transistor to be tested; Step S102: Substituting the GaN transistor voltage and load voltage output by the physical model at each sampling moment, the inductor current and load voltage output by the mathematical model, and the on-resistance corresponding to each particle into the target fitness function to determine the fitness value of each particle; Step S103, with the goal of minimizing the fitness value, updating the local optimal position of each particle and the global optimal particle in the current iteration process; Step S104, determining whether the current number of iterations has reached the maximum number of iterations or whether the fitness value of the current global optimal particle has converged; if not, updating the position and velocity of each particle and jumping to step S102; if so, executing step S105; Step S105 : obtaining a global optimal particle of a particle swarm optimization algorithm, and determining the on-resistance of the gallium nitride transistor to be tested based on the global optimal particle.

3. The gallium nitride transistor on-resistance identification method according to claim 2, characterized in that: Before updating the position and velocity of each particle and jumping to step S102, the method further includes: The current inertia weight of the particle swarm optimization algorithm is updated using the current number of iterations, the maximum number of iterations, the initial inertia weight of the algorithm, and the inertia weight corresponding to the maximum number of iterations.

4. The gallium nitride transistor on-resistance identification method according to any one of claims 1 to 3, characterized in that: The step of determining a target state-space transfer function of an equivalent circuit of the buck converter using an inductor current and a capacitor voltage in the buck converter as state variables includes: Determine a first state-space transfer function of the equivalent circuit when the gallium nitride transistor to be tested is in an on state, using the inductor current and the capacitor voltage in the buck converter as state variables; Determine a second state-space transfer function of the equivalent circuit when the gallium nitride transistor to be tested is in an off state, using the inductor current and the capacitor voltage in the buck converter as state variables; The first state-space transfer function and the second state-space transfer function are fused to determine a target state-space transfer function of the equivalent circuit.

5. The gallium nitride transistor on-resistance identification method according to any one of claims 1 to 3, characterized in that: The equivalent circuit of the buck converter includes a first equivalent resistor and an equivalent constant voltage source corresponding to the freewheeling diode, a second equivalent resistor and an equivalent switch corresponding to the gallium nitride transistor to be tested, a DC voltage source, an energy storage inductor, a first parasitic resistor of the energy storage inductor, a filter capacitor, a second parasitic resistor of the filter capacitor, and a load resistor; The positive electrode of the DC voltage source is connected to one end of the second equivalent resistor, the other end of the second equivalent resistor is connected to one end of the equivalent switch, and the other end of the equivalent switch, one end of the first parasitic resistor, and one end of the first equivalent resistor are connected in common; The other end of the first equivalent resistor is connected to the negative electrode of the equivalent constant voltage source, the other end of the first parasitic resistor is connected to one end of the energy storage inductor, and the other end of the energy storage inductor, one end of the load resistor and the positive electrode of the filter capacitor are connected in common; The negative electrode of the filter capacitor is connected to one end of the second parasitic resistor, and the negative electrode of the DC voltage source, the positive electrode of the equivalent constant voltage source, the other end of the second parasitic resistor and the other end of the load resistor are connected in common.

6. A device for identifying on-resistance of a gallium nitride transistor, characterized in that: include: An acquisition module, configured to acquire information of a plurality of target electrical parameters of a physical model of a buck converter at each sampling moment; The buck converter is an electronic device in which the GaN transistor to be tested is located; a processing module, configured to determine, based on a plurality of target electrical parameter information of the physical model at each sampling moment, an inductor current and a load voltage outputted by a mathematical model of the buck converter corresponding to the inductor current and the load voltage; the mathematical model of the buck converter being obtained by discretely modeling the buck converter; an identification module, configured to iteratively solve the on-resistance of the gallium nitride transistor output by the mathematical model based on the inductor current and load voltage output by the mathematical model, with the goal of minimizing the deviation between the output voltages corresponding to the mathematical model and the physical model at all sampling moments, to obtain the on-resistance of the gallium nitride transistor to be tested; Wherein, the device is used for: Determining a target state-space transfer function of an equivalent circuit of the buck converter using an inductor current and a capacitor voltage within the buck converter as state variables; Performing discrete modeling of the buck converter based on the target state-space transfer function using the Runge-Kutta method to determine a mathematical model of the buck converter; The identification module is specifically used for: Determining a first output voltage deviation based on the mathematical model and the gallium nitride transistor voltage output by the physical model at each sampling moment, and determining a second output voltage deviation based on the mathematical model and the load voltage output by the physical model at each sampling moment; determining a target fitness function of a particle swarm optimization algorithm based on the first output voltage deviation and the second output voltage deviation; With the goal of minimizing the fitness value of the target fitness function, the inductor current and load voltage corresponding to the output of the mathematical model are input into the particle swarm optimization algorithm, and the on-resistance of the gallium nitride transistor output by the mathematical model is iteratively solved to obtain the on-resistance of the gallium nitride transistor to be tested.

7. An electronic device, characterized in that: include: at least one memory for storing a computer program; At least one processor is used to execute the program stored in the memory. When the program stored in the memory is executed, the processor is used to execute the method according to any one of claims 1 to 5.

8. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed on a processor, the processor is caused to execute the method according to any one of claims 1 to 5.

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