Transistor-Level Timing Prediction Method and System for Critical Path Standard Cells

Abstract

The present invention discloses a transistor-level timing prediction method and system for critical path standard cells. The method includes the steps of: obtaining the intrinsic characteristics of the standard cell at the transistor level and the state characteristics of the standard cell; performing feature fusion on the intrinsic characteristics of the standard cell at the transistor level and the state characteristics to obtain the timing characteristics of the standard cell; analyzing based on the timing characteristics of the standard cell to predict the timing data of the standard cell at the transistor level; training a timing analysis model based on the timing data of the standard cell at the transistor level to obtain a trained timing analysis model for predicting the predicted standard cell to obtain a timing prediction result. The present invention can efficiently handle the timing prediction problem in ultra-large-scale circuit design, especially for standard cells in undefined libraries; through the automation and optimization of timing prediction, the design cycle is shortened, the consumption of computing resources is reduced, and the timing optimization process is accelerated.

Description

Technical Field

[0001] The present invention mainly relates to the field of integrated circuit technology, and particularly relates to a transistor-level timing prediction method and system for critical path standard cells. Background Art

[0002] With the continuous development of integrated circuit technology, the complexity of standard cells used in chip design has gradually increased. Especially in transistor-level design, how to accurately and efficiently perform timing analysis has become an important challenge in integrated circuit design. Standard cell timing analysis is one of the key technologies in integrated circuit design for evaluating the timing performance of a circuit, and usually involves predicting the timing characteristics of each standard cell in the circuit to ensure that the circuit can operate stably at a predetermined clock frequency.

[0003] Current standard cell timing analysis methods mainly rely on traditional physical modeling and simulation technologies, such as analog simulation based on SPICE models or static timing analysis tools. Although these methods can provide accurate timing analysis results, when faced with ultra-large-scale circuits, due to the huge computational amount, the processing time and resource consumption are often very high, resulting in an extended design cycle and increased development costs. In addition, the accuracy of traditional methods is limited by the accuracy of the model and the setting of simulation parameters, and it is prone to errors when dealing with complex circuit topologies and non-linear effects.

[0004] With the development of machine learning technology, data-driven timing analysis methods have gradually attracted attention. By using a large amount of historical data, machine learning methods can mine circuit timing characteristics from it and make predictions, thus providing a new idea for timing analysis. Especially the emergence of graph neural networks has provided new possibilities for solving the topology dependence problem in transistor-level standard cell timing analysis. By modeling the transistor-level topology of standard cells, graph neural networks can effectively capture the relationships between transistors and combine their key features for timing prediction, with good prediction accuracy and efficiency.

[0005] However, the existing timing analysis methods based on graph neural networks still have certain limitations. For example, in semi-custom ultra-large-scale integrated circuit design, the standard cells in the standard cell library often cannot achieve the best timing effect, so special standard cells need to be customized, such as customized standard cells where the fin numbers of transistors in the pull-up network and the pull-down network are not 1:1. But existing methods often cannot accurately handle special standard cells not defined in the standard cell library, resulting in inaccurate timing prediction results. At the same time, how to quickly extract the intrinsic features and state features of standard cells in complex circuits and perform efficient timing prediction based on these features is still a technical problem to be solved urgently.

[0006] Therefore, how to combine machine learning, especially graph neural networks, to improve the timing analysis accuracy and efficiency of transistor-level standard cells, especially in the face of special standard cells not defined in the standard cell library and complex circuits, remains an important research topic in the field of integrated circuit design. Summary of the Invention

[0007] Aiming at the technical problems existing in the prior art, the present invention provides a transistor-level timing prediction method and system for critical-path standard cells, which can shorten the design cycle, reduce the consumption of computing resources, and accelerate timing optimization.

[0008] The technical solution proposed by the present invention to solve the above technical problems is as follows:

[0009] A transistor-level timing prediction method for critical-path standard cells includes the steps of:

[0010] Obtain the intrinsic characteristics of the standard cell at the transistor level and the state characteristics of the standard cell; wherein the intrinsic characteristics of the standard cell at the transistor level are the attribute characteristics inherent in the standard cell that do not change with the state conditions.

[0011] Fuse the intrinsic characteristics of the standard cell at the transistor level with the state characteristics to obtain the timing characteristics of the standard cell.

[0012] Analyze based on the timing characteristics of the standard cell to predict the timing data of the standard cell at the transistor level.

[0013] Train the timing analysis model based on the timing data of the standard cell at the transistor level to obtain a trained timing analysis model to predict the predicted standard cell and obtain the timing prediction result.

[0014] Preferably, the specific process of obtaining the intrinsic characteristics of the standard cell at the transistor level is as follows:

[0015] Extract the circuit topology information of the standard cell at the transistor level and the key information of the standard cell at the transistor level in the standard cell netlist, and construct the intrinsic characteristics of the standard cell at the transistor level.

[0016] Preferably, the specific process of extracting the circuit topology information of the standard cell at the transistor level and the key information of the standard cell at the transistor level is as follows:

[0017] Extract the circuit topology information of the standard cell at the transistor level from the standard cell netlist, and construct a heterogeneous graph of the standard cell at the transistor level with transistors, input pins, output pins, ground, and power as nodes and the wire nets connecting the nodes as edges; at the same time, extract the corresponding key information of the standard cell at the transistor level in combination with the timing arc information of the standard cell.

[0018] Preferably, the specific process of fusing the intrinsic features and state features at the standard cell transistor level to obtain the timing features of the standard cell is as follows:

[0019] Construct a customized graph neural network based on the difference in the correlation of topological nodes at the standard cell transistor level to achieve feature embedding of the intrinsic features at the standard cell transistor level, and convert the high-dimensional, discrete or structured intrinsic features at the standard cell transistor level into a low-dimensional continuous vector representation;

[0020] Construct a feature embedding network for the state features of the standard cell to achieve the embedding of the state features of the standard cell, and convert the high-dimensional, discrete or structured state features of the standard cell into a low-dimensional continuous vector representation;

[0021] Construct a feature fusion network for the intrinsic features at the transistor level and the state features of the standard cell to achieve the feature fusion of the intrinsic features at the transistor level and the state features of the standard cell, and obtain the timing features of the standard cell.

[0022] Preferably, the specific process of constructing a customized graph neural network based on the difference in the correlation of topological nodes at the standard cell transistor level to achieve feature embedding of the intrinsic features at the standard cell transistor level is as follows:

[0023] Use different graph convolution methods for information transmission between different nodes; specifically, take the transistor node features and the connection edges between transistors, and use the graph attention network for information transmission; take the input pin node and transistor node features and the connection edges between the input pin and transistors, and use the graph convolution network for information transmission; take the transistor node and output pin node features and the connection edges between the transistor and output pins, and use the graph convolution network for information transmission; take the power node and transistor node features and the connection edges between the power and transistors, and use the graph sampling aggregation network for information transmission; take the transistor node and ground node features and the connection edges between the transistor and ground, and use the graph sampling aggregation network for information transmission.

[0024] Preferably, the specific process of training the timing analysis model based on the timing data at the standard cell transistor level to obtain the trained timing analysis model includes:

[0025] Based on the timing data of the standard cells in the existing library, perform data augmentation to obtain an extended training data set;

[0026] Perform supervised learning on the constructed model based on the extended training data set, optimize the parameters of the model through backpropagation, and at the same time introduce regularization techniques during the training process to ensure the generalization ability of the model for unseen data; at the same time, adjust the hyperparameters, select the optimal model configuration, and obtain the trained timing analysis model.

[0027] Preferably, based on the timing data of standard cells in the existing library, the specific process of data augmentation to obtain the extended training dataset is as follows:

[0028] Parse the standard cell library file, and extract the delay lookup table between the input transition time, output load, and delay corresponding to different timing arcs of each standard cell;

[0029] According to the values of the input transition time and output load in the delay lookup table, generate multiple interpolations between every two adjacent values to obtain n×n input transition time and output load interpolations;

[0030] According to the generated interpolations of the input transition time and output load, combine with the interpolation algorithm to generate the corresponding n×n delay results;

[0031] According to the generated interpolations of the input transition time and output load, use SPICE simulation to generate the corresponding n×n cell delay results.

[0032] Preferably, the specific process of obtaining the intrinsic characteristics of the standard cell transistor level is as follows:

[0033] Parse the standard cell netlist, extract the topological relationship between transistors, input pins, output pins, power supply, and ground in the standard cell, and form a heterogeneous graph of different types of nodes;

[0034] Parse the standard cell netlist, extract the information of each transistor; at the same time, parse the standard cell library file and analyze the current process state information, extract the threshold voltage and channel length information of the current transistor; use the information as the initial features of the transistor nodes in the heterogeneous graph;

[0035] Analyze the current timing arc state, extract the input pin, input pin state, other input pin states, monotonic correlation between the input pin and the output pin, whether the input pin is rising edge or falling edge, whether the output pin is rising edge or falling edge, the state of the output pin, and the input transition time and output load in the current state to obtain the state information;

[0036] According to the state information, initialize the node features of the input pin and the output pin;

[0037] Parse the standard cell library file and analyze the process corner state information of the current standard cell to obtain the voltage value, initialize the feature of the power supply node to the voltage value, and at the same time initialize the feature of the ground node to 0.

[0038] Preferably, the specific process of obtaining the state characteristics of the standard cell is as follows:

[0039] Parse the standard cell library file and extract process information as the status features of the current standard cell; the process information includes process corners, temperature, the height of the standard cell, and the area of the standard cell.

[0040] Perform feature normalization on the status features of the standard cell to obtain the final status features.

[0041] The present invention also discloses a transistor-level timing prediction system for critical path standard cells, including a memory and a processor connected to each other. A computer program is stored on the memory, and when the computer program is run by the processor, it executes the steps of the method described above.

[0042] Compared with the prior art, the advantages of the present invention are as follows:

[0043] The transistor-level timing prediction method for critical path standard cells of the present invention first extracts transistor-level circuit topology information from the standard cell netlist, constructs a transistor-level heterogeneous graph, and extracts key information in combination with timing arc information; secondly, constructs a customized graph neural network model based on the extracted transistor-level features; at the same time, analyzes process information to extract standard cell status features and constructs a status feature embedding network; subsequently, obtains the timing prediction result through feature fusion and a timing prediction network. This method can efficiently handle timing prediction problems in ultra-large-scale circuit designs, especially for standard cells in undefined libraries; through the automation and optimization of timing prediction, the design cycle is shortened, the consumption of computing resources is reduced, and the timing optimization and ECO processes are accelerated. Compared with traditional timing analysis methods, the present invention has obvious advantages in terms of efficiency and adaptability and has good industrial application prospects.

[0044] The transistor-level timing prediction method for critical path standard cells of the present invention has the following advantages:

[0045] 1. Accelerate the timing ECO process: Utilizing the efficient inference ability of the graph neural network model, the present invention can quickly perform timing prediction of standard cells in ultra-large-scale circuit designs. For standard cells not defined in the standard cell library, the present invention can also perform timing prediction, thereby guiding and accelerating the timing ECO (Engineering Change Order) process, reducing the time and computing resources required for manual adjustment and simulation.

[0046] 2. Reduce the consumption of computing resources: Through the timing prediction method based on the graph neural network, compared with traditional simulation methods (such as SPICE simulation) that require a large amount of physical model calculations, the present invention can complete timing prediction in a shorter time with fewer computing resources. This not only improves the efficiency of timing analysis but also reduces the demand for hardware resources and the computing burden of the system.

[0047] 3. Easy to expand and apply: The timing analysis method of the present invention is based on a data-driven machine learning model and has strong scalability in practical applications. With the accumulation of more training data, the timing prediction accuracy of the model can be continuously improved. In addition, the present invention can be compatible with existing integrated circuit design toolchains and is easy to integrate into the existing electronic design automation (EDA) environment, having good industrial application prospects.

[0048] In summary, the present invention shows obvious advantages over the prior art in terms of timing prediction accuracy, efficiency, generalization ability, and computational resource consumption, and has important practical application value. Brief Description of the Drawings

[0049] Figure 1 It is a flowchart of the transistor-level timing prediction method of the present invention in an embodiment.

[0050] Figure 2 It is a framework diagram of the transistor-level standard cell timing analysis model based on graph neural network of the present invention.

[0051] Figure 3 It is a diagram of the information transfer process of a transistor node in the heterogeneous graph neural network of the present invention. Detailed Embodiments

[0052] The present invention will be further described below in conjunction with the accompanying drawings of the specification and specific embodiments.

[0053] As Figure 1 shown, the transistor-level timing prediction method for critical path standard cells provided by the embodiment of the present invention includes the following steps:

[0054] S1. Extract the transistor-level circuit topology information of the standard cell from the standard cell netlist, and construct a standard cell transistor-level heterogeneous graph with transistors, input pins, output pins, ground, and power supply as nodes and the wire network connecting the nodes as edges; at the same time, extract the corresponding standard cell transistor-level key information in combination with the standard cell timing arc information;

[0055] According to the extracted standard cell transistor-level heterogeneous graph and key information, construct the standard cell transistor-level intrinsic features as the input data of the customized graph neural network model; where the definition of the standard cell transistor-level intrinsic features is: the attribute features (such as the connection relationship of transistors in the standard cell, the transistor width-to-length ratio, etc.) that are inherent in the standard cell and do not change with state conditions (such as voltage, temperature, etc.);

[0056] S2. Extract the state features of the standard cell according to the process information of the standard cell to provide more dimensional data support for subsequent timing analysis;

[0057] S3. Construct a customized graph neural network based on the correlation differentiation of the transistor-level topology nodes of standard cells to achieve feature embedding of the intrinsic features of standard cells at the transistor level, and convert high-dimensional, discrete, or structured data into low-dimensional continuous vector representations for subsequent processing by machine learning models;

[0058] S4. Construct a feature embedding network for the state features of standard cells to achieve the embedding of the state features of standard cells, and convert high-dimensional, discrete, or structured data into low-dimensional continuous vector representations for subsequent processing by machine learning models; among them, new state features are added to enhance the accuracy and adaptability of timing prediction; specifically, the feature embedding network includes a multi-layer perceptron with two hidden layers, and Relu is used as the activation function;

[0059] S5. Construct a feature fusion network for the transistor-level intrinsic features and the standard cell state features to achieve the feature fusion of the transistor-level intrinsic features and the standard cell state features, and obtain the timing features of standard cells; specifically, in the feature fusion network, construct a tensor splicing layer, followed by a Batchnormal layer to ensure the generalization ability of the network model;

[0060] S6. Construct a timing prediction network, based on the timing features obtained by the feature fusion network, process the complex non-linear relationships in the standard cell timing analysis, and predict the timing results of the standard cell at the transistor level. Specifically, the timing prediction network includes a multi-layer perceptron with two hidden layers, and Relu is used as the activation function;

[0061] S7. Based on the timing data of standard cells in the existing library, perform data augmentation to expand the training data set to improve the accuracy of timing prediction;

[0062] S8. Perform supervised learning on the constructed model based on the extended training data, optimize the parameters of the model through backpropagation, and at the same time introduce appropriate regularization techniques during the training process to ensure the generalization ability of the model for unseen data; at the same time, adjust the hyperparameters, select the optimal model configuration, and obtain the trained timing analysis model;

[0063] S9. According to steps S1 and S2, extract the features of the standard cell to be predicted to obtain the transistor-level intrinsic features and state features;

[0064] S10. Input the extracted transistor-level intrinsic features and state features into the trained timing analysis model to predict the timing analysis results.

[0065] The transistor-level timing prediction method for critical path standard cells of the present invention first extracts transistor-level circuit topology information from the standard cell netlist, constructs a transistor-level heterogeneous graph, and extracts key information in combination with timing arc information; secondly, constructs a customized graph neural network model based on the extracted transistor-level features; at the same time, analyzes process information to extract standard cell state features, and constructs a state feature embedding network; subsequently, obtains a timing prediction result through feature fusion and a timing prediction network. This method can efficiently handle timing prediction problems in ultra-large-scale circuit designs, especially standard cells in undefined libraries; through the automation and optimization of timing prediction, the design cycle is shortened, the consumption of computing resources is reduced, and the timing optimization and ECO processes are accelerated. Compared with traditional timing analysis methods, the present invention has obvious advantages in terms of efficiency and adaptability, and has good industrial application prospects.

[0066] In a specific embodiment, step S1 includes:

[0067] S101. Parse the standard cell netlist, extract the topological relationships among transistors, input pins, output pins, power supply, and ground in the standard cell, and form a heterogeneous graph including four different types of nodes;

[0068] S102. Parse the standard cell netlist, extract information of each transistor, such as transistor type, width-to-length ratio of the transistor, number of gates of the transistor, etc.; at the same time, parse the standard cell library file and analyze the current process state information, and extract information such as the threshold voltage and channel length of the current transistor; use the above information as the initial features of the transistor nodes in the heterogeneous graph;

[0069] S103. Analyze the current timing arc state, extract the input pin, input pin state, other input pin states, monotonic correlation between the input pin and the output pin, whether the input pin is rising edge or falling edge, whether the output pin is rising edge or falling edge, the state of the output pin, and the input transition time and output load in the current state to obtain state information;

[0070] S104. According to the state information, initialize the input pin and output pin node features according to the following rules; among them, one-hot encoding is used for each label.

[0071] When initializing the input pin features, it specifically includes the following labels 1-4 and the input transition time:

[0072] Label 1: Mark whether the current timing arc is from this pin to the output pin, and there are two states: (1) Yes, (2) No.

[0073] Marker 2: Mark the monotonic correlation between this pin and the output pin, with four states: (1) positive monotonic correlation, (2) negative monotonic correlation, (3) non-monotonic correlation, (4) input pin of non-current timing arc, and the monotonic correlation between this pin and the output pin is not concerned.

[0074] Marker 3: Mark whether this pin is a rising edge or a falling edge, with three states: (1) rising edge, (2) falling edge, (3) input pin of non-current timing arc, and whether this pin is a rising edge or a falling edge is not concerned.

[0075] Marker 4: Mark the state of this pin, with three states: (1) low level, (2) high level, (3) its state does not affect the current timing arc.

[0076] Input transition time: The input transition time under the current timing arc, with two cases: (1) If it is the input pin of the current timing arc, it is set to the input transition time under the current timing arc; (2) If it is the input pin of non-current timing arc, it is set to 0.

[0077] When initializing the output pin characteristics, it specifically includes the following Marker 5-6 and output load:

[0078] Marker 5: Mark whether the output pin is a rising edge or a falling edge, with two states: (1) rising edge, (2) falling edge.

[0079] Marker 6: Mark the state of the output pin, with two states: (1) low level, (2) high level.

[0080] Output load: The output load value under the current timing arc.

[0081] S105. Parse the standard cell library file and analyze the process corner status information of the current standard cell to obtain the voltage value, initialize the characteristics of the power supply node to the voltage value, and at the same time initialize the characteristics of the ground node to 0.

[0082] In the above process, the intrinsic characteristics of the standard cell at the transistor level not only include the physical parameters of the transistor (such as type, width-to-length ratio, number of gates, etc.), but also include the characteristics of the power supply and ground signals of the circuit. In digital circuit design, the voltage values of the power supply and ground are key factors affecting the logic state and timing of the circuit. Therefore, initializing the characteristics of the power supply node to the voltage value and initializing the characteristics of the ground node to 0 can ensure that the power supply situation of the actual circuit can be accurately reflected during circuit simulation.

[0083] In a specific embodiment, step S2 includes:

[0084] S201. Parse the standard cell library file and extract process information, such as process corner, temperature, height of the standard cell, area of the standard cell, etc., as the status characteristics of the current standard cell;

[0085] S202. Perform feature normalization on the state features of the standard cells to improve the model performance.

[0086] In a specific embodiment, step S3 includes:

[0087] Adopt different graph convolution methods between different nodes to perform information transmission more efficiently and reasonably. Specifically, take the transistor node features and the connection edges between transistors, and use the graph attention network for information transmission; take the input pin node and transistor node features and the connection edges between the input pins and transistors, and use the graph convolution network for information transmission; take the transistor node and output pin node features and the connection edges between the transistors and output pins, and use the graph convolution network for information transmission; take the power node and transistor node features and the connection edges between the power supply and transistors, and use the graph sampling aggregation network for information transmission; take the transistor node and ground node features and the connection edges between the transistors and ground, and use the graph sampling aggregation network for information transmission.

[0088] In a specific embodiment, step S7 includes:

[0089] S701. Parse the standard cell library file, and extract the 8×8 delay lookup table of the input transition time, output load, and delay corresponding to different timing arcs of each standard cell;

[0090] S702. According to the values of the input transition time and output load in the delay lookup table, generate 100 interpolations between every two adjacent values to obtain 700×700 input transition time and output load interpolations;

[0091] S703. According to the generated interpolations of the input transition time and output load, and in combination with the interpolation algorithm, generate the corresponding 700×700 unit delay results;

[0092] S704. According to the generated interpolations of the input transition time and output load, use SPICE simulation to generate the corresponding 700×700 unit delay results.

[0093] Specifically, the delay results generated by the interpolation algorithm in step S703 are an estimate based on the original data, while the unit delay results generated by SPICE simulation in S704 are closer to the actual behavior of the circuit. In timing prediction, the data generated by these two methods can provide different information: the interpolation results can be used for quick estimation and prediction, while the simulation results can be used for accurate circuit analysis and verification. By combining these two methods, the model can be trained more comprehensively to improve its prediction accuracy.

[0094] In a specific embodiment, step S8 includes:

[0095] Process the training data according to steps S1 and S2 of feature engineering to provide high-quality input data for model training;

[0096] Pass the input data to each network layer of the model through forward propagation and output the timing prediction results of standard cells;

[0097] Calculate the mean square error between the prediction result and the actual delay as the loss function;

[0098] Adopt the backpropagation algorithm to optimize the weights and parameters of the model. By calculating the gradients of the loss function with respect to the parameters of each layer and using the Adam optimizer to update the weights of the network;

[0099] During the training process, the L2 regularization and Dropout methods are introduced to enhance the generalization ability of the model and avoid overfitting. By adding the sum of the squares of the weights to the loss function, the excessive values of the model parameters are restricted, thus avoiding the model from relying too much on the noise in the training data. At the same time, randomly "discard" a part of the neurons in each training step, forcing the model to pay more attention to the global features during training rather than relying only on specific neuron paths.

[0100] Through adjusting hyperparameters such as the learning rate, regularization strength, number of network layers, etc., perform multiple model trainings and select the optimal model configuration.

[0101] The transistor-level timing prediction method for critical-path standard cells of the present invention has the following advantages:

[0102] 1. Accelerate the timing ECO process: Utilizing the efficient inference ability of the graph neural network model, the present invention can quickly perform timing prediction of standard cells in ultra-large-scale circuit design. For standard cells not defined in the standard cell library, the present invention can also perform timing prediction, thereby guiding and accelerating the timing ECO (Engineering Change Order) process, reducing the time and computing resources required for manual adjustment and simulation.

[0103] 2. Reduce the consumption of computing resources: Through the timing prediction method based on the graph neural network, compared with traditional simulation methods (such as SPICE simulation) that require a large amount of physical model calculations, the present invention can complete timing prediction in a shorter time with fewer computing resources. This not only improves the efficiency of timing analysis but also reduces the demand for hardware resources and the computing burden on the system.

[0104] 3. Easy to expand and apply: The timing analysis method of the present invention is based on a data-driven machine learning model and has strong scalability in practical applications. With the accumulation of more training data, the timing prediction accuracy of the model can be continuously improved. In addition, the present invention can be compatible with existing integrated circuit design toolchains and is easy to integrate into the existing electronic design automation (EDA) environment, having good industrial application prospects.

[0105] In summary, the present invention shows obvious advantages over the prior art in terms of timing prediction accuracy, efficiency, generalization ability, and computational resource consumption, and has important practical application value.

[0106] To better understand the above technical solutions, the above technical solutions will be described in detail below in conjunction with the accompanying drawings of the specification and specific implementation manners.

[0107] As Figure 2 shown, in the corresponding prediction model framework, the left side is the input of the model ( Figure 2 the standard cell library file and netlist in ), the upper left corner is the transistor-level heterogeneous graph and standard cell intrinsic feature embedding module extracted (where A1 and A2 in the transistor-level heterogeneous graph are input pins, P1 and P2 are PMOS transistors, and N1 and N2 are NMOS transistors), the lower left corner MLP network is the state feature embedding module of the standard cell, and the right side MLP network is the fusion network and output module of the standard cell state feature and transistor-level intrinsic feature.

[0108] The transistor-level timing prediction method for critical path standard cells provided by the present invention specifically includes the following steps:

[0109] Feature engineering:

[0110] S1. Extract the transistor-level circuit topology information of the standard cell from the standard cell netlist, and construct a standard cell transistor-level heterogeneous graph with transistors, input pins, output pins, ground, and power as nodes and the wire networks connecting the nodes as edges; at the same time, extract the corresponding standard cell transistor-level key information in combination with the standard cell timing arc information; the specific steps are as follows:

[0111] S101. In this embodiment, parsing the standard cell netlist is carried out using a written python script, which can efficiently and accurately extract the unit transistor-level circuit topology information, and use the HeteroData class in the torch_geometric library of python to construct a heterogeneous graph data structure containing 5 types of nodes: transistors, input pins, output pins, power supply, and ground.

[0112] S102. The standard cell library file is parsed using a written Python script, or the Liberty library of Python can also be used for parsing, which can achieve high efficiency and speed. The extracted transistor information and process status information, namely whether the transistor is a Pmos transistor or an Nmos transistor, the number of transistor gates, the number of fins of the transistor, the channel length of the transistor, and the threshold voltage of the transistor, are used as the initialization features of the transistor node.

[0113] S103 - S104. The current timing arc state is analyzed using a written Python script, which can quickly initialize the node features of the input and output pins according to the corresponding rules, and one - hot encoding is used for each marker.

[0114] S105. The standard cell library file is parsed using a written Python script, and the voltage value under the process corner state of the current standard cell is used as the initialization feature value of the power supply node, and the feature of the ground node is initialized to 0.

[0115] S2. Extract the state features of the standard cell according to the process information of the standard cell to provide more - dimensional data support for subsequent timing analysis; specifically:

[0116] S201. The standard cell library file is parsed using a written Python script, and the process corner, temperature, height of the standard cell, and area of the standard cell are used as the state features of the current standard cell, and the process corner information is encoded using one - hot encoding.

[0117] S202. The MinMaxScaler function in the scikit - learn library of Python is used to perform normalization operations on the data.

[0118] Model construction:

[0119] S3. Construct a customized graph neural network based on the difference in the relevance of the transistor - level topology nodes of the standard cell to achieve feature embedding of the intrinsic features of the standard cell at the transistor level, and convert high - dimensional, discrete or structured data into low - dimensional continuous vector representations for subsequent processing by machine learning models;

[0120] As Figure 3 shown, in step S3, a customized heterogeneous graph neural network is constructed based on the torch_geometric library of Python. Among them Figure 3 describes the information transfer process of a PMOS transistor node P2 in the heterogeneous graph neural network, where A1, A2, and A3 are input pins, P1 is a PMOS transistor, and M1 and M2 are NMOS transistors.

[0121] Specifically, take the transistor node features and the connection edges between transistors, and use GATconv in the torch_geometric library to construct a network layer for convolutional calculation. As shown in the left figure of Figure 3 , it describes the information transfer between transistor P2 and other transistors, and its feature representation obtains a new representation through network convolutional calculation. .

[0122] Take the input pin node, transistor node features, and the connection edges between the input pin and the transistor, and use GCNconv in the torch_geometric library to construct a network layer for convolutional calculation. As shown in the right figure of Figure 3 , it describes the information transfer between transistor P2 and the input pin, and its feature representation obtains a new representation through network convolutional calculation. .

[0123] Take the transistor node, output pin node features, and the connection edges between the transistor and the output pin, and use GCNconv in the torch_geometric library to construct a network layer for convolutional calculation. As shown in the middle ellipsis part of Figure 3 , it describes the information transfer between transistor P2 and the output pin, and its feature representation obtains a new representation through network convolutional calculation. .

[0124] Take the power supply node, transistor node features, and the connection edges between the power supply and the transistor, and use SAGEconv in the torch_geometric library to construct a network layer for convolutional calculation. As shown in the middle ellipsis part of Figure 3 , it describes the information transfer between transistor P2 and the power supply node, and its feature representation obtains a new representation through network convolutional calculation. .

[0125] Take the transistor node, ground node features, and the connection edges between the transistor and the ground, and use SAGEconv in the torch_geometric library to construct a network layer for convolutional calculation. As shown in the middle ellipsis part of Figure 3 , it describes the information transfer between transistor P2 and the ground node, and its feature representation obtains a new representation through network convolutional calculation. .

[0126] After each graph convolution, calculate the feature representation of the node to obtain a new node feature representation. As shown in the lower part of the feature transfer part of Figure 3 , a new feature representation of transistor P2 node is obtained. .

[0127] S4. Construct a feature embedding network for the standard cell state features to embed the standard cell state features, convert high-dimensional, discrete or structured data into low-dimensional continuous vector representations for subsequent processing by machine learning models; where new state features are added to enhance the accuracy and adaptability of time series prediction;

[0128] Specifically, in step S4, use the torch library in Python to construct three fully connected layers. The first two layers use Relu as the activation function, and the third layer directly outputs a tensor.

[0129] S5. Construct a feature fusion network for the transistor-level intrinsic features and the standard cell state features to achieve the feature fusion of the transistor-level intrinsic features and the standard cell state features, and obtain the standard cell time series features;

[0130] Specifically, in step S5, use the global_mean_pool function in the torch_geometric library in Python to perform global average pooling on the output of the heterogeneous graph neural network. Subsequently, use the cat function in the torch library in Python to concatenate the pooled features with the features output by S4 to obtain the time series feature representation, and then connect a Batchnormal layer after it.

[0131] S6. Construct a time series prediction network to process the complex non-linear relationships in the standard cell time series analysis based on the time series features obtained from the feature fusion network, and predict the time series results at the transistor level of the standard cell.

[0132] Specifically, in step S6, use the torch library in Python to construct three fully connected layers, all using Relu as the activation function, and the third layer outputs the prediction result.

[0133] Model training:

[0134] S7. Based on the time series data of the standard cells in the existing library, perform data augmentation to expand the training data set to improve the accuracy of time series prediction. Specifically:

[0135] S701. Use a script written in Python to parse the standard cell library file and extract the 8×8 delay lookup table of the input transition time, output load, and delay corresponding to different timing arcs of each standard cell.

[0136] S702. Use a script written in Python to generate 100 interpolations between every two adjacent values according to the input transition time and output load values in the delay lookup table, obtaining 700×700 input transition time and output load interpolations.

[0137] S703. The script written in Python generates the unit delay results corresponding to 700×700 by interpolating the generated input transition time and output load and combining the interpolation algorithm.

[0138] S704. Write a tcl script to generate the unit delay results corresponding to 700×700 by interpolating the generated input transition time and output load and using SPICE simulation.

[0139] S8. Perform supervised learning on the constructed model based on the extended training data, optimize the parameters of the model through backpropagation, and introduce appropriate regularization techniques during the training process to ensure the generalization ability of the model for unseen data; at the same time, adjust the hyperparameters, select the optimal model configuration, and obtain the trained timing analysis model.

[0140] Specifically, in step S8, use Python to combine the state features of standard cells and heterogeneous graphs to construct a new data structure and load it into the Dataloader written in the Dataloader of the torch_geometric library based on Python; load the constructed timing prediction model, use mode.train() to set the model training mode, and obtain the timing prediction results of standard cells output by the model; use MSEloss in the torch library of Python as the loss function; use loss.backward() in Python for backpropagation to optimize the model weights and parameters, and use the Adam optimizer to update the network weights; implement L2 regularization by directly passing the weight_decay parameter of the Adam optimizer to the optimizer. At the same time, add a dropout layer in the torch library before the last fully connected layer of the model to avoid the model relying too much on the noise in the training data and strengthen the generalization ability of the model; finally, set the hyperparameters of the model to a learning rate of 0.0001, a regularization strength of 0.01, and two layers for the multi-layer perceptron.

[0141] Model prediction:

[0142] S9. Extract the features of the standard cell to be predicted according to steps S1 and S2 to obtain the transistor-level intrinsic features and state features. Specifically, use the written Python script for feature extraction and construct a data structure to load it into the Dataloader.

[0143] S10. Input the extracted transistor-level intrinsic features and state features into the trained timing analysis model to predict the timing analysis results. Specifically, load the optimal model, set the model to the test mode through model.test(), do not enable the dropout layer, input the data in the Dataloader, and obtain the timing prediction results.

[0144] An embodiment of the present invention further discloses a transistor-level timing prediction system for critical path standard cells, including a memory and a processor connected to each other. A computer program is stored on the memory, and when the computer program is run by the processor, it executes the steps of the method described above. The prediction system of the present invention corresponds to the above prediction method and has the same advantages as those of the above prediction method.

[0145] The present invention can also implement all or part of the processes in the above embodiment method through hardware related to computer program instructions. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, it can implement the steps of the above method embodiment. Among them, the computer program includes computer program code, and the computer program code can be in the form of source code, object code, executable file or some intermediate form, etc. The computer-readable storage medium includes: any entity or device that can carry computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disc, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electrical carrier signal, telecommunication signal, and software distribution medium, etc. The memory is used to store computer programs and / or modules. The processor realizes various functions by running or executing the computer programs and / or modules stored in the memory and calling the data stored in the memory. The memory can include high-speed random access memory and can also include non-volatile memory, such as hard disk, memory, plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, at least one magnetic disk storage device, flash device, or other volatile solid-state storage devices, etc.

[0146] The above is only the preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions within the idea of the present invention belong to the protection scope of the present invention. It should be noted that for those of ordinary skill in the art, several improvements and refinements made without departing from the principle of the present invention should be regarded as within the protection scope of the present invention.

Claims

1. A transistor-level timing prediction method for critical path standard cells, characterized in that: Includes steps: Acquire the standard cell transistor-level intrinsic characteristics and the state characteristics of the standard cell; wherein the standard cell transistor-level intrinsic characteristics are the property characteristics inherent in the standard cell that do not change with the state conditions; The standard cell transistor-level intrinsic features and state features are fused to obtain the standard cell timing features; Analyze the timing characteristics of the standard cell to predict the timing results of the standard cell transistor level; specifically, train the timing analysis model based on the timing data of the standard cell transistor level to obtain the trained timing analysis model to predict the standard cell to be predicted, and obtain the timing prediction results; The specific process of training the timing analysis model based on the timing data of the standard unit transistor level to obtain the trained timing analysis model includes: Based on the timing data of standard cells in the existing library, data amplification is performed to obtain an expanded training data set; Based on the expanded training data set, the constructed model is subjected to supervised learning, and the model parameters are optimized through back propagation. At the same time, regularization technology is introduced in the training process to ensure the generalization ability of the model to unseen data. At the same time, the hyperparameters are adjusted and the optimal model configuration is selected to obtain a trained time series analysis model.

2. The transistor-level timing prediction method for critical path standard cells according to claim 1, characterized in that: The specific process of obtaining the intrinsic characteristics of the standard cell transistor level is: The circuit topology information of the standard cell transistor level and the key information of the standard cell transistor level in the standard cell netlist are extracted to construct the intrinsic features of the standard cell transistor level.

3. The transistor-level timing prediction method for critical path standard cells according to claim 2, characterized in that: The specific process of extracting the standard cell transistor-level circuit topology information and the standard cell transistor-level key information in the standard cell netlist is as follows: The standard cell transistor-level circuit topology information is extracted from the standard cell netlist, and a standard cell transistor-level heterogeneous graph is constructed with transistors, input pins, output pins, ground and power supply as nodes and wire nets connecting the nodes as edges; at the same time, the corresponding standard cell transistor-level key information is extracted in combination with the standard cell timing arc information.

4. The transistor-level timing prediction method for critical path standard cells according to claim 1, 2 or 3, characterized in that: The specific process of fusing the standard cell transistor-level intrinsic features with the state features to obtain the standard cell timing features is as follows: Construct a customized graph neural network based on the differentiation of topological node correlation at the standard unit transistor level, realize feature embedding of standard unit transistor level intrinsic features, and convert high-dimensional, discrete or structured standard unit transistor level intrinsic features into low-dimensional continuous vector representation; Construct a feature embedding network of standard cell state features to embed the standard cell state features and convert high-dimensional, discrete or structured standard cell state features into low-dimensional continuous vector representations; A feature fusion network of transistor-level intrinsic features and standard cell state features is constructed to achieve feature fusion of transistor-level intrinsic features and standard cell state features to obtain standard cell timing features.

5. The transistor-level timing prediction method for critical path standard cells according to claim 4, characterized in that: The specific process of building a customized graph neural network based on the differentiation of topological node correlation at the standard unit transistor level and realizing feature embedding of the intrinsic features at the standard unit transistor level is as follows: Different graph convolution methods are used to transfer information between different nodes; specifically, the transistor node features and the connection edges between transistors are taken, and a graph attention network is used for information transfer; the input pin node and the transistor node features and the connection edges between the input pin and the transistor are taken, and a graph convolution network is used for information transfer; the transistor node and the output pin node features and the connection edges between the transistor and the output pin are taken, and a graph convolution network is used for information transfer; the power node and the transistor node features and the connection edges between the power supply and the transistor are taken, and a graph sampling aggregation network is used for information transfer; the transistor node and the ground node features and the connection edges between the transistor and the ground are taken, and a graph sampling aggregation network is used for information transfer.

6. The transistor-level timing prediction method for critical path standard cells according to claim 1, characterized in that: Based on the timing data of standard cells in the existing library, data amplification is performed to obtain the expanded training data set. The specific process is as follows: Parse the standard cell library file and extract the delay lookup table between the input jump time, output load and delay corresponding to different timing arcs of each standard cell; According to the input transition time and output load values ​​in the delay lookup table, multiple interpolation values ​​are generated between each two adjacent values ​​to obtain n×n input transition time and output load interpolation values; According to the interpolation of the generated input transition time and output load, combined with the interpolation algorithm, the corresponding n×n delay result is generated; Based on the generated input transition time and output load interpolation, SPICE simulation is used to generate the corresponding n×n unit delay results.

7. The transistor-level timing prediction method for critical path standard cells according to claim 1, 2 or 3, characterized in that: The specific process of obtaining the intrinsic characteristics of the standard cell transistor level is: Parse the standard cell netlist, extract the topological relationship between transistors, input pins, output pins, power supply and ground in the standard cell, and form a heterogeneous graph of different types of nodes; Parse the standard cell netlist to extract information about each transistor; parse the standard cell library file and analyze the current process status information to extract the threshold voltage and channel length information of the current transistor; Using each information as initialization feature of transistor nodes in the heterogeneous graph; Analyze the current timing arc state, extract the input pins in the current state, the input pin states, the states of other input pins, the monotonic correlation between the input pins and the output pins, whether the input pins are rising delay or falling delay, whether the output pins are rising delay or falling delay, the states of the output pins, as well as the input jump time and the output load, to obtain the state information; Initialize input pin and output pin node features according to the state information; The standard cell library file is parsed and the process corner status information of the current standard cell is analyzed to obtain the voltage value, and the characteristics of the power node are initialized to the voltage value, and the characteristics of the ground node are initialized to 0.

8. The transistor-level timing prediction method for critical path standard cells according to claim 1, 2 or 3, characterized in that: The specific process of obtaining the state characteristics of the standard cell is: Parsing the standard cell library file and extracting process information as the state characteristics of the current standard cell; the process information includes process angle, temperature, height of the standard cell and area of ​​the standard cell; The state characteristics of the standard unit are normalized to obtain the final state characteristics.

9. A transistor-level timing prediction system for critical path standard cells, comprising a memory and a processor connected to each other, wherein a computer program is stored in the memory, characterized in that: When the computer program is executed by a processor, the computer program performs the steps of the method according to any one of claims 1 to 8.

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