A circuit device for the fast configuration bitstream of an FPGA

Abstract

A circuit device for quickly configuring the bitstream of an FPGA provided by the present invention includes a configuration interface and a configuration controller. The bitstream data enters the configuration controller through the configuration interface. The configuration controller includes a configuration control circuit and a bitstream frame distribution circuit. The configuration control circuit parses the bitstream file to obtain the content of the configuration data area. There are multiple storage areas in the configuration memory of the FPGA. The configuration control circuit finds the first data frame of each storage area in the configuration data area, combines the data frames at the same position of each storage area into a large-bitwidth data frame, and sends it to the bitstream frame distribution circuit. The bitstream frame distribution circuit divides the combined large-bitwidth data frame and sends it to each storage area in parallel. The circuit device for quickly configuring the bitstream of the FPGA of the present invention adopts parallel configuration, which can greatly improve the configuration speed and resource utilization rate.

Description

Technical Field

[0001] The present invention belongs to the technical field of FPGA configuration, and particularly relates to a circuit device for quickly configuring the bitstream of an FPGA. Background Art

[0002] FPGA (Field Programmable Gate Array) is a semiconductor device, which consists of programmable logic units and programmable interconnection resources. Different from the fixed-function ASIC (Application-Specific Integrated Circuit), the hardware function of the FPGA can be reprogrammed by downloading different configuration data. The FPGA has high flexibility and rapid prototyping capabilities and is widely used in fields such as digital signal processing, communication, embedded systems, artificial intelligence, and automation.

[0003] The bitstream file is a binary file used to configure the FPGA. It contains the configuration information of all programmable resources inside the FPGA, including the settings of logic units, connection methods, and the configuration of I / O pins. The bitstream file is generated by FPGA design software, which synthesizes, places, and routes the user's design description (usually a hardware description language such as Verilog or VHDL) to generate the corresponding bitstream file. The bitstream file configures all the transistors inside the FPGA chip in the form of binary data. For the same FPGA chip, different circuits correspond to bitstream files of the same size but different contents. The bitstream file can be divided into three parts: the register configuration area, the configuration data area, and the check information area. The register configuration area contains the register addresses and values related to the FPGA configuration bitstream, and this part of the content determines information such as the mode, rate, and bitstream scale of the FPGA configuration bitstream. The configuration data area is the core part of the bitstream file and contains the data used to configure the FPGA logic resources and functional modules. This part of the data determines the specific configuration of the internal logic units, connection resources, and I / O resources of the FPGA.

[0004] A frame is the basic unit of FPGA configuration data. The position of the data frame corresponding to each row and column of the FPGA circuit in the bitstream file is fixed, so the position of the data frame corresponding to a specific row and column can be located in the bitstream file. Currently, there are multiple modes of bitstream configuration, such as the master mode, the slave mode, and the JTAG mode. Regardless of which mode is used, the principle is to import the bitstream file into the FPGA through the configuration interface, and the configuration controller inside the FPGA controls the configuration circuit to write the bitstream into the configuration memory (CRAM).

[0005] However, when the configuration circuit of the configuration controller in the prior art writes the bitstream into the configuration memory, it needs to configure row by row, column by column, and frame by frame. Therefore, the configuration time is relatively long, especially for application scenarios that require quick startup or frequent reconfiguration, resulting in an overly long configuration time. Summary of the Invention

[0006] The present invention provides a circuit device for quickly configuring the bitstream of an FPGA. By adopting parallel configuration, the configuration speed can be greatly improved, and the resource utilization rate can be increased.

[0007] Other objects and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0008] To achieve one or part or all of the above objects or other objects, a circuit device for quickly configuring the bitstream of an FPGA provided by a technical solution of the present invention includes a configuration interface and a configuration controller. The bitstream data enters the configuration controller through the configuration interface; the configuration controller includes a configuration control circuit and a bitstream frame distribution circuit; the configuration control circuit analyzes the bitstream file to obtain the content of the configuration data area; there are multiple storage areas in the configuration memory of the FPGA; the configuration control circuit finds the data frame files corresponding to each storage area in the configuration data area, combines the data frames at the same positions of each storage area into a large-bitwidth data frame, and sends it to the bitstream frame distribution circuit; the bitstream frame distribution circuit divides the combined large-bitwidth data frame and sends it to each storage area in parallel.

[0009] The configuration controller further includes a decryption and decompression circuit. The decryption and decompression circuit decrypts and decompresses the input bitstream data, and sends the decrypted and decompressed bitstream data to the configuration control circuit.

[0010] The FPGA divides the configuration memory into multiple rows and columns of storage areas equal to the number of rows and columns of the internal logic resources of the FPGA chip according to the physical layout of the rows and columns of the internal logic resources of the chip; according to several sub-circuits included in each column of logic resources of the FPGA circuit, each column of storage areas is divided into several corresponding data frame placement areas.

[0011] Columns with the same position in different rows of storage areas have multiple data frame placement areas with equal quantities.

[0012] The configuration control circuit searches for the data frame files corresponding to each data frame placement area row by row and column by column in the configuration data area of the bitstream file, combines the data frame files corresponding to the data frame placement areas with the same position between different rows into a large-bitwidth data frame, and sends it to the bitstream frame distribution circuit for splitting and restoring. The restored data frame files are sent to the corresponding data frame placement areas in the data memory in parallel.

[0013] The configuration control circuit merges data frames in the row order of the configuration memory storage area; the bitstream frame distribution circuit splits the merged data frames in the row order of the configuration memory storage area;

[0014] There are multiple data channels in the bitstream frame distribution circuit, each row storage area of the configuration memory corresponds to a data channel, and the split data frames enter the data channels in parallel.

[0015] In one clock cycle, the bitstream frame distribution circuit parallelly sends the restored multiple data frames to the data frame placement areas at the same positions in each row of the configuration memory; the bitstream frame distribution circuit sequentially configures data frame files for each column of data storage areas from top to bottom until all data frame placement areas in a column of data storage areas are configured with data frame files; the bitstream frame distribution circuit sequentially configures data frame files column by column until all data frame placement areas in all columns are configured with data frame files.

[0016] There are two-level cache devices arranged between the configuration control circuit and the bitstream frame distribution circuit; the two-level cache devices include an L1 cache and an L2 cache; the configuration control circuit searches for the data frame files corresponding to the current data frame placement area in the configuration data area, merges the data frame files corresponding to the data frame placement areas at the same positions between different rows into a large-bitwidth data frame, and caches the large-bitwidth data frame in the L1 cache; the configuration control circuit preloads in advance the data frame files corresponding to the next data frame placement area according to the order of the data frame placement areas in each column, and merges them into a large-bitwidth data frame file and caches it in the L2 cache; after the bitstream frame distribution circuit takes away the data frame from the L1 cache, the data frame in the L2 cache is sent into the L1 cache, and the configuration control circuit continues to preload the data frame files in the next data frame placement area of the configuration memory.

[0017] A check circuit is also arranged in the configuration controller. After all data frames in the configuration memory are configured, the check circuit reads back the configuration data in the configuration memory and performs CRC check on the read-back data; the configuration control circuit analyzes the content of the check information area of the bitstream file, and feeds back the content of the check information area to the check circuit. The check circuit performs exclusive OR operation on the read-back data with a preset generating polynomial to obtain a check code, compares the check code with the content of the check information area, and outputs a check result.

[0018] If the check code is the same as the content in the check information area, the check is successful; otherwise, the check fails. The check circuit feeds back the check result to the configuration control circuit. If the check is successful, the configuration control circuit raises the DONE signal and the INIT_B signal of the FPGA. If the check fails, the configuration control circuit lowers the DONE signal and the INIT_B signal of the FPGA, resets the FPGA again, and re-performs the configuration bitstream process.

[0019] Compared with the prior art, the beneficial effects of the present invention mainly include: According to the division of the storage area in the FPGA configuration memory, the configuration control circuit finds the data frame files in each data frame placement area in the storage areas of the same column in different rows at specific positions in the configuration data area of the bitstream file, combines the found multiple data frame files into a large bit-width data frame file, and performs segmentation and input through the bitstream frame distribution circuit, so that the configuration of data frames in multiple rows can be completed simultaneously, greatly improving the data configuration efficiency and having a high resource utilization rate.

[0020] To make the above and other objects, features, and advantages of the present invention more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, makes a detailed description as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following described drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0022] Figure 1 It is a schematic diagram of the bitstream file structure.

[0023] Figure 2 It is a schematic diagram of the circuit device for the FPGA fast configuration bitstream of the present invention.

[0024] Figure 3 It is a schematic diagram of the storage area inside the configuration memory of the present invention.

[0025] Figure 4 It is a schematic diagram of writing the configuration data of the first frame in the first row and the first column in Embodiment 1.

[0026] Figure 5 It is a schematic diagram of writing the last frame of configuration data in Embodiment 1. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0027] The foregoing and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as: up, down, left, right, front or back, etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for illustration and not for limiting the present invention.

[0028] Embodiment 1

[0029] Embodiment 1 provides a circuit device for the fast configuration bitstream of an FPGA, including a configuration interface and a configuration controller. The bitstream data enters the configuration controller through the configuration interface. The configuration controller includes a configuration control circuit and a bitstream frame distribution circuit. The configuration control circuit analyzes the bitstream file to obtain the content of the configuration data area. There are multiple storage areas in the configuration memory of the FPGA. The configuration control circuit finds the data frame file corresponding to each storage area in the configuration data area, combines the data frames at the same position of each storage area into a large-bitwidth data frame, and sends it to the bitstream frame distribution circuit. The bitstream frame distribution circuit divides the combined large-bitwidth data frame and sends it to each storage area in parallel.

[0030] The following specifically explains the solution of the present invention with reference to the accompanying drawings.

[0031] An FPGA generally consists of a programmable logic gate array structure composed of several rows and columns. The rows of the FPGA are the horizontal arrangement units in its internal structure, each row contains multiple columns, and the columns are the vertical arrangement units in the FPGA internal structure, each column contains several sub-circuits (such as CLB units, DSP units, etc.). The configuration data of the FPGA is usually organized and managed in units of frames. Each frame contains the configuration information of a specific area circuit (sub-circuit) (such as wiring resources or I / O blocks, etc.). Usually, each column circuit contains several areas of circuits. Therefore, configuring a column of circuits of the FPGA requires several frames of configuration data.

[0032] In the configuration memory CRAM of the present application, different data storage areas are divided. See Figure 3 , there are multiple rows and columns of storage areas in the configuration memory CRAM, and the multiple rows and columns of storage areas form a storage array. The number of rows and columns of the storage areas in the configuration memory CRAM is arranged according to the row and column layout of the logical resources inside the FPGA. There are multiple data frame placement areas corresponding to each column of the storage area. Each data frame placement area can hold a data frame, and each data frame is used for the configuration of a specific sub-circuit of a column of circuits of the FPGA. The number of columns of the storage areas between different rows is the same, and the columns with the same storage area position have an equal number of multiple data frame placement areas. That is, the number of columns of each row of storage areas in the configuration memory CRAM and the number and arrangement of the data frame placement areas of each column are the same.

[0033] See Figure 1 the schematic diagram of the bitstream file. A bitstream file is a binary file used to configure an FPGA. It contains the configuration information of all programmable resources inside the FPGA, including the settings of logic units, wiring methods, the configuration of I / O pins, etc. The bitstream file is generated by FPGA design software, which synthesizes, places, and routes the user's design description (usually a hardware description language such as Verilog or VHDL) to generate the corresponding bitstream file. The bitstream file configures all transistors inside the FPGA chip in the form of binary data. For the same FPGA chip, different circuits correspond to bitstream files of the same size but different contents. The bitstream file can be divided into three parts: the register configuration area, the configuration data area, and the check information area. The register configuration area contains the register addresses and values related to the FPGA configuration bitstream. This part of the content determines information such as the mode, rate, and bitstream scale of the FPGA configuration bitstream. The configuration data area is the core part of the bitstream file and contains the data used to configure the FPGA logic resources and functional modules. This part of the data determines the specific configuration of the internal logic units, connection resources, and I / O resources of the FPGA.

[0034] See Figure 2 , the circuit structure of Embodiment 1 includes a configuration interface. The configuration interface is used to receive the bitstream file. Different FPGA configuration methods have different configuration interfaces. The configuration controller receives the external bitstream file through the configuration interface. The bitstream file enters the decryption and decompression circuit inside the configuration controller. The decryption and decompression circuit performs decryption and decompression operations on the bitstream file. The steps of decryption and decompression are prior art and will not be elaborated here in this application. The bitstream file after decryption and decompression operations enters the configuration control circuit. The configuration control circuit parses the bitstream file and performs a merging process on the bitstream file. The specific merging process steps are as follows: Parse the bitstream file to obtain the content of the configuration data area, and find each frame of data in the configuration data area according to the storage area position of each data frame that needs to be input into the configuration memory. At the same time, place the data frame files corresponding to the data frames in the same position in the columns of the same storage area row and merge them into a large bit-width data frame. The merged large bit-width data frame is transmitted to the bitstream frame distribution circuit for splitting. After the bitstream frame distribution circuit splits and restores the large bit-width data frame, it distributes it in parallel to the data frame placement areas in the same position in the columns of the same storage area row within one clock cycle, thereby completing the configuration of one data frame in multiple storage areas within one clock cycle. After completing the configuration of the current data frame, continue with the configuration of the next data frame until the configuration of all columns of data frames is completed.

[0035] The merging order and the splitting order are the same. The configuration control circuit merges the data frames in the row order of the configuration memory storage area (that is, merges the data frames at the same positions in each row); the bitstream frame distribution circuit splits the merged data frames in the row order of the configuration memory storage area.

[0036] To achieve parallel transmission, there are multiple data channels in the bitstream frame distribution circuit. Each row storage area of the configuration memory corresponds to a data channel, and the split data frames enter the data channels in parallel and are sent to the data memory.

[0037] The distribution order of the bitstream frame distribution circuit for data frames is as follows: the data configuration frames in each column are configured in the order from top to bottom. When the data frames in one column are configured, then configure column by column until all the data frames in all columns are configured. Specifically: first, for the data storage area of the selected column, configure the data frame files in the order from top to bottom into the data frame placement area until there are data frame files configured in all the data frame placement areas of the selected column. When all the data frame placement areas of the selected column are configured with data frame files, configure the data frame files of the next column in the order of the columns of the data storage area.

[0038] To improve the configuration efficiency, two-level cache devices are provided between the configuration control circuit and the bitstream frame distribution circuit; see Figure 2 , the two-level cache devices include L1 cache and L2 cache; the configuration control circuit searches for the data frame files corresponding to the current data frame placement area in the configuration data area, merges the data frame files corresponding to the data frame placement areas at the same positions between different rows into a large-bitwidth data frame, and caches the large-bitwidth data frame into the L1 cache; the configuration control circuit preloads in advance the data frame files corresponding to the next data frame placement area according to the order of the data frame placement areas in each column, and merges them into a large-bitwidth data frame file and caches it into the L2 cache; after the bitstream frame distribution circuit takes away the data frame from the L1 cache, the data frame in the L2 cache is sent into the L1 cache, and the configuration control circuit continues to preload the data frame files in the next data frame placement area of the configuration memory.

[0039] After the configuration is completed, the verification circuit reads back the configuration data in the configuration memory and performs CRC verification on the read-back data. The verification process is as follows: the verification circuit performs exclusive OR operation on the read-back data based on a specific generating polynomial (such as CRC-16, CRC-32, etc.) to obtain a verification code, and compares the verification code with the content of the verification information area of the bitstream file. If the two are the same, it means the verification is successful; if they are different, it means the verification fails. The verification circuit feeds back the verification result to the configuration control circuit. If the verification is successful, the configuration control circuit raises the DONE signal and the INIT_B signal of the FPGA; if the verification fails, the configuration control circuit lowers the INIT_B signal of the FPGA.

[0040] Example 1 is described by taking an FPGA circuit with a circuit scale of 6 rows, 128 columns, and 512 frames as an example. After the bitstream file enters the configuration controller through the configuration interface, the decryption and decompression circuit performs decryption and decompression operations on the bitstream information. The configuration control circuit first configures the corresponding register values according to the content of the register configuration area of the bitstream file and the register address. Next, the configuration control circuit finds the first frame configuration data of the first column of each row of the FPGA at a specific position in the configuration data area of the bitstream file, a total of 6 frames. The above 6 frames of data are merged into a large bit-width data frame and sent to the bitstream frame distribution circuit. After receiving the large bit-width configuration data, the bitstream frame distribution circuit splits and restores it into 6 frames of configuration data, and distributes the 6 frames of configuration data in parallel to the configuration storage area circuit corresponding to the first frame of the first column of each row of the FPGA within one clock cycle. At this time, the situation of writing configuration data into the FPGA configuration memory is as Figure 4 shown. Then, the configuration control circuit finds the configuration data of the second frame of the first column of each row of the FPGA at a specific position in the configuration data area of the bitstream file. After being merged by the configuration control circuit, split and restored by the bitstream frame distribution circuit, it is distributed in parallel to the configuration control area circuit corresponding to the second frame of the first column of each row of the FPGA within one clock cycle, and so on, until the configuration of the last column of each row of the FPGA is completed. Data frames are written to the data frame placement area of all columns in the above manner. The schematic diagram of the configuration memory for writing the last frame of configuration data is as Figure 5 shown. When the configuration is completed, the verification circuit reads back the configuration data in the configuration memory and performs CRC verification on the read-back data. The verification circuit feeds back the verification result to the configuration control circuit. If the verification is successful, the configuration control circuit raises the DONE signal and the INIT_B signal of the FPGA; if the verification fails, the configuration control circuit lowers the INIT_B signal of the FPGA.

[0041] The above has introduced in detail a circuit device for an FPGA fast configuration bitstream provided by the present invention. Specific examples are used in this article to elaborate on the structure and working principle of the present invention. The description of the above embodiments is only used to help understand the method and core idea of the present invention. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of the present invention, several improvements and modifications can still be made to the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A circuit device for fast configuration of code stream of FPGA, characterized in that: It includes a configuration interface and a configuration controller, and the code stream data enters the configuration controller through the configuration interface; The configuration controller includes a configuration control circuit and a code stream frame distribution circuit; The configuration control circuit parses the code stream file to obtain the content of the configuration data area; There are multiple storage areas in the FPGA’s configuration memory; The configuration control circuit finds the data frame files in each data frame placement area in the storage area of ​​the same column of different rows in the configuration data area, merges the found multiple data frame files into a large bit width data frame file, and sends it to the code stream frame distribution circuit; The code stream frame distribution circuit divides the combined large bit width data frame and sends it to each storage area in parallel.

2. The circuit device for fast FPGA configuration code stream according to claim 1, characterized in that: The configuration controller also includes a decryption and decompression circuit, which decrypts and decompresses the input code stream data and sends the decrypted and decompressed code stream data to the configuration control circuit.

3. The circuit device for fast FPGA configuration code stream according to claim 1, characterized in that: The FPGA divides the configuration memory into a plurality of rows and columns of storage areas equal in number to the rows and columns of the internal logic resources of the FPGA chip according to the physical layout of the rows and columns of the internal logic resources of the chip; According to the number of sub-circuits included in each column of logic resources of the FPGA circuit, each column of storage area is divided into a number of corresponding data frame placement areas.

4. The circuit device for fast FPGA configuration code stream according to claim 3, characterized in that: Columns with the same storage area position in different rows have multiple data frame placement areas of equal number.

5. The circuit device for fast FPGA configuration code stream according to claim 3, characterized in that: The configuration control circuit searches for the data frame file corresponding to each data frame placement area row by row and column by column in the configuration data area of ​​the code stream file, merges the data frame files corresponding to the data frame placement areas with the same position between different rows into a large bit width data frame, and sends it to the code stream frame distribution circuit for segmentation and restoration. The restored data frame files are sent in parallel to the corresponding data frame placement areas in the data storage device.

6. The circuit device for fast configuration of code stream of FPGA according to claim 5, characterized in that: The configuration control circuit merges data frames according to the row order of the configuration memory storage area; The code stream frame distribution circuit divides the merged data frame according to the row order of the storage area of ​​the configuration memory; The code stream frame distribution circuit has a plurality of data channels, each row storage area of ​​the configuration memory corresponds to a data channel, and the divided data frames enter the data channels in parallel.

7. The circuit device for fast FPGA configuration code stream according to claim 5, characterized in that: The code stream frame distribution circuit sends the restored multiple data frames in parallel to the data frame placement area at the same position of each row in the configuration memory within one clock cycle; The code stream frame distribution circuit sequentially configures a data frame file to each data frame placement area for each column of data storage area from top to bottom until all data frame placement areas of a column of data storage area are configured with data frame files; The code stream frame distribution circuit configures the data frame files in sequence column by column until the data frame placement areas of all columns are configured with data frame files.

8. The circuit device for fast FPGA configuration code stream according to claim 6, characterized in that: A two-level cache device is provided between the configuration control circuit and the code stream frame distribution circuit; The two-level cache device includes an L1 cache and an L2 cache; The configuration control circuit searches for a data frame file corresponding to the current data frame placement area in the configuration data area, merges the data frame files corresponding to the data frame placement areas at the same position between different rows into a large bit width data frame, and caches the large bit width data frame into the L1 cache; The configuration control circuit preloads the data frame file corresponding to the next data frame placement area according to the order of the data frame placement areas in each column, and merges them into a large bit width data frame file and caches them in the L2 cache; After the code stream frame distribution circuit takes the data frame from the L1 cache, the data frame in the L2 cache is sent to the L1 cache, and the configuration control circuit continues to preload the data frame file in the next data frame placement area of ​​the configuration memory.

9. The circuit device for fast configuration of code stream of FPGA according to claim 1, characterized in that: The configuration controller is also provided with a check circuit. When all data frames in the configuration memory are configured, the check circuit reads back the configuration data in the configuration memory and performs a CRC check on the read-back data. The configuration control circuit parses the content of the check information area of ​​the code stream file, and feeds back the content of the check information area to the check circuit. The check circuit performs an XOR operation on the read-back data based on a preset generating polynomial to obtain a check code, compares the check code with the content of the check information area, and outputs a check result.

10. The circuit device for fast configuration of code stream of FPGA according to claim 9, characterized in that: If the verification code is the same as the content of the verification information area, the verification is successful, otherwise the verification fails; The verification circuit feeds back the verification result to the configuration control circuit. If the verification is successful, the configuration control circuit pulls up the DONE signal and INIT_B signal of the FPGA; If the verification fails, the configuration control circuit pulls down the FPGA's DONE signal and INIT_B signal, resets the FPGA, and re-performs the configuration bit stream process.

Images