Storage device and storage system

Abstract

The invention provides a storage device and a storage system. The memory device includes: a reference voltage generator configured to generate a reference voltage; and a data input / output (I / O) buffer configured to receive a data signal having a first phase, generate a phase control signal having a second phase opposite the first phase, and generate an output signal based on the data signal, the phase control signal, and the reference voltage.

Description

Technical Field

[0001] The present disclosure relates to a storage device and a storage system. Background Art

[0002] Dynamic random access memory (DRAM) is a random access semiconductor memory that stores each bit of data in a memory cell that is usually composed of a micro capacitor and a transistor. Since the charge on the capacitor gradually leaks away, a memory refresh circuit is used to refresh the data periodically. Data transmission methods used for DRAM include multi-point channels that simultaneously connect multiple chips to a signal line to increase the transmission data capacity and single-ended methods that connect one chip to a signal line.

[0003] Most memories use a single-ended approach to reduce the number of signal lines and pins. In the single-ended approach, the voltage difference between the reference voltage and the data can be used to detect the data. However, parasitic resistance, parasitic inductance, and parasitic capacitance may exist at the input pins of the DRAM chip. The reference voltage may fluctuate due to these parasitic components, thereby reducing the accuracy of the storage device. Summary of the invention

[0004] The present disclosure seeks to provide a memory device capable of providing a stable reference voltage.

[0005] According to an embodiment of the present disclosure, a storage device includes: a reference voltage generator and a data input / output (I / O) buffer. The reference voltage generator is configured to generate a reference voltage. The data input / output (I / O) buffer is configured to receive a data signal having a first phase, generate a phase control signal having a second phase opposite to the first phase, and generate an output signal based on the data signal, the phase control signal and the reference voltage.

[0006] According to an embodiment of the present disclosure, a storage system includes: a memory controller and a storage device. The memory controller is configured to send a data signal having a first phase. The storage device is configured to receive the data signal, and generate an output signal corresponding to the data signal based on a reference voltage for detecting the data signal, a phase control signal having a second phase opposite to the first phase, and the data signal.

[0007] According to an embodiment of the present disclosure, a storage device includes: a reference voltage generator and a data input / output (I / O) buffer. The reference voltage generator is configured to generate a reference voltage. The data input / output (I / O) buffer is configured to receive a reference voltage through a first node, receive a data signal having a first phase through a third node, generate a phase control signal having a second phase opposite to the first phase, generate an output signal by amplifying a difference between the reference voltage and the data signal, and output the output signal through a second node. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram illustrating a storage system according to an embodiment.

[0009] Figure 2 is a block diagram showing a storage device according to an embodiment.

[0010] Figure 3 is a circuit diagram showing an input buffer of a memory device according to an embodiment.

[0011] Figure 4 It is shown Figure 3 A timing diagram of the operation of the input buffer is shown in FIG.

[0012] Figure 5 is a circuit diagram showing a data input / output (IO) buffer according to an embodiment.

[0013] Figure 6 is a circuit diagram showing a data IO buffer according to an embodiment.

[0014] Figure 7 It is shown Figure 5 and Figure 6 A timing diagram of the operation of the input buffer is shown in FIG.

[0015] Figure 8 is a graph showing AC amplitude and AC phase according to frequency.

[0016] Fig. 9 is a diagram illustrating a receiving apparatus according to an embodiment.

[0017] Fig.10 is a block diagram illustrating a computing system according to an embodiment. DETAILED DESCRIPTION

[0018] In the following detailed description, only certain embodiments of the present disclosure are shown and described by way of illustration. As those skilled in the art will realize, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present disclosure.

[0019] Therefore, the drawings and description will be considered as illustrative in nature, rather than restrictive. Throughout the specification, similar reference numerals designate similar elements. In the flow charts described with reference to the drawings, the order of operations may be changed, several operations may be merged, some operations may be divided, and specific operations may not be performed.

[0020] In addition, words written in the singular may be construed as singular or plural unless a specific word such as "one" or "single" is used.

[0021] Figure 1 is a block diagram illustrating a storage system according to an embodiment.

[0022] Reference Figure 1 , the memory system 10 includes a memory controller 100 (eg, a controller circuit) and a memory device 200 .

[0023] In some embodiments, the memory device 200 and the memory controller 100 are connected through a channel and can exchange signals through the channel. At the same time, the type of signal transmitted between the memory device 200 and the memory controller 100 can be preset, and the memory device 200 and the memory controller 100 can exchange signals according to the predetermined type.

[0024] The memory controller 100 may access the memory device 200 according to a request from an external host. The memory controller 100 may control the storage operation of the memory device 200 by providing a signal to the memory device 200. The signal may include a command CMD and an address ADDR. The command may include a read / write command. The read / write command may be a command for performing a read operation of reading data stored in the memory device 200 or a write operation of writing data to the memory device 200.

[0025] The memory controller 100 may send a signal according to the data DATA to the memory device 200 through a channel. In an embodiment, the memory controller 100 sends a signal using a single-ended signaling method. The memory device 200 may receive a signal sent through a channel from the memory controller 100, and determine a bit in the transmitted signal by comparing the transmitted signal with a reference signal. The number of channels required to implement the single-ended signaling may be less than the number of channels required to implement the dual-ended signaling (or differential signaling) method. The dual-ended signaling method may be a method of receiving a signal sent through a channel from the memory controller 100 and comparing the transmitted signal to determine a bit in the transmitted signal. In the following, it is assumed that the memory controller 100 sends a signal to the memory device 200 through a single-ended signaling method.

[0026] The memory device 200 includes a data input / output (IO) buffer 210 and a reference voltage generator 230 .

[0027] The data IO buffer 210 may receive data DATA to be written to the memory device 200 from the memory controller 100 as a data input signal D_IN. The data IO buffer 210 may read the data DATA and provide the read data to the memory controller 100. In an embodiment, the data IO buffer 210 includes a phase control buffer 211 and an input buffer 213.

[0028] The phase control buffer 211 may generate a phase control signal SIG_PC based on the data input signal D_IN received from the memory controller 100. The phase control buffer 211 may transmit the generated phase control signal SIG_PC to the input buffer 213.

[0029] The input buffer 213 may receive the data input signal D_IN from the memory controller 100. The input buffer 213 may receive the reference voltage VREF from the reference voltage generator 230.

[0030] The input buffer 213 may process the data input signal D_IN based on the reference voltage VREF. In an embodiment, the input buffer 213 converts the data input signal D_IN by comparing the reference voltage VREF with the data input signal D_IN.

[0031] In an embodiment, the input buffer 213 also receives the phase control signal SIG_PC from the phase control buffer 211. The input buffer 213 can compensate the reference voltage VREF based on the phase control signal SIG_PC, and process the data input signal D_IN based on the compensated reference voltage. For example, the input buffer 213 can convert the data input signal D_IN by comparing the compensated reference voltage with the data input signal D_IN.

[0032] Thereafter, the input buffer 213 may output the processed data input signal D_IN as the output signal OUT. For example, the input buffer 213 may generate the output signal OUT by amplifying the difference between the reference voltage and the data input signal D_IN.

[0033] The reference voltage generator 230 may generate various voltages for driving the memory device 200. The reference voltage generator 230 may receive a power supply voltage from the outside and generate a reference voltage VREF based on the power supply voltage. In an embodiment, the reference voltage generator 230 includes a bandgap reference (BGR) circuit.

[0034] The reference voltage VREF may be a voltage used by the data IO buffer 210 to determine a data value of the data input signal D_IN from the memory controller 100. In an embodiment, the reference voltage VREF is an average value of the voltage of the data input signal D_IN.

[0035] Figure 2 is a block diagram showing a storage device according to an embodiment.

[0036] Reference Figure 2 , the memory device 30 includes a memory cell array 310, a sense amplifier circuit 311, a control logic 320 (e.g., a logic circuit), an address register 330, a bank control logic 340 (e.g., a logic circuit), a row decoder 350 (e.g., a decoder circuit), a column decoder 360 (e.g., a decoder circuit), an I / O gating circuit 370, an ECC engine 375 (e.g., a logic circuit), a data IO buffer 380, and a reference voltage generator 390. The memory device 200 may be implemented using the memory device 30.

[0037] Although Figure 2 It is illustrated that the sense amplifier circuit 311 , the row decoder 350 , and the column decoder 360 include a plurality of sense amplifier circuits, a plurality of row decoders, and a plurality of column decoders connected to each memory bank, but the present disclosure is not limited thereto.

[0038] The memory cell array 310 may include a plurality of memory banks 310a-310h. The plurality of memory banks 310a-310h may store data from a memory controller ( Figure 1 100) received data DATA. For example, each of the plurality of memory banks 310a to 310h may be a dynamic random access memory (DRAM) including a plurality of volatile memory cells, and may be a dynamic random access memory (DRAM) such as a thyristor random access memory (TRAM), a static random access memory (SRAM), and a double data rate synchronous dynamic random access memory (DDR SDRAM). In some embodiments, each of the plurality of memory banks 310a to 310h may be a phase change random access memory (PRAM) having a resistive memory cell, a resistive random access memory (RRAM), a magnetic random access memory (MRAM), and a ferroelectric random access memory FRAM.

[0039] Each of the memory banks 310a to 310h may include a plurality of rows, a plurality of columns, and a plurality of memory cells MC arranged at intersections of the plurality of rows and the plurality of columns. Each of the memory cells MC may include one transistor and one capacitor.

[0040] In some embodiments, a plurality of rows may be defined by a plurality of word lines WL, and a plurality of columns may be defined by a plurality of bit lines BL. The memory device 30 may perform a read operation or a write operation of a data input signal D_IN with respect to a plurality of memory cells MC.

[0041] Despite Figure 2 Eight memory banks BANK0 to BANK7 310a to 310h are shown in FIG. 3 , but the number of memory banks is not limited thereto.

[0042] The sense amplifier circuit 311 may include a plurality of bit line sense amplifiers connected to the plurality of bit lines BL of the memory cell array 310. The plurality of bit line sense amplifiers may detect data input and output through the bit lines BL, and input and output the detected data.

[0043] The control logic 320 may control the operation of the memory device 30. For example, the control logic 320 may generate a control signal so that the memory device 30 performs a read operation or a write operation. The control logic 320 may include a device for decoding a memory controller (e.g., Figure 1 At least one of a command decoder for receiving a command CMD received by the storage device 30 and a mode register for setting an operation mode of the storage device 30.

[0044] The address register 330 may receive data from the memory controller ( Figure 1 The address ADDR may include a bank address BANK_ADDR, a row address ROW_ADDR indicating a row of the memory cell array 310, and a column address COL_ADDR indicating a column of the memory cell array 310. The address register 330 may provide the received bank address BANK_ADDR to the bank control logic 340, provide the received row address ROW_ADDR to the row address multiplexer (RAMUX) 351, and provide the received column address COL_ADDR to the column decoder 360.

[0045] The bank control logic 340 may generate a bank control signal in response to the bank address BANK_ADDR. The row decoder 350 and the column decoder 360 may activate the corresponding bank in response to the bank control signal. In response to the bank control signal, the row decoder 350 corresponding to the bank address BANK_ADDR among the plurality of row decoders 350a to 350h may be activated, and the column decoder 360 corresponding to the bank address BANK_ADDR among the plurality of column decoders 360a to 360h may be activated.

[0046] The row address multiplexer 351 may receive the row address ROW_ADDR from the address register 330 and receive the row address REF_ADDR to be refreshed from the refresh control circuit 353. The row address multiplexer 351 may selectively output the row address ROW_ADDR received from the address register 330 and the row address REF_ADDR received from the refresh control circuit 353 to the row decoder 350.

[0047] The row decoder 350 may select a row to be activated from a plurality of rows of the memory cell array 310 based on the row address ROW_ADDR or REF_ADDR received from the row address multiplexer 351. The row decoder 350 may apply a driving voltage to a word line corresponding to the row to be activated. In some embodiments, a plurality of row decoders 350a to 350h may be provided corresponding to the plurality of memory banks 310a to 310h, respectively.

[0048] The column decoder 360 may select a column to be activated from among a plurality of columns of the memory cell array 310 based on a column address. The column decoder 360 may activate a sense amplifier circuit 311 corresponding to the column address COL_ADDR through an I / O gating circuit 370 to select a column to be activated. In some embodiments, a plurality of memory banks 310a to 310h may be provided corresponding to the plurality of column decoders 360a to 360h, respectively.

[0049] The I / O gating circuit 370 gates the I / O data and may include a data latch for storing data read from the memory cell array 310. The data read from the memory cell array 310 may be detected by the sense amplifier circuit 311 and stored in the I / O gating circuit 370 (e.g., data latch). The data detected by the sense amplifier circuit 311 may be stored in the I / O gating circuit 370 as a codeword CW.

[0050] In addition, the I / O strobe circuit 370 may include a write driver for writing data to the memory cell array 310. The I / O strobe circuit 370 may write the codeword CW to the memory cell array 310 through the write driver. The I / O strobe circuit 370 may send the codeword CW to the ECC engine 375 or receive the codeword CW from the ECC engine 375.

[0051] The ECC engine 375 may perform ECC decoding on the codeword CW stored in the I / O gating circuit 370. When an error is detected in the codeword CW, the ECC engine 375 may generate an error signal while correcting the error, and provide the corrected codeword CW as main data MD to the memory controller ( Figure 1 of 100).

[0052] In addition, the ECC engine 375 may perform ECC decoding on the main data MD received through the data IO buffer 380. In an embodiment, the ECC engine 375 generates parity bits based on the main data MD, and provides the main data MD and the parity bits as a codeword CW to the I / O gating circuit 370. The data IO buffer 380 may provide data read from the memory cell array 310 to the memory controller ( Figure 1 of 100).

[0053] Data IO buffer 380 can be obtained from the memory controller ( Figure 1 100) receives a data input signal D_IN to be written to the memory cell array 310. The data IO buffer 380 may generate main data MD based on the received data input signal D_IN, and provide the generated main data MD to the ECC engine 375.

[0054] In an embodiment, the data IO buffer 380 includes a phase control buffer 381 and an input buffer 383. The phase control buffer 381 may generate a phase control signal SIG_PC based on the data input signal D_IN. The phase control buffer 381 may send the phase control signal SIG_PC to the input buffer 383. The input buffer 383 may process the data input signal D_IN based on the phase control signal SIG_PC and the reference voltage VREF, and generate an output signal based on the processed input signal D_IN. The input buffer 383 may provide the output signal as the main data MD to the ECC engine 375.

[0055] The reference voltage generator 390 may generate various voltages for driving the memory device 30. The reference voltage generator 390 may receive a power supply voltage from the outside and generate a reference voltage VREF based on the power supply voltage. The reference voltage VREF may be a voltage used by the data IO buffer 380 to detect input data. The reference voltage generator 390 may send the reference voltage VREF to the data IO buffer 380. In an embodiment, the data IO buffer 380 detects data by amplifying the difference between the data input signal D_IN and the reference voltage VREF.

[0056] Figure 3 is a circuit diagram showing a non-optimized data IO buffer.

[0057] Specifically, Figure 3 is a diagram showing that when the data IO buffer 400 does not include a phase control buffer ( Figure 3 381) in the diagram is a circuit diagram of the data IO buffer 400.

[0058] The data IO buffer 400 may convert the received data input signal D_IN by comparing the received data input signal D_IN with a reference voltage VREF.

[0059] Reference Figure 3 , the data IO buffer 400 includes a first transistor TX1, a second transistor TX2, a third transistor TX3 and a fourth transistor TX4.

[0060] The data input signal D_IN may be input to a data input node (eg, the first node N1 ) and the reference voltage VREF may be input to a reference voltage input node (eg, the second node N2 ).

[0061] The gate of the first transistor TX1 is connected to the first node N1, the source of the first transistor TX1 is connected to the third node N3, and the drain of the first transistor TX1 is connected to the first output node NOUT1. In this case, the data input signal D_IN is input to the gate of the first transistor TX1 through the first node N1.

[0062] Input capacitor C io Connected between the first node N1 and ground.

[0063] The first resistor R1 is connected between the first output node NOUT1 and the first power supply voltage VDD1.

[0064] The gate of the second transistor TX2 is connected to the second node N2, the source of the second transistor TX2 is connected to the third node N3, and the drain of the second transistor TX2 is connected to the second output node NOUT2. In this case, the reference voltage VREF is connected to the reference resistor R vref The reference voltage VREF supplied to the second node N2 is connected to the gate of the second transistor TX2.

[0065] Reference capacitor C vref The reference voltage VREF is connected between the second node N2 and the ground. Accordingly, the signal of the direct current (DC) component of the reference voltage VREF cannot pass. In some embodiments, the reference voltage VREF may be an average value of the voltage value of the data input signal D_IN. For example, the reference voltage VREF may be a DC voltage with a constant level. Accordingly, a constant level voltage may be provided to the second node N2. The reference resistor R vref can be set to have a small resistance value, and the reference capacitor C vref can be set to have a large capacitance to provide a constant level of voltage to the second node N2. vref When the resistance value is small, the fluctuation of the voltage applied to the second node N2 due to the fluctuation of the reference voltage VREF can be small.vref With a large capacitance, the DC component of the reference voltage VREF can be easily stored.

[0066] However, a parasitic capacitor Cp may exist between the second output node NOUT2 and the second node N2. Accordingly, a change in the second output signal OUT2 may affect the voltage applied to the second node N2. For example, when the second output signal OUT2 changes from a logic low L to a logic high H, the voltage applied to the second node N2 may also increase, and when changing from a logic high H to a logic low L, the voltage applied to the second node N2 may decrease. Therefore, even if a reference voltage VREF of a DC level is input, the voltage of the second node N2 may fluctuate due to the influence of the parasitic capacitor Cp.

[0067] The second resistor R2 is connected between the second output node NOUT2 and the second power supply voltage VDD2.

[0068] The relationship between the second output signal OUT2 and the second node N2 in the frequency domain is as follows.

[0069] (Formula 1)

[0070]

[0071] As shown in Equation 1, the voltage of the second node N2 may affect the second output signal OUT2 .

[0072] The drains of the third transistor TX3 and the fourth transistor TX4, the source of the first transistor TX1 to which the data input signal D_IN is input, and the source of the second transistor TX2 to which the reference voltage VREF is input may be connected to become a third node N3. The sources of the third transistor TX3 and the fourth transistor TX4 are connected to a node receiving a ground GND voltage. That is, the third transistor TX3 and the fourth transistor TX4 may be connected in parallel. The gates of the third transistor TX3 and the fourth transistor TX4 receive a bias voltage BIAS.

[0073] The bias voltage BIAS can be controlled by the reference voltage VREF and the power supply voltage VDD. Accordingly, the sum of the currents flowing from the drain of the third transistor TX3 and the fourth transistor TX4 to the source can be constant. That is, the third transistor TX3 and the fourth transistor TX4 can operate as a constant current source. When the bias voltage BIAS has a constant level, the current amplitude can remain constant. In other words, the sum of the first current I1 flowing through the first transistor TX1 and the second current I2 flowing through the second transistor TX2 can also remain constant.

[0074] The first power supply voltage VDD1 and the second power supply voltage VDD2 are shown as different voltages, but the present disclosure is not limited thereto. For example, the first power supply voltage VDD1 and the second power supply voltage VDD2 may be the same voltage.

[0075] When the voltage level of the data input signal D_IN is constantly at a logic low L or a logic high H, the current flowing through the third transistor TX3 may be constant. Accordingly, the current flowing through the fourth transistor TX4 may also be constant. Accordingly, the second output node NOUT2 may output a second output signal OUT2 at a constant level.

[0076] When the voltage level of the data input signal D_IN changes from logic low L to logic high H, the gate voltage of the first transistor TX1 increases, so the first current I1 flowing through the first transistor TX1 may increase. In this case, due to the input capacitor C io is connected to the first node N1, so a voltage of a constant level, ie, a signal having a DC component cannot pass through. When the first current I1 increases, a voltage drop increases due to the first resistor R1, so a voltage applied to the first output node NOUT1 may decrease.

[0077] Meanwhile, when the voltage level of the data input signal D_IN changes from logic low L to logic high H, the first current I1 increases, so the second current I2 may decrease. When the second current I2 decreases, the voltage drop decreases due to the second resistor R2, so the voltage applied to the second output node NOUT2 may increase.

[0078] When the voltage level of the data input signal D_IN changes from logic high H to logic low L, the gate voltage of the first transistor TX1 decreases, so the first current I1 flowing through the first transistor TX1 may decrease. When the first current I1 decreases, the voltage applied to the first output node NOUT1 may increase.

[0079] Meanwhile, when the voltage level of the data input signal D_IN transitions from logic high H to logic low L, the first current I1 decreases, and thus the second current I2 may increase. When the second current I2 increases, the voltage applied to the second output node NOUT2 may decrease.

[0080] The first output signal OUT1 may have a phase opposite to that of the data input signal D_IN. Specifically, the first output signal OUT1 may change from a logic high H to a logic low L in response to a change in the first current I1 when the data input signal D_IN changes from a logic low L to a logic high H, and may change from a logic low L to a logic high H in response to a change in the first current I1 when the data input signal D_IN changes from a logic high H to a logic low L.

[0081] The second output signal OUT2 may have the same phase as the data input signal D_IN. Specifically, the second output signal OUT2 may change from a logic low L to a logic high H in response to a change in the second current I2 when the data input signal D_IN changes from a logic low L to a logic high H, and may change from a logic high H to a logic low L in response to a change in the second current I2 when the data input signal D_IN changes from a logic high H to a logic low L.

[0082] However, as shown in the above formula 1, the voltage of the second node N2 may be affected by the coupling phenomenon between the second node N2 and the second output node NOUT2. Accordingly, the voltage of the second node N2 may have noise having the same phase as the data input signal D_IN. When noise appears in the voltage of the second node N2, it may be substantially the same as receiving a reference voltage including noise. As described above, the data IO buffer 400 may compare the reference voltage with the data input signal D_IN to convert the reference voltage into the main data MD. However, when the reference voltage VREF fluctuates, it may be difficult for the data IO buffer 400 to accurately detect the data in the data input signal D_IN.

[0083] Figure 4 It shows that according to Figure 3 Timing diagram of the operation of the data IO buffer. Figure 4 A level change of the data input signal D_IN, a level change of the first output node NOUT1, a level change of the second output node NOUT2, and a level change of the voltage V(N2) of the second node N2 are shown.

[0084] During time t401 to t403, the data input signal D_IN changes from logic low L to logic high H. As the voltage level of the data input signal D_IN input to the gate of the first transistor TX1 increases, the first current I1 may increase. As the first current I1 increases, the second current I2 may decrease.

[0085] At time t402, as the data input signal D_IN changes from logic low L to logic high H, the first output signal OUT1 may change from logic high H to logic low L. In addition, the second output signal OUT2 may change from logic low L to logic high H. Figure 4 It is shown that the first output signal OUT1 and the second output signal OUT2 transition at the same time at time t402, but the present disclosure is not limited thereto. For example, in response to a change in the data input signal D_IN, the first output signal OUT1 and the second output signal OUT2 may transition after a certain period of time.

[0086] During a certain period from time t403 , the voltage V( N2 ) may include a noise voltage having a positive value.

[0087] Specifically, the noise voltage may be an influence of the fluctuation of the second output signal OUT2 due to the parasitic capacitor Cp on the voltage V(N2) of the second node N2. Due to the noise voltage, the data IO buffer 400 may erroneously detect the data input signal D_IN. For example, the data IO buffer 400 may detect the data in the data input signal D_IN by amplifying the difference between the reference voltage VREF including the noise voltage and the data input signal D_IN. However, the difference between the reference voltage VREF and the data input signal D_IN may change due to the noise voltage. Accordingly, the data IO buffer 400 cannot accurately detect the data in the data input signal D_IN.

[0088] During time t403 to t404 , the data input signal D_IN is logic high H.

[0089] When the data input signal D_IN is a logic high H, the first output signal OUT1 may be a logic low L and the second output signal OUT2 may be a logic high H. Since the data input signal D_IN is maintained at a constant level, the influence of the data input signal D_IN on the second node N2 due to the parasitic capacitor Cp may be reduced. Accordingly, the voltage V(N2) may be maintained at a constant level of voltage. For example, the voltage V(N2) may be maintained at the reference voltage VREF.

[0090] During time t404 to t406 , the data input signal D_IN changes from logic high H to logic low L.

[0091] As the voltage level of the data input signal D_IN input to the gate of the first transistor TX1 decreases, the first current I1 may decrease. When the first current I1 decreases, the second current I2 may increase.

[0092] At time t404, when the data input signal D_IN changes from logic high H to logic low L, the first output signal OUT1 may change from logic low L to logic high H. In addition, the second output signal OUT2 may change from logic high H to logic low L. Although Figure 4 It is shown that the first output signal OUT1 and the second output signal OUT2 transition at the same time at time t405, but the present disclosure is not limited thereto. For example, in response to a change in the data input signal D_IN, the first output signal OUT1 and the second output signal OUT2 may transition after a certain period of time.

[0093] During a certain period from time t406 , the voltage V( N2 ) may include a noise voltage having a negative value.

[0094] During time t406 to t407 , the data input signal D_IN is logic low L.

[0095] When the data input signal D_IN is logic low L, the first output signal OUT1 may be logic high H and the second output signal OUT2 may be logic low L. Since the data input signal D_IN is maintained at a constant level, the influence of the data input signal D_IN on the second node N2 due to the parasitic capacitor Cp may be reduced. Accordingly, the voltage V(N2) may be maintained at a constant level of voltage. For example, the voltage V(N2) may be maintained at the reference voltage VREF.

[0096] The operation of the data IO buffer 400 after time t407 may be substantially the same as the operation of the input buffer during time t401 to t406 .

[0097] Figure 5 is a circuit diagram showing a data IO buffer according to an embodiment.

[0098] like Figure 5 As shown in FIG. 1 , the data IO buffer 380 also includes a connection to the Figure 3 The phase of the input buffer 383 controls the buffer 381.

[0099] Unless otherwise specified, the input buffer 383 may be similar to the reference Figure 3 Data IO buffer 400 is described.

[0100] The first input terminal of the phase control buffer 381 is connected to the first node N1 to receive the input data signal D_IN. The second input terminal of the phase control buffer 381 receives the bias voltage BIAS. The second input terminal can be connected to the gates of the transistors TX3 and TX4. The output terminal of the phase control buffer 381 is connected to the fourth node N4.

[0101] In an embodiment, the phase capacitor C C Connected between the fourth node N4 and the second node N2.

[0102] The phase control buffer 381 can reduce the influence of the second output node NOUT2 on the second node N2 through the parasitic capacitor Cp. In an embodiment, the phase control buffer 381 receives the input data signal D_IN, generates a signal having an opposite phase to the input data signal D_IN based on the input data signal D_IN, and generates a signal having an opposite phase to the input data signal D_IN through the phase capacitor Cp. C The phase control signal SIG_PC is transmitted to the second node N2.

[0103] For example, the phase control signal SIG_PC may have a size or amplitude sufficient to eliminate the noise caused by the second node N2 due to the parasitic capacitor Cp. In an embodiment, based on the input data signal D_IN, the type of channel transmitting the input data signal D_IN, the memory controller ( Figure 1 100) type etc. to preset the size or amplitude of the phase control signal SIG_PC.

[0104] As another example, the magnitude of the phase control signal SIG_PC may be greater than a magnitude sufficient to eliminate the noise caused by the second node N2. For example, the magnitude of the phase control signal SIG_PC may be greater than a magnitude sufficient to eliminate the noise caused by the second node N2. The memory controller ( Figure 1 100) can transmit data DATA to the storage device ( Figure 1 For example, when the memory controller ( Figure 1 When data is transmitted through a channel such as a coaxial cable, a PCB trace, etc., the bandwidth of the channel may be limited due to channel load, skin effect, dielectric loss, etc., so the high-frequency component of the data DATA may be weakened. The phase control signal SIG_PC having a magnitude greater than a magnitude sufficient to eliminate the noise caused by the second node N2 may compensate for the high-frequency component of the data DATA weakened when transmitted through the channel.

[0105] Figure 6 is a circuit diagram showing a data IO buffer according to an embodiment.

[0106] Figure 6 is a circuit diagram exemplarily showing a phase control buffer 381 according to an embodiment.

[0107] like Figure 6 As shown in , the phase control buffer 381 includes a fifth transistor TX5 and a sixth transistor TX6.

[0108] A gate of the fifth transistor TX5 is connected to the first node N1, a drain of the fifth transistor TX5 is connected to the fourth node N4, and a source of the fifth transistor TX5 is connected to the fifth node N5.

[0109] The bias voltage BIAS is input to the gate of the sixth transistor TX6 , the drain of the sixth transistor TX6 is connected to the fifth node N5 , and the source of the sixth transistor TX6 is connected to the ground power source GND.

[0110] The third resistor R3 is connected between the fourth node N4 and a node receiving the third power supply voltage VDD3. S The phase capacitor C may be connected between the fifth node N5 and the ground power supply GND.C The voltage of the phase control buffer 381 observed from the fourth node N4 can be expressed as Equation 2 in the frequency domain.

[0111] (Formula 2)

[0112]

[0113] In addition, when the phase control buffer 381 is included, the relationship between the second output signal OUT2 and the second node N2 can be expressed as Equation 3 in the frequency domain.

[0114] (Formula 3)

[0115]

[0116] In this case, assuming that the magnitude of the second output signal OUT2 is the same as the magnitude of the phase control signal SIG_PC, that is, assuming that the second output signal OUT2 is gm*RL*D_IN, Equation 3 can be expressed as Equation 4.

[0117] (Formula 4)

[0118]

[0119] As shown in Formula 4, by setting the third resistor R3 and the phase capacitor Cp based on the preset values ​​of the second resistor R2 and the parasitic capacitor Cp, C The coupling effect of the second output signal OUT2 on the reference voltage VREF caused by the parasitic capacitor Cp can be adjusted by adjusting the value of the parasitic capacitor Cp. For example, the value obtained by multiplying the resistance value of the second resistor R2 by the capacitance value of the parasitic capacitor Cp is the same as the value obtained by multiplying the resistance value of the third resistor R3 by the capacitance value of the phase capacitor Cc. C When the capacitance values ​​of the third resistor R3 and the phase capacitor C are the same, V(N2) may have a value of 0. Alternatively, when the third resistor R3 and the phase capacitor C C When the value of V(N2) is set to increase the coupling effect of the second output signal OUT2 on the reference voltage VREF, V(N2) may have a negative value.

[0120] exist Figure 6 , an embodiment of a possible phase control buffer 381 is shown and described, but the present disclosure is not limited thereto. For example, the phase control buffer 381 may be various buffers in a form in which the phase of the input data signal D_IN is inverted, and thus, the input data signal D_IN may be sent to a node to which a reference voltage is input.

[0121] Figure 7 It is shown Figure 5 and Figure 6 A timing diagram of the operation of the input buffer is shown in FIG.

[0122] Figure 7 A level change of the data input signal D_IN, a level change of the phase control signal SIG_PC, a level change of the first output node NOUT1, a level change of the second output node NOUT2, and a level change of the voltage V(N2) of the second node N2 are shown.

[0123] During time t701 to t703 , the data input signal D_IN changes from logic low L to logic high H.

[0124] As the voltage level of the data input signal D_IN input to the gate of the first transistor TX1 increases, the first current I1 may increase. As the first current I1 increases, the second current I2 may decrease.

[0125] At time t702, as the data input signal D_IN changes from logic low L to logic high H, the first output signal OUT1 may change from logic high H to logic low L. In addition, the second output signal OUT2 may change from logic low L to logic high H. Although Figure 7 It is shown that the first output signal OUT1 and the second output signal OUT2 transition at the same time at time t702 , but the present disclosure is not limited thereto, and the first output signal OUT1 and the second output signal OUT2 may transition after a certain period of time in response to a change in the data input signal D_IN.

[0126] Meanwhile, as the data input signal D_IN changes from logic low L to logic high H, the phase control signal SIG_PC may change to an AC voltage having a negative value, which is an opposite phase to the data input signal D_IN. Figure 7 The phase control signal SIG_PC is shown to change at time t702, but the present disclosure is not limited thereto. For example, the phase control buffer 381 receives the data input signal D_IN, so the time when the phase control signal SIG_PC changes may change according to the time taken to output the phase control signal SIG_PC.

[0127] During a certain period of time from time t703 , the voltage V( N2 ) may be maintained at a constant level.

[0128] Positive noise caused by the parasitic capacitor Cp of the second node N2 may be offset by the negative voltage of the phase control signal SIG_PC.

[0129] In an embodiment, the absolute value of the voltage value of the phase control signal SIG_PC is greater than the absolute value of the amplitude of the noise. Figure 7It is shown that the voltage value of the phase control signal SIG_PC is similar to the voltage value of the noise, and thus the voltage V(N2) has a DC level, but the present disclosure is not limited thereto. When the voltage value of the phase control signal SIG_PC is greater than the voltage value of the noise, the voltage V(N2) may have an AC voltage having a negative value. The time during which the phase control signal SIG_PC is generated based on the data input signal D_IN and the time during which the noise in the voltage V(N2) is generated by the second output signal OUT2 may be the same or may be similar.

[0130] During time t703 to t704 , the data input signal D_IN may be logic high H.

[0131] When the data input signal D_IN is a logic high H, the first output signal OUT1 may be a logic low L and the second output signal OUT2 may be a logic high H. Since the data input signal D_IN is maintained at a constant level, the influence of the data input signal D_IN on the second node N2 due to the parasitic capacitor Cp may be reduced. Accordingly, the voltage V(N2) may be maintained at a voltage at a constant level. For example, the voltage V(N2) may be maintained at a reference voltage VREF. In addition, since the data input signal D_IN is maintained at a constant level, the phase control signal SIG_PC may also be maintained at a constant level.

[0132] During time t704 to t706 , the data input signal D_IN may change from logic high H to logic low L.

[0133] As the voltage level of the data input signal D_IN input to the gate of the first transistor TX1 decreases, the first current I1 may decrease. As the first current I1 decreases, the second current I2 may increase.

[0134] At time t704, as the data input signal D_IN changes from logic high H to logic low L, the first output signal OUT1 may change from logic low L to logic high H. In addition, the second output signal OUT2 may change from logic high H to logic low L. Although Figure 7 It is shown that the first output signal OUT1 and the second output signal OUT2 transition at the same time at time t705, but the present disclosure is not limited thereto. For example, in response to a change in the data input signal D_IN, the first output signal OUT1 and the second output signal OUT2 may transition after a certain period of time.

[0135] Meanwhile, as the data input signal D_IN changes from logic high H to logic low L, the phase control signal SIG_PC may change to an AC voltage having a positive value, which is an opposite phase of the data input signal D_IN. Figure 7The phase control signal SIG_PC is shown to change at time t705, but the present disclosure is not limited thereto. Since the phase control buffer 381 receives the data input signal D_IN, the time during which the phase control signal SIG_PC changes may vary according to the time taken to output the phase control signal SIG_PC.

[0136] During a certain period of time from time t706 , the voltage V( N2 ) may be maintained at a constant level.

[0137] Negative noise caused by the parasitic capacitor Cp of the second node N2 may be offset by the positive voltage of the phase control signal SIG_PC.

[0138] In some embodiments, the absolute value of the voltage value of the phase control signal SIG_PC may be greater than the absolute value of the amplitude of the noise. Figure 7 It is shown that the voltage value of the phase control signal SIG_PC is close to the voltage value of the noise, and thus the voltage V(N2) has a DC level, but the present disclosure is not limited thereto. When the voltage value of the phase control signal SIG_PC is greater than the voltage value of the noise, the voltage V(N2) may have an AC voltage having a positive value.

[0139] During time t706 to t707 , the data input signal D_IN may be logic low L.

[0140] When the data input signal D_IN is a logic low L, the first output signal OUT1 may be a logic high H and the second output signal OUT2 may be a logic low L. Since the data input signal D_IN is maintained at a constant level, the influence of the data input signal D_IN on the second node N2 due to the parasitic capacitor Cp may be reduced. Accordingly, the voltage V(N2) may be maintained at a voltage at a constant level. For example, the voltage V(N2) may be maintained at a reference voltage VREF. In addition, since the data input signal D_IN is maintained at a constant level, the phase control signal SIG_PC may also be maintained at a constant level.

[0141] The operation of the input buffer after time t707 may be substantially the same as the operation of the data IO buffer 380 during time t701 to t706 .

[0142] Figure 8 is a graph showing AC amplitude and AC phase according to frequency. Specifically, Figure 8 is a graph showing AC amplitude and AC phase when the memory device is double data rate 5 (DDR5). According to the DDR5 standard, the memory device can operate at a speed of 72 gigahertz (GHz). According to Figure 8The memory device may be designed to have maximum efficiency at the fastest frequency at which the memory device can run, ie, at a clock of approximately 3.7 GHz.

[0143] A first curve 801 is a curve showing AC amplitude according to frequency. A second curve 803 is a curve showing AC phase according to frequency.

[0144] As shown in the first curve 801, as the frequency increases, the AC amplitude may gradually increase and then decrease after about 3.73 GHz. In addition, as shown in the second curve 803, even if the frequency increases before about 3.73 GHz, the AC phase is maintained at a constant level, but the phase may be reversed based on about 3.73 GHz. That is, at 3.73 GHz, the memory device may have an AC phase of 180°.

[0145] Fig. 9 is a diagram illustrating a receiving apparatus according to an embodiment.

[0146] Reference Fig. 9 The receiving device 900 includes a transceiver 920, a data IO buffer 930, a reference voltage generator 940, and a control logic 950 (eg, a logic circuit). The data IO buffer 930 may be composed of Figure 5 or Figure 6 The data IO buffer 380 is implemented.

[0147] The transceiver 920 may transmit and receive wireless signals through the antenna 910 .

[0148] The reference voltage generator 940 may generate various voltages for driving the receiving device 900. The reference voltage generator 940 may receive a power supply voltage from the outside and generate a reference voltage VREF based on the power supply voltage.

[0149] The data IO buffer 930 may process a signal received by the transceiver 920 and convert the signal into a signal that may be processed by the control logic 950. In an embodiment, the data IO buffer 930 includes a phase control buffer 931 and an input buffer 932.

[0150] The phase control buffer 931 may generate a phase control signal SIG_PC based on a signal received from the transceiver 920. In some embodiments, the phase control signal SIG_PC may be a signal having an opposite phase to the signal received from the transceiver 920. The phase control buffer 931 may transmit the generated phase control signal SIG_PC to the input buffer 932.

[0151] The input buffer 932 may receive a signal from the transceiver 920. The input buffer 932 may receive a reference voltage VREF from the reference voltage generator 940. The input buffer 932 may process the signal received from the transceiver 920 based on the reference voltage VREF. In an embodiment, the input buffer 932 converts the signal by comparing the reference voltage VREF with the data input signal D_IN. The input buffer 932 may send the converted signal as an output signal OUT to the control logic 950.

[0152] The control logic 950 may process the output signal OUT received from the data IO buffer 930. The control logic 950 may output the processed signal to the transceiver 920. The transceiver 920 may change the signal output from the control logic 950 into a wireless signal and transmit the changed wireless signal to an external device through the antenna 910.

[0153] Fig.10 is a block diagram illustrating a computing system according to an embodiment.

[0154] Reference Fig.10 , the computing system 1000 includes a processor 1010, a memory device 1040, a memory controller 1030, a storage device 1020, a communication interface 1050, and a bus 1060. The computing system 1000 may also include other general components. In some embodiments, the computing system 1000 may be an on-board data recording system disposed in a vehicle.

[0155] The processor 1010 controls the overall operation of each component of the computing system 1000. The processor 1010 may be implemented as at least one of various processing units such as a central processing unit (CPU), an application processor (AP), and a graphic processing unit (GPU).

[0156] The memory device 1040 stores various data and commands. The memory controller 1030 controls data or commands transmitted to and from the memory device 1040. In an embodiment, the memory controller 1030 may be provided as a chip independent of the processor 1010. In an embodiment, the memory controller 1030 may be provided as an internal component of the processor 1010. The memory device 1040 may be implemented as a reference Figure 1 , Figure 2 and Figures 5 to 8 Describes the storage device.

[0157] In a non-optimized input buffer within a memory device, a reference voltage may be affected by a parasitic capacitor between a node to which the reference voltage is input and an output node through which an output voltage is output. Accordingly, the memory device cannot accurately detect a received signal due to noise in the reference voltage.

[0158] However, the storage device 1040 according to the embodiment can generate a signal having an opposite phase to the input signal, and feed back the signal having the opposite phase to the node to which the reference voltage is input. Accordingly, the storage device 1040 can offset the influence of the reference voltage on the output voltage. Accordingly, the storage device 1040 can accurately detect the received signal. In addition, by controlling the amplitude of the signal having the opposite phase and adding a high-frequency AC current component to the reference voltage, the storage device 1040 can have an increased voltage gain in the high-frequency domain.

[0159] The memory device 1020 stores programs and data in a non-transitory manner. In an embodiment, the communication interface 1050 supports wired and wireless Internet communications of the computing system 1000. In addition, the communication interface 1050 may support various communication methods other than Internet communications. The bus 1060 provides a communication function between components of the computing system 1000. The bus 1060 may include at least one type of bus according to the communication protocol between the components.

[0160] In the above, embodiments have been disclosed in the drawings and the specification. Although specific terms have been used to describe the embodiments in this specification, these terms are only for the purpose of illustrating the technical spirit of the present disclosure and are not used to limit the scope of the present disclosure described in the claims. Therefore, those skilled in the art will understand that various modifications and other equivalent embodiments can be made therefrom.

Claims

1. A storage device, comprising: a reference voltage generator configured to generate a reference voltage; as well as A data input / output buffer configured to receive a data signal having a first phase, generate a phase control signal having a second phase opposite to the first phase, and generate an output signal based on the data signal, the phase control signal and the reference voltage.

2. The storage device according to claim 1, wherein: The data input / output buffer comprises: an input buffer configured to receive the data signal and the phase control signal and generate the output signal by amplifying a difference between the reference voltage and the data signal; and A phase control buffer is configured to receive the data signal and generate the phase control signal.

3. The storage device according to claim 2, wherein: The input buffer comprises: a first node, the first node receiving the reference voltage; a second node, the second node being configured to output the output signal; and A third node receives the data signal as input.

4. The storage device according to claim 3, wherein: A first input terminal of the phase control buffer is connected to the third node, and an output terminal of the phase control buffer is connected to the first node.

5. The storage device according to claim 3, wherein: The input buffer comprises: a fourth node, the fourth node receiving a bias voltage based on the reference voltage and a power supply voltage; a first transistor including a gate connected to the third node; a second transistor including a gate connected to the first node; and at least one transistor including a gate connected to the fourth node and connected in parallel to a drain of the first transistor and a drain of the second transistor, and The output signal is a node voltage corresponding to a current flowing in the second transistor.

6. The storage device according to claim 5, wherein: The phase control buffer comprises: a third transistor including a gate connected to the third node; and a fourth transistor including a gate connected to the fourth node and a source connected to the drain of the third transistor, and The phase control signal is output through the source of the third transistor.

7. The storage device according to claim 3, wherein: The phase control signal is an alternating voltage having a negative first voltage value in response to the data signal transitioning from a first level to a second level higher than the first level.

8. The storage device according to claim 7, wherein: The input buffer includes a parasitic capacitor between the first node and the second node, The reference voltage has noise caused by the output signal due to the parasitic capacitor, and An absolute value of the first voltage value is greater than an amplitude of the noise.

9. The storage device according to claim 3, wherein: The phase control signal is an alternating voltage having a positive second voltage value in response to the data signal transitioning from a second level to a first level lower than the second level.

10. The storage device according to claim 9, wherein: The input buffer includes a parasitic capacitor between the first node and the second node, The reference voltage has noise caused by the output signal due to the parasitic capacitor, and An absolute value of the second voltage value is greater than an amplitude of the noise.

11. A storage system, comprising: a memory controller configured to send a data signal having a first phase; as well as A storage device configured to receive the data signal and generate an output signal corresponding to the data signal based on a reference voltage for detecting the data signal, a phase control signal having a second phase opposite to the first phase, and the data signal.

12. The storage system according to claim 11, wherein: The storage device comprises: a first node, the first node receiving the reference voltage; a second node, the second node being used to output the output signal; a third node, the third node receiving the data signal as input; a fourth node, the fourth node receiving a bias voltage based on the reference voltage and a power supply voltage; a first transistor including a gate connected to the third node; a second transistor including a gate connected to the first node; and at least one transistor including a gate connected to the fourth node and connected in parallel to a drain of the first transistor and a drain of the second transistor, and The output signal is a node voltage corresponding to a current flowing in the second transistor.

13. The storage system according to claim 12, wherein: The storage device also includes: a third transistor including a gate connected to the third node; and a fourth transistor including a gate connected to the fourth node and a source connected to the drain of the third transistor, and The phase control signal is output through the source of the third transistor.

14. The storage system according to claim 13, wherein: The storage device also includes: a phase capacitor connected between a source of the third transistor and the first node; and A storage capacitor is connected between a source of the fourth transistor and ground.

15. The storage system according to claim 12, wherein: The phase control signal is an alternating voltage having a negative first voltage value in response to the data signal transitioning from a first level to a second level higher than the first level.

16. The storage system according to claim 15, wherein: The memory device includes a parasitic capacitor between the first node and the second node, The reference voltage has noise caused by the output signal due to the parasitic capacitor, and An absolute value of the first voltage value is greater than an amplitude of the noise.

17. The storage system according to claim 12, wherein: The phase control signal is an alternating voltage having a positive second voltage value in response to the data signal transitioning from a second level to a first level lower than the second level.

18. The storage system according to claim 17, wherein: The memory device includes a parasitic capacitor between the first node and the second node, The reference voltage has noise caused by the output signal due to the parasitic capacitor, and An absolute value of the second voltage value is greater than an amplitude of the noise.

19. A storage device, comprising: a reference voltage generator configured to generate a reference voltage; as well as A data input / output buffer, the data input / output buffer being configured to receive a reference voltage through a first node, receive a data signal having a first phase through a third node, generate a phase control signal having a second phase opposite to the first phase, generate an output signal by amplifying a difference between the reference voltage and the data signal, and output the output signal through a second node.

20. The storage device according to claim 19, wherein: The data input / output buffer comprises: a fourth node, the fourth node receiving a bias voltage based on the reference voltage and a power supply voltage; a third transistor including a gate connected to the third node; and a fourth transistor including a gate connected to the fourth node and a source connected to the drain of the third transistor, and The phase control signal is a signal output to the first node through the source of the third transistor.

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