Wireless passive ferroelectric memory

Abstract

The invention discloses a wireless passive ferroelectric memory. The wireless passive ferroelectric memory comprises an antenna, a radio frequency analog front end, a digital baseband and a ferroelectric random access memory, the antenna is configured to receive signals and transmit signals; the radio frequency analog front end is configured to convert a digital signal into a radio frequency signal; and the digital baseband is connected between the radio frequency analog front end and the ferroelectric random access memory, and is configured to be matched with the radio frequency analog front end to store external data to the ferroelectric random access memory or output the data stored in the ferroelectric random access memory to the outside. Therefore, the wireless passive ferroelectric memory solves the problems of high power consumption, small capacity, slow writing and the like of the traditional memory by utilizing the unique advantages of low writing voltage, low power consumption, high storage density and large storage capacity of the ferroelectric random access memory, and provides an efficient, reliable and flexible storage solution for the radio frequency identification technology.

Description

Technical Field

[0001] The present application relates to the field of storage, and in particular to a wireless passive ferroelectric memory. Background Art

[0002] Traditional RFID technology has gradually revealed its limitations in terms of power consumption, storage capacity and data persistence.

[0003] Specifically, for example, the traditional RFID technology uses an electrically erasable programmable read only memory (EEPROM) storage array, whose write voltage is as high as 15V, so an additional high-voltage charge pump circuit needs to be designed, which seriously increases the overall power consumption of the chip, and at the same time causes the overall size of the storage array to currently not exceed 8MB, which has certain capacity limitations. In addition, the write speed of ordinary EEPROM is slow, the write bandwidth is not high, and there is a problem of limited data transmission efficiency.

[0004] Therefore, how to develop a wireless storage chip with low power consumption, large capacity and high security has become an urgent problem to be solved. Summary of the invention

[0005] One advantage of the present application is that it provides a wireless passive ferroelectric memory, wherein the wireless passive ferroelectric memory fully utilizes the unique advantages of the non-volatile memory of the ferroelectric random access memory, can be designed to significantly reduce power consumption while ensuring reading performance, and extend the service life of the device, and is expected to meet the urgent needs for big data storage in the future.

[0006] According to one aspect of the present application, a wireless passive ferroelectric memory is provided, which includes: an antenna configured to receive and transmit signals; a ferroelectric random access memory; a radio frequency analog front end connected to the antenna and configured to convert digital signals into radio frequency signals; and a digital baseband connected between the radio frequency analog front end and the ferroelectric random access memory and configured to cooperate with the radio frequency analog front end to store external data in the ferroelectric random access memory or output data stored in the ferroelectric random access memory to the outside; wherein the radio frequency analog front end includes an impedance matching network, a rectifier circuit, a voltage stabilizing circuit, a reference circuit and a modem; the impedance matching network is coupled to the antenna; the rectifier circuit and the The voltage stabilizing circuit is connected between the impedance matching network and the digital baseband, and is configured to convert the radio frequency signal into a global power supply to provide an operating voltage for the wireless passive ferroelectric memory; one end of the reference circuit is connected to the rectifier circuit, and the other end is connected to the voltage stabilizing circuit and the modem; the reference circuit is configured to provide a global reference voltage and reference current; the modem is connected between the impedance matching network and the digital baseband, and is configured to receive data sent from an external reader / writer and demodulate the fundamental wave signal and transmit the data from the digital baseband to the external reader / writer; the digital baseband includes a verification module; the verification module is configured to verify the read data of the ferroelectric random access memory.

[0007] In one embodiment of the wireless passive ferroelectric memory according to the present application, the RF analog front end further includes a power-on reset circuit; the power-on reset circuit is connected to the rectifier circuit and is configured to generate a reset signal by detecting a rectifier voltage; the digital baseband further includes an initialization module. The initialization module is configured to initialize the wireless passive ferroelectric memory.

[0008] In one embodiment of the wireless passive ferroelectric memory described in the present application, the RF analog front end also includes a clock circuit; the clock circuit is connected to the digital baseband and is configured to generate a clock signal required by the digital baseband.

[0009] In one embodiment of the wireless passive ferroelectric memory described in the present application, the clock circuit includes an oscillator, a temperature sensor and a temperature compensation circuit; the temperature sensor and the temperature compensation circuit are connected to the oscillator; the temperature sensor is configured to detect the operating temperature of the clock circuit, and the temperature compensation circuit adjusts the parameters of the oscillator based on the operating temperature of the clock circuit.

[0010] In one embodiment of the wireless passive ferroelectric memory according to the present application, the digital baseband further includes a clock control module; the clock control module is configured to generate, distribute and manage a clock signal of the wireless passive ferroelectric memory.

[0011] In one embodiment of the wireless passive ferroelectric memory described in the present application, the digital baseband also includes an encoding module, a decoding module, a command processing module and a pseudo-random number module; the command processing module is used to process the command signal; the encoding module is configured to encode the received signal and convert the analog signal into a digital signal; the decoding module is configured to decode the baseband signal; the pseudo-random number module is configured to generate a unique random number through a pseudo-random number.

[0012] In one embodiment of the wireless passive ferroelectric memory described in the present application, the ferroelectric random access memory includes a cell array, a control signal module and a sensitive amplifier buffer; the control signal module and the sensitive amplifier buffer are connected to the cell array; the cell array includes a plurality of storage cells; the control signal module is configured to generate an interactive signal for controlling the storage cells so as to control the read and write states of each of the storage cells; the sensitive amplifier buffer includes a sensitive amplifier and an input-output buffer.

[0013] In one embodiment of the wireless passive ferroelectric memory described in the present application, the ferroelectric random access memory also includes a plurality of pre-charge transistors; each group of the pre-charge transistors corresponds to at least one of the storage units; each group of the pre-charge transistors includes at least one pre-charge transistor connected to a preset signal line.

[0014] In one embodiment of the wireless passive ferroelectric memory described in the present application, each of the storage cells is connected to an inverted bit line; the ferroelectric random access memory also includes a reference level generation module, which is configured to generate a reference level; it includes a first reference cell, a second reference cell and a control transistor; the first reference cell is connected to a bit line; the second reference cell is connected to another bit line; and the control transistor is connected between two bit lines.

[0015] In one embodiment of the wireless passive ferroelectric memory described in the present application, the first reference unit includes a first reference transistor, a first reference ferroelectric capacitor and a first write-back transistor; the parameters of the first reference transistor are completely consistent with the parameters of the selection transistor of the memory cell; the parameters of the first reference ferroelectric capacitor are completely consistent with the parameters of the ferroelectric capacitor of the memory cell; the second reference unit includes a second reference transistor, a second reference ferroelectric capacitor and a second write-back transistor; the parameters of the second reference transistor are completely consistent with the parameters of the selection transistor of the memory cell; the parameters of the second reference ferroelectric capacitor are completely consistent with the parameters of the ferroelectric capacitor of the memory cell.

[0016] Further objectives and advantages of the present application will be fully reflected through understanding of the following description and drawings.

[0017] These and other objects, features and advantages of the present application are fully reflected in the following detailed description, drawings and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] By describing the embodiments of the present application in more detail in conjunction with the accompanying drawings, the above and other purposes, features and advantages of the present application will become more apparent. The accompanying drawings are used to provide a further understanding of the embodiments of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the present application and do not constitute a limitation of the present application. In the accompanying drawings, the same reference numerals generally represent the same components or steps.

[0019] Figure 1 The figure shows a schematic structural block diagram of a wireless passive ferroelectric memory according to an embodiment of the present application.

[0020] Figure 2 The figure shows a schematic structural block diagram of a wireless passive ferroelectric random access memory according to an embodiment of the present application.

[0021] Figure 3 A partial circuit diagram of a wireless passive ferroelectric random access memory according to an embodiment of the present application is illustrated.

[0022] Figure 4 The figure shows a timing diagram of a wireless passive ferroelectric random access memory according to an embodiment of the present application. DETAILED DESCRIPTION

[0023] Below, the exemplary embodiments according to the present application will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application, and it should be understood that the present application is not limited to the exemplary embodiments described here.

[0024] It is understood that the term "one" should be understood as "at least one" or "one or more", that is, in one embodiment, the number of an element can be one, while in another embodiment, the number of the element can be multiple, and the term "one" cannot be understood as a limitation on the number. "Multiple" means greater than or equal to two.

[0025] Although ordinals such as "first," "second," and the like will be used to describe various components, those components are not limited herein. The term is used only to distinguish one component from another. For example, a first component may be referred to as a second component, and likewise, a second component may be referred to as a first component without departing from the teachings of the present application. The term "and / or" as used herein includes any and all combinations of one or more associated listed items.

[0026] The terms used herein are only used for the purpose of describing various embodiments and are not intended to be limiting. As used herein, the singular form is intended to include the plural form, unless the context clearly indicates an exception. It will also be understood that the terms "including" and / or "having" when used in this specification specify the presence of the described features, numbers, operations, components, elements, or combinations thereof, without excluding the presence or addition of one or more other features, numbers, operations, components, elements, or combinations thereof.

[0027] like Figures 1 to 4 As shown, the wireless passive ferroelectric memory according to the embodiment of the present application is illustrated. Considering that the ferroelectric random access memory 40 (Ferroelectric Random Access Memory Random Access Memory, FRAM) has non-volatility, the present application adopts FRAM as the storage medium of the radio frequency identification technology, and provides new ideas for the design and optimization of the radio frequency identification technology with its unique advantages of low write voltage, low power consumption, high storage density and large storage capacity.

[0028] The wireless passive ferroelectric memory does not need an external power supply, and can obtain energy through wireless energy harvesting technology (such as radio frequency energy harvesting) to realize internal power supply, and transmit and store data through wireless signals. The ferroelectric random access memory 40 is non-volatile, and the data can still be stored for a long time even if the wireless signal is interrupted or the energy disappears.

[0029] Specifically, Figure 1As shown, the wireless passive ferroelectric memory includes an antenna 10, a radio frequency analog front end 20, a digital baseband 30 and a ferroelectric random access memory 40. The antenna 10 is configured to receive signals and transmit signals to realize wireless signal transmission; specifically, the radio frequency signal is converted from an electromagnetic wave to an electrical signal during the process of receiving the signal, and the electrical signal is converted to an electromagnetic wave during the process of transmitting the signal. The radio frequency analog front end 20 is connected between the antenna 10 and the digital baseband 30, and is configured to convert a digital signal into a radio frequency signal, wherein the digital signal comes from the digital baseband 30. The digital baseband 30 is connected between the radio frequency analog front end 20 and the ferroelectric random access memory 40, and is configured to cooperate with the radio frequency analog front end 20 to store external data in the ferroelectric random access memory 40 or output the data stored in the ferroelectric random access memory 40 to the outside.

[0030] More specifically, the RF analog front end 20 includes an impedance matching network 21, a rectifier circuit 22, a voltage regulator circuit 23, a reference circuit 24 and a modem 25. The impedance matching network 21 is coupled to the antenna 10, and is mainly used to ensure the impedance matching between the antenna 10 and the RF front end circuit, so as to maximize the energy transmission efficiency and meet the band required by the protocol. The rectifier circuit 22 and the voltage regulator circuit 23 are connected between the impedance matching network 21 and the digital baseband 30, and are configured to convert the RF signal into a global power supply to provide a power supply operating voltage VDD for the wireless passive ferroelectric memory, so as to realize power supply without an external power supply. The voltage regulator circuit 23 is connected to the digital baseband 30; the rectifier circuit 22 is connected between the impedance matching network 21 and the voltage regulator circuit 23. One end of the reference circuit 24 is connected to the rectifier circuit 22, and the other end is connected to the voltage regulator circuit 23 and the modem 25. The reference circuit 24 is configured to provide a global reference voltage Vref and a reference current Ibias. The modem 25 is connected between the impedance matching network 21 and the digital baseband 30, and is configured to receive data sent from an external reader and writer, demodulate a fundamental wave command (Commond) signal, and transmit the data from the digital baseband 30 to the external reader and writer. The modem 25 uses the principle of backscatter modulation to enable the external reader and writer to receive the data transmitted from the digital baseband 30.

[0031] In one embodiment of the present application, the RF analog front end 20 further includes a power-on reset circuit. The power-on reset circuit is connected to the rectifier circuit 22 and is configured to generate a reset (Rst) signal by detecting a rectified voltage Vrect in a radio frequency identification (RFID) so as to initialize the wireless passive ferroelectric memory when it is powered on.

[0032] In one embodiment of the present application, the RF analog front end 20 further includes a clock circuit 26. The clock circuit 26 is connected to the digital baseband 30 and is configured to generate a clock (CLK) signal required by the digital baseband 30.

[0033] It is worth mentioning that the clock circuit 26 may be affected by ambient temperature or voltage fluctuations, resulting in unstable clock signals. The present application proposes that the clock stability can be improved by introducing a temperature compensation mechanism in the clock circuit 26; the clock drift can be reduced by using a high-precision oscillator; and the clock accuracy can be improved by synchronizing the clock signal with an external device.

[0034] Accordingly, in one embodiment of the present application, the clock circuit 26 includes an oscillator (not shown in the figure), a temperature sensor (not shown in the figure) and a temperature compensation circuit (not shown in the figure). The temperature sensor and the temperature compensation circuit are connected to the oscillator. The temperature sensor is configured to detect the operating temperature of the clock circuit 26, and the temperature compensation circuit adjusts the parameters of the oscillator, for example, the frequency of the oscillator, based on the operating temperature of the clock circuit 26.

[0035] In another embodiment of the present application, the oscillator in the clock circuit 26 is an oscillator with higher precision.

[0036] In yet another embodiment of the present application, the clock circuit 26 is configured to synchronize the clock of an external device.

[0037] It should be understood that the stability of the clock signal may be improved in other ways, for example, by stabilizing the voltage in the clock circuit 26, performing aging compensation, improving anti-interference performance, and using a phase-locked loop and a digital phase-locked loop.

[0038] When the wireless passive ferroelectric memory detects a valid command signal generated from the outside, data is read out from the ferroelectric random access memory 40 according to the command, and a corresponding response signal is generated to the modem 25, which is transmitted to an external source or the information transmitted by the external source is stored in the ferroelectric random access memory 40.

[0039] Accordingly, the digital baseband 30 is further configured to return a response signal to the modem 25 based on the signal of the RF analog front end 20 , for example, a power supply operating voltage signal, a reset signal, a clock signal, and a command signal.

[0040] Specifically, the digital baseband 30 includes an encoding module 37, a decoding module 32 and a command processing module 35. The command processing module 35 is used to process the command signal. The encoding module 37 is configured to encode the received signal and convert the analog signal into a digital signal. The decoding module 32 is configured to decode the baseband signal.

[0041] In one embodiment of the present application, the digital baseband 30 further includes a pseudo-random number module 34. The pseudo-random number module 34 is configured to generate a unique random number through a pseudo-random number, wherein the unique random number can be used as an encryption key to ensure the security of data transmission.

[0042] In one embodiment of the present application, the digital baseband 30 further includes a clock control module 36. The clock control module 36 is configured to generate, distribute and manage the clock signal of the wireless passive ferroelectric memory to ensure that each module works in coordination according to a predetermined rhythm.

[0043] In one embodiment of the present application, the digital baseband 30 further includes an initialization module 31. The initialization module 31 is configured to initialize the wireless passive ferroelectric memory. Specifically, the initialization module 31 can initialize the wireless passive ferroelectric memory based on the reset signal.

[0044] It is worth mentioning that, considering that the performance of the ferroelectric random access memory 40 may be affected by environmental factors (e.g., temperature, radiation), which may cause data corruption or read errors, the present application proposes to set a verification module 33 for verifying the read data of the ferroelectric random access memory 40. Specifically, the verification can be performed by a cyclic redundancy check code (CRC).

[0045] The digital baseband 30 communicates with the ferroelectric random access memory 40 via the word line WL (x64), the bus interface DBI and the data bus DBO, the control signal read enable (RE) signal, the write enable (WE) signal, and the sense amplifier enable (SEN) signal. The word line (Word Line, WL) is used to select the corresponding bit line (Bit Line, BL), wherein the bit line (BL) is used to transmit data and position.

[0046] Figure 2An exemplary structure of the ferroelectric random access memory 40 is shown. The ferroelectric random access memory 40 includes a cell array 41, a control signal module 42, and a sensitive amplifier buffer 43. The sensitive amplifier 431 includes an input-output buffer 432 (i.e., an IO buffer) and a sensitive amplifier 431. The control signal module 42 and the sensitive amplifier buffer 43 are connected to the cell array 41.

[0047] The cell array 41 includes a plurality of storage cells 411. The plurality of storage cells 411 are arranged in a row and column arrangement to form the cell array 41. The number of the storage cells 411 is not limited by the present application. In an example of the present application, the cell array 41 has 64 rows and 16 columns of storage cells 411, including 64*16 storage cells 411, that is, 1024 storage cells 411.

[0048] The control signal module 42 is configured to receive a read enable (RE) signal, a write enable (WE) signal, a sense amplifier enable (SEN) signal and a word line (WL) signal; and is further configured to generate an interactive signal for controlling the storage unit 411 based on the read enable (RE) signal, the write enable (WE) signal, the sense amplifier enable (SEN) signal and the word line (WL) signal, specifically, the read and write states of each of the storage units 411 can be controlled.

[0049] Each of the sensitive amplifier buffers 43 is connected to at least one of the storage units 411, and is used to output the read data or input the data D[15:0] to be written. In an example of the present application, each of the sensitive amplifier buffers 43 is connected to a column of storage units 411; and can be arranged at the end of each column of storage units 411.

[0050] Figure 3 The local circuit diagram between the cell array 41 and the sensitive amplifier buffer 43 is shown. Each of the sensitive amplifiers 431 is coupled to a bit line (BL) and an inverted bit line (BLB), and is connected to a sensitive amplifier enable (SEN) line and a digital output (DO) signal line. The inverted bit line (BLB) is logically opposite to the bit line (BL), for example, when the bit line expresses "1", the inverted bit line (BLB) expresses "0". The sensitive amplifier 431 connected to the bit line (BL) and the inverted bit line (BLB) can further amplify the signals on the bit line (BL) and the inverted bit line (BLB). The ferroelectric random access memory 40 is connected to a plurality of bit lines (BL) and inverted bit lines (BLB), for example, a first bit line (BL1) and a first inverted bit line (BLB1), a second bit line (BL2) and a second inverted bit line (BLB2).

[0051] Each of the memory cells 411 is connected to an anti-bit line (BLB), a word line (WL) and a plate line (PL). The memory cell 411 includes a gate transistor 4111 and a ferroelectric capacitor 4112. One end of the ferroelectric capacitor 4112 is connected to the gate transistor 4111, and the other end is connected to the plate line (PL). The plate line (PL) can provide a pulse control signal when reading and writing data to the ferroelectric capacitor 4112 of the memory cell 411. The gate of the gate transistor 4111 is connected to the word line (WL), one of the other two ends is connected to the ferroelectric capacitor 4112, and the other end of the other two ends is connected to the anti-bit line (BLB).

[0052] The memory cell 411 stores data by controlling the polarization state of the ferroelectric capacitor 4112 through signals of a word line (WL), a plate line (PL), and a bit line ().

[0053] The ferroelectric random access memory 40 further includes a plurality of pre-charge transistors 44 and a reference level generating module. Each group of the pre-charge transistors 44 corresponds to at least one of the storage cells 411 ; each group of the pre-charge transistors 44 includes at least one pre-charge transistor 44 .

[0054] In an example of the present application, each group of the pre-charge transistors 44 includes three pre-charge transistors 44; each group of the pre-charge transistors 44 corresponds to a column of the storage cells 411. Among the three pre-charge transistors 44, the gate of each pre-charge transistor 44 is connected to a preset (PRE) signal line, wherein one of the other two ends of each pre-charge transistor 44 in the two pre-charge transistors 44 is connected to a common ground line, and the other end is connected to the pre-charge transistor 44 adjacent thereto.

[0055] The reference level generating module is configured to generate a reference level, and includes a first reference unit 451, a second reference unit 452, and a control transistor 453. The first reference unit 451 is connected to a bit line (BL), for example, a first bit line (BL1); the second reference unit 452 is connected to another bit line (BL), for example, a second bit line (BL2); the control transistor 453 is connected between two bits (BL), for example, between the first bit line (BL1) and the second bit line (BL2).

[0056] The first reference unit 451 includes a first reference transistor 4511, a first reference ferroelectric capacitor 4512 and a first write-back transistor 4513. The parameters of the first reference transistor 4511 are completely consistent with the parameters of the gate transistor 4111 of the storage unit 411; the parameters of the first reference ferroelectric capacitor 4512 are completely consistent with the parameters of the ferroelectric capacitor 4112 of the storage unit 411.

[0057] The first reference transistor 4511 and the first reference ferroelectric capacitor 4512 are connected. The first write-back transistor 4513 is connected to the first reference ferroelectric capacitor 4512. Specifically, one end of the first reference ferroelectric capacitor 4512 is connected to the first reference transistor 4511 and the first write-back transistor 4513, and the other end is connected to the reference plate line (RPL). The gate of the first reference transistor 4511 is connected to the read word line (RWL), one of the other two ends is connected to the first reference ferroelectric capacitor 4512, and the other end of the other two ends is connected to a bit line (BL), for example, the first bit line (BL1). The gate of the first write-back transistor 4513 is connected to the write word line (WWL), one of the other two ends is connected to the first reference ferroelectric capacitor 4512, and the other end of the other two ends is connected to the reference signal (RS) line. The reference signal (RS) line is used to provide a write-back control signal. The reference plate line (RPL), the read word line (RWL), and the write word line (WWL) are used to control the reading and writing of the first reference cell 451 and the second reference cell 452. The reference plate line (RPL) is used to provide a pulse control signal for the first reference cell 451 and the second reference cell 452. The write word line (WWL) is used to control the writing of the first reference cell 451 and the second reference cell 452. The read word line (RWL) is used to control the reading of the first reference cell 451 and the second reference cell 452.

[0058] The second reference unit 452 includes a second reference transistor 4521, a second reference ferroelectric capacitor 4522, and a second write-back transistor 4523. The parameters of the second reference transistor 4521 are completely consistent with the parameters of the gate transistor 4111 of the storage unit 411; the parameters of the second reference ferroelectric capacitor 4522 are completely consistent with the parameters of the ferroelectric capacitor 4112 of the storage unit 411.

[0059] The second reference transistor 4521 and the second reference ferroelectric capacitor 4522 are connected. The second write-back transistor 4523 is connected to the second reference ferroelectric capacitor 4522. Specifically, one end of the second reference ferroelectric capacitor 4522 is connected to the second reference transistor 4521 and the second write-back transistor 4523, and the other end is connected to the RPL line. The gate of the second reference transistor 4521 is connected to the RWL line, one of the other two ends is connected to the second reference ferroelectric capacitor 4522, and the other of the other two ends is connected to another bit line (BL), for example, the second bit line (BL2). The gate of the second write-back transistor 4523 is connected to the write word line (WWL) line, one of the other two ends is connected to the second reference ferroelectric capacitor 4522, and the other of the other two ends is connected to the common ground (VSS) line.

[0060] The gate of the control transistor 453 is connected to the equalization (EQ) line, and the other two ends are respectively connected to two bit lines (BL), for example, a first bit line ( BL1 ) and a second bit line ( BL2 ).

[0061] The first reference ferroelectric capacitor 4512 is used to store data "1"; the second reference ferroelectric capacitor 4522 is used to store data "0"; when reading data, the control transistor 453 connects two bit lines (BL), for example, the first bit line (BL1) and the second bit line (BL2), to generate a reference level between data 1 and 0.

[0062] Figure 4 Shown Figure 3The writing timing diagram of the cell array 41 in FIG. First, the PRE signal is enabled to turn on the precharge transistor 44, and the bit line (BL) and the anti-bit line (BLB) are precharged, for example, the first bit line (BL1) and the second bit line (BL2), the first anti-bit line (BLB1) and the second anti-bit line (BLB2). Then, the preset (PRE) signal is low and ready to start writing data; the word line (WL) and the read word line (RWL) signal are synchronously activated, and a positive level pulse is given to the plate line (PL) and the reference plate line (RPL), and the data of the ferroelectric capacitor 4112 is read to the anti-bit line BLB. At the same time, the first reference unit 451 and the second reference unit 452 make at least one of the bit lines (BL), for example, the first bit line (BL1) output "1" when the level is V1, and at least one of the bit lines (BL), for example, the second bit line (BL2) outputs "0" when the level is V0. Next, the equalization (EQ) signal is enabled to turn on the control transistor 453, so that every two bit lines (BL), for example, the first bit line (BL1) and the second bit line (BL2) are short-circuited and share the charge between them; so that a common reference voltage (V0+V1) / 2 is generated on every two bit lines (BL), for example, the first bit line (BL1) and the second bit line (BL2), and then the sense amplifier enable (SEN) signal activates the sense amplifier 431 to distinguish the voltage on each bit line (BL) and read the data. Finally, the write-back signal is enabled, and a positive voltage pulse is given to the refresh reference signal (RS) to write back the data for the first reference unit 451 and the second reference unit 452.

[0063] In summary, the wireless passive ferroelectric memory is explained. This application adopts ferroelectric memory as the storage medium, and utilizes the unique advantages of low write voltage, low power consumption, high storage density and large storage capacity of ferroelectric memory, and successfully solves the limitations of traditional electrically erasable programmable read-only memory in power consumption, capacity and write speed, that is, the traditional electrically erasable programmable read-only memory has high power consumption, small capacity, slow writing and other problems, and provides a more efficient, reliable and flexible storage solution for radio frequency identification technology. The use of ferroelectric memory does not require a high-voltage charge pump, power consumption is significantly reduced, storage density and write bandwidth are higher, breaking through the limitations of electrically erasable programmable read-only memory, and has the advantages of high speed, low power consumption, long retention time, etc.

[0064] The present application and its implementation methods are described above, and such description is not restrictive. The drawings show only one implementation method of the present application, and the actual structure is not limited thereto. In short, if ordinary technicians in the field are inspired by it and design structural methods and embodiments similar to the technical solution without creative design without departing from the inventive purpose of the present application, they should all fall within the protection scope of the present application.

Claims

1. A wireless passive ferroelectric memory, characterized in that: include: an antenna configured to receive a signal and transmit a signal; a ferroelectric random access memory; A radio frequency analog front end, connected to the antenna, configured to convert a digital signal into a radio frequency signal; and a digital baseband, connected between the RF analog front end and the ferroelectric random access memory, configured to cooperate with the RF analog front end to store external data in the ferroelectric random access memory or output data stored in the ferroelectric random access memory to the outside; wherein the RF analog front end includes an impedance matching network, a rectifier circuit, a voltage stabilizing circuit, a reference circuit and a modem; the impedance matching network is coupled to the antenna; the rectifier circuit and the voltage stabilizing circuit are connected between the impedance matching network and the digital baseband, and are configured to convert the RF signal into a global power supply , providing an operating voltage for the wireless passive ferroelectric memory; one end of the reference circuit is connected to the rectifier circuit, and the other end is connected to the voltage stabilizing circuit and the modem; the reference circuit is configured to provide a global reference voltage and reference current; the modem is connected between the impedance matching network and the digital baseband, and is configured to receive data sent from an external reader and writer, demodulate the fundamental wave signal, and transmit the data from the digital baseband to the external reader and writer; the digital baseband includes a verification module; the verification module is configured to verify the read data of the ferroelectric random access memory.

2. The wireless passive ferroelectric memory according to claim 1, characterized in that: The RF analog front end also includes a power-on reset circuit; the power-on reset circuit is connected to the rectifier circuit and is configured to generate a reset signal by detecting the rectifier voltage; the digital baseband also includes an initialization module; the initialization module is configured to initialize the wireless passive ferroelectric memory.

3. The wireless passive ferroelectric memory according to claim 2, characterized in that: The RF analog front end also includes a clock circuit; the clock circuit is connected to the digital baseband and is configured to generate a clock signal required by the digital baseband.

4. The wireless passive ferroelectric memory according to claim 3, characterized in that: The clock circuit includes an oscillator, a temperature sensor and a temperature compensation circuit; the temperature sensor and the temperature compensation circuit are connected to the oscillator; the temperature sensor is configured to detect the operating temperature of the clock circuit, and the temperature compensation circuit adjusts the parameters of the oscillator based on the operating temperature of the clock circuit.

5. The wireless passive ferroelectric memory according to claim 3, characterized in that: The digital baseband further comprises a clock control module; the clock control module is configured to generate, distribute and manage a clock signal of the wireless passive ferroelectric memory.

6. The wireless passive ferroelectric memory according to claim 5, characterized in that: The digital baseband also includes an encoding module, a decoding module, a command processing module and a pseudo-random number module; the command processing module is used to process the command signal; the encoding module is configured to encode the received signal and convert the analog signal into a digital signal; the decoding module is configured to decode the baseband signal; the pseudo-random number module is configured to generate a unique random number through a pseudo-random number.

7. The wireless passive ferroelectric memory according to claim 1, characterized in that: The ferroelectric random access memory includes a cell array, a control signal module and a sensitive amplifier buffer; the control signal module and the sensitive amplifier buffer are connected to the cell array; the cell array includes a plurality of storage cells; the control signal module is configured to generate an interactive signal for controlling the storage cells so as to control the read and write states of each of the storage cells; the sensitive amplifier buffer includes a sensitive amplifier and an input-output buffer.

8. The wireless passive ferroelectric memory according to claim 7, characterized in that: The ferroelectric random access memory also includes a plurality of pre-charge transistors; each group of the pre-charge transistors corresponds to at least one of the storage cells; each group of the pre-charge transistors includes at least one pre-charge transistor connected to a preset signal line.

9. The wireless passive ferroelectric memory according to claim 8, characterized in that: Each of the storage cells is connected to an inverted bit line; the ferroelectric random access memory further comprises a reference level generating module configured to generate a reference level; comprising a first reference unit, a second reference unit and a control transistor; The first reference cell is connected to a bit line; The second reference unit is connected to another bit line; the control transistor is connected between two bit lines.

10. The wireless passive ferroelectric memory according to claim 9, characterized in that: The first reference unit includes a first reference transistor, a first reference ferroelectric capacitor and a first write-back transistor; the parameters of the first reference transistor are completely consistent with the parameters of the selection transistor of the storage unit; the parameters of the first reference ferroelectric capacitor are completely consistent with the parameters of the ferroelectric capacitor of the storage unit; the second reference unit includes a second reference transistor, a second reference ferroelectric capacitor and a second write-back transistor; the parameters of the second reference transistor are completely consistent with the parameters of the selection transistor of the storage unit; the parameters of the second reference ferroelectric capacitor are completely consistent with the parameters of the ferroelectric capacitor of the storage unit.

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