Memory device, memory system and operating method thereof

Abstract

A memory device, a memory system and an operating method thereof are provided. The method for operating the storage device includes: storing a first page of data in a cache latch; storing the first page of data in a first data latch, and storing the previous page of data in a second data latch; programming memory cells of a first page of a memory cell array by using the first page of data; storing the first page of data in a second data latch, and storing a second page of data in the first data latch; and programming the memory cells of the second page by using the second page data.

Description

Background Art

[0001] The present disclosure relates to a storage device, a storage system and an operating method thereof.

[0002] In a non-volatile memory device, it takes time to program data into a memory cell array of the memory device, and only one page of data can be programmed into the memory cell array each time. Thus, when writing multiple pages of data to the memory cell array continuously, it is necessary to wait for the programming of the current data page to be completed, and then transfer and program the next data page into the memory cell array. Therefore, the process of writing data to the memory cell array is inefficient and cannot provide continuous programming. Summary of the invention

[0003] In one aspect, a method for operating a storage device includes: storing a first page of data in a cache latch; storing the first page of data in a first data latch and storing a previous page of data in a second data latch; programming a first page of storage cells of a storage cell array using the first page of data; storing the first page of data in a second data latch and storing a second page of data in the first data latch; and programming a second page of storage cells using the second page of data.

[0004] In some embodiments, before programming the memory cells of the first page of the memory cell array with the first page of data, the method further includes: determining whether the previous page of data is successfully programmed.

[0005] In some implementations, in response to determining that the previous page of data is successfully programmed, the method further includes storing the second page of data in the cache latch.

[0006] In some implementations, in response to determining that the previous page of data is not successfully programmed, the method further includes: reading the previous page of data in the second data latch.

[0007] In some implementations, in response to determining that the previous page of data is not successfully programmed, the method further includes: reading the first page of data in the first data latch.

[0008] In some embodiments, in response to determining that the previous page of data is not successfully programmed, the method further includes: reading out one or more pages of data in the memory cells of the memory cell array.

[0009] In some embodiments, reading out the one or more pages of data in the memory cells of the memory cell array is triggered in response to a first read command. Reading out the first page of data in the first data latch and the previous page of data in the second data latch is triggered in response to a second read command.

[0010] In some embodiments, programming memory cells of a first page using the first page data includes: applying a program pulse to a word line corresponding to the memory cells of the first page according to the first page data; and verifying the memory cells of the first page.

[0011] In some implementations, programming memory cells of the first page using the first page data includes: configuring inhibit information of the memory cells to which the programming pulse is applied; and storing the inhibit information of the memory cells in a master latch.

[0012] In some implementations, verifying the memory cells of the first page includes storing verification information of the memory cells in a master latch.

[0013] In some embodiments, verifying the memory cells of the first page further includes applying a verification voltage to a word line corresponding to the memory cells of the first page.

[0014] In some implementations, verifying the memory cells of the first page further includes storing the verification result in the master latch.

[0015] In some implementations, the method further includes determining whether the first page data is successfully programmed.

[0016] In some embodiments, in response to determining that the first page data is successfully programmed, the method further includes storing the first page data in the second data latch, and storing the second page data in the first data latch.

[0017] In some embodiments, in response to determining that the first page data is not successfully programmed, the method further includes: determining whether the number of reprogramming cycles reaches a cycle threshold, and in response to determining that the number of reprogramming cycles reaches the cycle threshold, the method further includes: storing the first page data in the second data latch, and storing the second page data in the first data latch.

[0018] In some implementations, in response to determining that the number of cycles of the reprogramming has not reached the cycle threshold, the method further includes applying the programming pulse to the word line corresponding to the memory cell of the first page according to the first page data.

[0019] In some embodiments, each memory cell in the memory device is a single-level cell (SLC).

[0020] On the other hand, a memory device includes a memory cell array. The memory cell array includes memory cells; a peripheral circuit coupled to the memory cell array. The peripheral circuit includes: a page buffer coupled to the memory cell array. The page buffer includes: a cache latch; a first data latch; and a second data latch; and control logic coupled to the memory cell array. The peripheral circuit is configured to: store a first page of data in the cache latch; store the previous page of data in the second data latch, and store the first page of data in the first data latch; store the second page of data in the cache latch; program the memory cells of the first page of the memory cell array using the first page of data; store the first page of data in the second data latch, and store the second page of data in the first data latch; and program the memory cells of the second page of the memory cell array using the second page of data.

[0021] In some embodiments, after storing the previous page data in the second data latch and storing the first page data in the first data latch, the peripheral circuit is further configured to: read out the previous page data in the second data latch.

[0022] In some embodiments, after storing the previous page data in the second data latch and storing the first page data in the first data latch, the peripheral circuit is further configured to: read out the first page data in the first data latch.

[0023] In some embodiments, the peripheral circuit is further configured to: after programming memory cells of a second page of the memory cell array with the second page data, read out the previous page data in the second data latch.

[0024] In some implementations, the peripheral circuit is further configured to: in response to a programming failure of memory cells of the first page, read out the previous page data in the second data latch.

[0025] In some implementations, the page buffer further includes a master latch, and the control logic is further configured to store the previous page data in the master latch.

[0026] In some implementations, the peripheral circuit is configured to store the previous page data in the master latch after storing the second page data in the cache latch.

[0027] In some embodiments, when programming memory cells of a first page of the memory cell array using the first page data, the peripheral circuit is further configured to: disable the memory cells of the first page according to the previous page data in the master latch.

[0028] In some implementations, the page buffer further includes a bias latch. The peripheral circuit is further configured to verify the memory cells of the first page of the memory cell array.

[0029] In some embodiments, the peripheral circuit is configured to verify that the memory cells of the first page of the memory cell array are programmed with the first page of data after programming the memory cells of the first page of the memory cell array.

[0030] In some embodiments, the peripheral device configured to program the memory cells of the first page of the memory cell array using the first page data is also configured to: instruct a word line driver to apply a first programming voltage to a first word line corresponding to the memory cells of the first page of the memory cell array according to the first page data.

[0031] In some implementations, each memory cell in the memory cell array is a single-level cell (SLC).

[0032] In yet another aspect, the memory device includes a memory cell array and a peripheral circuit coupled to the memory cell array. The memory cell array includes memory cells. The peripheral circuit includes: a page buffer coupled to the memory cell array. The peripheral circuit is configured to: store a previous page of data and a first page of data in the page buffer; program memory cells of a first page of the memory cell array using the first page of data; store the first page of data and the second page of data in the page buffer; and program memory cells of a second page of the memory cell array using the second page of data.

[0033] On the other hand, a memory system includes a memory device, and a memory controller coupled to the memory device. The memory device includes: a memory cell array including memory cells; and a peripheral circuit coupled to the memory cell array. The peripheral circuit includes: a page buffer coupled to the memory cell array. The memory controller is configured to: send a query command to the memory cell array to confirm whether the previous page data is successfully programmed; and in response to the previous page data not being successfully programmed, send a first read command to read out the first page data and the previous page data in the page buffer.

[0034] In some implementations, in response to a previous page of data not being successfully programmed, a second read command is sent to read out one or more pages of data in the memory cells of the memory cell array.

[0035] In some embodiments, after sending a first read command to read out one or more pages of data in the memory cells of the memory cell array, and sending a second read command to read out the first page data in the first data latch and the previous page data in the second data latch, the memory controller is also configured to: reallocate new physical addresses of corresponding memory cells of the memory cell array to the previous page data and the current page data of the page buffer, and the one or more pages of data of the memory cell array; and program the previous page data, the current page data, and the one or more pages of data into the memory cell array using the new physical addresses.

[0036] In some embodiments, after sending a first read command to read out one or more pages of data in the memory cells of the memory cell array, and sending a second read command to read out the first page of data and the previous page of data in the page buffer, the memory controller is also configured to: erase the memory cells corresponding to the current physical address at which the current programming operation is performed; and program the previous page of data, the current page of data, and the one or more pages of data into the memory cell array using the current physical address.

[0037] In some embodiments, after sending a first read command to read out one or more pages of data in the memory cells of the memory cell array, and sending a second read command to read out the first page of data in the first data latch and the previous page of data in the second data latch, the memory controller is further configured to: reallocate new physical addresses of corresponding memory cells of the memory cell array to the previous page of data of the page buffer; and program the previous page of data into the memory cell array using the new physical address. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate certain aspects of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and enable those skilled in the relevant art to make and use the present disclosure.

[0039] Figure 1 A schematic circuit diagram of an example memory device including peripheral circuits according to some embodiments of the present disclosure is shown.

[0040] Figure 2 A block diagram of an example memory device including a memory cell array and peripheral circuits according to some embodiments of the present disclosure is shown.

[0041] Figure 3A A block diagram of an example memory device including a page buffer according to some embodiments of the present disclosure is shown.

[0042] Figure 3B A block diagram of an example memory system including a memory controller and a memory device according to some embodiments of the present disclosure is shown.

[0043] Figure 4A A table showing corresponding data included in an example page buffer during operation of an example memory device according to some embodiments of the present disclosure is shown.

[0044] Figure 4B A flowchart for operating an example storage device according to some embodiments of the present disclosure is shown.

[0045] Figure 4C A flow chart for operating an example storage system according to some embodiments of the present disclosure is shown.

[0046] Figure 4D A flow chart for operating an example storage system according to some embodiments of the present disclosure is shown.

[0047] Figure 4E A flow chart for operating an example storage system according to some embodiments of the present disclosure is shown.

[0048] Figure 5 A flowchart for operating an example storage device according to some embodiments of the present disclosure is shown.

[0049] Figure 6 A block diagram of an example system with storage is shown according to some implementations of the present disclosure.

[0050] Fig. 7A A diagram showing an example memory card having storage according to some embodiments of the present disclosure.

[0051] Figure 7B A diagram of an example solid state drive (SSD) having a storage device according to some embodiments of the present disclosure is shown.

[0052] The present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0053] Although specific configurations and arrangements are discussed, it should be understood that this is for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of the present disclosure. In addition, the present disclosure may also be used for a variety of other applications. The functions and structural features described in the present disclosure may be combined, adjusted, and modified with each other in a manner not specifically described in the accompanying drawings, so that these combinations, adjustments, and modifications are within the scope of the present disclosure.

[0054] In general, a term may be understood, at least in part, from its use in context. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a combination of features, structures, or characteristics in a plural sense, depending, at least in part, on the context. Similarly, terms such as "a," "an," or "the" may be understood to convey singular usage or to convey plural usage, depending, at least in part, on the context. Furthermore, the term "based on" may be understood to not necessarily be intended to convey an exclusive set of factors, but may, depending, at least in part, on the context, allow for the presence of additional factors that are not necessarily explicitly described.

[0055] When multiple pages of data are continuously written to the memory cell array, these page data can be temporarily stored in a page buffer (e.g., a cache latch or data latch in the page buffer), and then transferred and written to the memory cell array, thereby improving efficiency and providing continuous programming without waiting for the programming of the current data page to be completed before starting the next programming process. The method of storing the page data to be written in the cache latch or data latch of the page buffer during the programming of the current page data (i.e., during the NAND busy time, or the so-called page programming time (tPROG)) and then programming the page data to be written into the memory cell array is called cache programming. However, during the programming process, especially in a single-level cell (SLC) architecture, the data stored in the page buffer can only be retrieved after the current programming process is completed. Therefore, until the second page data is programmed, it is unknown whether the first page data is successfully programmed. In addition, before the second page data is programmed into the memory cell array, the first page data stored in the page buffer can be erased and replaced by the next page data cached therein. Therefore, the first page data stored in the page buffer cannot be read out to determine whether the first page data is successfully programmed. Furthermore, the destruction of the page data stored in the page buffer prevents the page data from being used for data recovery if one of the page data is unsuccessfully programmed.

[0056] In order to solve one or more of the above problems, the present disclosure proposes a solution, wherein the processing and use of latches in the page buffer are provided to retain the page data in the page buffer without being erased. In addition, the present disclosure also proposes a solution for using the page data stored in the page buffer for data recovery in response to one of the page data being unsuccessfully programmed.

[0057] Figure 1A schematic circuit diagram of a memory device 100 including peripheral circuits according to some aspects of the present disclosure is shown. The memory device 100 may include a memory cell array 101 and a peripheral circuit 102 coupled to the memory cell array 101. In some embodiments, the memory cell array 101 may be a NAND flash memory cell array, wherein the memory cells 106 are provided in the form of an array of three-dimensional (3D) NAND memory strings 108, each memory string 308 extending vertically above a substrate (not shown). In some embodiments, each 3D NAND memory string 108 includes a plurality of memory cells 106 coupled in series and stacked vertically. Each memory cell 106 may hold a continuous analog value, such as a voltage or charge, depending on the number of electrons trapped in the region of the memory cell 106. Each memory cell 106 may be a floating gate type memory cell including a floating gate transistor or a charge trapping type memory cell including a charge trapping transistor. Each array of 3D NAND memory strings 108 may include one or more 3D memory devices.

[0058] In some embodiments, each memory cell 106 is a single-level cell (SLC), which can have two possible storage states and can therefore store one bit of data. For example, a first storage state "0" can correspond to a first voltage range, and a second storage state "1" can correspond to a second voltage range. In some embodiments, each memory cell 106 is a multi-level cell (MLC) capable of storing more than a unit of data in four or more storage states. For example, an MLC can store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to assume a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from an erased state by writing one of three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for an erased state.

[0059] like Figure 1As shown, each 3D NAND memory string 108 may include a source select gate (SSG) transistor 110 at its source terminal and a drain select gate (DSG) transistor 112 at its drain terminal. The SSG transistor 110 and the DSG transistor 112 may be configured to activate a selected 3D NAND memory string 108 (column of the array) during read and program operations. In some embodiments, the sources of the SSG transistors 110 of the 3D NAND memory strings 108 in the same block 104 are coupled by a same source line (SL) 114 (e.g., a common SL), for example, to ground. According to some embodiments, the DSG transistor 112 of each 3D NAND memory string 108 is coupled to a corresponding bit line 116, from which data may be read or programmed via an output bus (not shown). In some embodiments, each 3D NAND memory string 108 is configured to be selected or deselected by applying a select signal (e.g., a select voltage higher than a threshold voltage of the DSG transistor 112) or a deselect voltage (e.g., a deselect voltage such as 0 V) ​​to a corresponding DSG transistor 112 via one or more DSG lines 113, and / or applying a select voltage (e.g., a select voltage higher than a threshold voltage of the SSG transistor 110) or a deselect voltage (e.g., 0 V) ​​to a corresponding SSG transistor 110 via one or more SSG lines 115.

[0060] like Figure 1 As shown, the 3D NAND memory string 108 can be organized into a plurality of blocks 104, each of which can have a common source line 114. In some embodiments, each block 104 is a basic data unit for an erase operation, i.e., all memory cells 106 on the same block 104 are erased at the same time. The memory cells 106 can be coupled by word lines 118, which select which row of memory cells 106 is affected by read and program operations. In some embodiments, each word line 118 is coupled to a row of memory cells 106, which is a basic data unit for programming and reading operations. Each word line 118 can be coupled to a plurality of control gates (gate electrodes) at each memory cell 106 in a corresponding row and a gate line coupling the control gates.

[0061] The peripheral circuit 102 may be coupled to the memory cell array 101 via the bit line 116, the word line 118, the source line 114, the SSG line 115, and the DSG line 113. As described above, the peripheral circuit 102 may include any suitable circuitry for facilitating the operation of the memory cell array 101 by applying a sensing voltage signal and / or a current signal to each target memory cell 106 via the bit line 106 and sensing a voltage signal and / or a current signal from each target memory cell 106 via the word line 118, the source line 114, the SSG line 115, and the DSG line 113. The peripheral circuit 102 may include various types of peripheral circuits formed using complementary metal oxide semiconductor (CMOS) technology. For example, Figure 2 Example peripheral circuits 102 are shown, including page buffers 204, column decoders / bit line drivers 206, row decoders / word line drivers 208, voltage generators 210, control logic 212, registers 214, interfaces (I / Fs) 216, and data buses 218. It should be appreciated that in some examples, additional peripheral circuits 102 may also be included.

[0062] The page buffer 204 may be configured to buffer data read from or programmed into the memory cell array 702 according to a control signal of the control logic 212. In one example, the page buffer 204 may store one or more pages of program data (write data) to be programmed into one or more rows of the memory cell array 101. In another example, the page buffer 204 also performs a program verification operation to ensure that the data has been correctly programmed into the memory cells 106 coupled to the selected word line 118.

[0063] The row decoder / word line driver 208 may be configured to be controlled by the control logic 212 and to select or deselect a block 104 of the memory cell array 101 and to select or deselect a word line 118 of the selected block 104. The row decoder / word line driver 208 may be further configured to drive the memory cell array 101. For example, the row decoder / word line driver 208 may drive the memory cell 106 coupled to the selected word line 118 using the word line voltage generated from the voltage generator 210. In some embodiments, the row decoder / word line driver 208 may include a decoder and a string driver (driving transistor) coupled to the local word line and the word line 118.

[0064] The voltage generator 210 can be configured to be controlled by the control logic 212 and generate word line voltages (e.g., read voltages, program voltages, pass voltages, local voltages, verification voltages, etc.) to be provided to the memory cell array 101. In some embodiments, the voltage generator 210 is part of a voltage source that provides voltages at various levels of different peripheral circuits 102, as described in detail below. Consistent with the scope of the present disclosure, in some embodiments, the voltages provided by the voltage generator 210 to, for example, the row decoder / word line driver 208 and the page buffer 204 are higher than certain levels sufficient to perform memory operations. For example, the voltage provided to the page buffer 204 can be between 2V and 3.3V, such as 3.3V, and the voltage provided to the row decoder / word line driver 208 can be greater than 3.3V, such as between 3.3V and 30V.

[0065] The column decoder / bit line driver 206 may be configured to be controlled by the control logic 212 and to select one or more 3D NAND memory strings 108 by applying a bit line voltage generated from the voltage generator 210. For example, the column decoder / bit line driver 206 may apply a column signal to select a set of N-bit data from the page buffer 204 to be output in a read operation.

[0066] The control logic 212 may be coupled to each peripheral circuit and configured to control the operation of the peripheral circuit 102. The register 214 may be coupled to the control logic 212 and may include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit 102.

[0067] The interface 216 can be coupled to the control logic 212 and configured to interface the memory cell array 101 with a memory controller (not shown). In some embodiments, the interface 216 is used as a control buffer to buffer and relay control commands received from the memory controller and / or the host (not shown) to the control logic 212, and status information received from the memory controller and / or the host from the control logic 212. The interface 216 is also coupled to the page buffer 204 and the column decoder / bit line driver 206 via the data bus 218, and is used as an input / output (I / O) interface and data buffer to buffer and relay programming data received from the memory controller and / or the host to the page buffer 204 and read data received from the page buffer 204 to the memory controller and / or the host. In some embodiments, the interface 216 and the data bus 218 are part of the I / O circuit of the peripheral circuit 102.

[0068] Figure 3AAn example memory device 100 is shown, which includes one or more page buffers 204, a memory cell array 101, a control logic 212 coupled to the page buffer 204 and the memory cell array 101, a register 214 coupled to the control logic 212, and an interface (I / F) 216. It should be understood that in some examples, additional components may also be included. The page buffer 204 may include one or more latches. In some embodiments, the page buffer 204 may include a cache latch (DC) 3331, (N-1) data latches (D1 to DN-1) (e.g., a first data latch (D1) 3333 and a second data latch (D2) 3335), a bias latch (DL) 3337, and a master latch (DS) 3339, where N is an integer greater than 1. It should be noted that the names of the latches are used for illustration purposes according to their use and / or the data stored in the page buffer, and are not limited to specific latches in the page buffer. All or some of these latches may be replaced by other latches in the page buffer.

[0069] The latches (e.g., DC 3331, D1 3333, D2 3335, DL 3337, or DS 3339) of the page buffer 204 may store one or more pages of programming data (write data) to be programmed into one or more rows of the memory cell array 101. These latches in the page buffer may also store relevant data in order to perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 106 coupled to the selected word line 118. These latches in the page buffer may also store relevant data in order to perform a data recovery operation to retrieve the data if the data has not been successfully programmed.

[0070] Figure 3B An example memory system 350 including a memory controller 300 and a memory device 100 according to some embodiments of the present disclosure is shown. The memory controller 300 includes a microprocessor 351, a controller register 353 coupled to the microprocessor 351, and a controller interface (I / F) 355 coupled between the microprocessor 351 and a host 357.

[0071] The memory controller 300 can manage the data stored in the storage device 100 and communicate with the host 357. The memory controller 300 can be configured to control the operation of the storage device 100, such as reading, erasing, programming operations, data recovery operations, or other operations according to some embodiments of the present disclosure. The memory controller 300 can be configured to control the operation by sending a command (e.g., a read command) or a command with a data address. In some embodiments, the memory controller 300 may also include a controller memory (e.g., a cache memory or a non-volatile memory) that stores tables, verification information, fail bit count information, or other information in an embodiment of the present disclosure. The memory controller 300 may also be configured to manage various functions regarding data stored or to be stored in the storage device 100, including but not limited to bad block management, garbage collection, logical to physical address conversion, and wear leveling. In some implementations, the memory controller 300 is also configured to: process error correction codes (ECC) for data read from or written to the storage device 100. The memory controller 300 may also perform any other suitable functions, such as formatting the storage device 100. For example, the memory controller 300 may communicate with an external device (e.g., a host 357) according to a specific communication protocol. The host 357 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 357 may be configured to send data to the memory device 100 or receive data from the memory device 100 via the memory controller 300.

[0072] Figure 4A A table showing corresponding data included in an example page buffer during operation of an example memory device according to some embodiments of the present disclosure is shown.

[0073] First, during the program prologue phase (e.g., program preparation process), the first programming operation begins, and the first user data is received from the host 357 to the control logic 212 via the memory controller 300, and is converted into the first page data (e.g., current programming data) to the page buffer 204. The cache latch (e.g., DC 3331) of the page buffer 204 is configured to store the current programming data (write data, or data to be programmed, also referred to as "page data" herein) of this phase. It is worth noting that under the SLC architecture, only one bit of data is stored. Therefore, only one page of data is required. Therefore, each latch can store at least one page of data, and in the programming phase, the latch can directly transfer the page data from the latch to the current page to be programmed. At this stage, the state bit of the DC for the cell in the programming state is 0, and the state bit of the DC for the cell in the erased state is 1.

[0074] Next, during the last program data backup phase, the last program data stored in the first data latch (e.g., D1 3333) of the page buffer 204 during the last program operation is transferred to the second data latch (e.g., D2 3335) of the page buffer 204. At this stage, the state bit of D2 for the cell in the program state is 0, and the state bit of D2 for the cell in the erase state is 1.

[0075] Next, after the last programming data in D1 is transferred and stored in D2, the last programming data in D1 can be erased and overwritten by the current programming data. In this way, during the (current) data transfer phase, the current programming data stored in DC is transferred to D1. At this stage, the state bit of D1 for the cell in the programming state is 0, and the state bit of D1 for the cell in the erased state is 1.

[0076] Next, after the current programming data in DC is transmitted and stored in D1, the current programming data in DC can be erased and overwritten by the next programming data. For example, the next user data can be received and converted into the next program data to be stored in the page buffer. Specifically, in the next page data cache-in phase, the next programming data is transmitted and stored in DC. At this stage, the state bit of DC for the cell in the programming state is 0, and the state bit of DC for the cell in the erased state is 1.

[0077] Next, during the first program inhibition process, the inhibition information of the memory cell to which the programming pulse is applied is configured according to the current page data. The master latch (e.g., DS 3339) of the page buffer 204 is configured to store the inhibition information (e.g., the programming pulse data in D1). The inhibition information may correspond to the cell in the erased state of the target level. At this stage, the state bit of DS for the cell in the programming state is 0, while the state bit of DC for the cell in the erased state is 1. The inhibition information may then be used to inhibit programming of the memory cell by using the current programming data stored in D1.

[0078] Next, after the programming phase, the first programming pulse phase begins. During the first programming pulse phase, the current programming data stored in DC is transferred and programmed to the memory cell array (eg, memory cell array 101).

[0079] Next, after the current page of the memory cell array is programmed, the first programming verification begins. During the first programming verification, a verification preset process can be performed, and the verification preset information can be stored in DS. For example, the inverted data in DS (i.e., the inverted data of the program data stored in D1) is transmitted and stored in DS. The inverted data in DS can be used to set the cell to be verified (i.e., the cell being programmed in the current page). At this stage, the DS status bit for the cell in the erased state and for the cell in the pass state is 0, while the DS status bit for the cell in the verification state is 1.

[0080] Next, during the verification sensing in the first programming verification, the verification information can be stored in the DS. For example, the inverted data in the DS (i.e., the inverted data of the verification preset stored in the DS) and the inverted sensed (SO) node data are transmitted and stored in the DS. Note that the SO node is a node that senses the cell current / voltage in a read operation. It is also a sensed node during the transmission of data between latches. The voltage level of the SO node varies according to the programming state of the cell being programmed in the current page. For example, if the voltage level of the SO node remains logically high, the cell of the current page is programmed, and if the voltage level of the SO node remains logically low, the cell of the current page is not programmed. At this stage, the state bit of the DS for the cell in the erased state and for the cell in the passed state is 0, while the state bit of the DS for the cell in the failed state is 1.

[0081] Next, during the verification failure bit count (VFC) setting phase after the verification sensing in the first programming verification, the VFC may be stored in other parts of the page buffer or in the memory of the memory controller. At this stage, the bias latch (e.g., DL 3337) of the page buffer 204 is configured to store the verification failure information (e.g., verification result) stored in the DS. The data stored in the DL is whether one of the memory cells has been verified. At this stage, the state bit of the DL for the cell in the erased state and the cell in the passed state is 0, while the state bit of the DS for the cell in the erased state is 1.

[0082] Next, during the verification recovery phase in the first program verification, the inverted data in DS (i.e., the inverted data of the verification sense stored in DS) is transmitted and stored in DS. At this stage, the state bit of DS for the cells in the programming state is 0, while the state bits of DS for the cells in the erased state and the cells in the pass state are 1.

[0083] Figure 4BA flow chart for operating an example storage device according to some embodiments of the present disclosure is shown. It should be noted that the latches described herein are for illustrative purposes. All or part of these latches may be replaced or exchanged with other latches.

[0084] First, at operation 402 , a previous page of data is stored in a first data latch (eg, D2 3333) of the page buffer 204 while a previous program is transmitted and stored in a second data latch (eg, D1 3335) of the page buffer 204 .

[0085] Next, at operation 404, after retrieving the previous page data, the user data of the current page is sent from the memory controller (e.g., memory controller 300) to the page buffer 204 and converted into the current page data. The current page data originally stored in the cache latch (e.g., DC 3331) is transferred and stored in the first data latch (e.g., D13333).

[0086] Next, at operation 406, the memory controller (e.g., memory controller 300) may send a command to the storage device (e.g., storage device 100) and determine whether the previous page of data was successfully programmed (passed) or unsuccessfully programmed (failed). If it is determined that the previous page of data was not successfully programmed (failed), the memory controller does not send the next page of data to the storage device, and the storage device continues to write the current page of data instead of the next page of data. In this way, a data recovery operation (e.g., operation 408) may be performed instead. The data recovery operation will be discussed later. On the contrary, if it is determined that the previous page of data was successfully programmed (passed), then at operation 410, the next page of data is sent from the memory controller to the cache latch DC.

[0087] Next, at operation 412, the inhibit information of the memory cell to which the programming pulse is applied is configured according to the current page data. As described above, the inhibit information of the memory cell of the current page (e.g., the first page) is stored in the master latch (e.g., DS3339). Specifically, the inhibit information stored in the DS corresponds to the cell of the erased state of the target level.

[0088] Next, at operation 414, a program pulse is applied to a word line corresponding to memory cells of a current page (eg, a first page) to program the memory cells of the current page.

[0089] Next, at operation 416, after the pulse programming, verification information is configured according to the current page data. Verification information of the memory cell to be verified is stored in DS. Specifically, since the current data stored in DS corresponds to the memory cell in the erased state, and the memory cell to be verified is at the first programming level (P1) opposite to the memory cell in the erased state, the data stored in DS can be inverted to the verification information of the memory cell to be verified.

[0090] Next, at operation 418, a verification voltage is applied to a word line corresponding to a memory cell of the current page (e.g., the first page), and a verification result is stored in DS. The verification result is whether the memory cell in the current page passes or fails. The verification failure information may be opposite to the verification information. Thus, the verification result (e.g., verification failure information) may be inverted data of the verification information.

[0091] Next, at operation 420, the verification failure information is transmitted from the DS to the bias latch (e.g., DL 3337). In some embodiments, a verification failure bit count (VFC) can be used to count the number of memory cells that failed to be written or had errors during the VFC setup phase after the verification sensing in the first programming verification, and the failure bit count can be stored in other parts of the storage device (e.g., other latches in the page buffer) or the memory controller (e.g., a memory in the memory controller, such as a cache memory or a non-volatile memory) to determine whether the current page data is successfully programmed (pass / fail). For example, if the failure bit count reaches a count threshold, it can be determined that the current page data is not successfully programmed (failed). It should be noted that in some embodiments, the memory controller may not be actively informed of the result of whether the current page data is successfully programmed (pass / fail). The memory controller requires a command to call out the result in order to start the data recovery process. In another example, if the failure bit count does not reach the count threshold, it can be determined that the current page data is successfully programmed (pass). If the current page data is successfully programmed, operation 402 of the second programming process can be started and the entire cache programming process can be performed to program the next page data. If the current page data is not successfully programmed, it means that the storage cells of the current page (e.g., the first page) should be reprogrammed using the same current page data. In this way, at operation 422, it is determined whether the number of reprogramming cycles reaches a threshold. That is, in order to prevent the storage cell from no longer being able to be reprogrammed (e.g., all storage cells are damaged), once the number of reprogramming cycles reaches a threshold, such as 10 to 1000 times, the reprogramming process can be stopped and the next programming process can be started (i.e., operation 402 of the second programming process is started). And when it is determined that the current page data is not successfully programmed and the number of reprogramming cycles does not reach the threshold, operation 412 is performed to configure the prohibition information, and then another pulse programming operation 414 is performed to program the storage cell again using the current page data.

[0092] FIG. 4C to FIG. 4E A flow chart of performing a data recovery operation 408 is shown in accordance with various embodiments of the present disclosure.

[0093] In the first type of data recovery operation 408-1, as Figure 4CAs shown, the operation starts at operation 451, where a first read command is sent from a memory controller to a storage device to read out a previous page of data in a page buffer (e.g., in D2). It should be noted that in some embodiments, before sending the first read command, the memory controller may check whether the storage device is in an idle state (i.e., once the pulse programming process of the current page of data is completed, the storage device enters an idle state). If it is determined that the storage device is in an idle state, operation 451 starts and the first read command is sent. And, if it is determined that the storage device is not in an idle state, the memory controller may wait for the completion of the pulse programming of the current page of data and start operation 451 until the storage device is converted to an idle state. Next, the operation proceeds to operation 453, where a second read command is sent from the memory controller to the storage device to read out one or more pages of data in the memory cell array. Next, the operation proceeds to operation 455, in which new physical addresses in the memory cell array corresponding to the previous page of data and the current page of data (which are temporarily stored in the latch of the page buffer) and one or more pages of data in the memory cell array are reallocated. Next, after reallocating new physical addresses in the memory cell array for these page data, the operation proceeds to operation 457, in which these page data are written to the memory cell array with the new physical address. That is, the previous page data, the current page data, and the original page data are all restored to the new physical address in the memory cell array, and the data recovery process is completed. In this way, even if the previous page data is not successfully programmed, the data recovery process will restore the previous page data, the current page data, and the original page data. The programming of the previous page data and the current page data can be repeated (for example, proceeding to operation 412) without continuing to program the next page data (for example, skipping operation 410).

[0094] In the second type of data recovery operation 408-3, as Figure 4DAs shown, the operation starts at operation 451, where a first read command is sent from a memory controller to a storage device to read out a previous page of data in a page buffer (e.g., in D2). Next, the operation proceeds to operation 453, where a second read command is sent from a memory controller to a storage device to read out one or more pages of data in a memory cell array. Next, the operation proceeds to operation 461, in which a new physical address corresponding to the previous page of data (which is temporarily stored in a latch of a page buffer) in the memory cell array is reallocated. Next, after reallocating the new physical address in the memory cell array for the previous page of data, the operation proceeds to operation 463, in which the previous page of data is written to the memory cell array using the new physical address. That is, only the previous page of data is restored to the new physical address in the memory cell array, and the data recovery process is completed. In this way, even if the previous page of data is not successfully programmed, the data recovery process will restore the previous page of data and store the previous page of data in the new physical address. Programming of the previous page of data may be repeated (eg, proceeding to operation 412 ) without continuing programming of the next page of data (eg, skipping operation 410 ).

[0095] In the third type of data recovery operation 408-5, as Figure 4E As shown, the operation starts at operation 451, where a first read command is sent from a memory controller to a storage device to read out the previous page of data in a page buffer (e.g., in D2). Next, the operation proceeds to operation 453, where a second read command is sent from a memory controller to a storage device to read out one or more pages of data in a memory cell array. Next, the operation proceeds to operation 471, where a memory cell corresponding to a current physical address at which a current write operation is performed is erased. Next, the operation proceeds to operation 473, where the previous page of data, the current page of data, and one or more pages of data in the memory cell array are written to the memory cell array using the current physical address corresponding to the current write operation. That is, the previous page of data, the current page of data, and the original page of data are all restored to the physical address being erased, and the data recovery process is completed. Since the current physical address of the current page is erased, and the previous page of data, the current page of data, and one or more pages of data in the memory cell array are written to the current physical address being erased, there is no need to use a new address.

[0096] Figure 5 A flowchart for operating an example storage device according to some embodiments of the present disclosure is shown. Figure 5, method 500 begins at operation 502, wherein a first page of data is stored in a cache latch to start a first programming operation. Next, method 500 proceeds to operation 504, wherein the first page of data is stored in a first data latch and a previous page of data is stored in a second data latch. Since the first page of data in the cache latch is transmitted, method 500 proceeds to operation 506, wherein, in response to determining that the previous page of data is successfully programmed, the second page of data is stored in the cache latch. Next, method 500 proceeds to operation 508, wherein the memory cells of the first page are programmed using the first page of data stored in the first data latch. The programming operation (e.g., pulse programming) may be any pulse programming operation in an embodiment of the present disclosure. Next, method 500 proceeds to operation 510, wherein the memory cells of the first page are verified according to any verification operation in an embodiment of the present disclosure. Next, method 500 proceeds to operation 512, wherein it is determined whether the first page of data is successfully programmed. And, next, the method 500 proceeds to operation 514, wherein, in response to the first page data being successfully programmed, the first page data is stored in the second data latch, and the second page data is stored in the first data latch to start a second programming operation. The specific processes of these operations can refer to the embodiments of the present disclosure, for example Figure 4A-4E implementation method.

[0097] Figure 6 A block diagram of a system 600 having a storage device according to some aspects of the present disclosure is shown. The system 600 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 6 As shown, system 600 may include a host 608 and a storage system 602 having one or more storage devices 604 and a memory controller 606. Host 608 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. Host 608 may be configured to send data to storage device 604 or receive data from storage device 404.

[0098] The storage device 604 can be any storage device disclosed herein, such as the storage device 100. In some implementations, each storage device 604 includes a storage device, as described in detail above.

[0099] According to some embodiments, the memory controller 606 is coupled to the storage device 604 and the host 608, and is configured to control the storage device 604. The memory controller 606 can be any memory controller disclosed herein, such as the memory controller 300. In some embodiments, each memory controller 606 includes a memory controller, as described in detail above. The memory controller 606 can manage the data stored in the storage device 604 and communicate with the host 608. In some embodiments, the memory controller 606 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media for electronic devices, such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 606 is designed to operate in a high duty cycle environment SSD or an embedded multimedia card (eMMC) used as a data storage and enterprise storage cell array for mobile devices (such as smartphones, tablets, laptops, etc.). The memory controller 606 can be configured to control the operation of the storage device 604, such as read, erase and program operations. The memory controller 606 may also be configured to manage various functions regarding data stored or to be stored in the storage device 604, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some implementations, the memory controller 606 is also configured to process error correction codes (ECC) for data read from or written to the storage device 604. Any other suitable functions may also be performed by the memory controller 606, such as formatting the storage device 604. The memory controller 606 may communicate with an external device (e.g., a host 608) according to a specific communication protocol. For example, the memory controller 606 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a firewire protocol, etc.

[0100] The memory controller 606 and the one or more storage devices 604 can be integrated into various types of storage devices, for example, included in the same package, such as a universal flash memory (UFS) package or an eMMC package. That is, the storage system 602 can be implemented and packaged into different types of terminal electronic products. Fig. 7AIn one example shown, the memory controller 606 and the single storage device 604 may be integrated into a memory card 702. The memory card 702 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 702 may also include a processor that connects the memory card 702 to a host (e.g., Figure 6 The memory card connector 704 is coupled to the host 608 in the embodiment of the present invention. Figure 7B In another example shown, the memory controller 606 and the plurality of storage devices 604 may be integrated into the SSD 706. The SSD 706 may also include a processor that interfaces the SSD 706 with a host (eg, Figure 6 In some implementations, the storage capacity and / or operating speed of the SSD 706 are greater than those of the memory card 702.

[0101] The foregoing description of specific embodiments can be readily modified and / or adapted for various applications. Therefore, such adaptations and modifications are intended to fall within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein.

[0102] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A method for operating a storage device, comprising: storing a first page of data in a cache latch; storing the first page of data in a first data latch and storing a previous page of data in a second data latch; Programming memory cells of a first page of a memory cell array using the first page of data; storing the first page data in the second data latch, and storing the second page data in the first data latch; as well as The memory cells of the second page are programmed with the second page data.

2. The method according to claim 1, wherein: Before programming the memory cells of the first page of the memory cell array using the first page data, the method further includes: It is determined whether the previous page data is successfully programmed.

3. The method according to claim 2, wherein: In response to determining that the previous page of data is successfully programmed, the method further includes: The second page of data is stored in the cache latch.

4. The method according to claim 2, wherein: In response to determining that the previous page of data is not successfully programmed, the method further includes: The previous page data in the second data latch is read out.

5. The method according to claim 4, wherein: In response to determining that the previous page of data is not successfully programmed, the method further includes: The first page data in the first data latch is read out.

6. The method according to claim 5, wherein: In response to determining that the previous page of data is not successfully programmed, the method further includes: One or more pages of data in the memory cells of the memory cell array are read out.

7. The method according to claim 6, wherein: Reading out the one or more pages of data in the memory cells of the memory cell array is triggered in response to a first read command, and wherein reading out the first page of data in the first data latch and the previous page of data in the second data latch is triggered in response to a second read command.

8. The method according to claim 1, wherein: Programming the memory cells of the first page using the first page data includes: applying a program pulse to a word line corresponding to the memory cell of the first page according to the first page data; and The memory cells of the first page are verified.

9. The method according to claim 8, wherein: Programming the memory cells of the first page using the first page data includes: configuring inhibition information of the memory cell to which the programming pulse is applied; and The inhibit information of the memory cell is stored in a master latch.

10. The method according to claim 8, wherein: Verifying the memory cells of the first page includes storing verification information of the memory cells in a master latch.

11. The method according to claim 9, wherein: Verifying the memory cells of the first page further includes applying a verification voltage to a word line corresponding to the memory cells of the first page.

12. The method according to claim 11, wherein: Verifying the storage unit of the first page further includes: The verification result is stored in the master latch.

13. The method according to claim 1, further comprising: It is determined whether the first page data is successfully programmed.

14. The method according to claim 13, wherein: In response to determining that the first page data is successfully programmed, the method further includes: The first page data is stored in the second data latch, and the second page data is stored in the first data latch.

15. The method according to claim 13, wherein: In response to determining that the first page of data is not successfully programmed, the method further includes: Determine whether the reprogramming cycle number reaches the cycle threshold, and In response to determining that the number of reprogramming cycles reaches the cycle threshold, the method further includes: The first page data is stored in the second data latch, and the second page data is stored in the first data latch.

16. The method according to claim 15, wherein: In response to determining that the number of reprogramming cycles does not reach the cycle threshold, the method further includes: A program pulse is applied to the word line corresponding to the memory cells of the first page according to the first page data.

17. The method according to claim 1, wherein: Each memory cell in the memory device is a single-level cell (SLC).

18. A storage device, comprising: A memory cell array, comprising a memory cell; A peripheral circuit is coupled to the memory cell array, the peripheral circuit comprising: A page buffer is coupled to the memory cell array, wherein the page buffer comprises: cache latch; a first data latch; and a second data latch; and control logic, coupled to the memory cell array, Wherein, the peripheral circuit is configured as follows: storing a first page of data in the cache latch; storing a previous page of data in the second data latch, and storing the first page of data in the first data latch; storing a second page of data in the cache latch; Programming memory cells of a first page of the memory cell array using the first page data; storing the first page data in the second data latch, and storing the second page data in the first data latch; and The memory cells of the second page of the memory cell array are programmed using the second page data.

19. The storage device according to claim 18, wherein: After storing the previous page data in the second data latch and storing the first page data in the first data latch, the peripheral circuit is further configured to: The previous page data in the second data latch is read out.

20. The storage device according to claim 19, wherein: After storing the previous page data in the second data latch and storing the first page data in the first data latch, the peripheral circuit is further configured to: The first page data in the first data latch is read out.

21. The storage device according to claim 19, wherein: The peripheral circuit is configured to read out the previous page data in the second data latch after programming memory cells of a second page of the memory cell array with the second page data.

22. The storage device according to claim 19, wherein: The peripheral circuit is configured to, in response to a programming failure of memory cells of the first page, read out the previous page data in the second data latch.

23. The storage device according to claim 18, wherein: The page buffer also includes a master latch, and the control logic is further configured to store the previous page data in the master latch.

24. The storage device according to claim 23, wherein: The peripheral circuit is configured to store the previous page data in the main latch after storing the second page data in the cache latch.

25. The storage device according to claim 23, wherein: When programming memory cells of a first page of the memory cell array using the first page data, the peripheral circuit is further configured to: disable the memory cells of the first page according to the previous page data in the master latch.

26. The storage device according to claim 23, wherein: The page buffer further includes: a bias latch, wherein the peripheral circuit is further configured as: Memory cells of the first page of the memory cell array are verified.

27. The storage device according to claim 26, wherein: The peripheral circuit is configured to verify that the memory cells of the first page of the memory cell array are after programming the memory cells of the first page of the memory cell array with the first page data.

28. The storage device according to claim 18, wherein: The peripheral circuit configured to program the memory cells of the first page of the memory cell array using the first page data is also configured to: instruct a word line driver to apply a first programming voltage to a first word line corresponding to the memory cells of the first page of the memory cell array according to the first page data.

29. The storage device according to claim 18, wherein: Each memory cell in the memory cell array is a single level cell (SLC).

30. A storage device comprising: A memory cell array, comprising a memory cell; as well as A peripheral circuit is coupled to the memory cell array, the peripheral circuit comprising: A page buffer coupled to the memory cell array, Wherein, the peripheral circuit is configured as follows: storing the previous page data and the first page data in the page buffer; Programming memory cells of a first page of the memory cell array using the first page data; storing the first page data and the second page data in the page buffer; and The memory cells of the second page of the memory cell array are programmed using the second page data.

31. A storage system comprising: Storage device; as well as A memory controller coupled to the memory device, wherein the memory device comprises: A memory cell array comprising memory cells; and A peripheral circuit, coupled to the memory cell array, comprises: a page buffer coupled to the memory cell array; Wherein, the memory controller is configured as: Sending a query command to the memory cell array to confirm whether the previous page of data is successfully programmed; and In response to the previous page data not being successfully programmed, a first read command is sent to read out the first page data and the previous page data in the page buffer.

32. The storage system according to claim 31, wherein: The memory controller is configured to send a second read command to read out one or more pages of data in the memory cells of the memory cell array in response to a previous page of data not being successfully programmed.

33. The storage system according to claim 31, wherein: After sending a first read command to read out one or more pages of data in the memory cells of the memory cell array, and sending a second read command to read out the first page of data in the first data latch and the previous page of data in the second data latch, the memory controller is further configured to: reallocating new physical addresses of corresponding memory cells of the memory cell array to the previous page data and the current page data of the page buffer and the one or more pages of data of the memory cell array; as well as The previous page data, the current page data, and the one or more pages of data are programmed into the memory cell array using the new physical address.

34. The storage system according to claim 31, wherein: After sending a first read command to read out one or more pages of data in the memory cells of the memory cell array, and sending a second read command to read out the first page of data and the previous page of data in the page buffer, the memory controller is further configured to: erasing a memory cell corresponding to a current physical address at which a current programming operation is performed; and The previous page data, the current page data, and the one or more pages of data are programmed into the memory cell array using the current physical address.

35. The storage system of claim 31, wherein: After sending a first read command to read out one or more pages of data in the memory cells of the memory cell array, and sending a second read command to read out the first page of data in the first data latch and the previous page of data in the second data latch, wherein the memory controller is further configured to: reallocating new physical addresses of corresponding memory cells of the memory cell array to the previous page data of the page buffer; and The previous page data is programmed into the memory cell array using the new physical address.

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