Memory operation method, memory and memory system

Abstract

The invention provides a memory operation method, a memory and a memory system, and relates to the technical field of memories. The memory comprises a memory cell array, and a memory cell in the memory cell array comprises a control grid electrode and a memory grid electrode which are connected with each other. The method comprises the following steps: applying a first voltage to a control gate of a selected memory cell in a memory cell array, applying a first programming voltage of a first duration to a memory gate of the selected memory cell, then performing verification operation on the selected memory cell, and when a verification operation result is that the selected memory cell does not pass the verification operation, executing a verification operation on the selected memory cell; a second programming voltage of a second duration is applied to the storage grid of the selected storage unit, the second duration is larger than the first duration, and / or the second programming voltage is larger than the first programming voltage. According to the method, the programming efficiency of the OTP storage unit is improved, and power leakage is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of memory technology, and in particular to a memory operation method, a memory, and a storage system. Background Art

[0002] One-Time Programmable (OTP) memory is a non-volatile memory that supports one-time programming and is widely used in memory chips such as flash memory and dynamic random access memory. OTP memory can only be programmed once, and the written data cannot be changed. It is usually used to store some important data that does not need to be modified.

[0003] The above information disclosed in this Background section is only for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute the prior art that is already known to one of ordinary skill in the art. Summary of the invention

[0004] The purpose of the present disclosure is to provide a memory operation method, a memory and a storage system.

[0005] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

[0006] According to one aspect of the present disclosure, a memory operation method is provided, wherein the memory comprises a memory cell array, wherein the memory cells in the memory cell array comprise connected control gates and storage gates, and the method comprises: applying a first voltage to the control gates of selected memory cells in the memory cell array; applying a first programming voltage of a first duration to the storage gates of the selected memory cells; performing a verification operation on the selected memory cells; and in response to a result of the verification operation being a failure, applying a second programming voltage of a second duration to the storage gates of the selected memory cells, wherein the second duration is greater than the first duration, and / or the second programming voltage is greater than the first programming voltage.

[0007] According to one embodiment of the present disclosure, in response to the result of the verification operation being failed, a second programming voltage of a second duration is applied to the storage gate of the selected storage cell, including: in response to the result of the verification operation being failed, the first duration is increased by a first predetermined step length to obtain the second step length, and / or, the first programming voltage is increased by a second predetermined step length to obtain the second programming voltage; and the second programming voltage of the second duration is applied to the storage gate of the selected storage cell.

[0008] According to one embodiment of the present disclosure, in response to the result of the verification operation being failed, a second programming voltage of a second duration is applied to the storage gate of the selected storage cell, including: obtaining a current programming count of the selected storage cell; in response to the result of the verification operation being failed, determining whether the current programming count of the selected storage cell is less than a preset programming count threshold; in response to determining that the current programming count of the selected storage cell is less than the preset programming count threshold, applying the second programming voltage of the second duration to the storage gate of the selected storage cell.

[0009] According to an embodiment of the present disclosure, applying a first programming voltage for a first duration to the storage gate of the selected storage cell includes: in response to determining that the current programming number of the selected storage cell is 0, obtaining the first programming voltage as a preset programming voltage, wherein the preset programming voltage is a programming voltage obtained through testing that can successfully program a preset proportion of storage gates; and applying the first programming voltage for the first duration to the storage gate of the selected storage cell.

[0010] According to an embodiment of the present disclosure, the memory cell array includes a memory cell pair having the same logical address, the memory cell pair including a memory cell and a redundant memory cell corresponding thereto; the method further includes: applying the first voltage to a control gate of a redundant memory cell corresponding to the selected memory cell; applying the first programming voltage of the first duration to a storage gate of the redundant memory cell; performing the verification operation on the redundant memory cell; and in response to determining that programming of the redundant memory cell has failed according to a result of the verification operation, applying the second programming voltage of the second duration to the storage gate of the redundant memory cell.

[0011] According to one embodiment of the present disclosure, the control gate of the selected memory cell is connected to a first word line, and the gate of the storage gate of the selected memory cell is connected to a second word line; applying a first voltage to the control gate of the selected memory cell in the memory cell array includes: applying the first voltage on the first word line within a first time period; applying a first programming voltage of a first duration to the storage gate of the selected memory cell includes: applying the first programming voltage of the first duration on the second word line within the first time period.

[0012] According to one embodiment of the present disclosure, the memory cell in the memory cell array also includes a first end connected to the control gate and a second end connected to the storage gate, and the control gate and the storage gate are both located between the first end and the second end; the first end of the selected memory cell is connected to a first bit line, and the second end of the selected memory cell is floating; applying a first voltage to the control gate of the selected memory cell in the memory cell array also includes: applying a ground voltage to the first bit line during the first time period.

[0013] According to an embodiment of the present disclosure, performing a verification operation on the selected storage cell includes: continuing to apply the first voltage to the first word line in a second time period after the first time period; and applying a verification voltage to the second word line in the second time period.

[0014] According to an embodiment of the present disclosure, performing a verification operation on the selected storage cell further includes: applying a ground voltage to the first bit line during the second time period.

[0015] According to one embodiment of the present disclosure, applying a second programming voltage for a second duration to the storage gate of the selected storage cell includes: continuing to apply the first voltage to the first word line in a third time period after the second time period; and applying the second programming voltage for the second duration to the second word line in the third time period.

[0016] According to an embodiment of the present disclosure, applying a second programming voltage of a second duration to the storage gate of the selected storage cell further includes: applying a ground voltage to the first bit line during the third time period.

[0017] According to one embodiment of the present disclosure, the control gates of unselected memory cells in the memory cell array are connected to a third word line, and the gates of the storage gates of the unselected memory cells are connected to a fourth word line; the method further includes: applying a second voltage to the third word line during the first time period, the second voltage being less than the first voltage; and applying a programming prohibition voltage to the fourth word line during the first time period.

[0018] According to an embodiment of the present disclosure, the first end of the unselected memory cell is connected to the second bit line, and the second end of the unselected memory cell is floating; the method also includes: in the first time period, applying a third voltage on the second bit line, and the third voltage is greater than the ground voltage.

[0019] According to another aspect of the present disclosure, a memory is provided, comprising: a memory cell array, wherein the memory cells in the memory cell array comprise connected control gates and storage gates; a peripheral circuit, wherein the peripheral circuit is coupled to the memory cell array and is configured to: apply a first voltage to the control gates of selected memory cells in the memory cell array; apply a first programming voltage of a first duration to the storage gates of the selected memory cells; perform a verification operation on the selected memory cells; and in response to a result of the verification operation being a failure, apply a second programming voltage of a second duration to the storage gates of the selected memory cells, wherein the second duration is greater than the first duration, and / or the second programming voltage is greater than the first programming voltage.

[0020] According to one embodiment of the present disclosure, the control gate of the selected memory cell is connected to a first word line, and the gate of the storage gate of the selected memory cell is connected to a second word line; the peripheral circuit includes a control circuit, a voltage generator, a word line driver and a bit line driver, wherein: the voltage generator is configured to generate a first voltage; the control circuit is configured to control the word line driver to apply the first voltage to the first word line within a first time period; the voltage generator is also configured to generate the first programming voltage; the control circuit is also configured to control the word line driver to apply the first programming voltage of the first duration to the second word line within the first time period.

[0021] According to one embodiment of the present disclosure, the memory cell in the memory cell array also includes a first end connected to the control gate and a second end connected to the storage gate, and the control gate and the storage gate are both located between the first end and the second end; the first end of the selected memory cell is connected to the first bit line, and the second end of the selected memory cell is floating; the control circuit is also configured to control the bit line driver to apply a ground voltage to the first bit line during the first time period.

[0022] According to one embodiment of the present disclosure, the voltage generator is also configured to generate a verification voltage; the control circuit is also configured to control the word line driver to continue applying the first voltage to the first word line in a second time period after the first time period; the control circuit is also configured to control the word line driver to apply the verification voltage to the second word line in the second time period.

[0023] According to an embodiment of the present disclosure, the control circuit is further configured to control the bit line driver to apply a ground voltage to the first bit line during the second time period.

[0024] According to one embodiment of the present disclosure, the voltage generator is also configured to generate a second programming voltage; the control circuit is also configured to control the word line driver to continue applying the first voltage to the first word line in a third time period after the second time period; the control circuit is also configured to control the word line driver to apply the second programming voltage of the second duration to the second word line in the third time period.

[0025] According to an embodiment of the present disclosure, the control circuit is further configured to control the bit line driver to apply a ground voltage to the first bit line during the third time period.

[0026] According to one embodiment of the present disclosure, the control gates of unselected memory cells in the memory cell array are connected to a third word line, and the gates of the storage gates of the unselected memory cells are connected to a fourth word line; the voltage generator is also configured to generate a second voltage, which is less than the first voltage; the control circuit is also configured to control the word line driver to apply the second voltage to the third word line within the first time period; the voltage generator is also configured to generate a programming prohibition voltage; the control circuit is also configured to control the word line driver to apply the programming prohibition voltage to the fourth word line within the first time period.

[0027] According to an embodiment of the present disclosure, the first end of the unselected memory cell is connected to the second bit line, and the second end of the unselected memory cell is floating; the voltage generator is also configured to generate a third voltage, and the third voltage is greater than the ground voltage; the control circuit is also configured to control the bit line driver to apply the third voltage on the second bit line during the first time period.

[0028] According to one embodiment of the present disclosure, the control circuit is also configured to increase the first time length by a first predetermined step length to obtain the second step length in response to the result of the verification operation being failed, and / or increase the first programming voltage by a second predetermined step length to obtain the second programming voltage.

[0029] According to one embodiment of the present disclosure, the control circuit is further configured to: obtain the current programming number of the selected storage cell; in response to the result of the verification operation being failed, determine whether the current programming number of the selected storage cell is less than a preset programming number threshold; in response to determining that the current programming number of the selected storage cell is less than the preset programming number threshold, apply the second programming voltage of the second duration to the storage gate of the selected storage cell.

[0030] According to one embodiment of the present disclosure, the control circuit is also configured to obtain the first programming voltage as a preset programming voltage in response to determining that the current programming number of the selected storage cell is 0, and the preset programming voltage is a programming voltage obtained through testing that can successfully program a preset proportion of storage gates.

[0031] According to an embodiment of the present disclosure, the memory cell array includes a memory cell pair having the same logical address, the memory cell pair including a memory cell and a redundant memory cell corresponding thereto; the control circuit is further configured to: apply the first voltage to the control gate of the redundant memory cell corresponding to the selected memory cell; apply the first programming voltage of the first duration to the storage gate of the redundant memory cell; perform the verification operation on the redundant memory cell; and in response to determining that the programming of the redundant memory cell has failed according to a result of the verification operation, apply the second programming voltage of the second duration to the storage gate of the redundant memory cell.

[0032] According to another aspect of the present disclosure, a memory is provided, comprising: a memory cell array; a peripheral circuit coupled to the memory cell array, the peripheral circuit comprising a fine-tuning circuit, the fine-tuning circuit comprising any one of the memories described above, and configured to perform fine-tuning operations on the memory cell array according to information stored in any one of the memories described above.

[0033] According to another aspect of the present disclosure, a storage system is provided, characterized by comprising any one of the above-mentioned memories and a controller coupled to the memory.

[0034] It is to be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The above and other objects, features and advantages of the present disclosure will become more apparent by describing in detail example embodiments thereof with reference to the attached drawings.

[0036] Figure 1 A block diagram showing an exemplary system with a memory according to an embodiment of the present disclosure is shown.

[0037] Figure 2A A block diagram of a memory system is shown as an example.

[0038] Figure 2B A block diagram of another memory system is shown as an example.

[0039] Figure 3 A schematic circuit diagram of a memory 300 including peripheral circuits provided in an embodiment of the present disclosure.

[0040] Figure 4A schematic diagram of a peripheral circuit provided in an embodiment of the present disclosure.

[0041] Figure 5 A schematic circuit diagram of an exemplary memory 500 including peripheral circuits is shown according to an exemplary embodiment.

[0042] Figure 6 A schematic diagram of a peripheral circuit provided in an embodiment of the present disclosure.

[0043] Figure 7 A schematic circuit diagram of an OTP memory 700 including a peripheral circuit provided in an embodiment of the present disclosure.

[0044] Figure 8 A schematic diagram of an OTP peripheral circuit provided in an embodiment of the present disclosure.

[0045] Fig. 9 The figure is a flow chart showing a memory operation method according to an exemplary embodiment.

[0046] Fig.10 Shows Fig. 9 FIG. 4 is a schematic diagram of the processing process of step S904 in one embodiment.

[0047] Fig.11 Shows Fig. 9 FIG. 5 is a schematic diagram of the processing process of step S908 in one embodiment.

[0048] Fig.12 Shows Fig. 9 FIG. 5 is a schematic diagram of the processing process of step S908 in another embodiment.

[0049] Fig.13A A programming voltage waveform with a stepped pulse width is shown as an example.

[0050] Fig. 13B A programming voltage waveform with stepped pulse height is shown as an example.

[0051] Fig.14 is a flowchart showing another memory operation method according to an exemplary embodiment.

[0052] Fig.15 Based on Figures 9 to 14 A schematic diagram of the program-verify operation flow of a memory is shown.

[0053] Fig.16 according to Figures 9 to 14 A schematic diagram of a flow chart of performing a programming operation on a selected memory cell in a first time period is shown.

[0054] Fig.17 according to Figures 9 to 14A schematic flow chart of performing a program inhibit operation on unselected memory cells in a first time period is shown.

[0055] Fig.18 is based on Fig.16 and Fig.17 The voltage waveforms of the selected memory cells and the unselected memory cells in the first programming stage are shown.

[0056] Fig.19 according to Figures 9 to 14 A schematic diagram of a flow chart of performing a verification operation on a selected storage unit in a second time period after the first time period is shown.

[0057] Fig. 20 is based on Fig.19 The voltage waveforms of the selected memory cells and the unselected memory cells in the verification stage are shown.

[0058] Fig.21 according to Figures 9 to 14 A schematic flow chart of performing a programming operation on a selected memory cell in a third time period after the second time period is shown.

[0059] Fig. 22 is based on Fig.21 The voltage waveforms of the selected memory cells and the unselected memory cells in the second programming stage are shown. DETAILED DESCRIPTION

[0060] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The accompanying drawings are only schematic illustrations of the disclosure and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted.

[0061] In addition, the described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, devices, steps, etc. may be adopted. In other cases, well-known structures, methods, devices, implementations or operations are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0062] In addition, the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. The symbol " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0063] In this disclosure, unless otherwise clearly specified and limited, terms such as "connection" should be understood in a broad sense, for example, it can be an electrical connection or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0064] Figure 1 A block diagram of an exemplary system with a memory in an embodiment of the present disclosure is shown. System 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality device, an augmented reality device, or any other suitable electronic device having a memory therein.

[0065] like Figure 1 As shown, the system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memories 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor) of an electronic device. The host 108 may be configured to send data to the memory 104 or receive data from the memory 104.

[0066] The memory 104 may be a non-volatile memory, a volatile memory, etc. The non-volatile memory may be a NAND flash memory (eg, a three-dimensional (3D) NAND flash memory). The volatile memory may be a dynamic random access memory (DRAM).

[0067] In some embodiments, the memory controller 106 is coupled to the memory 104 and the host 108 and is configured to control the memory 104. The memory controller 106 may manage data stored in the memory 104 and communicate with the host 108.

[0068] In some embodiments, the memory controller 106 is configured to send commands to the memory 104 to cause the memory 104 to read the information stored in the OTP memory when executed.

[0069] In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0070] In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment, such as a solid state drive (SSD) or an embedded multimedia card (eMMC), which can be used as data storage for mobile devices such as smartphones, tablet computers, laptop computers, etc., as well as enterprise storage arrays. The memory controller 106 can be configured to send commands to the memory 104 to cause the memory 104 to perform operations, such as read, erase, and program operations.

[0071] The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory 104 , including, but not limited to, bad block management, garbage collection, logical to physical address translation, wear leveling, and the like.

[0072] In some embodiments, the memory controller 106 is further configured to process error correction codes (ECC) on data read from or written to the memory 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 may communicate with an external device (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer mini interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0073] The memory controller 106 and the one or more memories 104 may be integrated into various types of storage devices, for example, included in the same package (eg, a universal flash storage (UFS) package or an eMMC package). That is, the memory system 102 may be implemented and packaged into different types of terminal electronic products.

[0074] Figure 2AA block diagram of a memory system is shown as an example. Figure 2A As shown, the memory controller 106 and the single memory 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (also known as a PCMCIA card, a Personal Computer Memory Card International Association card), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (e.g., an MMC card, an RS-MMC card, an MMCmicro card, etc.), an SD card (e.g., an SD card, a miniSD card, a microSD card, an SDHC card, etc.), a UFS card, etc. The memory card 202 may also include a computer that connects the memory card 202 to a host (e.g., Figure 1 A memory card connector 204 is coupled to the host 108 in the memory card connector.

[0075] Figure 2B FIG. 1 is a block diagram of another memory system. Figure 2B As shown, the memory controller 106 and the multiple memories 104 may be integrated into the SSD 206. The multiple memories 104 may include, for example, multiple NAND flash memories 1042 and one DRAM 1044. The SSD 206 may also include a host (e.g., Figure 1 In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0076] Figure 3 A schematic circuit diagram of a memory 300 including a peripheral circuit provided in an embodiment of the present disclosure. The memory 300 may be Figure 1 and Figure 2A Memory 104 in, or Figure 2B 1. The memory 300 may include a memory cell array 301 and a peripheral circuit 302 coupled to the memory cell array 301. The memory cell array 301 may be a NAND flash memory cell array, wherein the memory cells 306 are provided in the form of an array of memory strings 308 of the NAND flash memory, each memory string 308 extending vertically above a substrate (not shown).

[0077] In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 can hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 can be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0078] In some embodiments, each storage cell 306 can store 1 bit of data or 2 bits of data or more bits of data, that is, it can be a single-level cell (SLC) type, a multi-level cell (MLC) type, a triple-level cell (TLC) type, a quad-level cell (QLC) type or a higher level type.

[0079] like Figure 3 As shown, each memory string 308 may include a source select gate (SSG) 310 at its source terminal and a drain select gate (DSG) 312 at its drain terminal. SSG 310 and DSG 312 may be configured to activate the selected memory string 308 during read and program operations.

[0080] In some embodiments, the sources of the memory strings 308 in the same block 304 are coupled through the same source line (Source Line, SL) 314 (e.g., a common SL). For example, all memory strings 308 in the same block 304 have an array common source (Array Common Source, ACS). Figure 3 As shown, the memory string 308 can be organized into a plurality of blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each block 304 is a basic data unit for an erase operation, i.e., all memory cells 306 on the same block 304 are erased at the same time.

[0081] In some embodiments, the transistors of the DSG 312 of each memory string 308 are coupled to a corresponding bit line (BL) 316, and data can be read from or written to the bit line 316 via an output bus (not shown). Each memory string 308 can be configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistors having the DSG 312) or a deselection voltage (e.g., 0V) to the corresponding DSG 312 via one or more DSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistors having the SSG 310) or a deselection voltage (e.g., 0V) to the corresponding SSG 310 via one or more SSG lines 315.

[0082] like Figure 3As shown, the memory cells 306 of the memory string 308 may be coupled via a word line (WL) 318, which selects which row of memory cells 306 are affected by read and program operations. The peripheral circuit 302 may be coupled to the memory cell array 301 via a bit line 316, a word line 318, a source line 314, an SSG line 315, and a DSG line 313. The peripheral circuit 302 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory cell array 301 by applying a voltage signal and / or a current signal to each memory cell 306 that is the target of the operation and sensing a voltage signal and / or a current signal from each memory cell 306 that is the target of the operation via the bit line 316, the word line 318, the source line 314, the SSG line 315, and the DSG line 313. The peripheral circuit 302 may include various types of peripheral circuits formed using Metal-Oxide-Semiconductor (MOS) technology.

[0083] Figure 4 Schematic diagram of a peripheral circuit provided by an embodiment of the present disclosure. Figure 4 As shown, the peripheral circuit 302 may include a page buffer circuit / sense amplifier 404, a column decoder / BL driver 406, a row decoder / WL driver 408, a voltage generator 410, a control logic unit 412, a register 414, an input / output (I / O) circuit 416, and a data bus 418. It should be understood that in some examples, the peripheral circuit 302 may also include Figure 4 Additional peripheral circuits not shown.

[0084] In some embodiments, the page buffer circuit / sense amplifier 404 can be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to a control signal from the control logic unit 412. For example, the page buffer circuit / sense amplifier 404 can store a page of programming data (write data) to be programmed into the memory cell array 301. For another example, the page buffer circuit / sense amplifier 404 can also sense a low-power signal from the bit line 316 representing a data bit stored in the memory cell 306, and amplify a small voltage swing to a recognizable logic level in a read operation. The column decoder / BL driver 406 can be configured to be controlled by the control logic unit 412, and select one or more memory strings 308 by applying a bit line voltage generated from the voltage generator 410.

[0085] The row decoder / WL driver 408 may be configured to be controlled by the control logic unit 412, and select / deselect the block 304 of the memory cell array 301 and select / deselect the word line 318 of the block 304. The row decoder / WL driver 408 may also be configured to drive the word line 318 using the word line voltage generated from the voltage generator 410. In some embodiments, the row decoder / WL driver 408 may also select / deselect and drive the SSG line 314 and the DSG line 313. The voltage generator 410 may be configured to be controlled by the control logic unit 412, and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a local voltage, a verification voltage, etc.), a bit line voltage, a source line voltage, etc. to be supplied to the memory cell array 301.

[0086] The control logic unit 412 may be coupled to each portion of the peripheral circuit 302 and configured to control the operation of each portion. The register 414 may be coupled to the control logic unit 412 and may include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The input / output circuit 416 may be coupled to the control logic unit 412 and act as a control buffer to buffer the input / output information from the host ( Figure 4 The input / output circuit 416 may also be coupled to the column decoder / bit line driver 406 via the data bus 418 and act as a data I / O interface and data buffer to buffer data and relay it to or from the memory cell array 301.

[0087] In some embodiments, the peripheral circuit 302 may include a fine-tuning circuit ( Figure 3 (not shown in the figure), the fine-tuning circuit can be coupled to a specific module in the peripheral circuit 302 to implement the fine-tuning function under the control of the control logic unit 412. For example, the voltage generator 410 can be provided with a fine-tuning circuit to fine-tune the generated voltage. For another example, the input / output circuit 416 can also be provided with a fine-tuning circuit to fine-tune the input / output signal. The peripheral circuit 302 can also include an OTP memory 420, which can be coupled to the control logic unit 412 to store information that does not need to be changed. The control logic unit 412 can perform corresponding fine-tuning operations according to the information stored in the OTP memory 420 to implement the fine-tuning function.

[0088] Figure 5A schematic circuit diagram of an exemplary memory 500 including a peripheral circuit is shown according to an exemplary embodiment. The memory 500 may be Figure 1 and Figure 2A Memory 104 in, or Figure 2B 1044 in an example. The memory 500 may include a memory cell array 501 and a peripheral circuit 502 coupled to the memory cell array 501. The memory cell array 501 may include one or more memory banks 504. Each memory bank 504 includes a word line 514 (e.g., WL1, WL2, WL3 ... WLm), a bit line 516 (e.g., BL1, BL2, BL3 ... BLn), and a cross-point device 508 formed between the word line 514 and the bit line 516. In some embodiments, each cross-point device 508 may include a DRAM cell of a paired transistor and a capacitor. In order to operate each memory bank 504 of the memory cell array 501, a word line voltage (V WL ), and a bit line voltage (V BL ).

[0089] Figure 6 Schematic diagram of a peripheral circuit provided by an embodiment of the present disclosure. Figure 6 As shown, the peripheral circuit 502 may include a row decoder / word line (WL) driver 602, a page buffer / sense amplifier 604, a column decoder / bit line (BL) driver 606, a register 608, a control logic unit 610, and an input / output (I / O) circuit 612, etc. It should be understood that in some embodiments, the peripheral circuit 502 may also include Figure 6 Additional peripheral circuits not shown.

[0090] The row decoder / word line (WL) driver 602 may be configured to be controlled by the control logic unit 610 and the word line 514 of the selected bank 504 of the memory cell array 501. The row decoder / word line driver 602 may also be configured to drive the selected word line 514.

[0091] The page buffer / sense amplifier 604 may be configured to read data from the memory cell array 501 and program (write) data to the memory cell array 501 according to a control signal from the control logic unit 610. In some embodiments, the page buffer / sense amplifier 604 may store a page of programming data (write data) to be programmed into the memory cell array 601. In other embodiments, the page buffer / sense amplifier 604 may perform a program verification operation to ensure that the data has been correctly programmed into the cross-point device 508 coupled to the selected word line 514. In yet other embodiments, the page buffer / sense amplifier 604 may also sense a low-power signal from the bit line 516 (which represents a data bit stored in the cross-point device 508) in a read operation and amplify the small voltage swing to a recognizable logic level.

[0092] The column decoder / bit line (BL) driver 606 may be configured to be controlled by the control logic unit 610 and select one or more cross point devices 508. The input / output (I / O) circuit 612 may be coupled to the page buffer / sense amplifier 604 and / or the column decoder / bit line driver 606 and may be configured to receive and receive data from the bus ( Figure 6 The data inputted by the memory cell array 501 is directed (routed) to a desired memory cell region (e.g., Figure 6 One or more memory banks 504 in the memory cell area, and directing (routing) data output from a desired memory cell area to a bus.

[0093] In some embodiments, the peripheral circuit 502 may include a fine-tuning circuit ( Figure 5 (not shown in the figure), the fine-tuning circuit can be coupled to a specific module in the peripheral circuit 502 to implement the fine-tuning function under the control of the control logic unit 610. For example, the fine-tuning circuit can be coupled to the row decoder / word line driver 602 to fine-tune the control operation of the word line. For another example, the input / output circuit 610 can be provided with a fine-tuning circuit to fine-tune the input / output signal. The peripheral circuit 502 can also include an OTP memory 614 coupled to the control logic unit 610 to store information that does not need to be changed. The control logic unit 610 can perform corresponding fine-tuning operations according to the information stored in the OTP memory 614 to implement the fine-tuning function.

[0094] Figure 7 A schematic circuit diagram of an OTP memory 700 including a peripheral circuit provided in an embodiment of the present disclosure. The OTP memory 700 may be Figure 4 OTP memory 420, Figure 6700 may include an OTP memory cell array 701 and an OTP peripheral circuit 702 coupled to the OTP memory cell array 701. A memory cell 704 in the OTP memory cell array 701 may include a control transistor 7042 and a storage transistor 7044 connected to each other. The gate of the control transistor 7042 is a control gate, and the gate of the storage transistor 7044 is a storage gate. The control gate and the storage gate are respectively connected to word lines (e.g., WL1, WL2, ..., WLj in the figure) and are controlled by word line voltages.

[0095] In some embodiments, the OTP peripheral circuit 702 is configured to execute the memory operation method provided in the embodiment of the present disclosure. It is understood that the OTP peripheral circuit 702 can be configured to execute the memory operation method provided in the embodiment of the present disclosure according to the instruction received from the memory controller 106.

[0096] In some embodiments, the memory cell 704 may further include a first end connected to the control gate (for example, the drain of the control transistor 7042) and a second end connected to the storage gate (for example, the source of the storage transistor 7044), and the control gate and the storage gate are both located between the first end and the second end. The first end of the memory cell 704 is connected to the bit line (for example, BL1, BL2, ..., BLi in the figure) and is controlled by the bit line voltage. The second end of the memory cell 704 is floating. In the case where the first end of the memory cell 704 is the drain of the control transistor 7042 and the second end of the memory cell 704 is the source of the storage transistor 7044 (this case is used as an example in the embodiments of the present disclosure, but is not limited thereto), the source of the control transistor 7042 is connected to the drain of the storage transistor 7044.

[0097] In some embodiments, there may be multiple memory cells connected to one bit line and one word line, and each of the memory cells may be connected to one data line (DL). Figure 7 (not shown in the figure), when performing operations such as programming and verification on the memory cell, a ground voltage may be applied to the corresponding DL.

[0098] In some embodiments, the storage gate may be an anti-fuse gate, and the selected memory cell may be programmed by applying a high voltage to a word line connected to the anti-fuse gate to break down the storage transistor of the selected memory cell.

[0099] Figure 8 Schematic diagram of an OTP peripheral circuit provided by an embodiment of the present disclosure. Figure 4As shown, the OTP peripheral circuit 702 may include a page buffer circuit / sense amplifier 804, a column decoder / BL driver 806, a row decoder / WL driver 808, a voltage generator 810, and a control circuit 812. It should be understood that in some examples, the OTP peripheral circuit 702 may also include a page buffer circuit / sense amplifier 804, a column decoder / BL driver 806, a row decoder / WL driver 808, a voltage generator 810, and a control circuit 812. Figure 8 Additional peripheral circuits not shown.

[0100] In some embodiments, the page buffer circuit / sense amplifier 804 may be configured to read data from the OTP memory cell array 701 and program (write) data to the OTP memory cell array 701 according to a control signal from the control circuit 812. For example, the page buffer circuit / sense amplifier 804 may store programming data (write data) to be programmed into the OTP memory cell array 301. For another example, the page buffer circuit / sense amplifier 804 may also sense a low-power signal representing a data bit stored in the memory cell 704 from the bit lines BL1 to BLi in the OTP memory cell array 701, and amplify a small voltage swing to a recognizable logic level in a read operation. The column decoder / BL driver 806 may be configured to be controlled by the control circuit 812, and select the corresponding memory cell 704 by applying a bit line voltage generated from the voltage generator 810.

[0101] The row decoder / WL driver 808 may be configured to be controlled by the control circuit 812, and select / deselect the word line of the control transistor 7042 of the memory cell 704 (e.g., WL1, WL4, WL5 in the OTP memory cell array 701). The row decoder / WL driver 808 may also be configured to drive the word line of the storage transistor 7044 of the memory cell 704 (e.g., WL2, WL3, WLj in the OTP memory cell array 701) using the word line voltage generated from the voltage generator 810. The voltage generator 810 may be configured to be controlled by the control circuit 812, and generate the word line voltage (e.g., read voltage, program voltage, verification voltage, program inhibit voltage, etc.), the bit line voltage, etc. to be supplied to the OTP memory cell array 701.

[0102] In some embodiments, the OTP memory cell array 701 may include memory cell pairs having the same logical address ( Figure 7 and Figure 8 ), the memory cell pair includes a memory cell 704 and a corresponding redundant memory cell. Based on the same logical address of the memory cell 704 and the corresponding redundant memory cell, the control circuit 812 can control the row decoder / WL driver 808, the voltage generator 810, the column decoder / BL driver 806, etc. to perform the same operation on the memory cell 704 and the corresponding redundant memory cell.

[0103] Fig. 9 FIG. 1 is a flow chart of a memory operation method according to an exemplary embodiment. Fig. 9 The method shown can be applied, for example, to Figure 8 The OTP memory of the OTP peripheral circuit shown is used to program the OTP memory cell array.

[0104] refer to Fig. 9 , the method 90 provided in the embodiment of the present disclosure may include the following steps S902 to S908.

[0105] In step S902 , a first voltage is applied to a control gate of a selected memory cell in a memory cell array.

[0106] In some embodiments, the first voltage may be a turn-on voltage of a control gate of a selected memory cell, for example, 2.5V, 3.0V, 3.5V, etc. The OTP peripheral circuit may be configured to generate the first voltage through a voltage generator, and the control circuit controls a word line driver to apply the first voltage to a first word line connected to the control gate of the selected memory cell, so as to turn on a control transistor of the selected memory cell, thereby turning on the connection between the drain of the memory transistor of the selected memory cell and the first bit line.

[0107] In step S904 , a first programming voltage of a first duration is applied to the storage gate of the selected memory cell.

[0108] In some embodiments, applying the first programming voltage for the first duration may be applying a programming pulse, the width of the pulse being the first duration, and the height of the pulse being the first programming voltage. The first programming voltage may be the breakdown voltage of the storage gate of the selected storage cell, for example, 6V, 6.5V, 7.0V, etc. The first duration and the first programming voltage actually used may be set according to the current programming times, and the implementation in some exemplary embodiments may refer to Fig.10 .

[0109] In some embodiments, the OTP peripheral circuit can be configured to generate a first programming voltage through a voltage generator, control a word line driver by a control circuit to apply a first programming voltage of a first duration to a second word line connected to a storage gate of a selected storage cell, and apply a ground voltage to a first bit line through a bit line driver to form a high voltage difference between the gate and the drain of a storage transistor of the selected storage cell to break down the storage transistor.

[0110] In step S906, a verification operation is performed on the selected storage unit.

[0111] In some embodiments, the first voltage may continue to be applied to the first word line connected to the control gate of the selected memory cell, the ground voltage may continue to be applied to the first bit line connected to the first end of the selected memory cell, and a verification voltage may be applied to the second word line connected to the storage gate of the selected memory cell to perform a verification operation on the selected memory cell. The magnitude of the verification voltage may be selected according to the actual situation of the storage gate.

[0112] In step S908, in response to the verification operation failing, a second programming voltage of a second duration is applied to the storage gate of the selected storage cell, wherein the second duration is greater than the first duration and / or the second programming voltage is greater than the first programming voltage.

[0113] In some embodiments, if the result of the verification operation is failure, the next programming pulse can be applied to the storage gate of the selected storage cell while applying a first voltage to the control gate of the selected storage cell to turn on the control transistor, and the probability of successful programming can be increased by increasing the width and / or height of the pulse.

[0114] In some embodiments, if the result of the verification operation is passed, the next memory cell may be selected for programming, thereby avoiding applying too many times of high voltage to the memory cell whose gate is connected to the first word line.

[0115] According to the memory operation method provided by the embodiment of the present disclosure, a first voltage is applied to the control gate of a selected memory cell in a memory cell array, a first programming voltage of a first duration is applied to the memory gate of the selected memory cell, and then a verification operation is performed on the selected memory cell. When the result of the verification operation is failure, a second programming voltage of a second duration is applied to the memory gate of the selected memory cell, wherein the second duration is greater than the first duration, and / or the second programming voltage is greater than the first programming voltage. Through the verification step after programming, a targeted increase in the programming pulse width / height is achieved, and programming can be stopped when the verification passes, thereby improving the programming efficiency of the OTP memory cell while ensuring successful programming, reducing the application of high voltage to the OTP memory cell, alleviating the pressure on the OTP memory cell, and reducing the power leakage of the OTP memory.

[0116] Fig.10 Shows Fig. 9 The processing process of step S904 in one embodiment is shown in FIG. Fig.10 As shown, in the embodiment of the present disclosure, the above step S904 may further include the following steps S1002 to S1004.

[0117] Step S1002 , in response to determining that the current programming times of the selected memory cell is 0, obtaining a first programming voltage as a preset programming voltage, wherein the preset programming voltage is a programming voltage obtained through testing to successfully program a preset proportion of memory gates.

[0118] In some embodiments, when programming a memory cell, it may not be possible to program by applying a programming pulse only once. A counting module may be set to record the current programming times of the memory cell. When it is determined that the current programming times recorded by the counting module corresponding to the selected memory cell is 0, that is, this programming is the first programming of the selected memory cell, the preset programming voltage of the programming voltage of the memory gate that can successfully program a preset proportion obtained in the test can be used as the first programming voltage. For example, if the programming voltage of 80% of the memory gates that can be successfully programmed obtained in the test is 6V, the programming voltage of 85% of the memory gates that can be successfully programmed is 6.5V, and the programming voltage of 90% of the memory gates that can be successfully programmed is 7.0V, 6V that can successfully program 80% of the memory gates can be selected as the first programming voltage to minimize the voltage applied to the unselected memory cells connected to the second word line.

[0119] Step S1004 , applying a first programming voltage of a first duration to the storage gate of the selected storage cell.

[0120] In some embodiments, the first duration may also be the shortest pulse width obtained in a test that can successfully program a preset proportion of storage gates by applying a corresponding preset programming voltage, thereby also shortening the time for applying a high voltage to unselected storage cells connected to the second word line.

[0121] According to the method provided in the embodiment of the present disclosure, when the selected memory cell is programmed for the first time, the preset programming voltage obtained in the test that can successfully program a preset proportion of the memory gates can be used as the first programming voltage, and the shortest pulse width that can successfully program a preset proportion of the memory gates by applying the corresponding preset programming voltage can be used to minimize the magnitude and time of the voltage applied to the unselected memory cells connected to the same word line, thereby avoiding to a certain extent device aging caused by multiple application of high voltages to the unselected memory cells when some selected memory cells are difficult to break down and need to be programmed multiple times.

[0122] Fig.11 Shows Fig. 9 The processing process of step S908 in one embodiment is shown in FIG. Fig.11 As shown, in the embodiment of the present disclosure, the above step S908 may further include the following steps S1102 to S1106.

[0123] Step S1102, obtaining the current programming times of the selected memory cell.

[0124] Step S1104 , in response to the result of the verification operation being failed, determining whether the current programming count of the selected memory cell is less than a preset programming count threshold.

[0125] Step S1106 , in response to determining that the current programming count of the selected memory cell is less than a preset programming count threshold, applying a second programming voltage of a second duration to the storage gate of the selected memory cell.

[0126] In some embodiments, a preset programming times threshold value may be set for the total programming times of a storage cell. In the case where the result of the verification operation after programming the selected storage cell once is not passed, if it is determined that the current programming times recorded by the counting module corresponding to the selected storage cell does not exceed the preset programming times threshold value, the next programming operation may be continued for the selected storage cell to increase the probability of successful programming of the selected storage cell.

[0127] In other embodiments, when the result of the verification operation after programming the selected memory cell once is failed, if it is determined that the current programming number of the selected memory cell is not less than (for example, equal to) a preset programming number threshold, programming of the selected memory cell can be stopped and the programming failure of the memory cell can be recorded to avoid applying excessive high voltage to the memory cells connected on the same word line.

[0128] According to the method provided in the embodiment of the present disclosure, by setting a preset programming number threshold for the total programming number of times for a memory cell, when the result of the verification operation after programming the selected memory cell once is failed, programming is continued only when it is determined that the current programming number does not exceed the preset programming number threshold, thereby improving the programming success rate while avoiding applying excessive high voltage to the OTP memory.

[0129] Fig.12 Shows Fig. 9 FIG. 1 is a schematic diagram of the processing process of step S908 in another embodiment. Fig.12 As shown, in the embodiment of the present disclosure, the above step S908 may further include the following steps S1202 to S1204.

[0130] Step S1202, in response to the verification operation failing, increasing the first time length by a first predetermined step length to obtain a second step length, and / or increasing the first programming voltage by a second predetermined step length to obtain a second programming voltage.

[0131] Step S1204: applying a second programming voltage of a second duration to the storage gate of the selected memory cell.

[0132] In some embodiments, when the result of the verification operation after programming the selected memory cell once is not passed, a stepping programming operation with increasing pulse width and / or height may be performed on the selected memory cell. Fig.13A and Fig. 13B according to Fig.12 Two exemplary programming voltage waveforms are shown.

[0133] Fig.13A An example of a programming voltage waveform with a stepped pulse width is shown. Fig.13A As shown, the pulses from left to right represent programming pulses applied on the word line connected to the storage gate of the selected memory cell from the first programming to the Pmax (corresponding to the preset programming number threshold) programming, wherein the height of the pulse applied each time is the same, the pulse width of the first programming is W, and the pulse width increases by step (corresponding to the first predetermined step length) each time from the first programming to the Pmax programming.

[0134] Fig. 13B An example of a programming voltage waveform with a step pulse height is shown. Fig. 13B As shown, the pulses from left to right represent programming pulses applied on the word line connected to the storage gate of the selected memory cell from the first programming to the Pmax-th programming, wherein the width of the pulse applied each time is the same, the height of the first programming pulse is V, and the pulse height increases by step' (corresponding to the second predetermined step length) each time from the first programming to the Pmax-th programming.

[0135] It should be understood that the number of times each memory cell is programmed is determined by the verification result after each programming, and may be any number from 1 to Pmax. Fig.13A and Fig. 13B The waveforms in the figure are for illustration only. In actual application, both the pulse width and the pulse height can be stepped.

[0136] According to the method provided in the embodiment of the present disclosure, by using a step programming method of stepping pulse width and / or height, the probability of successful programming next time can be increased when the previous programming is unsuccessful, thereby improving the programming efficiency of the OTP storage unit.

[0137] Fig.14 FIG. 1 is a flow chart showing another memory operation method according to an exemplary embodiment. Fig.14 The method shown can be applied, for example, to Figure 8 The OTP memory of the OTP peripheral circuit shown is used to program the selected memory cell and its corresponding redundant memory cell in the OTP memory cell array.

[0138] refer to Fig.14, the method 140 provided in the embodiment of the present disclosure may include the following steps S1402 to S1408.

[0139] In step S1402, a first voltage is applied to control gates of a selected memory cell and its corresponding redundant memory cell in a memory cell array.

[0140] In step S1404, a first programming voltage of a first duration is applied to the storage gates of the selected memory cell and its corresponding redundant memory cell.

[0141] In step S1406, a verification operation is performed on the selected storage unit and its corresponding redundant storage unit.

[0142] In some embodiments, the selected memory cell and its corresponding redundant memory cell have the same logical address, so the voltage applied in the programming operation and the verification operation on the selected memory cell and its corresponding redundant memory cell is the same. In steps S1402 to S1406, the time for operating the selected memory cell and the time for operating the corresponding redundant memory cell may be different. Taking step S1402 as an example, for example, the first voltage may be applied to the control gate of the selected memory cell, the first voltage may be applied to the control gate of the corresponding redundant memory cell, and so on.

[0143] In step S1408, in response to the result of the verification operation of the selected memory cell and / or the corresponding redundant memory cell being failed, a second programming voltage of a second duration is applied to the storage gates of the selected memory cell and the corresponding redundant memory cell, wherein the second duration is greater than the first duration, and / or the second programming voltage is greater than the first programming voltage.

[0144] In some embodiments, when verification operations on the selected memory cell and the corresponding redundant memory cell fail, a second programming voltage of a second duration may be applied to the storage gates of the selected memory cell and the corresponding redundant memory cell, that is, programming is stopped if one of the selected memory cell and the redundant memory cell is successfully programmed. This can reduce the number of times a high voltage is applied to the memory cells connected to the same word line while ensuring that at least one of the selected memory cell and the corresponding redundant memory cell is successfully programmed.

[0145] In other embodiments, when one of the verification operations of the selected memory cell and the corresponding redundant memory cell fails, a second programming voltage of a second duration can be applied to the storage gates of the selected memory cell and its corresponding redundant memory cell, thereby ensuring that programming is successful in both the selected memory cell and the corresponding redundant memory cell, thereby realizing the redundant storage function of the OTP memory.

[0146] Fig.15 Based on Figures 9 to 14 FIG. 1 is a schematic diagram of a memory programming-verification operation flow chart. Fig.15 The process shown may include the following steps S1502 to S1522.

[0147] Step S1502, the process starts.

[0148] Step S1504, obtaining a first address, selecting a storage unit and its corresponding redundant storage unit. The first address may be the first address among a plurality of addresses to be programmed, and each address may point to a storage unit pair.

[0149] Step S1506 , for the selected memory cell and its corresponding redundant memory cell, initialize the programming times X, and obtain the values ​​of programming pulse parameters W and V.

[0150] Step S1508, performing programming and verification operations on the selected memory cell and its corresponding redundant memory cell. The implementation method may refer to step S902, step S904 and step S1406.

[0151] Step S1510, determining whether the verification result is passed. The implementation method may refer to step S1408.

[0152] Step S1512: if the verification result is passed (eg, logic "1"), it is determined whether the current programming address is the last address among the multiple addresses to be programmed.

[0153] Step S1514, if the current programming address is not the last address among the multiple addresses to be programmed, then obtain the next programming address (second address) and return to step S1506.

[0154] Step S1516: If the current programming address is the last address among the multiple addresses to be programmed, the programming is successful and the process ends.

[0155] Step S1518, if the verification result of step S1510 is not passed (for example, logic "0"), it is determined whether the current programming number X is Pmax.

[0156] Step S1520: If the current programming number X is not Pmax, then update the current programming number X=X+1, update the programming pulse parameters W=W+1 and / or V=V+1, and return to step S1508. The implementation method may refer to step S908, Fig.12 , Fig.13A and Fig. 13B .

[0157] Step S1522: if the current programming number X is Pmax, the programming fails and the process ends.

[0158] According to the programming-verification process provided in the embodiment of the present disclosure, the process can be executed in the form of a state machine when programming the OTP memory. Without adding additional overhead and ensuring successful programming, the programming efficiency of the OTP memory cell can be improved, the programming time of the OTP memory cell can be shortened, the high voltage applied to the OTP memory cell can be reduced, the high current passing through the OTP memory can be reduced, and the power leakage of the OTP memory can be reduced.

[0159] In some embodiments, the control gate of the selected memory cell is connected to the first word line, the gate of the storage gate of the selected memory cell is connected to the second word line, and the first end of the selected memory cell is connected to the first bit line. The control gates of the unselected memory cells are connected to the third word line, the gates of the storage gates of the unselected memory cells are connected to the fourth word line, and the first ends of the unselected memory cells are connected to the second bit line. Figures 16 to 22 This is shown as an example Figures 9 to 14 Implementation methods and voltage waveforms of programming and verification operations in FIG.

[0160] Fig.16 according to Figures 9 to 14 FIG. 1 is a flow chart showing a process of programming a selected memory cell in a first time period. Fig.16 , the method 16 provided in the embodiment of the present disclosure may include the following steps S1602 to S1606.

[0161] In step S1602, a first voltage is applied to a first word line in a first time period.

[0162] In step S1604, within a first time period, a first programming voltage of a first duration is applied to the second word line.

[0163] In step S1606, a ground voltage is applied to the first bit line in a first time period.

[0164] Fig.17 according to Figures 9 to 14 FIG. 1 is a flow chart showing a process of performing a program inhibit operation on unselected memory cells in a first time period. Fig.17 , the method 17 provided in the embodiment of the present disclosure may include the following steps S1702 to S1706.

[0165] In step S1702, within a first time period, a second voltage is applied to the third word line, where the second voltage is lower than the first voltage.

[0166] In some embodiments, the second voltage may be a ground voltage (0V) or 0.5V, etc., that is, there is no need to turn on the control transistors of the unselected memory cells.

[0167] In step S1704, a program inhibit voltage is applied to the fourth word line during a first period of time.

[0168] In some embodiments, the program inhibition voltage may be much smaller than the first program voltage, such as 1V, 1.05V, 1.1V, etc., to avoid a high voltage difference between the gate and the drain of the storage transistor of the unselected memory cell.

[0169] In step S1706, within the first time period, a third voltage is applied to the second bit line, and the third voltage is greater than the ground voltage.

[0170] According to the method provided by the embodiment of the present disclosure, by applying a second voltage less than the turn-on voltage to the third word line connected to the control gate of the unselected memory cell during the first time period for programming the selected memory cell, applying a programming inhibition voltage less than the first programming voltage to the fourth word line connected to the storage gate of the unselected memory cell, and applying a third voltage greater than the ground voltage to the second bit line connected to the first end of the unselected memory cell, it is possible to effectively avoid the formation of a high voltage difference between the gate and the drain of the storage transistor of the unselected memory cell, thereby achieving programming inhibition of the unselected memory cell.

[0171] Fig.18 is based on Fig.16 and Fig.17 The voltage waveform diagram of the selected memory cell and the unselected memory cell in the first programming stage is shown. Fig.18 As shown, in the first time period Tpgm1, a first voltage V1 is applied to the first word line (selected CG WL) connected to the control gate of the selected memory cell, a first programming voltage Vpgm1 is applied to the second word line (selected MG WL) connected to the storage gate of the selected memory cell, and a ground voltage is applied to the first bit line (selected BL) connected to the first end of the selected memory cell, so as to implement the programming operation on the selected memory cell. Also in the first time period Tpgm1, a ground voltage (second voltage) is applied to the third word line (unselected CG WL) connected to the control gate of the unselected memory cell, a programming inhibition voltage Vpass is applied to the fourth word line (unselected MG WL) connected to the storage gate of the unselected memory cell, and a third voltage V3 is applied to the second bit line (unselected BL) connected to the first end of the unselected memory cell, so as to implement the programming inhibition operation on the unselected memory cell.

[0172] Fig.19 according to Figures 9 to 14 FIG. 1 is a flow chart showing a verification operation performed on a selected storage unit in a second time period after a first time period. Fig.19 , the method 19 provided in the embodiment of the present disclosure may include the following steps S1902 to S1906.

[0173] In step S1902, during the second time period, the first voltage continues to be applied to the first word line.

[0174] In step S1904, a verification voltage is applied to the second word line in a second time period.

[0175] In step S1906, during the second time period, a ground voltage is applied to the first bit line.

[0176] Fig. 20 is based on Fig.19 The voltage waveform diagram of the selected memory cell and the unselected memory cell in the verification stage is shown. Fig.19 As shown, in the second time period Tverf, the first voltage V1 is continuously applied to the first word line (selected CG WL) connected to the control gate of the selected memory cell, the verification voltage Vread is applied to the second word line (selected MG WL) connected to the storage gate of the selected memory cell, and the ground voltage is applied to the first bit line (selected BL) connected to the first end of the selected memory cell, so as to implement the verification operation of the selected memory cell. Also in the second time period Tverf, the ground voltage (second voltage) is continuously applied to the third word line (unselected CG WL) connected to the control gate of the unselected memory cell, the programming inhibition voltage Vpass is continuously applied to the fourth word line (unselected MG WL) connected to the storage gate of the unselected memory cell, and the third voltage V3 is continuously applied to the second bit line (unselected BL) connected to the first end of the unselected memory cell, so as to implement the programming (and verification) inhibition operation of the unselected memory cell.

[0177] Fig.21 according to Figures 9 to 14 FIG. 1 is a flow chart showing a process of performing a programming operation on a selected memory cell in a third time period after the second time period. Fig.21 , the method 21 provided in the embodiment of the present disclosure may include the following steps S2102 to S2106.

[0178] In step S2102, in a third time period, the first voltage continues to be applied to the first word line.

[0179] In step S2104, within a third time period, a second programming voltage of a second duration is applied to the second word line.

[0180] In step S2106, during a third period of time, a ground voltage is applied to the first bit line.

[0181] Fig. 22 is based on Fig.21 The voltage waveform diagram of the selected memory cell and the unselected memory cell in the second programming stage is shown. Fig. 22As shown, in the second programming stage, i.e., the third time period Tpgm2, the first voltage V1 is continuously applied to the first word line (selected CG WL) connected to the control gate of the selected memory cell, the second programming voltage Vpgm2 is applied to the second word line (selected MG WL) connected to the storage gate of the selected memory cell, and the ground voltage is continuously applied to the first bit line (selected BL) connected to the first end of the selected memory cell, so as to implement the programming operation on the selected memory cell. Also in the third time period Tpgm2, the ground voltage (second voltage) is continuously applied to the third word line (unselected CG WL) connected to the control gate of the unselected memory cell, the programming inhibition voltage Vpass is continuously applied to the fourth word line (unselected MG WL) connected to the storage gate of the unselected memory cell, and the third voltage V3 is continuously applied to the second bit line (unselected BL) connected to the first end of the unselected memory cell, so as to implement the programming inhibition operation on the unselected memory cell.

[0182] The exemplary embodiments of the present disclosure are specifically shown and described above. It should be understood that the present disclosure is not limited to the detailed structures, configurations or implementations described herein; on the contrary, the present disclosure is intended to cover various modifications and equivalent configurations included in the spirit and scope of the appended claims.

Claims

1. A memory operation method, characterized in that: The memory comprises a memory cell array, wherein a memory cell in the memory cell array comprises a control gate and a memory gate connected to each other, and the method comprises: applying a first voltage to a control gate of a selected memory cell in the memory cell array; Applying a first programming voltage of a first duration to a storage gate of the selected storage cell; performing a verification operation on the selected storage unit; In response to a failure of the verification operation, a second programming voltage of a second duration is applied to the storage gate of the selected storage cell, wherein the second duration is greater than the first duration and / or the second programming voltage is greater than the first programming voltage.

2. The method according to claim 1, characterized in that: In response to a result of the verification operation being a failure, applying a second programming voltage for a second duration to the storage gate of the selected storage cell comprises: In response to a result of the verification operation being failed, increasing the first time duration by a first predetermined step length to obtain the second step length, and / or increasing the first programming voltage by a second predetermined step length to obtain the second programming voltage; The second programming voltage is applied to the storage gate of the selected memory cell for the second duration.

3. The method according to claim 1 or 2, characterized in that: In response to a result of the verification operation being a failure, applying a second programming voltage for a second duration to the storage gate of the selected storage cell comprises: Obtaining the current programming count of the selected storage unit; In response to a result of the verification operation being a failure, determining whether a current programming count of the selected memory cell is less than a preset programming count threshold; In response to determining that the current programming number of the selected memory cell is less than a preset programming number threshold, the second programming voltage of the second duration is applied to the storage gate of the selected memory cell.

4. The method according to claim 3, characterized in that Applying a first programming voltage for a first duration to the storage gate of the selected storage cell comprises: In response to determining that the current programming number of the selected memory cell is 0, obtaining the first programming voltage as a preset programming voltage, wherein the preset programming voltage is a programming voltage obtained through testing to successfully program a preset proportion of memory gates; The first programming voltage is applied to the storage gate of the selected memory cell for the first duration.

5. The method according to any one of claims 1 to 4, characterized in that: The memory cell array includes a memory cell pair having the same logical address, and the memory cell pair includes a memory cell and a redundant memory cell corresponding thereto; The method further comprises: Applying the first voltage to a control gate of a redundant memory cell corresponding to the selected memory cell; Applying the first programming voltage of the first duration to the storage gate of the redundant memory cell; performing the verification operation on the redundant storage unit; In response to determining that the redundant memory cell fails in programming according to the result of the verification operation, applying the second programming voltage for the second duration to the storage gate of the redundant memory cell.

6. The method according to any one of claims 1 to 5, characterized in that The control gate of the selected memory cell is connected to a first word line, and the gate of the storage gate of the selected memory cell is connected to a second word line; Applying a first voltage to a control gate of a selected memory cell in the memory cell array comprises: In a first time period, applying the first voltage to the first word line; Applying a first programming voltage for a first duration to the storage gate of the selected storage cell comprises: During the first time period, the first programming voltage of the first duration is applied to the second word line.

7. The method according to claim 6, characterized in that The memory cell in the memory cell array further comprises a first end connected to the control gate and a second end connected to the storage gate, wherein the control gate and the storage gate are both located between the first end and the second end; A first end of the selected memory cell is connected to a first bit line, and a second end of the selected memory cell is floating; Applying a first voltage to a control gate of a selected memory cell in the memory cell array further comprises: During the first time period, a ground voltage is applied to the first bit line.

8. The method according to claim 6 or 7, characterized in that: Performing a verification operation on the selected storage unit includes: In a second time period after the first time period, continuing to apply the first voltage to the first word line; During the second time period, a verification voltage is applied to the second word line.

9. The method according to claim 8, characterized in that Performing a verification operation on the selected storage unit also includes: During the second time period, a ground voltage is applied to the first bit line.

10. The method according to claim 8 or 9, characterized in that: Applying a second programming voltage for a second time period to the storage gate of the selected storage cell comprises: In a third time period after the second time period, continuing to apply the first voltage to the first word line; In the third time period, the second programming voltage of the second duration is applied to the second word line.

11. The method according to claim 10, characterized in that Applying a second programming voltage of a second duration to the storage gate of the selected storage cell also includes: During the third time period, a ground voltage is applied to the first bit line.

12. The method according to any one of claims 6 to 11, characterized in that The control gates of unselected memory cells in the memory cell array are connected to a third word line, and the gates of the memory gates of the unselected memory cells are connected to a fourth word line; The method further comprises: In the first time period, applying a second voltage to the third word line, wherein the second voltage is less than the first voltage; During the first period of time, a program inhibition voltage is applied to the fourth word line.

13. The method according to any one of claims 6 to 12, characterized in that The first end of the unselected memory cell is connected to the second bit line, and the second end of the unselected memory cell is floating; The method further comprises: In the first time period, a third voltage is applied to the second bit line, and the third voltage is greater than a ground voltage.

14. A memory, characterized in that: include: A memory cell array, wherein a memory cell in the memory cell array comprises a control gate and a memory gate connected to each other; A peripheral circuit, coupled to the memory cell array, is configured to: applying a first voltage to a control gate of a selected memory cell in the memory cell array; Applying a first programming voltage of a first duration to a storage gate of the selected storage cell; performing a verification operation on the selected storage unit; In response to a failure of the verification operation, a second programming voltage of a second duration is applied to the storage gate of the selected storage cell, wherein the second duration is greater than the first duration and / or the second programming voltage is greater than the first programming voltage.

15. The memory according to claim 14, characterized in that: The control gate of the selected memory cell is connected to a first word line, and the gate of the storage gate of the selected memory cell is connected to a second word line; The peripheral circuit includes a control circuit, a voltage generator, a word line driver and a bit line driver, wherein: The voltage generator is configured to generate a first voltage; The control circuit is configured to control the word line driver to apply the first voltage to the first word line within a first time period; The voltage generator is further configured to generate the first programming voltage; The control circuit is further configured to control the word line driver to apply the first programming voltage of the first duration to the second word line during the first time period.

16. The memory according to claim 15, characterized in that: The memory cell in the memory cell array further comprises a first end connected to the control gate and a second end connected to the storage gate, wherein the control gate and the storage gate are both located between the first end and the second end; A first end of the selected memory cell is connected to a first bit line, and a second end of the selected memory cell is floating; The control circuit is further configured to control the bit line driver to apply a ground voltage to the first bit line during the first time period.

17. The memory according to claim 15 or 16, characterized in that: The voltage generator is further configured to generate a verification voltage; The control circuit is further configured to control the word line driver to continue applying the first voltage to the first word line in a second time period after the first time period; The control circuit is further configured to control the word line driver to apply the verification voltage to the second word line during the second time period.

18. The memory according to claim 17, characterized in that: The control circuit is further configured to control the bit line driver to apply a ground voltage to the first bit line during the second time period.

19. The memory according to claim 17 or 18, characterized in that: The voltage generator is further configured to generate a second programming voltage; The control circuit is further configured to control the word line driver to continue applying the first voltage to the first word line in a third time period after the second time period; The control circuit is further configured to control the word line driver to apply the second programming voltage of the second duration to the second word line during the third time period.

20. The memory according to claim 19, characterized in that The control circuit is further configured to control the bit line driver to apply a ground voltage to the first bit line during the third time period.

21. The memory according to any one of claims 15 to 20, characterized in that: The control gates of unselected memory cells in the memory cell array are connected to a third word line, and the gates of the memory gates of the unselected memory cells are connected to a fourth word line; The voltage generator is further configured to generate a second voltage, the second voltage being lower than the first voltage; The control circuit is further configured to control the word line driver to apply the second voltage to the third word line during the first time period; The voltage generator is further configured to generate a program inhibit voltage; The control circuit is further configured to control the word line driver to apply the program inhibition voltage to the fourth word line during the first time period.

22. The memory according to claim 21, characterized in that The first end of the unselected memory cell is connected to the second bit line, and the second end of the unselected memory cell is floating; The voltage generator is further configured to generate a third voltage, the third voltage being greater than a ground voltage; The control circuit is further configured to control the bit line driver to apply the third voltage to the second bit line during the first time period.

23. The memory according to any one of claims 15 to 22, characterized in that: The control circuit is also configured to, in response to a failure result of the verification operation, increase the first time length by a first predetermined step length to obtain the second step length, and / or increase the first programming voltage by a second predetermined step length to obtain the second programming voltage.

24. The memory according to any one of claims 15 to 23, characterized in that: The control circuit is further configured to: Obtaining the current programming count of the selected storage unit; In response to a result of the verification operation being a failure, determining whether a current programming count of the selected memory cell is less than a preset programming count threshold; In response to determining that the current programming number of the selected memory cell is less than a preset programming number threshold, the second programming voltage of the second duration is applied to the storage gate of the selected memory cell.

25. The memory according to claim 24, characterized in that The control circuit is also configured to obtain the first programming voltage as a preset programming voltage in response to determining that the current programming number of the selected memory cell is 0, wherein the preset programming voltage is a programming voltage obtained through testing that can successfully program a preset proportion of storage gates.

26. The memory according to any one of claims 15 to 25, characterized in that: The memory cell array includes a memory cell pair having the same logical address, and the memory cell pair includes a memory cell and a redundant memory cell corresponding thereto; The control circuit is further configured to: Applying the first voltage to a control gate of a redundant memory cell corresponding to the selected memory cell; Applying the first programming voltage of the first duration to the storage gate of the redundant memory cell; performing the verification operation on the redundant storage unit; In response to determining that the redundant memory cell fails in programming according to the result of the verification operation, applying the second programming voltage for the second duration to the storage gate of the redundant memory cell.

27. A memory, characterized in that: include: A memory cell array; A peripheral circuit coupled to the memory cell array, the peripheral circuit comprising a fine-tuning circuit, the fine-tuning circuit comprising the memory as claimed in any one of claims 14-26, and configured to perform a fine-tuning operation on the memory cell array according to information stored in the memory as claimed in any one of claims 14-26.

28. A storage system, characterized in that: The invention comprises the memory as claimed in claim 27 and a controller coupled to the memory.

Images