A method and structure for embedding a glass substrate chip

Abstract

The application relates to the technical field of chip packaging, in particular to a packaging method and structure of a buried glass substrate chip. The method comprises the following steps: S1, obtaining a glass core plate; S2, slotting and fixing a chip in the groove; S3, pressing a layer of resin material; S4, forming a first copper plating layer; S5, forming an inner layer circuit; S6, pressing a layer of resin material and bonding another glass core plate; S7, sputtering a second copper plating layer; S8, forming an outer layer circuit; S9, pressing a layer of resin material; S10, TGV punching, the through-hole bottom falls on the pad of the chip; S11, forming a seed layer in the through-hole and performing chemical copper plating to form a copper surface layer, which is electrically connected with the chip, the inner layer circuit and the outer layer circuit. Compared with the prior art, the rigidity and hardness of the glass are utilized to bury the glass substrate, the overall three-dimensional height of the chip structure is reduced to thin the chip, one or more layers of chips can be buried in the glass substrate, and the height of the overall glass substrate chip is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, in particular to a packaging method and structure for an embedded glass substrate chip. Background Art

[0002] Since the 1970s, chip substrate materials have evolved from lead frames to ceramic substrates in the 1990s, and now organic substrates are the most common. However, organic substrates can cause warping and flatness issues during production, affecting packaging performance. Furthermore, limited substrate space limits the number of dies that can be stacked.

[0003] Since September 2023, Intel's pioneering efforts in supporting GCS have laid the foundation for industry-wide adoption, and the company has announced product launches after 2025, furthering Moore's Law. Glass substrates have advantages over organic substrates: (1) Ultra-low flatness. This improves lithography focus depth and interconnect dimensional stability; (2) Good thermal and mechanical stability. Able to withstand higher temperatures and more resilient in data center applications; (3) Enables higher interconnect density; and (4) Reduces pattern deformation by 50%.

[0004] Glass substrate packaging technology improves CoWoS-S technology. TSMC's 2.5D packaging technology, CoWoS-S, connects the chip to a silicon interposer and then connects the stacked chip to a substrate, thus achieving a three-dimensional chip-interposer-substrate packaging structure. Glass substrate packaging technology has improved it: (1) Substrate material: from FC-BGA substrate to glass core substrate; (2) Interposer: from silicon to glass substrate; (3) Key technology: from through-silicon via (TSV) to through-glass via (TGV).

[0005] Current glass substrates typically use a symmetrical design to laminate ABF material on both sides for building-up stacking. However, this process has the disadvantage of making asymmetrical glass substrates difficult. Furthermore, current glass substrate development is intended to replace FCBGA organic substrates, but the normal thickness of glass substrates is slightly thicker than organic substrates. The chip packaging and bumping process required to connect the chip after the glass substrate is manufactured increases the thickness of the chip stack (chip + glass substrate thickness). Finally, current glass substrate chips primarily utilize the bumping process, where the chip is connected to the bump on the glass substrate. This exposes the chip outside the substrate, increasing the risk of abnormal failure during the packaging process. Summary of the Invention

[0006] In order to overcome the deficiencies of the prior art, the present invention provides a packaging method and structure for an embedded glass substrate chip.

[0007] To achieve the above objectives, a packaging method for embedded glass substrate chips is designed, comprising the following steps:

[0008] S1, pre-treating the glass and thinning it to obtain a glass core board;

[0009] S2, through the laser drilling process, grooves are made on the surface of the glass core board and the chip is fixed in the groove;

[0010] S3, after the chip is fixed, a first resin material layer is pressed on the upper surface of the chip and the upper surface of the glass core board;

[0011] S4, copper plating on the upper surface of the first resin material layer to form a first copper plating layer;

[0012] S5, forming an inner layer circuit on the first copper plating layer;

[0013] S6, laminating a second resin material layer on the upper surface of the inner circuit to wrap the inner circuit, and applying an adhesive layer on the second resin material layer on the inner circuit to bond another glass core board;

[0014] S7, sputtering a second copper plating layer on the upper surface of another glass core board;

[0015] S8, forming an outer layer circuit on the second copper plating layer;

[0016] S9, laminating a third resin material layer on the upper surface of the outer circuit layer;

[0017] S10, TGV drilling is performed on the glass core board, and the bottom of the through hole falls on the pad of the chip.

[0018] S11, forming a seed layer in the through hole, and performing chemical copper plating to form a copper surface layer, the copper surface layer electrically connecting the chip, the inner layer circuit, and the outer layer circuit.

[0019] The following steps are also included:

[0020] S12, forming a photopolymerization protective layer on the upper surface of the copper surface layer;

[0021] S13, irradiating the photopolymerized protective layer with ultraviolet light and developing it to form an opening, exposing the copper surface layer on the surface, and forming an anti-oxidation layer on the outer side of the copper surface layer;

[0022] S14, planting balls on the exposed copper surface layer;

[0023] S15, sputtering a shielding layer on the outside of the package body. The shielding layer is made of a Ti layer, a stainless steel layer, or a metal layer capable of shielding signals, with a thickness of 30 to 100 μm.

[0024] The shielding layer is an EMI coating layer formed by a sputtering process.

[0025] The specific method of step S2 is as follows: S21, cleaning the bottom of the groove; S22, coating a layer of adhesive on the inner wall of the groove; S23, fixing the chip in the groove by bonding with a DAF film; in step S21, the groove is cleaned by high-cleaning acid or plasma cleaning.

[0026] The high-cleaning acid is an AC organic acid formed by mixing sulfuric acid or formic acid with acetic acid, with a concentration of 5%.

[0027] In the step S3, the resin material is selected from one of ABF material, PP material and PI material.

[0028] In the step S4, a thin copper layer is first plated on the upper surface of the first resin material layer, and then thickened electroplating is performed on the copper surface to form a first copper plating layer. The thickness of the first copper plating layer is 20-30 μm.

[0029] In the step S10, the inner wall of the through hole (8) is treated by a composite additive, wherein the composite additive is a mixture of leveling agents S1, S2, and S3, wherein the leveling agent S1 is (CH) n N m OH, mass fraction is 10%~15%; leveling agent S2 uses H x (SO3) y (CH2) z 2. The mass fraction is 20%~40%; the leveling agent S3 is N x (CH3) y (CH2) z , mass fraction 30%~50%, the balance is water.

[0030] In the step S14, a hollow fixture is installed at the bottom of the chip during ball planting, and a nitrogen reflow chamber is used.

[0031] The structure of an embedded glass substrate chip prepared based on a packaging method includes a glass core board, a groove is provided on one side of the glass core board, and the chip is fixed in the groove by adhesive glue and DAF film. A first resin material layer is provided on the upper surface of the chip and the upper surface of the glass core board. A first copper plating layer, a second resin material layer, another glass core board, a second copper plating layer, and a third resin material layer are provided on the outer side of the first resin material layer in sequence. A through hole is provided on the outermost third resin material layer, and the through hole passes through the third resin material layer, the second copper plating layer, another glass core board, the second resin material layer, the first copper plating layer, and the first resin material layer. The bottom of the hole falls on the chip's solder pad. The through hole is provided with a copper surface layer. The copper surface layer is electrically connected to the chip, the circuit on the first copper plating layer, and the circuit on the second copper plating layer to form a package body.

[0032] A photopolymerization protective layer is provided on the upper surface of the outermost copper surface layer and is connected to the solder balls. A shielding layer is provided on the outside of the package body.

[0033] Compared with the prior art, the present invention has the following beneficial effects:

[0034] 1. Utilizing the rigidity and hardness of glass, the glass substrate is embedded in it, reducing the overall three-dimensional height of the chip structure to thin the chip. One or more layers of chips can be embedded in the glass substrate, reducing the overall height of the glass substrate chip.

[0035] 2. TGV drilling technology is used to open through-holes in the glass and connect the chip pad and the glass substrate layer to achieve electrical interconnection. A multi-additive composite system is used to treat the surface inside the through-hole to complete the filling and plating of through-holes with a depth-to-diameter ratio of 20:1 or above.

[0036] 3. Utilizing glass substrate lamination technology, a multi-layer glass substrate is produced by bonding the glass with a coating adhesive layer, which increases the strength of the substrate while also increasing the wiring density of the circuits.

[0037] 4. Taking advantage of the hardness of the underlying glass, the chip is embedded inside the glass to protect the chip, while reducing the use of MD resin material to achieve a thinner chip thickness.

[0038] 5. Using EMI technology to sputter a metal layer on the surface of the bottom glass can enhance the bottom hardness and shield interference signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 Schematic diagram of step S1 of the present invention.

[0040] Figure 2 Schematic diagram of step S2 of the present invention.

[0041] Figure 3 Schematic diagram of step S3 of the present invention.

[0042] Figure 4 Schematic diagram of step S4 of the present invention.

[0043] Figure 5 Schematic diagram of step S5 of the present invention.

[0044] Figure 6 Schematic diagram of step S6 of the present invention.

[0045] Figure 7 Schematic diagram of step S7 of the present invention.

[0046] Figure 8 Schematic diagram of step S8 of the present invention.

[0047] Figure 9 Schematic diagram of step S9 of the present invention.

[0048] Figure 10 Schematic diagram of step S10 of the present invention.

[0049] Figure 11 Schematic diagram of step S11 of the present invention.

[0050] Figure 12 Schematic diagram of step S12 of the present invention.

[0051] Figure 13 Schematic diagram of step S13 of the present invention.

[0052] Figure 14 Schematic diagram of step S14 of the present invention.

[0053] Figure 15 This is a schematic diagram of step S15 of the present invention.

[0054] Figure 16 It is a structural schematic diagram of the present invention. DETAILED DESCRIPTION

[0055] The present invention will be further described below with reference to the accompanying drawings.

[0056] like Figures 1 to 15 As shown, the packaging method of the embedded glass substrate chip in this embodiment includes the following steps:

[0057] S1, pre-treating the glass and thinning it to obtain a glass core board 1;

[0058] S2, using a laser drilling process, grooves are made on the upper surface of the glass core board 1, and the chip 2 is fixed in the grooves;

[0059] S3, after the chip 2 is fixed, a first resin material layer 5-1 is pressed onto the upper surface of the chip 2 and the upper surface of the glass core board;

[0060] S4, copper plating is performed on the upper surface of the first resin material layer 5-1 to form a first copper plating layer 6;

[0061] S5, forming an inner layer circuit on the first copper plating layer 6;

[0062] S6, laminating a first resin material layer 5-1 on the upper surface of the inner circuit to wrap the inner circuit, and applying an adhesive layer on the second resin material layer 5-2 on the inner circuit to bond another glass core board 1;

[0063] S7, sputtering a second copper plating layer 7 on the upper surface of another glass core board 1;

[0064] S8, forming an outer layer circuit on the second copper plating layer 7;

[0065] S9, laminating a third resin material layer 5-3 on the upper surface of the outer circuit layer;

[0066] S10, TGV drilling is performed on the glass core board 1, and the bottom of the through hole 8 falls on the pad 21 of the chip 2,

[0067] S11, forming a seed layer in the through hole 8, and performing chemical copper plating to form a copper surface layer 9, the copper surface layer 9 electrically connecting the chip 2, the inner layer circuit, and the outer layer circuit.

[0068] The following steps are also included:

[0069] S12, forming a photopolymerization protective layer 10 on one side of the copper surface layer 9;

[0070] S13, irradiating the photopolymerized protective layer 10 with ultraviolet light and developing it to form an opening, exposing the copper surface layer 9 on the surface, and forming an anti-oxidation layer on the outside of the copper surface layer 9;

[0071] S14, planting balls on the copper surface layer 9;

[0072] S15: Sputter a shielding layer 11 on the outside of the package. The shielding layer is made of Ti, stainless steel, or a metal layer capable of shielding signals, with a thickness of 30-100 μm. In practice, the shielding layer 11 is an EMI coating formed by a sputtering process.

[0073] In step S1, the glass is thinned to 150-200 μm by a grinder, and the flatness of the surfaces of both sides of the obtained glass core board 1 is less than 0.05 μm.

[0074] The specific method of step S2 is as follows: S21, cleaning the bottom of the groove; S22, applying a layer of adhesive 3 to the inner wall of the groove; S23, bonding and fixing the chip 2 in the groove via DAF film 4. In step S21, the groove is cleaned using a high-cleaning acid or plasma cleaning. The high-cleaning acid is an organic acid (AC) formed by mixing sulfuric acid or formic acid with acetic acid, with a concentration of 5%.

[0075] In step S3, the resin material is selected from one of ABF material, PP material, and PI material.

[0076] In step S4, a thin copper layer is first plated on the surface of the first resin material layer 5-1, and then a thicker copper layer is electroplated on the copper surface to form a first copper-plated layer 6. The thickness of the first copper-plated layer 6 is 20-30 μm. In practice, the copper plating is carried out in two steps. The first copper plating is copper plating, which mainly plates a thin copper layer on the resin surface to increase the bonding strength of the electroplated copper. The second copper layer is mainly electroplated with a thick copper layer, which is used to form the circuit.

[0077] In step S5, a 20 / 20 μm inner layer circuit is formed on the upper surface of the first copper plating layer 6 by lamination, exposure, etching, and development processes. In specific use, etching can be performed using a sodium perchlorate system solution using a vacuum two-fluid.

[0078] In step S6, the glass core board 1 is thinned, ground and polished several times to a thickness of 30-50 μm.

[0079] In step S8, a 15 / 15 μm outer layer circuit is formed on the upper surface of the second copper plating layer 7 through the MSAP process of lamination, exposure, development, electroplating, etching, and development. The thickness of the second copper plating layer 7 is 10-17 μm.

[0080] In step S10, the diameter of the through hole 8 is 5-20 μm, and the aspect ratio is less than or equal to 20:1. In step S10, the inner wall of the through hole 8 is treated with a composite additive, and the composite additive is a mixture of leveling agents S1, S2, and S3. The leveling agent S1 is (CH) n N m OH, mass fraction is 10%~15%; leveling agent S2 uses H x (SO3) y (CH2) z 2. The mass fraction is 20%~40%; the leveling agent S3 is N x (CH3) y (CH2) z , mass fraction 30%~50%, the balance is water.

[0081] In step S12, the protective layer is made of solder resist material or PI material, and the thickness of the photopolymerized protective layer 10 is 15-30 μm.

[0082] In step S14, a hollow fixture is installed at the bottom of the chip 2 during ball implantation, and a nitrogen reflow chamber is used.

[0083] In step S13, when in use, a layer of OSP or anti-rust layer is formed to prevent oxidation.

[0084] like Figure 16As shown, the structure of the embedded glass substrate chip obtained by the above packaging method includes a glass core board, a groove is provided on one side of the glass core board 1, and the chip 2 is fixed in the groove by adhesive glue 3 and DAF film 4, and a first resin material layer 5-1 is provided on the upper surface of the chip 2 and the upper surface of the glass core board 1. The outer side of the first resin material layer 5-1 is provided with a first copper plating layer 6, a second resin material layer 5-2, another glass core board 1, a second copper plating layer 7, and a third resin material layer 5-3 in sequence, and a through hole is provided on the outermost third resin material layer 5-3. The through hole 8 passes through the third resin material layer 5-3, the second copper plating layer 7, another glass core board 1, the second resin material layer 5-2, the first copper plating layer 6, and the first resin material layer 5-1. The bottom of the hole falls on the pad 21 of the chip 2, and the through hole 8 is provided with a copper surface layer 9. The copper surface layer 9 electrically connects the chip 2, the circuit on the first copper plating layer 6, and the circuit on the second copper plating layer 7 to form a package body.

[0085] A photopolymerization protective layer 10 is provided on the upper surface of the outermost copper surface layer 9 and is connected to solder balls 12 . A shielding layer 11 is provided on the outer side of the package body.

[0086] The CTE of the glass core is smaller than that of existing Si and BT materials. The present invention takes advantage of the small CTE of the glass core. The glass core has good flatness, which can reduce the gap between the chip and the glass substrate, and ultimately reduce the warping of the substrate and the warping of the packaged chip.

[0087] In the existing glass substrate stacking process, some processes first complete stacking and pressing, and then groove to bury the chip. The present invention first buries the core and then performs substrate stacking and pressing to add layers. In order to reduce CTE, a second glass core board pressing is also added.

[0088] In the present invention, the chip is embedded in the glass core board 1 of the first layer. The chip is first embedded in the glass core board 1 and then the substrate is laminated and pressed to make the circuit. In this way, the board-level or wafer-level core embedding process can be realized to increase the alignment. Because the core is embedded first and then the circuit and substrate are aligned with the chip as the reference, the alignment can be more precise and the error between layers can be reduced. In addition, the chip is placed on the first layer of chips, which is close to the outer layer, which is easy to dissipate heat during the operation of the chip. Furthermore, the present invention directly plates an EMI metal layer on the outside of the glass core board 1 of the first layer, which makes heat conduction faster.

Claims

1. A method for packaging an embedded glass substrate chip, characterized in that: The steps include: S1, pre-treating the glass and thinning it to obtain a glass core board (1); S2, using a laser drilling process to create grooves on the upper surface of the glass core board (1), and fixing the chip (2) in the grooves; S3, after the chip (2) is fixed, a first resin material layer (5-1) is pressed onto the upper surface of the chip (2) and the upper surface of the glass core board (1); S4, copper plating is performed on the upper surface of the first resin material layer (5-1) to form a first copper plating layer (6); S5, forming an inner layer circuit on the first copper plating layer (6); S6, laminating a second resin material layer (5-2) on the upper surface of the inner layer circuit to wrap the inner layer circuit, and coating an adhesive layer on the second resin material layer (5-2) on the inner layer circuit to bond another glass core board (1); S7, sputtering a second copper plating layer (7) on the upper surface of another glass core board (1); S8, forming an outer layer circuit on the second copper plating layer (7); S9, laminating a third resin material layer (5-3) on the upper surface of the outer circuit layer; S10, TGV drilling is performed on the glass core board (1), and the bottom of the through hole (8) falls on the pad (21) of the chip (2). S11, forming a seed layer in the through hole (8), and performing chemical copper plating to form a copper surface layer (9), the copper surface layer (9) being electrically connected to the chip (2), the inner layer circuit, and the outer layer circuit.

2. The method for packaging a buried glass substrate chip according to claim 1, wherein: The following steps are also included: S12, forming a photopolymerization protective layer (10) on the upper surface of the copper surface layer (9); S13, irradiating the photopolymerization protective layer (10) with ultraviolet light and developing it to form an opening, exposing the copper surface layer (9) on the surface, and forming an anti-oxidation layer on the outside of the copper surface layer (9); S14, planting a ball on the exposed copper surface layer (9); S15, sputtering a shielding layer (11) on the outside of the package body, wherein the shielding layer is made of a Ti layer, a stainless steel layer, or a metal layer capable of shielding signals, and has a thickness of 30 to 100 μm.

3. The method for packaging an embedded glass substrate chip according to claim 2, wherein: Alternatively, the shielding layer (11) is an EMI coating formed by a sputtering process.

4. The method for packaging an embedded glass substrate chip according to claim 1, wherein: The specific method of step S2 is as follows: S21, cleaning the bottom of the groove; S22, coating a layer of adhesive (3) on the inner wall of the groove; S23, bonding and fixing the chip (2) in the groove through a DAF film (4); in step S21, the groove is cleaned by high-cleaning acid or plasma cleaning.

5. The method for packaging an embedded glass substrate chip according to claim 4, wherein: The high-cleaning acid is an AC organic acid formed by mixing sulfuric acid or formic acid with acetic acid, with a concentration of 5%.

6. The method for packaging an embedded glass substrate chip according to claim 1, wherein: In the step S3, the resin material is selected from one of ABF material, PP material and PI material.

7. The method for packaging an embedded glass substrate chip according to claim 1, wherein: In the step S4, a thin copper layer is first plated on the upper surface of the first resin material layer (5-1), and then thickened electroplating is performed on the copper surface to form a first copper plating layer (6). The thickness of the first copper plating layer (6) is 20-30 μm.

8. The method for packaging an embedded glass substrate chip according to claim 1, wherein: In the step S10, the inner wall of the through hole (8) is treated by a composite additive, wherein the composite additive is a mixture of leveling agents S1, S2, and S3, wherein the leveling agent S1 is (CH) n N m OH, mass fraction is 10%~15%; leveling agent S2 uses H x (SO3) y (CH2) z 2. The mass fraction is 20%~40%; the leveling agent S3 is N x (CH3) y (CH2) z , mass fraction 30%~50%, the balance is water.

9. The method for packaging an embedded glass substrate chip according to claim 2, wherein: In the step S14, a hollow fixture is installed at the bottom of the chip (2) during ball planting, and a nitrogen reflow cavity is used.

10. A structure of an embedded glass substrate chip prepared by the packaging method according to any one of claims 1 to 9, comprising a glass core board, characterized in that: The glass core board (1) is provided with a groove on one side, and the chip (2) is fixed in the groove by adhesive glue (3) and DAF film (4). The upper surface of the chip (2) and the upper surface of the glass core board (1) are provided with a first resin material layer (5-1). The outer side of the first resin material layer (5-1) is provided with a first copper plating layer (6), a second resin material layer (5-2), another glass core board (1), a second copper plating layer (7), and a third resin material layer (5-3) in sequence. A through hole is provided on the outermost third resin material layer (5-3). The through hole (8) passes through the third resin material layer (5-3), the second copper plating layer (7), another glass core board (1), the second resin material layer (5-2), the first copper plating layer (6), and the first resin material layer (5-1). The bottom of the hole falls on the pad (21) of the chip (2). The through hole (8) is provided with a copper surface layer (9). The copper surface layer (9) is electrically connected to the chip (2), the circuit on the first copper plating layer (6), and the circuit on the second copper plating layer (7) to form a package.

11. The structure of the embedded glass substrate chip according to claim 10, characterized in that: A photopolymerization protective layer (10) is provided on the upper surface of the outermost copper surface layer (9), and is connected to the solder balls (12). A shielding layer (11) is provided on the outer side of the package body.

Images