A method and system for repairing faults in silicon vias of three-dimensional integrated circuits

Abstract

The present invention discloses a method and system for repairing faults in through-silicon vias (TSVs) of three-dimensional integrated circuits. The method first establishes a switch matrix composed of n×n switch units, and then connects it to n×n TSVs and n redundant TSVs to form a TSV repair circuit. After locating the position of the faulty TSV, using the faulty TSV as the starting point and the redundant TSV as the ending point, path planning is carried out between the starting point and the ending point, and finally the faulty TSV is repaired according to the planned path. The present invention improves the TSV repair efficiency and flexibility without significantly increasing the hardware and delay overheads.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging and assembly, and in particular to a method and system for repairing faults of through-silicon vias in three-dimensional integrated circuits. Background Art

[0002] With the continuous miniaturization of semiconductor processes and the improvement of system integration, two-dimensional planar integrated circuits are gradually approaching the physical limit in terms of performance, power consumption, and area. 3D ICs tightly integrate multiple chips with different functions within a limited silicon area through vertical stacking and through-silicon via (TSV) technology, achieving high-density vertical interconnection, improving communication bandwidth, and reducing signal delay and power consumption. However, voids, stress, and impurities are easily introduced during processes such as deep reactive ion etching, TSV filling, and planarization, resulting in structural defects and functional failures of TSVs. In addition, high power density and thermal imbalance will exacerbate the risks of electromigration and stress failure of TSVs. In the face of these faults, without an effective detection and repair mechanism, the entire 3D chip may be scrapped due to the failure of a small number of TSVs, resulting in cost waste and yield decline.

[0003] Existing TSV repair methods include router structures, ring structures, honeycomb structures, etc. However, it is difficult to meet the requirements for rapid and efficient repair of TSV faults solely relying on traditional methods. The main reason is that existing TSV redundancy strategies mostly rely on a large number of redundant TSVs and multiplexers (MUXs), which often introduce high latency, area, and design complexity while achieving a high repair rate. In addition, when encountering severe clustering faults, traditional routing architectures or grouping strategies may also be difficult to meet the requirements for efficient repair. Summary of the Invention

[0004] Object of the Invention: The object of the present invention is to provide a method and system for repairing faults of through-silicon vias in three-dimensional integrated circuits, which can improve the TSV repair efficiency and flexibility without significantly increasing the hardware and latency overhead, and meet the requirements for the future development of 3D IC design towards larger scale and higher reliability.

[0005] Technical Solution: The method for repairing faults of through-silicon vias in three-dimensional integrated circuits according to the present invention includes the following steps:

[0006] (1) Establish a switch matrix composed of n×n switch units. Each switch unit includes four transmission transistors G1, G2, G3, and G4 connected in sequence at the head and tail. The connection points between the four transmission transistors are used as external connection points, which are connected to other switch units to form a switch matrix;

[0007] Each switch unit further includes a fifth transmission transistor G5. One end of G5 is connected between G1 and G4, and the connection point is called the first node;

[0008] The other ends of the G5s are all connected to the through-silicon vias, and the first nodes on the edge rows or edge columns in the switch matrix are all connected to redundant through-silicon vias, obtaining a through-silicon via repair circuit;

[0009] (2)Read the test results of the through-silicon vias in the through-silicon via repair circuit to obtain the positions of m faulty through-silicon vias, where m ≤ n;

[0010] Convert the circuit diagram of the through-silicon via repair circuit into a network node graph. In the network node graph, a node represents the connection between the ends of a transmission transistor, and two nodes are connected to form an edge;

[0011] (3)Using the faulty through-silicon vias as the starting points and the redundant through-silicon vias as the ending points, according to the preset priority order of the through-silicon vias, use the breadth-first search algorithm to perform path planning between the starting points and the ending points to obtain m paths, and use the paths to repair the faulty through-silicon vias;

[0012] Among them, the edges in the network node graph included in each path represent that the transmission transistor is in the on state, and the remaining transmission transistors are in the off state.

[0013] Further, in step (3), the path planning between the starting point and the ending point using the breadth-first search algorithm includes path connectivity constraints and path overlap constraints;

[0014] The path connectivity constraint is that each node in each path is an adjacent node and there are no duplicate nodes;

[0015] The path overlap constraint is that there are no reused nodes in each path.

[0016] Further, in step (3), before using the breadth-first search algorithm to perform path planning between the starting point and the ending point, it also includes pairing the starting point and the ending point: sequentially select a starting point according to the preset priority order, calculate the Manhattan distance between the starting point and each optional ending point, select the ending point with the shortest Manhattan distance to pair with the starting point, and save the matching pairs of the starting point and the ending point to a form;

[0017] Among them, each ending point is only matched with one starting point, and the unmatched ending points are optional ending points.

[0018] Further, in step (3), sequentially select a matching pair according to the preset priority order, use the breadth-first search algorithm to perform path planning. When there is a situation where the path cannot be successfully planned, perform a forward exchange of the ending point;

[0019] The forward exchange end point is as follows: delete all the obtained paths, exchange the current matching pair with the matching pair of the previous priority order, update the form, and sequentially select a matching pair according to the priority order in the updated form, and perform path planning using the breadth - first search algorithm; the maximum number of forward exchanges is set to n times.

[0020] Further, in step (3), when after performing the forward exchange end point n times, in the case where path planning using the breadth - first search algorithm fails to successfully plan a path, perform the backward exchange end point;

[0021] The backward exchange end point is as follows: delete all the obtained paths, for the form before performing the forward exchange end point, exchange the current matching pair with the matching pair of the next priority order, update the form, and sequentially select a matching pair according to the priority order in the updated form, and perform path planning using the breadth - first search algorithm; the maximum number of backward exchanges is set to n times.

[0022] The fault repair system for the through - silicon vias of the three - dimensional integrated circuit of the present invention includes:

[0023] A switch matrix establishment unit, used to establish a switch matrix composed of n×n switch units. The switch unit includes four transmission transistors G1, G2, G3, and G4 connected end - to - end in sequence. The connection points between the four transmission transistors are used as external connection points and are connected to other switch units to form a switch matrix;

[0024] The switch unit further includes a fifth transmission transistor G5. One end of G5 is connected between G1 and G4, and the connection point is called the first node;

[0025] The other end of G5 is connected to the through - silicon via. The first nodes on the edge rows or edge columns in the switch matrix are all connected to redundant through - silicon vias to obtain a through - silicon via repair circuit;

[0026] A through - silicon via test result reading unit, used to read the test results of the through - silicon vias in the through - silicon via repair circuit to obtain the positions of m faulty through - silicon vias, where m≤n;

[0027] A network node graph conversion unit, used to convert the circuit diagram of the through - silicon via repair circuit into a network node graph. In the network node graph, nodes represent the connections between the ends of transmission transistors, and two nodes are connected to form an edge;

[0028] A faulty through - silicon via repair unit, used to use the faulty through - silicon via as the starting point and the redundant through - silicon via as the ending point, and perform path planning between the starting point and the ending point using the breadth - first search algorithm according to the preset priority order of the through - silicon vias to obtain m paths, and use the paths to repair the faulty through - silicon vias;

[0029] Among them, the edges in the network node graph included in each path represent that the transmission transistor is in the on state, and the remaining transmission transistors are in the off state.

[0030] Further, in the failed silicon via repair unit, the path planning between the start point and the end point using the breadth-first search algorithm includes path connectivity constraints and path overlap constraints;

[0031] The path connectivity constraint is that each node in each path is an adjacent node and there are no duplicate nodes;

[0032] The path overlap constraint is that there are no reused nodes in each path.

[0033] Further, in the failed silicon via repair unit, before using the breadth-first search algorithm to perform path planning between the start point and the end point, it also includes pairing the start point and the end point: sequentially selecting a start point according to the preset priority order, calculating the Manhattan distance between the start point and each optional end point, selecting the end point with the shortest Manhattan distance to pair with the start point, and saving the matching pairs of the start point and the end point to a form;

[0034] Among them, each end point is only matched with one start point, and the unmatched end points are optional end points;

[0035] In the failed silicon via repair unit, sequentially selecting a matching pair according to the preset priority order, using the breadth-first search algorithm to perform path planning. When there is a situation where the path cannot be successfully planned, perform forward swapping of the end point;

[0036] The forward swapping of the end point is: deleting all the obtained paths, swapping the current matching pair with the matching pair of the previous priority order, updating the form, sequentially selecting a matching pair according to the priority order in the updated form, and using the breadth-first search algorithm to perform path planning; the maximum number of forward swaps is set to n times;

[0037] When after performing n times of forward swapping of the end point, there is a situation where the path cannot be successfully planned using the breadth-first search algorithm, perform backward swapping of the end point;

[0038] The backward swapping of the end point is: deleting all the obtained paths, for the form before performing the forward swapping of the end point, swapping the current matching pair with the matching pair of the next priority order, updating the form, sequentially selecting a matching pair according to the priority order in the updated form, and using the breadth-first search algorithm to perform path planning; the maximum number of backward swaps is set to n times.

[0039] The electronic device described in the present invention includes a memory, a processor, and a computer program stored on the memory and executable on the processor. When the computer program is loaded into the processor, the fault repair method for the through-silicon vias of the three-dimensional integrated circuit is implemented.

[0040] The computer-readable storage medium described in the present invention stores a computer program. When the computer program is executed by a processor, the fault repair method for the through-silicon vias of the three-dimensional integrated circuit is implemented.

[0041] Beneficial effects: Compared with the prior art, the advantages of the present invention are as follows: The present invention uses transmission transistors to construct basic switching units, and uses the basic switching units to form a switching matrix to replace the routing structure (MUX) in the traditional repair algorithm, effectively controlling the hardware overhead. The construction of the switching matrix enables all faulty TSVs not greater than the redundant TSV quantity (theoretically, the maximum number of faulty TSVs that can be repaired) to be repaired, and the repair rate is 100%, solving the problem that the traditional repair algorithm cannot be repaired in some highly clustered cases. The test algorithm is simple and has a low time complexity, shortening the running time of the automatic test equipment and saving the repair cost. Description of the Drawings

[0042] Figure 1 It is a flowchart of the fault repair method of the present invention.

[0043] Figure 2 It is a schematic diagram of the structure of the basic switching unit according to an embodiment of the present invention.

[0044] Figure 3 It is a schematic diagram of the network structure of the switching matrix according to an embodiment of the present invention.

[0045] Figure 4 It is a network node diagram according to an embodiment of the present invention.

[0046] Figure 5 It is a schematic diagram of the test result file according to an embodiment of the present invention.

[0047] Figure 6 It is a schematic diagram of the path planning result after executing the breadth-first search algorithm once according to an embodiment of the present invention.

[0048] Figure 7 It is a schematic diagram of the path planning result after executing the first end-point exchange algorithm 5 times according to an embodiment of the present invention.

[0049] Figure 8 It is a schematic diagram of the path planning result after executing the second end-point exchange algorithm once according to an embodiment of the present invention.

[0050] Figure 9 It is a schematic diagram of the signal matrix according to an embodiment of the present invention. Detailed Embodiments

[0051] The technical solution of the present invention will be further described below in conjunction with the accompanying drawings.

[0052] As Figure 1 shown, the method for repairing faults in the through-silicon vias of the three-dimensional integrated circuit includes the following steps.

[0053] Step 1, Design of the basic switch unit circuit structure composed of five transmission transistors.

[0054] As Figure 2 shown in (a) therein, the basic circuit structure includes: four transmission transistors are connected end to end to form a rhombus structure, one end of the fifth transistor is connected to the right endpoint of the rhombus, and the other end is connected to the TSV; according to this basic circuit structure, a basic switch unit is designed. As Figure 2 shown in (b) therein, the basic switch unit is composed of five transmission transistors, among which four transmission transistors (G1, G2, G3, G4) are connected end to end to form a rhombus structure, and one end of the fifth transmission transistor (G5) is connected to any vertex of the rhombus inside the rhombus, and the other end is used to connect to the TSV; in this embodiment, the right endpoint of the fifth transmission transistor is connected to the right vertex of the rhombus, and the left endpoint is used to connect to the TSV. The advantage of this is that when searching for a repair path for a faulty TSV each time, the BFS algorithm will give priority to trying the right-side nodes, so as to get closer to the right-side redundant TSV faster, reduce the redundant paths caused by unnecessary probes, and try to obtain a shorter path as much as possible.

[0055] The four vertices of the rhombus structure of the basic switch unit are used as external connection points to connect to the connection points of other basic switch units to form a switch array structure, Figure 2 which is represented by an extended line segment in (b) therein.

[0056] Step 2, Design of the switch matrix structure constructed by n×n scale switch units.

[0057] The basic switch units are arranged in an array structure, and the directions of each basic switch unit are the same, so that when TSVs at different positions fail, the algorithm will give priority to path probing on the same side, which can effectively avoid the occurrence of path conflicts. The general structure is an n×n switch array, called a switch matrix (SM, Switch-Matrices). Specifically, it is shown as connecting the left vertex of the first switch unit to the right vertex of the next switch unit, and connecting the left vertex of the second switch unit to the right vertex of the next switch unit, and connecting accordingly to the nth switch unit to form a switch row; and connecting the lower vertex of the switch unit corresponding to the previous switch row to the upper vertex of the switch unit corresponding to the next switch row, and connecting accordingly to the nth row to form a switch matrix.

[0058] Step 3, Corresponding functional connection between the switch matrix and the TSV array.

[0059] Construct a TSV array of n×n scale to simulate a single group of TSV arrays of signals to be repaired. Connect the TSV array to the already constructed switch matrix correspondingly. Each TSV is connected to the unconnected end of the fifth transmission transistor in the basic switch unit. At the same time, the unconnected ends of the outermost column of the switch matrix are respectively connected to a redundant TSV, and finally a through-silicon via repair circuit is formed. As Figure 3 shown, in this embodiment, taking n = 5 as an example, each TSV is connected to the left end point of the fifth transmission transistor in each basic switch unit, and the rightmost column of the switch matrix is connected to the redundant TSV. Specifically, the right end point of the fifth transmission transistor is connected to the redundant TSV (R1, R2, R3, R4, R5).

[0060] Step 4: Read the TSV interconnection test result file to identify the faulty TSVs.

[0061] Read the TSV test result file. The result file contains the fault conditions of the TSV array of the corresponding scale (n×n). The encoding rule is that binary "1" represents that the TSV at the corresponding position is detected without fault, and binary "0" represents that the TSV at the corresponding position is a faulty TSV. The result file contains n rows, and each row has n-bit encoding, constituting the test result of the fault conditions of the corresponding n×n signal TSV array. Extract and identify the position coordinates of m faulty TSVs, which are used as the basis for the start and end point matching and path planning in the next step, where m≤n.

[0062] Step 5: Convert the circuit diagram of the through-silicon via repair circuit into a corresponding network node diagram, and convert the problem of switching the repair signal of the faulty through-silicon via into a start-end pair path planning problem.

[0063] Convert the circuit diagram of the through-silicon via repair circuit into a corresponding network node diagram, as Figure 2 shown in (c). The network node diagram contains nodes and edges. The nodes represent the connection points between the ends of the transmission transistors that make up the basic switch unit. Two connected nodes form an edge, representing the line connecting the transmission transistors or the basic switch units.

[0064] The faulty TSV is used as the start point, and the redundant TSV is used as the end point.

[0065] Step 6: Perform start-end matching according to the priority order and relying on the shorter Manhattan distance first as the heuristic, and record the start-end matching form.

[0066] According to the preset TSV priority, select a start point for processing in turn, calculate the Manhattan distance between the start point and all optional end points, select the group of start and end points with the shortest Manhattan distance as the current matching pair until each start point has an end point corresponding to it. Finally, obtain m matching pairs, and record the matching pairs in the start-end matching form (hereinafter referred to as the form).

[0067] Among them, each end point only matches one start point, and the unmatched end points are optional end points.

[0068] Step 7: Run the breadth-first search algorithm (BFS) for path planning in the order of priority, check and return the path planning information; for the case where all start-end path matches cannot be completed, run the end point swapping algorithm, update the form, and re-perform path planning. If all path planning is successful, output the path information file, convert it into a signal matrix, and perform fault repair according to the path corresponding to the signal matrix; if there is a situation where a path cannot be planned, return the result as repair failure.

[0069] According to the preset TSV priority, select a matching pair from the form in sequence, and use BFS for path planning. The path planning needs to satisfy the path connectivity constraint and the path overlap constraint. The path connectivity constraint is that each node in each path is an adjacent node and there are no duplicate nodes; the path overlap constraint is that there are no reused nodes in all paths.

[0070] If a situation where the path cannot be successfully planned occurs, run the first end point swapping algorithm. First, clear all the previously completed and stored path planning results, swap the end points of the current matching pair and the previous sequential matching pair, and update the form at the same time. Then, perform the BFS path planning process again in sequence according to the latest form. This process is called forward swapping of end points. If a situation where the path cannot be planned still occurs, continue to swap the end points forward until all paths are completely planned. The maximum number of forward swaps is set to n times.

[0071] If a situation where the path cannot be successfully planned occurs after performing the first end point swapping algorithm n times, run the second end point swapping algorithm. Clear the current form and read the form saved in step 6 (that is, go back to before running the first end point swapping algorithm), clear all the previously completed and stored path planning results, swap the end points of the current matching pair and the next sequential matching pair, and update the form at the same time. Then, perform the BFS path planning process again in sequence according to the latest form. This process is called backward swapping of end points. If a situation where the path cannot be planned still occurs, continue to swap the end points backward until all paths are completely planned. The maximum number of backward swaps is set to n times.

[0072] Among them, the first matching pair and the m-th matching pair in the form form a front-back relationship. The first pair is the next sequential matching pair of the m-th pair, and the m-th pair is the previous sequential matching pair of the first pair.

[0073] If, after executing the second end-point exchange algorithm n times, the situation where the path cannot be successfully planned still occurs, clear all path planning information and return the result as repair failure. If all path planning has been completed and the path information has been stored, return that the path search is successful and exit the algorithm, and return the result as repair success.

[0074] When the result is repair success, run the path conversion signal matrix algorithm. Extract the edges in each path in the path information, and filter out the coordinates of the edges existing on the basic switch unit. Mark binary "1" at the corresponding positions in the signal matrix, and mark binary "0" at the remaining positions in the signal matrix. Each binary "1" in the signal matrix represents that the transmission transistor at the corresponding position should be in the "on" state after repair, which is equivalent to a short circuit in electrical connection and can form a signal path. Each binary "0" in the signal matrix represents that the transmission transistor at the corresponding position should be in the "off" state after repair, which is equivalent to an open circuit in electrical connection and cannot form a signal path. In actual use, other representation methods can also be used, such as using binary "0" to represent the "on" state and binary "1" to represent the "off" state, etc.

[0075] The method of the present invention is verified by specific experiments below.

[0076] Taking a 5×5 switch array as an example, in the network node graph, the position coordinates of the TSV contain three elements: row, col, and id. Row represents the row in the array, col represents the column in the array, and id is the node coordinate of the basic switch unit connecting the TSV in the corresponding node graph. The position id value corresponding to the TSV connection is 0.

[0077] Each matching pair stored in the form contains three elements, namely the start point, the end point, and the Manhattan distance between the two. The pairing is denoted as Point-pair(start, goal, instance).

[0078] The following is a separate explanation from the following two aspects.

[0079] (1) The process of converting a 5×5 switch matrix connecting a TSV array into a network node graph.

[0080] For a TSV array of a specific scale, taking a 5×5 scale with a total of 25 signal TSVs as an example, which are connected to a 5×5 switch matrix. After converting the circuit diagram into a node diagram, the signal TSV (or faulty TSV) is located at the center position of the switch, denoted as node 0, represented as id = 0; Node 0 is connected to the right node of the switch (denoted as node 1); Node 1 is connected to the upper node of the switch (denoted as node 2) and the lower node (denoted as node 4), as well as the left node of the right switch (denoted as node 3; except for the switches in the rightmost column); Node 2 is also connected to node 3 and the 4th node of the upper switch (except for the switches in the uppermost row); Node 3 is also connected to the 1st node of the left switch (except for the switches in the leftmost column); Node 4 is also connected to the 2nd node of the lower switch (except for the switches in the lowermost row).

[0081] Refer to Figure 4 , select the switch in the second row and second column as the most typical connection relationship for explanation. Node 0 (1, 1, 0) is connected to node 1 (1, 1, 1); Node 1 is connected to node 2 (1, 1, 2) and node 4 (1, 1, 4); Node 2 (1, 1, 2) is also connected to node 3 (1, 1, 3) and the 4th node in the upper row (0, 1, 4); Node 3 is also connected to the 1st node on the right (1, 0, 1); Node 4 is also connected to the 2nd node below (2, 1, 2).

[0082] Refer to Figure 4 , in the switch in the first row and first column, the coordinate of node 0 is (0, 0, 0). Similarly, the coordinates of nodes 1 - 4 are (0, 0, 1), (0, 0, 2), (0, 0, 3), and (0, 0, 4) respectively. There is no additional connection relationship for nodes 2 and 3.

[0083] Refer to Figure 4 , on the right side of node 1 in the switch in the first row and last column, in addition to being connected to nodes 2 and 4 in the same switch, it is also connected to the right node R0, representing the connection relationship with the redundant TSV.

[0084] (2) Read the test result file, identify the faulty TSV, and match the start and end points according to the priority.

[0085] Refer to Figure 5, which is the test result file, shows the fault conditions of each TSV in the 5×5 TSV array. Among them, the binary "1" corresponds to the position where the TSV is a faulty TSV. In this embodiment, the coordinates of all faulty TSVs are (0, 1, 0), (1, 1, 0), (3, 1, 0), (2, 1, 0), and (0, 0, 0) respectively. Sort the known faulty TSVs according to the priority. The priority order in this embodiment is: {0, 4, 0}, {1, 4, 0}, {2, 4, 0}, {3, 4, 0}, {4, 4, 0}, {0, 3, 0}, {4, 3, 0}, {1, 3, 0}, {3, 3, 0}, {0, 2, 0}, {4, 2, 0}, {2, 3, 0}, {1, 2, 0}, {3, 2, 0}, {0, 1, 0}, {4, 1, 0}, {2, 2, 0}, {1, 1, 0}, {3, 1, 0}, {0, 0, 0}, {4, 0, 0}, {2, 1, 0}, {1, 0, 0}, {3, 0, 0}, {2, 0, 0}. After sorting the starting points according to the priority order, the order is: (0, 1, 0), (1, 1, 0), (3, 1, 0), (0, 0, 0), (2, 1, 0). Calculate the Manhattan distance from each starting point to each ending point in turn, and select the one with the shortest distance as the current ending point pair each time. The used ending points cannot be used again. The matching form result of this embodiment is:

[0086] 1. Starting point: (0, 1, 0), Ending point: R0;

[0087] 2. Starting point: (1, 1, 0), Ending point: R1;

[0088] 3. Starting point: (3, 1, 0), Ending point: R3;

[0089] 4. Starting point: (0, 0, 0), Ending point: R2;

[0090] 5. Starting point: (2, 1, 0), Ending point: R4.

[0091] The matching form result after this embodiment triggers the first ending point exchange algorithm 5 times and the second ending point exchange algorithm 1 time is:

[0092] 1. Starting point: (0, 1, 0), Ending point: R0;

[0093] 2. Starting point: (1, 1, 0), Ending point: R1;

[0094] 3. Starting point: (3, 1, 0), Ending point: R3;

[0095] 4. Starting point: (2, 1, 0), Ending point: R2;

[0096] 5. Starting point: (0, 0, 0), ending point: R4.

[0097] Refer to Figure 6 , which is a schematic diagram of the path planning result after performing the breadth - first search algorithm once in this embodiment. It can be seen from the figure that the full - path planning was not successfully carried out, meeting the triggering condition of the first end - point exchange algorithm, and starting to execute the first end - point exchange algorithm.

[0098] Refer to Figure 7 , which is a schematic diagram of the path planning result after performing the first end - point exchange algorithm 5 times in this embodiment. It can be seen from the figure that the full - path planning was still not successfully carried out. At this time, it meets the triggering condition of the second end - point exchange algorithm, and starts to execute the second end - point exchange algorithm.

[0099] Refer to Figure 8 , which is a schematic diagram of the path planning result after performing the second end - point exchange algorithm once in this embodiment. It can be seen from the figure that the program finally outputs all five valid paths, and the path planning is successfully carried out.

[0100] Refer to Figure 9 , extract the edges in each path, and screen out the coordinates of the edges existing on the basic switch unit, mark binary "1" at the corresponding positions of the signal matrix. Mark binary "0" at the remaining positions of the signal matrix. The signal matrix is used as the input of the switch matrix to control the construction of the repair path. Figure 9 The red edges in are the edges passed by the path, and the corresponding switches need to be closed. The fault repair system for the through - silicon vias of the three - dimensional integrated circuit of the present invention includes:

[0101] A switch matrix establishment unit, used to establish a switch matrix composed of n×n switch units. The switch unit includes four transmission transistors G1, G2, G3, and G4 connected in sequence at the first and last positions. The connection points between the four transmission transistors are used as external connection points to connect with other switch units to form a switch matrix;

[0102] The switch unit further includes a fifth transmission transistor G5. One end of G5 is connected between G1 and G4, and its connection point is called the first node;

[0103] The other end of G5 is connected to the through - silicon via. The first nodes on the edge rows or edge columns in the switch matrix are all connected to redundant through - silicon vias to obtain a through - silicon via repair circuit;

[0104] A through - silicon via test result reading unit, used to read the through - silicon via test results of the through - silicon via array to obtain the positions of m faulty through - silicon vias, where m≤n;

[0105] A network node graph conversion unit is used to convert the circuit diagram of a through-silicon via repair circuit into a network node graph. In the network node graph, nodes represent the connections between the ends of transmission transistors, and two nodes connected together form an edge.

[0106] A faulty through-silicon via repair unit is used to take the faulty through-silicon via as the starting point and the redundant through-silicon via as the ending point, and perform path planning between the starting point and the ending point according to the preset priority order of the through-silicon vias by using the breadth-first search algorithm to obtain m paths, and use the paths to repair the faulty through-silicon vias.

[0107] Among them, the edges in the network node graph included in each path represent that the transmission transistor is in the on state, and the rest of the transmission transistors are in the off state.

[0108] The computer-readable storage medium may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, flash memory, or any other medium that can store program code in the form of instructions or data structures and can be accessed by a computer.

[0109] The processor is used to execute the computer program stored in the memory to implement each step in the method involved in the above embodiments.

Claims

1. A method for repairing a fault of a three-dimensional integrated circuit through silicon via, characterized in that: The steps include: (1) Establishing a switch matrix consisting of n×n switch units, wherein the switch unit includes four transmission transistors G1, G2, G3 and G4 connected end to end in sequence, and the connection point between the four transmission transistors serves as an external connection point, which is connected to other switch units to form a switch matrix; The switch unit further includes a fifth transmission transistor G5, one end of which is connected between G1 and G4, and the connection point thereof is referred to as a first node; The other ends of G5 are all connected to TSVs, and the first nodes on edge rows or edge columns in the switch matrix are all connected to redundant TSVs, thereby obtaining a TSV repair circuit; (2) reading the test results of the through silicon vias in the through silicon via repair circuit to obtain the positions of m faulty through silicon vias, where m≤n; converting the circuit diagram of the through silicon via repair circuit into a network node diagram, in which a node represents a connection between two ends of a transmission transistor, and two nodes are connected to form an edge; (3) Taking the faulty TSV as the starting point and the redundant TSV as the end point, and using a breadth-first search algorithm to plan a path between the starting point and the end point according to a preset priority order of the TSVs, m paths are obtained, and the faulty TSV is repaired using the paths; The edges in the network node graph included in each path represent that the transmission transistor is in the on state and the other transmission transistors are in the off state.

2. The method for repairing a fault of a three-dimensional integrated circuit through silicon via according to claim 1, characterized in that: In step (3), the path planning between the starting point and the end point using the breadth-first search algorithm includes path connectivity constraints and path overlap constraints; The path connectivity constraint is that each node in each path is an adjacent node and there is no duplicate node; The path overlap constraint is that there are no reused nodes in each path.

3. The method for repairing a fault of a three-dimensional integrated circuit through silicon via according to claim 1, characterized in that: In step (3), before using the breadth-first search algorithm to plan the path between the starting point and the end point, the method further includes pairing the starting point and the end point: selecting a starting point in turn according to a preset priority order, calculating the Manhattan distance between the starting point and each optional end point, selecting the end point with the shortest Manhattan distance to pair with the starting point, and saving the matching pair of the starting point and the end point to a form; Each endpoint matches only one starting point, and unmatched endpoints are optional endpoints.

4. The method for repairing a fault of a three-dimensional integrated circuit through silicon via according to claim 3, characterized in that: In step (3), a matching pair is selected in turn according to a preset priority order, and a path is planned using a breadth-first search algorithm. When a path is not successfully planned, a forward exchange of endpoints is performed; The end point of the forward exchange is: deleting all the obtained paths, exchanging the current matching pair with the matching pair of the previous priority order, updating the table, selecting a matching pair in turn according to the priority order in the updated table, and using the breadth-first search algorithm for path planning; the maximum number of forward exchanges is set to n times.

5. The method for repairing a fault of a three-dimensional integrated circuit through silicon via according to claim 4, characterized in that: In step (3), after executing n forward exchange endpoints, if the path planning is unsuccessful using the breadth-first search algorithm, the backward exchange endpoint is performed; The backward exchange end point is: deleting all the obtained paths, exchanging the current matching pair with the matching pair of the next priority order for the table before the forward exchange end point, updating the table, selecting a matching pair in turn according to the priority order in the updated table, and performing path planning using a breadth-first search algorithm; The maximum number of backward exchanges is set to n.

6. A three-dimensional integrated circuit through silicon via fault repair system, characterized in that: include: A switch matrix establishing unit, used to establish a switch matrix consisting of n×n switch units, wherein the switch unit includes four transmission transistors G1, G2, G3 and G4 connected in sequence end to end, and the connection point between the four transmission transistors is used as an external connection point to connect with other switch units to form a switch matrix; The switch unit further includes a fifth transmission transistor G5, one end of which is connected between G1 and G4, and the connection point thereof is referred to as a first node; The other ends of G5 are all connected to TSVs, and the first nodes on edge rows or edge columns in the switch matrix are all connected to redundant TSVs, thereby obtaining a TSV repair circuit; A through silicon via test result reading unit, used to read the test result of the through silicon via in the through silicon via repair circuit, and obtain the positions of m faulty through silicon vias, m≤n; A network node graph conversion unit, used for converting a circuit diagram of a through silicon via repair circuit into a network node graph, in which a node represents a connection between two ends of a transmission transistor, and two nodes are connected to form an edge; A faulty TSV repair unit is used to use the faulty TSV as a starting point and the redundant TSV as an end point, and to plan a path between the starting point and the end point using a breadth-first search algorithm according to a preset priority order of the TSVs to obtain m paths, and to repair the faulty TSV using the paths; The edges in the network node graph included in each path represent that the transmission transistor is in the on state and the other transmission transistors are in the off state.

7. The three-dimensional integrated circuit through silicon via fault repair system according to claim 6, characterized in that: In the faulty through silicon via repair unit, the path planning between the starting point and the end point using the breadth-first search algorithm includes path connectivity constraints and path overlap constraints; The path connectivity constraint is that each node in each path is an adjacent node and there is no duplicate node; The path overlap constraint is that there are no reused nodes in each path.

8. The three-dimensional integrated circuit through silicon via fault repair system according to claim 6, characterized in that: In the faulty through silicon via repair unit, before using the breadth-first search algorithm to plan the path between the starting point and the end point, the starting point and the end point are paired: a starting point is selected in turn according to a preset priority order, the Manhattan distance between the starting point and each optional end point is calculated, the end point with the shortest Manhattan distance is selected to pair with the starting point, and the matching pair of the starting point and the end point is saved in a form; Each endpoint is matched with only one starting point, and the unmatched endpoints are optional endpoints; In the faulty through silicon via repair unit, a matching pair is selected in turn according to the preset priority order, and the path is planned using the breadth-first search algorithm. When the path planning is unsuccessful, the end point is forward exchanged; The end point of the forward exchange is: deleting all the obtained paths, exchanging the current matching pair with the matching pair of the previous priority order, updating the table, selecting a matching pair in turn according to the priority order in the updated table, and performing path planning using the breadth-first search algorithm; the maximum number of forward exchanges is set to n times; After executing n forward exchange endpoints, if the path planning is unsuccessful using the breadth-first search algorithm, the backward exchange endpoint is performed; The end point of the backward exchange is: delete all the obtained paths, exchange the current matching pair with the matching pair of the next priority order for the table before the forward exchange end point, update the table, select a matching pair in turn according to the priority order in the updated table, and use the breadth-first search algorithm to plan the path; the maximum number of backward exchanges is set to n times.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the computer program is loaded into a processor, the fault repair method of a three-dimensional integrated circuit through silicon via according to any one of claims 1 to 5 is implemented.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the fault repair method of a three-dimensional integrated circuit through silicon via according to any one of claims 1 to 5 is implemented.

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