Package substrate and method for manufacturing package substrate

Abstract

The present specification relates to a package substrate and a method for manufacturing a package substrate. In the package substrate according to the present specification, the core layer includes a glass core having a first surface and a second surface facing each other, and a cavity portion penetrating the glass core; an element module is arranged in the cavity part; the element module is formed by modularizing more than one cavity element and a cavity distribution layer through a capsule layer; the cavity distribution layer is a redistribution layer disposed on an upper portion of the cavity element. Therefore, misalignment caused by metal pitch difference generated when the cavity element is embedded is improved, the bonding pad pitch formed in the cavity element is enlarged, and the reject ratio occurring when the cavity element is connected and packaged can be greatly reduced.

Description

Technical Field

[0001] The present invention relates to a packaging substrate, a semiconductor package, a method for manufacturing a packaging substrate, a method for manufacturing a semiconductor package, etc. Background Art

[0002] In the manufacture of electronic products, the realization of circuits on semiconductor wafers is called the front-end process (FE), and the assembly of wafers into a state that can be used in actual products is called the back-end process (BE), which includes the packaging process.

[0003] Recently, the four core technologies of the semiconductor industry that enable the rapid development of electronic products include semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology is developing in various forms such as line widths of nanometer units below microns, more than tens of millions of cells, high-speed operations, and large amounts of heat dissipation, but there is no corresponding perfect packaging technology to back it up. Therefore, the electrical performance of semiconductors is not determined by the performance of semiconductor technology itself, but by packaging technology and its electrical connections.

[0004] As the material of the package substrate, ceramic or resin is suitable. In the case of a ceramic substrate such as a silicon substrate, the resistance value is high or the dielectric constant is high, so it is not easy to mount high-performance and high-frequency semiconductor components. In the case of a resin substrate, relatively high-performance and high-frequency semiconductor components can be mounted, but there are limitations in reducing the pitch of the wiring.

[0005] Recently, glass plates are used as high-end package substrates. Through holes are formed in the glass substrate, and conductive materials are applied to the through holes, thereby shortening the wiring length between the element and the motherboard, and achieving excellent electrical characteristics.

[0006] Related prior arts include Korean Patent Publication No. 10-2023-0008017, Japanese Patent Publication JP05114041, and the like. Summary of the invention

[0007] Problem that the invention aims to solve

[0008] An embodiment of the present invention aims to provide a packaging substrate and a method for manufacturing the packaging substrate as follows: the misalignment caused by a metal pitch difference generated when embedding a cavity element is improved.

[0009] In addition, an implementation example aims to provide a packaging substrate and a method for manufacturing the packaging substrate as follows: the pitch of pads formed on the cavity element is enlarged, thereby reducing the defect rate that may occur when connecting the package.

[0010] In addition, an implementation example aims to provide a packaging substrate and a method for manufacturing the packaging substrate as follows: by embedding a cavity element, the length of the electrical path is shortened, thereby reducing heat generation and electrical loss.

[0011] Means used to solve problems

[0012] In order to achieve the above-mentioned object, a packaging substrate according to an implementation example is a packaging substrate including a core layer.

[0013] The packaging substrate includes a core layer, the core layer includes a glass core and a cavity portion, the glass core has a first surface and a second surface facing each other, and the cavity portion passes through the glass core.

[0014] A device module is disposed in the cavity portion.

[0015] The element module is modularized by using a capsule layer to form more than one cavity element and a cavity distribution layer.

[0016] The cavity distribution layer is a redistribution layer disposed on an upper portion of the cavity element.

[0017] The cavity distribution layer may include at least two layers of the redistribution circuit layer.

[0018] The redistribution circuit layer includes i) a cavity bump layer; or ii) a through hole and circuit layer.

[0019] The cavity bump layer is a buffer layer, and the buffer layer is a conductive layer connected to the upper portion of the cavity element and capable of transmitting an electrical signal to the cavity element.

[0020] The through hole and the circuit layer are conductive layers connected to the cavity bump layer and transmitting electrical signals.

[0021] The vias may connect conductive layers in an up-down direction (xz or yz) in a circuit pattern.

[0022] The circuit layer may connect the conductive layer along a planar direction (xy) in a circuit pattern.

[0023] The cavity distribution layer may include: a first redistribution line distribution circuit layer, which is provided with the cavity bump layer; and a second redistribution line distribution circuit layer, which is formed by recessing the module insulation layer to provide the through hole and the circuit layer.

[0024] The module insulating layer is an insulating layer configured in the module.

[0025] A core conductive layer may be formed on the glass core, and the core conductive layer is a metal circuit pattern disposed on a surface of the glass core.

[0026] The pitch of the redistribution circuit layer may be smaller than the pitch of the core conductive layer.

[0027] A pitch of the second redistribution circuit layer may be greater than a pitch of the first redistribution circuit layer.

[0028] A pitch of the third redistribution circuit layer may be greater than a pitch of the second redistribution circuit layer.

[0029] A pad width of the second redistribution circuit layer may be greater than a pad width of the first redistribution circuit layer.

[0030] A metal pad width of the third redistribution circuit layer may be greater than a metal pad width of the second redistribution circuit layer.

[0031] The component module may include active components.

[0032] The component module may also include passive components.

[0033] The package substrate may further include an upper layer disposed on an upper portion of the core layer.

[0034] A pitch of the conductive pattern disposed on the lower surface of the upper layer may be greater than a minimum pitch of the cavity distribution layer.

[0035] The package substrate may further include a lower layer disposed below the core layer.

[0036] A pitch of the conductive pattern disposed on the upper surface of the lower layer may be greater than a minimum pitch of the cavity distribution layer.

[0037] In order to achieve the above object, a method for manufacturing a package substrate according to an implementation example includes: a preparation step of preparing a glass core having a cavity and a component module; and an arrangement step of arranging the component module in the cavity.

[0038] The element module is modularized by using a capsule layer to form more than one cavity element and a cavity distribution layer.

[0039] The cavity distribution layer is a redistribution layer disposed on an upper portion of the cavity element.

[0040] The cavity distribution layer includes at least two redistribution circuit layers.

[0041] The redistribution circuit layer may include i) a cavity bump layer, or ii) a via and circuit layer.

[0042] The cavity bump layer is a buffer layer, and the buffer layer is a conductive layer connected to the upper portion of the cavity element and capable of transmitting an electrical signal to the cavity element.

[0043] The through hole and circuit layer are conductive layers connected to the cavity bump layer and transmitting electrical signals to the outside of the component module.

[0044] The method for manufacturing the package substrate may further include a core conductive layer forming step.

[0045] The core conductive layer forming step may be performed between the preparing step and the arranging step or after the arranging step.

[0046] The core conductive layer forming step is a step of forming a core conductive layer on the glass core.

[0047] The pitch of the redistribution circuit layer may be smaller than the pitch of the core conductive layer.

[0048] The farther the redistribution circuit layer is from the cavity element in the cavity distribution layer, the wider the pitch of the redistribution circuit layer may become.

[0049] The component modules can be manufactured by modular steps.

[0050] The modularization step is a step of configuring a cavity distribution layer on the upper portion of the cavity element.

[0051] The cavity distribution layer includes at least two redistribution circuit layers.

[0052] The cavity distribution layer may be formed by a semi-additive process (SAP).

[0053] The component module includes active components.

[0054] The component module may also include passive components and be molded.

[0055] Effects of the Invention

[0056] The method for manufacturing a package substrate and the package substrate using the same according to the embodiment can improve misalignment caused by a metal pitch difference that may be generated when a cavity element is embedded.

[0057] In addition, the method for manufacturing a package substrate of the implementation example and the package substrate using the same can enlarge the pad pitch formed on the cavity element, thereby significantly reducing the defect rate that may occur when connecting the package.

[0058] In addition, the method for manufacturing a packaging substrate of the embodiment and the packaging substrate using the same can shorten the length of the electrical path by embedding the cavity element, thereby reducing heat generation and electrical loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1is a conceptual diagram illustrating a cross-sectional structure of a packaging substrate according to an implementation example.

[0060] Figure 2 is a conceptual diagram illustrating a cross-sectional structure of a packaging substrate according to another implementation example.

[0061] Figure 3 (a) and (b) are conceptual diagrams illustrating a portion of a package substrate of an implementation example in cross section.

[0062] Figure 4 The flowchart uses a cross section to illustrate a core distribution layer generation process in a manufacturing process of a package substrate according to an implementation example.

[0063] Figure 5 The flowchart uses a cross section to illustrate a process of generating an insulating layer in a process of manufacturing a package substrate according to an implementation example.

[0064] Figure 6 This is an example of a cross-sectional structure of a package substrate generated according to an implementation example.

[0065] Figure 7 and Figure 8 They are enlarged Figure 6 A cross-sectional view of a component module in a packaging substrate.

[0066] Fig. 9 It is a cross-sectional flow chart for explaining SAP (semi-additive process) according to an implementation example.

[0067] Fig.10 is an example of a cross-sectional structure of a packaging substrate generated according to another implementation example.

[0068] Description of Reference Numerals

[0069] 100: Semiconductor device 10: Motherboard

[0070] 30: semiconductor element portion 32: first semiconductor element

[0071] 34: second semiconductor element 36: third semiconductor element

[0072] 20: Package substrate 21, 21a: Glass substrate

[0073] 22: core layer 223: core insulation layer

[0074] 26: Upper layer 28: Cavity

[0075] 213: First side 214: Second side

[0076] 23: Core through hole 24: Core distribution layer

[0077] 241: Core distribution pattern 26: Upper layer

[0078] 251: Upper distribution pattern 252: Blind through hole

[0079] 253: Upper insulation layer

[0080] 271: Upper surface connection electrode 272: Upper surface connection pattern

[0081] 28: Cavity 281: Internal space

[0082] 29: Lower layer

[0083] 40: Cavity component 45: Component module

[0084] 70: Cavity distribution layer

[0085] 48: capsule layer 720: module insulation layer

[0086] 70a: first redistribution circuit layer 70b: second redistribution circuit layer

[0087] 70c: third redistribution circuit layer 705: through hole

[0088] 703: Circuit layer

[0089] 701: Cavity bump layer 63: Core conductive layer

[0090] 40a: Active component in the cavity component 40b: Passive component in the cavity component

[0091] 50: Connecting part 51: Component connecting part

[0092] 52: Plate connection

[0093] 60: Overlay DETAILED DESCRIPTION

[0094] In order to facilitate a general understanding of the methods, devices and / or systems described in this specification, a detailed description is provided as follows. However, various changes, modifications and equivalents of the methods, devices and / or systems described in this specification will be apparent after understanding the contents proposed by this application. For example, the order of actions described in this specification is merely an example and is not limited to the actions recorded in this specification. In addition to the steps that must be performed in a certain order, the order of operations can be changed according to the understanding of the contents disclosed in this application. In addition, the description of known features may be omitted in order to improve the clarity and conciseness of the description after understanding the disclosure of this application. However, the omission of this feature and this description is not intended to be recognized as common knowledge.

[0095] The features described in this specification may be implemented in different forms and shall not be limited to the examples described in this specification. On the contrary, the embodiments described in this specification are provided to illustrate a part of the implementation methods of the various feasible methods, devices and / or systems described in this specification to be clarified after the disclosure of this application.

[0096] In this specification, the terms "first", "second", "third", etc. may be used to describe various parts, components, regions, layers or sections, but these parts, components, regions, layers or sections shall not be limited by such words. On the contrary, such terms are used for the purpose of distinguishing a combined part, component, region, layer or section from its combined part, component, region, layer or section. Therefore, the first part, component, region, layer or section mentioned in the embodiments described in this specification may also be referred to as the second part, component, region, layer or section without departing from the teachings of the embodiments.

[0097] Throughout the specification, when an element such as a layer, region, or substrate is described as being "located on," "connected to," or "bonded to" another element, it may be described as being directly "located on," "connected to," or "bonded to" the other element or as having one or more other elements interposed therein. In contrast, when describing a component as "directly located on," "directly connected to," or "directly bonded to," no other elements may be interposed therein. Similarly, expressions such as "between," "directly between," and "in contact with," "directly in contact with," may also be interpreted as described above.

[0098] The terms used in this specification are only used to illustrate specific examples and are not used to limit disclosure. For the singular form used in this specification, unless there is a clear different statement in the context, the plural form may also be included. The term "and / or" used in this specification includes any one of the related items or a combination of more than two items. The terms "including", "constituting" and "having" used in this specification refer to the existence of specified features, numbers, actions, elements, components and / or these combinations, and do not exclude the existence or increase of more than one other features, numbers, actions, elements, components and / or these combinations. In this specification, the term "may" is used with respect to examples or embodiments (for example, what examples or embodiments may include or implement), which refers to the existence of at least one example or embodiment that includes or implements such features, but not all examples are limited to this.

[0099] In the present application, “B is located on A” means that B is directly in contact with A or is disposed on A with other layers or structures interposed therebetween, and thus it should not be interpreted that B is in direct contact with A.

[0100] Unless otherwise defined, all terms used in this specification have the same meaning as commonly understood by one of the common techniques in the technical field to which the present invention belongs. Terms such as commonly used and defined in dictionaries should be interpreted as having the same meaning as in the context of the prior art and the present invention, and shall not be interpreted with idealized or overly formal meanings unless explicitly defined herein.

[0101] In the one or more examples, the description of "A and / or B" refers to "A, B, or A and B."

[0102] In the one or more examples, terms such as “first”, “second”, “A” or “B” are used to distinguish the same terms.

[0103] In the one or more examples described above, the singular form is interpreted in the text as also including the plural form unless otherwise specifically mentioned.

[0104] Figure 1 is a conceptual diagram illustrating a cross-sectional structure of a packaging substrate according to an implementation example; Figure 2 is a conceptual diagram illustrating a structure of a packaging substrate according to another implementation example in cross section; Figure 3 (a) and (b) are conceptual diagrams illustrating a portion of a package substrate of an implementation example in cross section.

[0105] In order to achieve the above-mentioned purpose, the semiconductor device 100 according to the implementation example includes: a semiconductor element portion 30, which is provided with one or more semiconductor elements 32, 34, 36; a packaging substrate 20, which is electrically connected to the semiconductor element; and a motherboard 10, which is electrically connected to the packaging substrate 20, and transmits external electrical signals to the semiconductor elements 32, 34, 36 and is connected to each other.

[0106] According to an implementation example, the packaging substrate 20 includes: a core layer 22 , an upper layer 26 and a cavity portion 28 . The upper layer 26 is located on one surface of the core layer 22 . A cavity element 40 or an element module 45 can be configured in the cavity portion 28 .

[0107] The semiconductor element portion 30 is an element mounted on a semiconductor device and is mounted on the package substrate 20 via connection electrodes, etc. Specifically, as the semiconductor element portion 30, computing elements (first element 32, second element 34) such as a CPU, a GPU, etc., memory elements (third element 36) such as a memory chip, etc., etc. can be applied, but any semiconductor element mounted on a semiconductor device can be applied without limitation.

[0108] The motherboard 10 can be a motherboard such as a printed circuit board or a printed wiring board.

[0109] Optionally, the packaging substrate 20 may further include a lower layer (not shown), and the lower layer is located below the core layer.

[0110] The core layer 22 may include: a glass substrate 21, including a first area 221 and a second area 222, the first area 221 having a first thickness, the second area 222 being adjacent to the first area 221 and having a second thickness, the second thickness having a thickness less than the first thickness (half cavity) or a thickness of 0 mm (full cavity); a plurality of core through holes 23, penetrating the glass substrate 21 along a thickness direction; and a core distribution layer 24, located on a surface of the glass substrate 21 or the core through holes 23, and electrically connecting a first surface 213 and a second surface 214 of the glass substrate 21 through the core through holes 23, the second surface 214 and the first surface facing each other. Figure 2 and Figure 3 A form called full cavity is proposed in which the second region of the glass substrate is opened.

[0111] The second region 222 of the core layer 22 may function as a cavity structure.

[0112] In the same region, the glass substrate 21 has a first surface 213 and a second surface 214 facing each other, and the two surfaces are substantially parallel to each other, so that the glass substrate 21 has a predetermined thickness as a whole.

[0113] The inner space 281 formed by the thickness difference between the first region 221 and the second region 222 plays a role in accommodating a part or all of the cavity element 40 or the element module 45 .

[0114] The glass substrate 21 may include a core through hole 23 that penetrates the first face 213 and the second face 214. The core through hole 23 may be formed in both the first region 221 and the second region 222 and formed in a desired pitch and pattern.

[0115] As a packaging substrate for semiconductor devices, a stacked form of silicon substrates and organic substrates has been used in the past. In the case of silicon substrates, due to the semiconductor characteristics, there is a risk of generating parasitic elements when applied to high-speed circuits, and there is a disadvantage of relatively large power loss. In addition, in the case of organic substrates, a large area is required to form a more complex distribution pattern, but this does not conform to the trend of ultra-miniaturized electronic device manufacturing. In order to form a complex distribution pattern within a set size, the pattern actually needs to be refined, but due to the material characteristics of polymers and other materials applicable to organic substrates, there are actually limitations in terms of pattern refinement.

[0116] In the implementation example, as a method for solving these problems, the glass substrate 21 is used as a support body for the core layer 22. In addition, by using the core through hole 23 formed by penetrating the glass substrate 21 together with the glass substrate 21, a package substrate 20 having characteristics of further shortening the length of the current flow, further miniaturization, faster response and less loss is provided.

[0117] The glass substrate 21 is preferably a glass substrate suitable for semiconductors, such as a borosilicate glass substrate, an alkali-free glass substrate, etc., but is not limited thereto.

[0118] The core through hole 23 passes through the glass substrate 21. The core through hole 23 may be formed by removing a predetermined area of ​​the glass substrate 21, and specifically, may be formed by etching a plate-shaped glass by physical and / or chemical methods.

[0119] Specifically, the core through hole 23 may be formed by forming a defect (stain) on the surface of the glass substrate using a laser or the like and then performing chemical etching, laser etching, or the like, but the present invention is not limited thereto.

[0120] Based on the unit area (1 cm×1 cm) of the glass substrate 21, the number of the core through holes 23 may be 100 to 3,000, 100 to 2,500, or 225 to 1,024. When such pitch conditions are met, a conductive layer may be formed and the performance of the package substrate may be improved.

[0121] The core distribution layer 24 includes a core distribution pattern 241 and a core insulation layer 223. The core distribution pattern 241 is a conductive layer that electrically connects the first surface and the second surface of the glass substrate through a through hole, and the core insulation layer 223 surrounds the core distribution pattern. The core layer 22 forms a conductive layer through the core through hole inside and acts as an electrical channel that crosses the glass substrate 21, and connects the upper and lower parts of the glass substrate at a relatively short distance, so that it can have the characteristics of faster transmission of electrical signals and low loss. For example, the conductive layer can be applied to, for example, a copper-plated layer, but is not limited thereto.

[0122] The shape of the cavity 28 can actually be circular, triangular, quadrilateral, hexagonal, octagonal, cross-shaped, etc., and there is no limitation on the shape.

[0123] The shape of the cavity element 40 can be substantially cylindrical, rectangular hexahedron or polygonal.

[0124] The cavity portion may be implemented in the form of penetrating the first surface 213 and the second surface 214 of the glass substrate 21. In this case, the cavity portion may be formed by a process similar to that of forming the core through hole 23, and the area and shape of the through glass substrate 21 may be different from those of the core through hole 23.

[0125] In this implementation example, the insulating layer may be formed after arranging the cavity element 40 or the element module 45 in the cavity portion. That is, the insulating layer may also be formed in the cavity portion through the above-mentioned core insulating layer 223 forming process.

[0126] In the case where the cavity element 40 is directly disposed in the cavity portion, the core distribution pattern 241 is formed so as to be electrically connected to the cavity element 40. The case where the element module 45 is arranged in the cavity portion will be described later.

[0127] The cavity element 40 may include an active element such as a transistor or a power transmission element such as a multi-layer ceramic capacitor (MLCC), i.e., a passive element. In addition, the cavity element 40 may include an active element such as a computing element such as a CPU, a GPU, a memory element such as a memory chip, etc.

[0128] As described below, the cavity elements may also be modularized for insertion.

[0129] When an element such as a transistor that plays the role of converting an electrical signal between a motherboard and a semiconductor element portion into an appropriate level is used as the cavity element 40, a transistor or the like is used in a path of the packaging substrate 20, thereby providing a more efficient and faster semiconductor device 100.

[0130] In addition, power transmission components such as multilayer ceramic capacitors (MLCC) play an important role in the performance of semiconductor components. Power transmission components as passive components are usually applied to semiconductor components at least 200, and the characteristics of the conductive layer around the component are also affected by the performance when power is transmitted. In one implementation example, non-circular core vias that are not circular can be applied to places such as power transmission components where a low resistance conductive layer is required.

[0131] On the other hand, a passive element such as a capacitor may be inserted alone and used as the cavity element 40, or an element group including a plurality of passive elements may be formed in a manner of exposing electrodes in the form of being embedded between insulating layers (cavity element insulating layers) and then inserted into the cavity element. In the latter case, the operability of manufacturing the package substrate can be made smoother, and it is more conducive to making the insulating layer have a space that is reliable and sufficient to be located between complex elements.

[0132] On the other hand, in the case where an active element is used as a cavity element, there are additional considerations of wiring, heat dissipation, etc. This will be described later.

[0133] The glass substrate 21 serves as an intermediate and intermediary for connecting the semiconductor element 30 and the motherboard 10 at the upper and lower parts, respectively, and the core through hole 23 serves as a channel for transmitting its electrical signal, thereby achieving smooth transmission of the signal. For the purpose of distinguishing from the core through hole in the second area 222 described later, the core through hole arranged in the first area 221 is referred to as the first area core through hole 231.

[0134] An upper layer 26 is arranged on the first surface 213 .

[0135] The upper layer 26 may include an upper distribution layer 25 and an upper surface connection layer 27. The upper surface connection layer 27 is located on the upper distribution layer 25. The uppermost surface of the upper layer 26 may be protected by a covering layer 60. The covering layer 60 may be directly connected to the connection electrode of the semiconductor element part and an opening portion is formed in the covering layer 60.

[0136] The upper distribution layer 25 may include: an upper insulating layer 253 located on the first surface; and upper distribution patterns 251, which are conductive layers having a predetermined pattern and at least a portion of which is electrically connected to the core distribution layer 24, and are built into the upper insulating layer 253. A plurality of upper distribution patterns 251 arranged one above the other may be connected to each other through blind vias 252.

[0137] The upper insulating layer 253 can be used as long as it is used as an insulating layer in a semiconductor element or a package substrate. For example, epoxy resin containing a filler can be used, but it is not limited thereto.

[0138] The insulator layer can be formed by forming and curing a coating layer, or by laminating an insulating film in an uncured or semi-cured state to the core layer 22 and curing it. In this case, if a reduced pressure lamination method is used, the insulator is recessed into the space inside the core through hole 23, so that the process can be performed efficiently.

[0139] According to an implementation example, even if multiple insulating layers are stacked, it may be difficult to distinguish the multiple insulating layers, and the multiple insulating layers are collectively referred to as upper insulating layers. In addition, the core insulating layer 223 and the upper insulating layer 253 may be made of the same insulating material, in which case the boundary cannot be actually distinguished. Alternatively, according to another implementation example, different curing pressures and temperatures are set for the multiple insulating layers, so that the boundary of the insulating layer can also be generated.

[0140] The upper distribution pattern 251 refers to a conductive layer located in the upper insulating layer 253 in a predetermined form, and can be formed, for example, by a build-up layer method. Specifically, an insulating layer is formed, and unnecessary portions of the insulating layer are removed, and then a conductive layer is formed by copper plating or the like, and unnecessary portions of the conductive layer are selectively removed, and then an insulating layer is re-formed on the conductive layer, and unnecessary portions are removed again, and then a conductive layer is formed by gold plating. This method can be repeated to form an upper distribution pattern 251 having a conductive layer formed in a vertical or horizontal direction in a desired pattern.

[0141] Since the upper distribution pattern 251 is located between the core layer 22 and the semiconductor element portion 30, in order to smoothly transmit electrical signals with the semiconductor element portion 30 and fully accommodate the desired complex pattern, at least a portion of the upper distribution pattern 251 includes a fine pattern. At this time, the fine pattern may refer to a pattern with a width and a spacing less than 4 μm, a pattern less than 3.5 μm, a pattern less than 3 μm, a pattern less than 2.5 μm, or a pattern of 2.3 μm. The width and spacing may be 1 μm or more (hereinafter, the same as the description of the fine pattern).

[0142] The upper surface connection layer includes an upper surface connection pattern 272 and an upper surface connection electrode 271 , at least a portion of which is electrically connected to the upper distribution pattern 251 and is located on the upper insulating layer 253 , and the upper surface connection electrode 271 electrically connects the semiconductor element portion 30 and the upper surface connection pattern 272 .

[0143] The upper surface connection pattern 272 may also be located on one surface of the upper insulating layer 253, or at least a portion of the upper surface connection pattern 272 may be exposed on the upper insulating layer 253 and embedded in the upper insulating layer 253. For example, in the case where the upper surface connection pattern is located on one side of the upper insulating layer, the upper insulating layer may be formed by gold plating or the like; in the case where a portion of the upper surface connection pattern is exposed on the upper insulating layer and embedded in the upper insulating layer, a portion of the insulating layer or the conductive layer may be removed by surface grinding, surface etching or the like after forming a copper plating layer or the like.

[0144] Similar to the upper distribution pattern 251 described above, at least a portion of the upper surface connection pattern 272 may include a fine pattern. The upper surface connection pattern 272 including the fine pattern enables more components to be electrically connected in a narrow area, thereby enabling smoother electrical signal connection between components or with the outside, thereby achieving a more integrated package.

[0145] The upper surface connection electrode 271 and the semiconductor element portion 30 may be directly connected via a terminal or the like, or may be connected via an element connection portion 51 such as a solder ball.

[0146] Compared with the first region 221, the thickness of the glass substrate 21 in the second region 222 is thinner, and the cavity element 40 can be provided in the internal space 281 formed by the thickness difference. In addition, the core through hole 23 and the core distribution layer 24 formed in the glass substrate 21 play the role of an electrical connection structure connecting the cavity element 40 and external elements.

[0147] In addition, as described above, a cavity portion penetrating the first surface 213 and the second surface 214 of the glass substrate 21 may be formed in the first region 221 (rather than the second region 222 ), and the cavity elements 40 may be arranged in the cavity portion.

[0148] The package substrate 20 is also connected to the motherboard 10. In the motherboard 10, the core distribution pattern 241 located on at least a portion of the second surface 214 of the core layer 22 can be directly connected to the terminal of the motherboard 10, and can also be electrically connected through a board connection portion 52 such as a solder ball. In addition, the core distribution pattern 241 in contact with the motherboard 10 can also be connected to the motherboard 10 through a lower layer (not shown) located at the lower part of the core layer 22. The element connection portion 51 and the board connection portion 52 are collectively referred to as a connection portion 50.

[0149] According to an example, in the package substrate 20 located between the semiconductor device portion 30 and the motherboard 10 , except for the glass substrate 21 , no additional substrate may be used.

[0150] In the past, an interposer and an organic substrate were stacked and applied between the connecting element and the motherboard. It is understood that this multi-stage form is applied for at least two reasons. One is that there is a scale problem when directly bonding the fine pattern of the element to the motherboard, and the other is that the wiring may be damaged due to the difference in thermal expansion coefficient during the bonding process or the driving process of the semiconductor device. In the implementation example, a glass substrate with a thermal expansion coefficient similar to that of the semiconductor element is applied, and a fine pattern with a small size (scale) sufficient to mount the element is formed on the first surface of the glass substrate and its upper layer to solve these problems.

[0151] Hereinafter, a method for manufacturing a package substrate according to an implementation example of the present invention will be described.

[0152] Figure 4 and Figure 5 The flowchart uses a cross section to illustrate a manufacturing process of a packaging substrate according to an implementation example.

[0153] First, if Figure 4As shown in (a), a glass substrate 21a having a flat first surface and a flat second surface is prepared, and a defect 21b (groove) is formed on the glass surface at a predetermined position in order to form a core through hole. The glass substrate can be a glass substrate used for an electronic device substrate, for example, an alkali-free glass substrate, but is not limited thereto. As a commercial product, products manufactured by manufacturers such as Corning, Schott, and AGC can be used. The defect (groove) can be formed by mechanical etching, laser irradiation, etc.

[0154] like Figure 4 As shown in (b), an etching step of forming a core through hole 23 by a physical or chemical etching process is performed on the glass substrate 21a formed with a defect 21b (groove). During the etching process, the glass substrate forms a through hole in the defective portion, and the surface of the glass substrate 21a can also be etched. In order to prevent such etching of the glass surface, a shielding film or the like can also be applied. However, considering the trouble of removing the shielding film after application, etc., the defective glass substrate itself can be etched. In this case, the thickness of the glass substrate with the core through hole can be slightly smaller than the thickness of the initial glass substrate.

[0155] After this, if Figure 4 As shown in (c) and (d) of FIG. 1 , the core layer manufacturing step can be performed by forming a conductive layer 21d on a glass substrate. As the conductive layer, a metal layer containing copper metal can be typically used, but is not limited thereto.

[0156] The surface of the glass (including the surface of the glass substrate and the surface of the core through hole) and the surface of the copper metal have different properties, so the adhesion can be reduced. In the implementation example, the adhesion between the glass surface and the metal can be improved by two methods, a dry method and a wet method.

[0157] The dry method is a method suitable for sputtering, that is, a method of forming a seed layer 21c on the glass surface and the inner diameter of the core through hole by sputtering metal. In the formation of the seed layer, different types of metals such as titanium, chromium, and nickel can be sputtered together with copper. In this case, the glass-metal adhesion can be improved by the anchoring effect of the interaction between the surface morphology of the glass and the metal particles.

[0158] The wet mode is that the mode of primer treatment is to utilize the compound material with the functional group of amine etc. to carry out pretreatment to form the mode of primer layer 21c.According to the desired adhesion degree, after pretreatment with silane coupling agent, primer treatment can be carried out with compound or particle with amine functional group.As mentioned above, the support substrate of realization example needs the high performance of the degree that can be enough to form fine pattern, and also should keep this high performance after primer treatment.Accordingly, when this primer comprises nanoparticle, preferably applicable to have the nanoparticle of the size below 150nm of average diameter, for example, the particle with amine group is preferably applicable to nanoparticle.Give an example, the bonding strength improver of the CZ series etc. manufacturing of applicable MEC company of described primer layer is formed.

[0159] The seed layer / undercoat layer 21c selectively forms a metal layer as a conductive layer in a state where the portion not required to form the conductive layer is removed or not removed. In addition, the seed layer / undercoat layer 21c selectively processes the required portion or the unnecessary portion for forming the conductive layer in the gold plating in an activated or inactivated state and then performs subsequent processes. For example, the activation or inactivation treatment may be applied to light irradiation treatment of a predetermined wavelength, chemical treatment, etc. The metal layer may be formed by a copper plating method used to manufacture semiconductor elements, but is not limited thereto.

[0160] like Figure 4 As shown in (e), a portion of the core distribution layer can be removed when it is not needed. After a portion of the seed layer is removed or deactivated, gold plating can be performed, so that a conductive layer can be formed in a predetermined pattern, thereby forming an etching layer 21e of the core distribution layer.

[0161] Figure 5 The manufacturing steps of forming an insulating layer and an upper distribution pattern are described according to an implementation example.

[0162] like Figure 5 As shown in (a), the core through hole may be subjected to an insulating layer forming step, wherein the insulating layer forming step is to fill the empty space with an insulating layer after forming the core distribution layer as the conductive layer. At this time, the applicable insulating layer may be manufactured in the form of a thin film, for example, a method of performing reduced pressure lamination on the insulating layer in the form of a thin film may be applied. If reduced pressure lamination is performed in this way, the insulating layer is sufficiently recessed into the empty space inside the core through hole, and the core insulating layer can be formed without a gap.

[0163] Figure 5 (b) to (e) illustrate the upper layer manufacturing steps.

[0164] The upper layer manufacturing step is a step of forming an upper distribution layer including an upper insulating layer and an upper distribution pattern on the core layer. The upper insulating layer can be formed by coating a resin composition or a laminated insulating film to form the insulating layer 23a. It is preferable to simply laminate the insulating film. The lamination of the insulating film can be carried out by laminating the insulating film and curing the insulating film. At this time, if a reduced pressure lamination method is applied, the insulating resin can be fully recessed to a layer where no conductive layer is formed inside the core through hole. At least a portion of the upper insulating layer is also directly connected to the glass substrate, so a material with sufficient adhesion is suitable. Specifically, the glass substrate and the upper insulating layer preferably have a property that the adhesion test value tested according to ASTM D3359 meets 4B or above.

[0165] The upper distribution pattern is formed by repeating the following process: forming the insulating layer 23a and forming the conductive layer 23c in a predetermined pattern, etching the unnecessary part to form an etching layer 23d of the conductive layer, and in the case of the conductive layer formed adjacently with the insulating layer in between, it can be formed by forming a blind through hole 23b in the insulating layer and then performing a gold plating process. The blind through hole can be formed by dry etching such as laser etching and plasma etching, and wet etching using a mask layer and an etching solution.

[0166] Afterwards, although not shown, an upper surface connection layer and a cover layer may be formed.

[0167] The upper surface connection pattern and the upper surface connection electrode can also be formed by a process similar to the formation of the upper distribution layer. Specifically, it can be formed by forming an etching layer of the insulating layer on the insulating layer 23e and then forming an etching layer of the conductive layer therein, but it is also possible not to use the etching method and selectively form only the conductive layer. The covering layer can form an opening (not shown) at a position corresponding to the upper surface connection electrode and expose the upper surface connection electrode, so that it can be directly connected to the component connection part or the terminal of the component.

[0168] If the upper layer is generated, the lower surface connection layer and the covering layer are formed, and the process of forming the lower layer can be performed. The lower distribution layer and / or the lower surface connection layer can be formed in a manner similar to the upper surface connection layer and the covering layer formation steps described above, and the covering layer (not shown) can be selectively formed.

[0169] refer to Figure 2 and Figure 3As described above, a cavity element may be embedded in the cavity portion, and the cavity element may include an active element or a passive element. On the other hand, fine metal wiring is required for the electrode connected to the active element, and the fine metal wiring may have a size difference with the metal wiring formed on the glass substrate. Since there is a difference in the size, i.e., the pitch, of the metal wiring to be connected to each other, misalignment may occur when the cavity element is built in, and defects may occur when the package is connected.

[0170] Accordingly, this specification proposes an embodiment that prevents misalignment between metal patterns that have a pitch difference with fine metal patterns that should be connected to active components, etc., thereby preventing defects. According to an implementation example of this specification, it is proposed that fine metal patterns of cavity components that should be connected to active components, etc. are pre-formed and embedded in cavity components such as active components. In addition, an implementation example of configuring redistribution lines in the following manner is proposed: the pitch of through holes connected to fine metal bumps and the pitch of circuit layers are gradually expanded as the layers are away from the active components, so as to facilitate the connection of high-density bump parts.

[0171] Figure 6 is an example of a cross-sectional structure of a packaging substrate generated according to an implementation example; Figure 7 and Figure 8 They are enlarged Figure 6 A cross-sectional view of a component module in a packaging substrate; Fig.10 is an example of a cross-sectional structure of a packaging substrate generated according to another implementation example.

[0172] Figures 6 to 8 The package substrate or component module is a conceptually simplified diagram for explaining the package substrate generated according to the implementation example, and can be used as a reference Figures 1 to 3 The content of the description.

[0173] For example, the core layer 22 includes a glass substrate 21 having a first surface and a second surface facing each other, and may further include a core through hole penetrating the glass substrate 21. A core conductive layer 63 may be formed on the surface of the glass substrate 21. The core conductive layer 63 is a general concept of the core distribution layer 24 and the core distribution pattern 241 described above.

[0174] The core conductive layer 63 is selectively formed on the inner wall surface of the core through hole. Figure 6 The cavity 28 can be formed by completely penetrating the first surface and the second surface of the glass substrate 21. Optionally, a core conductive layer 63 can be formed on the inner wall surface of the cavity. The component module 45 can be arranged inside the cavity 28. The cavity 28 can be formed simultaneously by the same formation step as the core through hole, or it can be formed separately after the core through hole is formed or before the core through hole is formed.

[0175] The element module 45 includes a cavity element 40 and a cavity distribution layer 70 . The cavity distribution layer 70 is a distribution layer formed on the upper portion of the cavity element 40 .

[0176] The element module 45 is modularized by using a capsule layer 48 to form one or more cavity elements 40 and a cavity distribution layer 70. The cavity distribution layer 70 is a redistribution layer disposed on the upper part of the cavity element 40 (see Figure 7 ).

[0177] According to an implementation example, the cavity element 40 may include an active element. Figure 6 The component module 45 disposed inside the cavity portion 28 is cut and packaged after the cavity allocation layer 70 is formed and can be inserted into the cavity portion 28 .

[0178] The cavity distribution layer 70 may include two or more layers or three or more layers of redistribution circuit layers. The redistribution circuit layer refers to i) the cavity bump layer 701 or ii) the through hole 705 and the circuit layer 703 included in the cavity distribution layer.

[0179] The i) cavity bump layer 701 is a buffer layer, which is a conductive layer connected to the upper portion of the cavity element 40 and capable of transmitting electrical signals to the cavity element 40 .

[0180] The through hole 705 and the circuit layer 703 are conductive layers that are connected to the cavity bump layer 701 and transmit electrical signals to the outside of the component module 45 .

[0181] The ii) through hole 705 and the circuit layer 703 (single layer) can be connected to the cavity bump layer 701. The through hole can connect the conductive layer along the up-down direction (xz or yz) in the circuit pattern. The circuit layer can connect the conductive layer along the planar direction (xy) in the circuit pattern. The ii) through hole 705 and the circuit layer 703 can transmit electrical signals to the outside of the cavity bump layer 701 and the additional through hole 705 and the circuit layer 703 or the core layer 22.

[0182] The ii) through holes and circuit layers may be arranged in more than one layer, and may be arranged in more than two layers in the redistribution circuit layer. In addition, the ii) through holes and circuit layers in the cavity allocation layer 70 may be arranged in less than 15 layers or less than 10 layers.

[0183] exist Figures 6 to 8 A three-layer configuration is illustrated, with one layer of i) cavity bump layer, and two layers of ii) via and circuit layer, but the configuration may be two layers, four layers, or more than five layers. Figure 8 is a flowchart illustrating a method for manufacturing a packaging substrate according to an implementation example.

[0184] The cavity distribution layer 70 may include a conductive layer (including a cavity bump layer 701, a through hole 705, a circuit layer 703) and an insulating layer. The insulating layer is used to distinguish the insulating layer of the core layer, the upper layer or the lower layer, and is called a module insulating layer 720. The module insulating layer 720 is an insulating layer configured in the module.

[0185] For example, the conductive layer may be a metal layer. The metal layer may refer to all metal patterns configured in a form similar to a circuit pattern. The metal layer includes a metal pattern. The metal layer may include a redistribution circuit layer and a metal pattern that is not a redistribution circuit layer. For example, the metal layer may also include a ground pattern and a heat dissipation pattern, but is not limited thereto.

[0186] like Figure 7 As shown, the cavity distribution layer 70 may include a first redistribution line distribution circuit layer 70a, a second redistribution line distribution circuit layer 70b, and a third redistribution line distribution circuit layer 70c.

[0187] The first rewiring distribution circuit layer 70 a may be a layer configured with a cavity bump layer 701 .

[0188] The second redistribution circuit layer 70b may be a layer in which the through hole 705 and the circuit layer 703 are recessed in the module insulating layer 720. The through hole and the circuit layer of the second redistribution circuit layer are respectively referred to as the first through hole and the first circuit layer for the purpose of distinguishing them from the through hole and the circuit layer of the third redistribution circuit layer.

[0189] The third redistribution wiring distribution circuit layer 70c may be a layer in which the through hole 705 and the circuit layer 703 are recessed and arranged in the module insulation layer 720. The through hole and the circuit layer of the third redistribution wiring distribution circuit layer are respectively referred to as the second through hole and the second circuit layer for the purpose of distinguishing them from the through hole and the circuit layer of the second redistribution wiring distribution circuit layer. The through hole may be a blind through hole.

[0190] The first redistribution line distribution circuit layer 70a, the second redistribution line distribution circuit layer 70b and the third redistribution line distribution circuit layer 70c can be stacked up and down in sequence. In this case, the cavity bump layer 701 is connected to the first through hole, the first through hole is connected to the first circuit layer, the first circuit layer is connected to the second through hole, and the second through hole can be connected to the second circuit layer. Through this redistribution circuit layer, electrical signals can be transmitted to the cavity element configured in the element module.

[0191] The circuit layer and the through hole can be arranged in the insulating layer.

[0192] The insulating layers configured in each layer of the first redistribution circuit layer 70a, the second redistribution circuit layer 70b, the third redistribution circuit layer 70c, etc. can be distinguished from each other, and depending on the situation, such as depending on the situation of applying the same insulating material, they may appear to be integrated and indistinguishable from each other.

[0193] In the redistribution circuit layer, the thickness of the circuit layers (excluding the cavity bump layer) respectively configured in the first circuit layer and the second circuit layer corresponding to the circuit layer area can be 2 μm or more, 3 μm or more, or 4 μm or more, and can be 20 μm or less. The thickness of the insulating layer of the cavity distribution layer can be 5 μm or more, 7 μm or more, or 10 μm or more. In addition, the thickness of the insulating layer of the cavity distribution layer can be 20 μm or less or 18 μm or less.

[0194] The precision of the redistribution line distribution circuit layer formed on the package substrate can be expressed by a pitch, which is the distance between the redistribution line distribution circuit layers. It can be seen that the narrower the pitch, the finer the pattern can be formed.

[0195] According to this implementation example, a core conductive layer 63 may be disposed on the glass core.

[0196] The pitch d1 of the core conductive layer 63 may be greater than the pitch d2 of the cavity distribution layer 70 formed on the cavity element 40 .

[0197] A finer conductive layer than the core layer 22 may be formed in the cavity element 40 .

[0198] The pitch of the cavity element 40, such as the pad, may be smaller than the pitch of the pad formed on the core layer 22. In this case, using active elements as cavity elements will be more conducive to effective signal transmission. Here, the pad refers to a conductive layer formed at the upper end or the lower end of the through hole as a frame of the through hole.

[0199] The pitch of the redistribution circuit layer may be smaller than the pitch of the core conductive layer 63 .

[0200] The case of a redistribution circuit layer connected to an active element requires a fine pitch. In the case of this implementation example, in order to prevent misalignment between the core conductive layer 63 formed on the glass substrate 21 and the active element, a fine metal pattern is formed on the active element in the form of a redistribution circuit layer to enable pitch matching.

[0201] In addition, the higher the number of layers of the cavity distribution layer 70 is (the farther away from the cavity element), the wider the pitch of the redistribution circuit layer can become.

[0202] When the width of the conductive layer of the first wiring distribution circuit layer 70a is wn1, the width of the metal wire of the second wiring distribution circuit layer 70b is wn2, and the width of the metal wire of the third wiring distribution circuit layer 70c is wn3, the width of the metal layer (wn1 < wn2 < wn3) can increase as the number of layers increases.

[0203] As Figure 8 shown, when the width of the metal pad of the first wiring distribution circuit layer 70a is w1, the width of the metal pad of the second wiring distribution circuit layer 70b is w2, and the width of the metal pad of the third wiring distribution circuit layer 70c is w3, the width of the metal pad (w1 < w2 < w3) can also increase as the number of layers increases.

[0204] The width of the conductive layer of the cavity distribution layer 70 formed on the cavity element 40 becomes wider toward the upper layer and can eventually be similar to the width of the core conductive layer 63 of the glass core. As the pattern width of the conductive layer increases, the pitch of the pads can also increase.

[0205] The second wiring distribution circuit layer 70b is a single-layer wiring distribution circuit layer disposed on the cavity element, and the third wiring distribution circuit layer 70c is a single-layer wiring distribution circuit layer disposed on the second wiring distribution circuit layer 70b. The pitch of the third wiring distribution circuit layer 70c can be greater than the pitch of the second wiring distribution circuit layer 70b.

[0206] In addition, the second wiring distribution circuit layer 70b is a single-layer wiring distribution circuit layer disposed on the first wiring distribution circuit layer 70a. The pitch of the second wiring distribution circuit layer 70b can be greater than the pitch of the first wiring distribution circuit layer 70a.

[0207] In this implementation example, when a cavity element that requires a fine bump pitch is embedded in a glass core, a fine conductive layer is formed on the cavity element in advance, and the pitch of the conductive layer is widened, so that it can be more easily aligned with pads having a large pitch.

[0208] An upper layer 26 can be formed on the upper part of the core layer 22.

[0209] The pitch of the conductive layer disposed on the lower surface of the upper layer can be greater than the minimum value of the wiring distribution circuit layer. The pitch of the conductive layer disposed on the lower surface of the upper layer can be the same as or greater than the maximum value of the wiring distribution circuit layer. At this time, the pitch of the conductive layer on the lower surface of the upper layer refers to a metal layer that transmits electrical signals except for layers such as a ground layer that are not for the purpose of transmitting electrical signals.

[0210] Optionally, a lower layer 29 can be formed on the lower part of the core layer 22.

[0211] The pitch of the conductive layer arranged on the upper surface of the lower layer 29 may be greater than the minimum pitch of the conductive layer of the redistribution circuit layer. In this case, the pitch of the conductive layer on the upper surface of the lower layer refers to the conductive layer for transmitting electrical signals, such as a metal layer, except for layers not for transmitting electrical signals, such as a ground layer.

[0212] On the other hand, the outermost conductive layer included in the cavity allocation layer 70 can be generated during the modular manufacturing process of the element module 45. In addition, the outermost conductive layer included in the cavity allocation layer 70 can also be generated during the wiring formation process of the upper layer 26 after the element module 45 is embedded.

[0213] A method for manufacturing the package substrate 20 according to an implementation example is described below.

[0214] The method for manufacturing a package substrate includes: a preparation step of preparing a glass core 21 having a cavity 28 and a device module 45 ; and an arrangement step of arranging the device module 45 in the cavity 28 .

[0215] The component module 45 is formed by modularizing more than one cavity component 40 and a cavity distribution layer 70 through a capsule layer 48. As described above, the cavity component 40 may include active components and may also include passive components.

[0216] The cavity distribution layer 70 is a redistribution layer disposed on the upper portion of the cavity element 40. The cavity distribution layer 70 may include at least two layers of redistribution circuit layers. The cavity distribution layer 70 may be formed by a process for forming a redistribution layer in a semiconductor manufacturing process.

[0217] The specific description of the cavity allocation layer 70 overlaps with the above description, and thus the detailed description is omitted.

[0218] The method for manufacturing the package substrate may further include a core conductive layer forming step.

[0219] The core conductive layer forming step may be performed between the preparing step and the arranging step or after the arranging step.

[0220] The core conductive layer forming step is a step of forming a core conductive layer on the glass core.

[0221] The pitch of the redistribution circuit layers 70a, 70b, 70c may be smaller than the pitch of the core conductive layer. As the number of the cavity distribution layers increases (the farther from the cavity element), the pitch of the redistribution circuit layers 70a, 70b, 70c may become wider.

[0222] The component modules can be manufactured by modular steps.

[0223] The modularization step is a step of configuring a cavity distribution layer 70 on the upper portion of the cavity element 40. After the configuration, a process of wrapping the cavity element 40 and the cavity distribution layer 70 with a capsule layer 48 for modularization may be further included.

[0224] The cavity distribution layer 70 may include at least two redistribution circuit layers 70a, 70b, and 70c.

[0225] The cavity distribution layer is formed by a SAP (semi-additive process) method.

[0226] The cavity component is an active component, and the component module may also include a passive component and be molded (packaged).

[0227] A pre-molding step may also be included after the modularization step.

[0228] The cavity element can be prepared in a form before cutting and cut after forming the cavity allocation layer, and then packaged. The cutting step is selectively applied when a plurality of cavity elements are arranged on one substrate.

[0229] The cavity elements are cut and fixed in position by a pre-molding process to form a cavity distribution layer, which can then be encapsulated again.

[0230] The method of manufacturing the package substrate 20 will be described in more detail.

[0231] The glass core 21 in which the cavity portion 28 is arranged and the element module 45 are prepared (preparation step).

[0232] The cavity portion 28 is a space in which the element module 45 is arranged.

[0233] The element module 45 is formed by forming a cavity distribution layer including at least two redistribution line distribution circuit layers on the upper portion of the cavity element 40, which can be prepared in advance through a separate step.

[0234] For fine wiring, the cavity distribution layer 70 may be formed by SAP (semi-additive process). SAP is a process of forming a circuit pattern by processing a through hole on a substrate combining a metal material and an insulating material and performing electroless copper plating, followed by a dry film bonding / exposure / development process and an electrolytic copper plating process.

[0235] SAP is a method used to form extremely fine metal wiring. Fig. 9 This process is shown exemplarily.

[0236] First, an insulating layer 91 is formed by lamination or the like, and a through hole 92 ( Fig. 9 (a)).

[0237] After that, impurities in the through hole 92 are selectively removed, and an adhesive 93 ( Fig. 9 (b)). That is, impurities in the through hole 92 can be removed. According to the implementation example, the adhesive for improving the adhesion between the metal film and the insulating layer may not be applied.

[0238] A conductive layer such as electroless copper is bonded to the top of the adhesive 93 in a thin film form, thereby forming a seed layer 94 (seed metallization, Fig. 9 (c)).

[0239] Thereafter, after a photoresist such as a dry film is laminated or coated on the upper portion of the seed layer 94, a photoresist layer 95 ( Fig. 9 (d)).

[0240] Then, the conductive layer 96 may be formed by electroplating a metal such as copper on the areas where the dry film photoresist has been removed ( Fig. 9 (e)).

[0241] Finally, the dry film photoresist is removed and the seed layer is removed by etching ( Fig. 9 (f)).

[0242] Repeat as Fig. 9 By using the SAP method, at least two layers of redistribution circuit layers can be formed on the upper portion of the cavity element 40. When the redistribution layer (RDL) is generated by the SAP method, the pitch of the metal layer (or metal pad) included in the redistribution circuit layer of the cavity element 40 can be smaller than the pitch of the core metal layer.

[0243] In addition, as the number of layers of the redistribution circuit layer of the cavity element 40 increases, the pitch of the redistribution circuit layer can be formed wider. Figure 7 As shown, the width of the metal pad of metal layer 71 may become wider as the number of layers increases, and the width of the metal pad whose height is aligned with the core conductive layer 63 may be similar to the width of the core metal layer.

[0244] For example, the width of the cavity bump layer 701 (metal terminal of the mold) at the lower end may be 40 μm or more, 45 μm or more, 50 μm or more, or 55 μm or more. The width of the cavity bump layer 701 (metal terminal of the mold) at the lower end may be 80 μm or less, 75 μm or less, 70 μm or less, 65 μm or less, 60 μm or less, or 55 μm or less.

[0245] The width of the conductive layer may gradually increase from the lower end of the distribution layer (cavity distribution layer) of the cavity element 40 toward the lower end of the upper layer.

[0246] For example, the width of the conductive layer is the same as described above.

[0247] For example, in the conductive layer at the upper end of the lower layer, the width of the conductive layer may be greater than 90 μm, greater than 95 μm, greater than 100 μm, or greater than 105 μm. The width of the conductive layer may be less than 180 μm, less than 175 μm, less than 170 μm, less than 165 μm, less than 160 μm, or less than 155 μm.

[0248] The width of the conductive layer may gradually increase from the lower end of the distribution layer (cavity distribution layer) of the cavity element 40 toward the upper end of the lower layer.

[0249] When embedding a cavity component 40 that requires a narrow pitch, specifically an active component, misalignment, i.e., misalignment, may occur due to the pitch difference of the conductive layer. In this implementation example, the alignment margin can be ensured by gradually expanding the pitch of the conductive layer in the wiring layer. Accordingly, when connecting the cavity component 40 to the core layer 22, defects that may occur when connecting the semiconductor component to the core layer 22 can be prevented. That is, according to this implementation example, the cavity component 40 is pre-generated with a fine RDL and then embedded in the core layer 22, thereby overcoming the pitch size-related problems.

[0250] If necessary, if the cavity distribution layer 70 is formed, a dicing process may be performed. This is a process of dicing the processed cavity element into chip units. In this regard, the redistribution layer is not actually implemented on the pre-set scribe line (a space of appropriate width so that when dicing chips / bare chips in a wafer, the chips can be divided without affecting the surrounding components).

[0251] As an example of a cutting method, blade cutting can be applied. If blade cutting is applied, a wheel-shaped saw blade can be used to separate the wafer into chip units, or the base tape after the process is completed can be separated into each packaging unit. Blade cutting is to cut the wafer using a saw blade at the end of a wheel reinforced with diamond powder, and tolerance is generated when the saw blade rotates, so it is necessary to ensure that the scribe line space is thicker than the wheel.

[0252] As another method of cutting, there are laser cutting and plasma cutting. In blade cutting, the blade is in physical contact with the wafer, so as the required thickness becomes thinner, the wafer is easily broken during the process. Therefore, a method developed is laser cutting. Laser cutting generally cuts the wafer by irradiating a laser on the back of the wafer. Since the wafer is cut by laser, there is no physical impact, and it is also suitable for cutting thin wafers. In addition, since the damage to the cut surface is small, the chip strength can also be improved.

[0253] Plasma dicing is a recently developed dicing method that utilizes plasma etching in semiconductor manufacturing processes (Fab). Since it uses quasi-gaseous substances instead of liquids, it is environmentally friendly, and since it is applied to the entire wafer at the same time, the dicing speed of each chip is also faster than other dicing processes.

[0254] Optionally, after cutting, the cavity element can be packaged by pre-molding. The packaging process refers to the step of wrapping the semiconductor element with a specific substance to protect it from the external environment. As one of the packaging methods, molding is to cover the chip and the wire with EMC (epoxy molding compound) which is a material made by mixing various inorganic materials in thermosetting resin, so as to provide protection from external physical and chemical impacts, and various adjustments can be made to the package size or shape.

[0255] In order to protect the cavity components and to perform packaging before the cavity portion 28 is provided with the component module 45 , pre-molding may be performed before final molding.

[0256] like Fig.10 As shown, in this process, passive components without wiring layers can also be packaged together with active components.

[0257] If the element module 45 is arranged in the cavity portion 28 after being selected (picked up), an upper layer can be formed on the upper part of the core layer 22 or a lower layer can be formed on the lower part of the core layer.

[0258] According to an implementation example, if the element module 45 is disposed in the cavity 28, the remaining space of the cavity 28 can be filled with an insulating material. The insulating material can be filled into the cavity 28 by an insulating layer forming process accompanying the distribution layer forming process of the upper layer 26 or the lower layer 29.

[0259] Fig.10 is an example of a cross-sectional structure of a packaging substrate generated according to another implementation example.

[0260] According to an implementation example, the component module 45 embedded in the cavity portion 28 of the glass core 21 may include a passive component 42 in addition to the active component 41 .

[0261] The passive component 42 may be packaged together with the active component during pre-molding. As shown in the figure, the cavity allocation layer may not be formed on the upper portion of the passive component 42.

[0262] According to another example, if a cavity distribution layer is also formed on the passive element, the passive element can also be packaged after forming at least two layers of redistribution circuit layers by the SAP method. After cutting, the passive element and the active element can be molded together and arranged in the cavity portion 28 of the glass substrate 21.

[0263] In addition, the component module may include more than two active components, or more than two active components and passive components, and may include a plurality of passive components formed with a distribution layer.

[0264] According to the method for manufacturing a package substrate of the embodiment described above and the package substrate using the same, the misalignment caused by the pitch difference of the conductive layer such as metal that may be generated when the cavity element is embedded is improved, and the pitch of the pad formed in the cavity element is expanded, so that the defect rate that may occur when connecting the package can be greatly reduced. In addition, the length of the electrical path is shortened by embedding the cavity element, thereby reducing heat generation and electrical loss.

[0265] The present invention as described above is described with reference to the embodiments shown in the accompanying drawings, but this is only exemplary, and anyone with ordinary knowledge in the relevant technical field can understand that various modifications and variations of the embodiments can be made therefrom. That is, the scope of rights of the present invention is not limited to the above-mentioned embodiments, and various modifications and improved forms of practitioners using the basic concepts of the embodiments defined by the claims are also included in the scope of rights of the embodiments. Therefore, the true technical protection scope of the present invention should be defined by the technical ideas of the claims.

Claims

1. A packaging substrate, comprising a core layer, characterized in that: The core layer comprises a glass core and a cavity portion, wherein the glass core has a first surface and a second surface facing each other, and the cavity portion passes through the glass core; A component module is disposed in the cavity portion; The element module is modularized by using a capsule layer to form more than one cavity element and a cavity distribution layer; The cavity distribution layer is a redistribution layer disposed on an upper portion of the cavity element.

2. The packaging substrate according to claim 1, characterized in that: The cavity distribution layer includes at least two layers of redistribution line distribution circuit layers; The redistribution circuit layer comprises: i) Cavity bump layer, or ii) through-holes and circuit layers; The cavity bump layer is a buffer layer, and the buffer layer is a conductive layer connected to the upper portion of the cavity element and capable of transmitting an electrical signal to the cavity element; The through hole and circuit layer are conductive layers connected to the cavity bump layer and transmitting electrical signals to the outside of the component module.

3. The packaging substrate according to claim 2, characterized in that: The cavity distribution layer comprises: A first redistribution circuit layer is provided with the cavity bump layer. The second redistribution wiring distribution circuit layer is formed by recessing the first through hole and the first circuit layer in the module insulation layer, and A third redistribution wiring distribution circuit layer is formed by recessing the module insulation layer to configure a second through hole and a second circuit layer; The module insulating layer is an insulating layer configured in the module.

4. The packaging substrate according to claim 2, characterized in that: A core conductive layer is formed on the glass core, and the core conductive layer is a metal circuit pattern configured on the surface of the glass core; The pitch of the redistribution circuit layer is smaller than the pitch of the core conductive layer.

5. The packaging substrate according to claim 3, characterized in that: The pitch of the second circuit layer is greater than the pitch of the first circuit layer.

6. The packaging substrate according to claim 3, characterized in that: A pad width of the second redistribution circuit layer is greater than a pad width of the first redistribution circuit layer.

7. The packaging substrate according to claim 1, characterized in that: The component module includes active components.

8. The packaging substrate according to claim 7, characterized in that: The component module also includes passive components.

9. The packaging substrate according to claim 1, characterized in that: Also includes: An upper layer, arranged on the upper part of the core layer; A pitch of the conductive pattern disposed on the lower surface of the upper layer is greater than a minimum pitch of the cavity distribution layer.

10. The packaging substrate according to claim 1, characterized in that: Also includes: A lower layer, arranged at the lower part of the core layer; A pitch of the conductive pattern disposed on the upper surface of the lower layer is greater than a minimum pitch of the cavity distribution layer.

11. A method for manufacturing a packaging substrate, characterized in that: include: A preparation step of preparing a glass core having a cavity and an element module, and an arranging step of arranging the component modules in the cavity portion; The element module is modularized by using a capsule layer to form more than one cavity element and a cavity distribution layer; The cavity distribution layer is a redistribution layer disposed on an upper portion of the cavity element.

12. The method for manufacturing a packaging substrate according to claim 11, characterized in that: The cavity distribution layer includes at least two layers of redistribution line distribution circuit layers; The redistribution circuit layer comprises: i) Cavity bump layer, or ii) through-holes and circuit layers; The cavity bump layer is a buffer layer, and the buffer layer is a conductive layer connected to the upper portion of the cavity element and capable of transmitting an electrical signal to the cavity element; The through hole and circuit layer are conductive layers connected to the cavity bump layer and transmitting electrical signals to the outside of the component module; The method for manufacturing the packaging substrate further includes: a core conductive layer forming step; The core conductive layer forming step is performed between the preparing step and the arranging step or after the arranging step; The core conductive layer forming step is a step of forming a core conductive layer on the glass core; The pitch of the redistribution circuit layer is smaller than the pitch of the core conductive layer.

13. The method for manufacturing a packaging substrate according to claim 11, characterized in that: The farther the redistribution line distribution circuit layer is from the cavity element in the cavity distribution layer, the wider the pitch of the redistribution line distribution circuit layer becomes.

14. The method for manufacturing a packaging substrate according to claim 11, characterized in that: The component modules are manufactured through modular steps; The modularization steps include: a step of disposing a cavity distribution layer on the upper portion of the cavity element, wherein the cavity distribution layer comprises at least two layers of redistribution circuit layers; and The step of forming the cavity distribution layer by a semi-additive method.

15. The method for manufacturing a packaging substrate according to claim 14, characterized in that: The component module includes active components; The component module also includes passive components and is formed by molding.

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