Dielectric layer projects

Abstract

The invention relates to a dielectric layer protrusion. The package (104) includes: a semiconductor die (200) having a device side (201) formed with circuitry; and first and second metal members (206) coupled to the device side and extending away from the device side. The package further includes a passivation layer (202) contacting the device side, at least a portion of the passivation layer positioned between the first metal member and the second metal member, the passivation layer including a top surface (205) facing away from the semiconductor die. The package further includes a plurality of passivation layer protrusions (PLPs) (204) coupled to and extending away from the top surface, the plurality of PLPs having a height in a range of 0.5 microns to 50 microns.

Description

Technical Field

[0001] The present disclosure relates to dielectric layer protrusions. Background Art

[0002] A semiconductor wafer is a round piece of semiconductor material (e.g., silicon) used to make semiconductor chips. Typically, complex manufacturing processes are used to form many integrated circuits on a single wafer. Forming such circuits on a wafer is called fabrication. After wafer fabrication, the wafer is cut into multiple pieces, called semiconductor dies, where each die contains one of the circuits. Cutting or sawing the wafer into individual dies is called singulation. The dies are then coupled to a lead frame and covered with a molding compound, which is then sawn to create a package. Summary of the invention

[0003] A package includes: a semiconductor die having a device side formed with circuitry; and a first metal member and a second metal member coupled to the device side and extending away from the device side. The package also includes a passivation layer contacting the device side, at least a portion of the passivation layer being positioned between the first metal member and the second metal member, the passivation layer including a top surface facing away from the semiconductor die. The package further includes a plurality of passivation layer protrusions (PLPs) coupled to the top surface and extending away from the top surface, the plurality of PLPs having a height ranging from 0.5 microns to 50 microns.

[0004] A method for manufacturing a package includes applying a first passivation layer on a device side of a semiconductor die, the device side including circuitry and a pair of metal features extending away from the device side. The method also includes applying a second passivation layer on the first passivation layer. The method further includes patterning the second passivation layer using photolithography to produce a plurality of passivation layer protrusions positioned between the pair of metal features and extending away from the semiconductor die, the plurality of passivation layer protrusions having a height in a range of 0.5 microns to 50 microns and a density in a range of 1 unit / square micron to 100 units / square micron. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a block diagram of an electronic device including a package with passivation and / or polyimide layer protrusions according to various examples.

[0006] Figure 2A is a cutaway cross-sectional view of a package having a passivation layer protrusion according to various examples.

[0007] Figure 2B is a top view of a package having a passivation layer protrusion according to various examples.

[0008] Figure 2C is a perspective view of a package having a passivation layer protrusion according to various examples.

[0009] Figure 3A is a cutaway cross-sectional view of a package with passivation and polyimide layer protrusions according to various examples.

[0010] Figure 3B is a top view of a package with passivation and polyimide layer protrusions according to various examples.

[0011] Figure 3C is a perspective view of a package with passivation and polyimide layer protrusions according to various examples.

[0012] Figure 4A is a cross-sectional view of a rectangular passivation and / or polyimide layer protrusion according to various examples.

[0013] Figure 4B is a top view of a rectangular passivation and / or polyimide layer protrusion according to various examples.

[0014] Figure 4C is a perspective view of a rectangular passivation and / or polyimide layer protrusion according to various examples.

[0015] Figure 5A 4 is a cross-sectional view of a star-shaped passivation and / or polyimide layer protrusion according to various examples.

[0016] Figure 5B is a top view of a star-shaped passivation and / or polyimide layer protrusion according to various examples.

[0017] Figure 5C is a perspective view of a star-shaped passivation and / or polyimide layer protrusion according to various examples.

[0018] Fig. 6A 1 is a cross-sectional view of an arc-shaped passivation and / or polyimide layer protrusion according to various examples.

[0019] Figure 6B is a top view of a curved passivation and / or polyimide layer protrusion according to various examples.

[0020] Figure 6C is a perspective view of a curved passivation and / or polyimide layer protrusion according to various examples.

[0021] Figures 7A to 7D 2 are electric field distributions achieved in a baseline package and a package including passivation and / or polyimide layer protrusions according to various examples.

[0022] Figure 8 is a flow chart of a method for manufacturing a package including a passivation layer protrusion according to various examples.

[0023] Figures 9A to 9D 1 is a process flow for manufacturing a package including a passivation layer protrusion according to various examples.

[0024] Fig.10 is a flow chart of a method for manufacturing a package including passivation and polyimide layer protrusions according to various examples.

[0025] Figures 11A to 11G Detailed description of the invention is provided below: A process flow for manufacturing a package including passivation and polyimide layer protrusions according to various examples. DETAILED DESCRIPTION

[0026] The package includes a semiconductor die having a device side with circuitry formed thereon. The device side may include metal features such as copper pillars, under bump metallization (UBM), metal traces, and the like. Dielectric layers such as passivation layers and polyimide layers may be stacked on the device side of the semiconductor die. The metal features may extend through such dielectric layers, or a network of metal features coupled to one another may extend through the dielectric material.

[0027] Often, the charge will migrate across the surface of the dielectric layer. More specifically, the charge can creep from a first metal component (e.g., a copper post) to a second metal component (e.g., another copper post) along the interface of the passivation layer and the polyimide layer. Similarly, the charge can creep from a first metal component to a second metal component along the interface of the polyimide layer and the molding compound. This charge can cause considerable damage. Interface defects, metal ion transport, and other such irregularities can also cause damage. The damage can include dielectric failure or breakdown, metal corrosion, metal migration (e.g., causing short circuits), and leakage failures. This damage can cause packaging defects and device failures.

[0028] The present disclosure describes various examples of packages having passivation and polyimide layer protrusions that mitigate the challenges described above. The protrusions extend away from the surface of the passivation and / or polyimide layer along which charge can creep. The protrusions have specific physical dimensions and shapes that inhibit charge creep between metal components along the passivation-polyimide interface and along the polyimide-molding compound interface. More generally, the protrusions inhibit charge creep between metal components along any dielectric to dielectric interface, which charge may otherwise creep along the dielectric to dielectric interface. In an example, the protrusions capture or store charge that would otherwise creep from one metal component to another along the dielectric interface. In an exemplary package, a semiconductor die has a device side in which a circuit system is formed, and a first metal component and a second metal component coupled to the device side and extending away from the device side. The passivation layer contacts the device side, and at least a portion of the passivation layer is positioned between the first metal component and the second metal component. The passivation layer includes a top surface facing away from the semiconductor die. A plurality of passivation layer protrusions (PLPs) are coupled to the top surface and extend away from the top surface. The plurality of PLPs have a height ranging from submicron level (i.e., 0.5 micron) to several microns (i.e., 50 microns). The aforementioned damage is mitigated by preventing charge creep across the dielectric interface.

[0029] Figure 1 1 is a block diagram of an electronic device 100 according to various examples, the electronic device including a package with a passivation and / or polyimide layer protrusion. For example, the electronic device 100 may include a personal computer, a laptop computer, a desktop computer, a notebook, a tablet computer, a smart phone, an appliance (e.g., a refrigerator, a television, an audio player, a video player, a video recorder, a lighting device, etc.), an automobile, an airplane, a spacecraft, etc. The electronic device 100 may include a printed circuit board (PCB) 102. A package 104 may in turn be coupled to the PCB 102. The package 104 may be any type of package in which charge can creep along a dielectric interface between metal components of the package, such as a wafer chip scale package (WCSP), a dual in-line package (DIP), a quad flat no-lead (QFN) package, etc. An example of the package 104 is now described with reference to the drawings.

[0030] Figure 2A1 is a cross-sectional view of a package 104 with a passivation layer protrusion according to various examples. The exemplary package 104 includes a semiconductor die 200. The die 200 includes a device side 201 in which a circuit system is formed. A dielectric layer 202, such as a passivation overcoat (PO) layer, contacts and covers the device side 201 of the die 200. As described in more detail below, the dielectric layer 202 includes a surface 205 facing away from the die 200 and the device side 201, wherein the surface 205 is coupled to a plurality of protrusions 204. A metal member 206 is coupled to the device side 201. For example, the metal member 206 includes copper. As shown, the protrusions 204 are at least located between the metal members 206, but the metal members 206 may also be included on other areas of the surface 205. A solder member 208 couples the metal member 206 to the metal bumps 210 through a redistribution layer (RDL) 212. RDL 212 includes a network of metal features that provide an electrical path between metal features 206 and metal bumps 210. As shown, molding compound 214 covers the various structures of package 104. Molding compound 214 is a dielectric material and contacts surface 205 and protrusions 204. Figure 2B A passivation layer protrusion according to each example Figure 2A FIG. 1 is a top view of package 104 . Figure 2C A passivation layer protrusion according to each example Figure 2A 104 is a perspective view of the package 104.

[0031] like Figures 2A to 2C As shown in FIG. 2 , the protrusion 204 extends from the surface 205 in a direction away from the die 200. The protrusion 204 may have any suitable shape, wherein Figures 2A to 6CSome illustrative, non-limiting shapes are depicted (e.g., with horizontal cross-sections that are rectangular, star-shaped, arc-shaped, etc.). The protrusions 204 form a lattice pattern on the surface 205, wherein the protrusions 204 are in close proximity to each other but do not touch each other, and wherein the protrusions 204 form a regular pattern on the surface 205. The lattice pattern causes the protrusions 204 to form a barrier to direct line of sight between any two metal members 206, meaning that a straight line cannot be drawn along the surface 205 between any two metal members 206 without intersecting at least one, if not more, of the protrusions 204. The spacing between the protrusions 204 ranges from 0.5 microns to 10 microns, wherein spacing below this range is disadvantageous because the charge density will cover an area greater than the distance between the protrusions 204 and will make the protrusions 204 minimally effective, and wherein spacing above this range is disadvantageous because the charge will be able to move over the surface and will adversely affect device performance. The density of the protrusions 204 ranges from 1 unit / square micron to 100 units / square micron, wherein a density below this range is disadvantageous because the charge density will cover an area greater than the distance between the protrusions 204 and will make the protrusions 204 minimally effective, and wherein a density above this range is disadvantageous because the charge will be able to move above the surface and will adversely affect device performance.

[0032] The protrusion 204 has a height in the range of 0.5 micrometers to 50 micrometers, wherein a height below this range is disadvantageous because charges will creep over the short height of the protrusion 204 and the electric field distribution will not be adequately controlled, and wherein a height above this range is disadvantageous due to manufacturing limitations. The protrusion 204 has a width in the range of 0.5 micrometers to 50 micrometers, wherein a width below this range is disadvantageous because the electric field distribution will not be adequately controlled, and wherein a width above this range is disadvantageous because charges will move a larger distance, thereby causing device failure. The protrusion 204 has a length in the range of 0.5 micrometers to 50 micrometers, wherein a length below this range is disadvantageous because the electric field distribution will not be adequately controlled, and wherein a length above this range is disadvantageous because charges will move a larger distance, thereby causing device failure.

[0033] The protrusions 204 may have the same orientation in space. For example, if the protrusions 204 are rectangular prisms, some or all of the protrusions 204 may be oriented parallel to each other on the surface 205. In an example, the protrusions 204 are oriented differently in space. For example, if Figure 2B and 2C As shown in , some protrusions 204 are oriented orthogonally to other protrusions 204 .

[0034] The protrusion 204 may include the same material (e.g., a passivation material) as the material forming the dielectric layer 202. The protrusion 204 may include a different material than the material forming the dielectric layer 202. Exemplary materials that may be used to form the dielectric layer 202, the protrusion 204, or both include silicon nitride, silicon dioxide, and silicon oxynitride. Neither the dielectric layer 202 nor the protrusion 204 covers the metal member 206.

[0035] Figure 3A is a cutaway cross-sectional view of a package 104 with passivation and polyimide layer protrusions according to various examples. Figure 3A Package 104 with Figure 2A The package is the same as 104, except Figure 3A The package 104 of the embodiment of the present invention includes an additional dielectric layer 300 that contacts the protrusions 204 and the surface 205 of the dielectric layer 202. In an example, the dielectric layer 300 is a polyimide layer. As shown, the dielectric layer 300 is coupled to and contacts a plurality of protrusions 302 on the surface 304. The protrusions 302 extend from the surface 304 in a direction away from the die 200. The protrusions 302 have the same physical and spatial characteristics (e.g., size, shape, spacing, orientation, density, etc.) as the protrusions 204 described above, and therefore, these characteristics are not described again herein. The molding compound 214 covers the various structures of the package 104 and contacts the surface 304 and the protrusions 302. Figure 3B A passivation and polyimide layer protrusion according to various examples Figure 3A FIG. 1 is a top view of package 104 . Figure 3C A passivation and polyimide layer protrusion according to various examples Figure 3A 104 is a perspective view of the package 104.

[0036] Figure 4A 2 is a cross-sectional view of a rectangular passivation layer protrusion 204 according to various examples. Figure 4B FIG. 2 is a top view of a rectangular passivation layer protrusion 204 according to various examples. Figure 4C 2 is a perspective view of a rectangular passivation layer protrusion 204 according to various examples. Figures 4A to 4C The protrusion is labeled as passivation layer protrusion 204, but Figures 4A to 4C The polyimide layer protrusion 302 may also be represented, for example, with reference to Figures 3A to 3C Polyimide layer protrusions are shown and described.

[0037] Figure 5A 2 is a cross-sectional view of a star-shaped passivation layer protrusion 204 according to various examples. Figure 5B FIG. 2 is a top view of a star-shaped passivation layer protrusion 204 according to various examples. Figure 5C 2 is a perspective view of a star-shaped passivation layer protrusion 204 according to various examples. Figures 5A to 5CThe protrusion is labeled as passivation layer protrusion 204, but Figures 5A to 5C The polyimide layer protrusion 302 may also be represented, for example, with reference to Figures 3A to 3C Polyimide layer protrusions are shown and described.

[0038] Fig. 6A is a cross-sectional view of an arc-shaped passivation layer protrusion 204 according to various examples. Figure 6B is a top view of the arc-shaped passivation layer protrusion 204 according to various examples. Figure 6C 2 is a perspective view of an arc-shaped passivation layer protrusion 204 according to various examples. Figures 6A to 6C The protrusion is labeled as passivation layer protrusion 204, but Figures 6A to 6C The polyimide layer protrusion 302 may also be represented, for example, with reference to Figures 3A to 3C Polyimide layer protrusions are shown and described.

[0039] Common Reference Figures 2A to 6C In operation, charge can creep between metal components of package 104, such as between metal members 206. Charge can creep along dielectric interfaces, such as along surface 205 ( Figure 2A ), or for example along the surface 205 between the dielectric layers 202, 300 ( Figure 3A ) or, for example, along the surface 304 between the dielectric layer 300 and the molding compound 214 ( Figure 3A ) creep. These creeping charges may have detrimental effects, such as those described above. However, the presence of the protrusions (e.g., protrusions 204, 302) mitigates the creep of charges along these dielectric interfaces. For example, referring to Figure 2A, the protrusions 204 mitigate charge creep along the surface 205 between the dielectric layer 202 and the molding compound 214. Charge creep must overcome the physical barrier presented by the protrusions 204, and protrusions 204 having specific key physical features described herein (i.e., specific length, width, and thickness ranges) are difficult for charge creep to physically cross. When a charge fails to cross the protrusions 204, the protrusions 204 are said to capture or contain the charge. Protrusions 204 having physical features within the ranges described herein but spaced far apart can provide a clear path for charge creep because the protrusions 204 can provide a clear line of sight between metal components (e.g., metal component 206) along which the charge can creep. Therefore, protrusions 204 within the specific key spacing and density ranges described herein are difficult for charge creep to physically cross. In this way, when charge attempts to creep between metal components of package 104, protrusion 204 will be seen as a physical barrier for the charge to creep over. Protrusion 302 operates in the same manner as described for protrusion 204, and therefore, this operation is not described again herein.

[0040] Figures 7A to 7D 2 are electric field distributions achieved in a baseline package and a package 104 including passivation and / or polyimide layer protrusions according to various examples. Fig. 7A A top view of the electric field distribution in a package lacking the protrusions described herein is provided, and Figure 7B A cutaway cross-sectional view of the electric field distribution in a package lacking the protrusions described herein is provided. Fig. 7A and 7B As shown in , the absence of protrusions on surface 700 facilitates charge creeping from metal component 702 along surface 700. Figure 7C A top view of the electric field distribution in a package 104 including a protrusion 204 as described herein is provided, and Fig.7D A cross-sectional view of the electric field distribution in the package 104 including the protrusion 204 as described herein is provided. As shown, the presence of the protrusion 204 mitigates the creep of charge from the metal member 206 along the surface 205. Specifically, the protrusion 204 captures the charge, as shown. The protrusion 302 operates in a similar manner to the protrusion 204, and therefore, the operation of the protrusion 302 is not repeated herein.

[0041] Figure 8 is a flow chart of a method 800 for manufacturing a package 104 including a passivation layer protrusion according to various examples. Figures 9A to 9D FIG. 1 is a process flow for manufacturing a package 104 including a passivation layer protrusion according to various examples. Figure 8 and 9A To 9D.

[0042] The method 800 includes applying a first passivation layer on a device side of a semiconductor die, wherein the device side includes circuitry and a pair of metal features extending away from the device side (802). Fig. 9A Metal features 206 are shown formed on the device side 201 of the die 200 and extending away from the device side 201. Additionally, a dielectric layer 202 (which may be referred to herein as a passivation layer 202) is on the device side 201.

[0043] The method 800 includes applying a second passivation layer on the first passivation layer (804). Fig. 9B Shown Fig. 9A The structure of FIG. 2 is different in that a second passivation layer 900 is applied to the first passivation layer 202. The second passivation layer 900 has the same thickness as that of the protrusion 204 described herein.

[0044] The method 800 includes patterning a second passivation layer using photolithography techniques to produce a plurality of passivation layer protrusions positioned between a pair of metal features and extending away from the semiconductor die, wherein the plurality of passivation layer protrusions have heights as described herein ( 806 ). Fig. 9C Shown Fig. 9B , except that the second passivation layer 900 has been subjected to photolithography (eg, appropriate positioning of a mask or reticle, exposure, and development) to form the protrusion 204 described herein.

[0045] The method 800 includes coupling a pair of metal members to the conductive terminals and covering the die, the metal members, and the first and second passivation layer protrusions with a molding compound (808). Fig.9D Shown Fig. 9C The structure of FIG. 1 is different in that a solder member 208, a metal bump 210, an RDL 212, and a molding compound 214 are added.

[0046] Fig.10 is a flow chart of a method 1000 for fabricating a package 104 including passivation and polyimide layer protrusions according to various examples. Figures 11A to 11G FIG. 1 is a process flow for manufacturing a package 104 including a passivation and a polyimide layer protrusion according to various examples. Fig.10 and 11A To 11G.

[0047] The method 1000 includes applying a first passivation layer on a device side of a semiconductor die, wherein the device side includes circuitry and a pair of metal features extending away from the device side (1002). Fig.11AMetal features 206 are shown formed on the device side 201 of the die 200 and extending away from the device side 201. Additionally, a passivation layer 202 is on the device side 201.

[0048] The method 1000 includes applying a second passivation layer on the first passivation layer (1004). Fig. 11B Shown Fig.11A The structure of FIG. 2 is different in that the second passivation layer 900 is applied to the first passivation layer 202. The second passivation layer 900 has the same thickness as the thickness of the protrusion 204, as described herein.

[0049] The method 1000 includes patterning a second passivation layer using photolithography to produce a plurality of passivation layer protrusions positioned between a pair of metal features and extending away from the semiconductor die, wherein the plurality of passivation layer protrusions have a height as described herein (1006). Fig. 11C Shown Fig. 11B , except that the second passivation layer 900 has been subjected to photolithography (eg, appropriate positioning of a mask or reticle, exposure, and development) to form the protrusion 204 described herein.

[0050] The method 1000 includes applying a first polyimide layer over the first passivation layer and the passivation layer protrusions (1008). Fig.11D Shown Fig. 11C The structure of FIG. 1 is different in that a first dielectric layer 300 (which may be referred to herein as a first polyimide layer 300 ) is applied on the first passivation layer 202 and the passivation layer protrusion 204 .

[0051] The method 1000 includes applying a second polyimide layer on the first polyimide layer (1010). Fig.11E Shown Fig.11D The structure of FIG. 1 is different in that a second polyimide layer 1100 is applied on the first polyimide layer 300. The second polyimide layer 1100 has the same thickness as the thickness of the protrusion 302, as described herein.

[0052] The method 1000 includes patterning a second polyimide layer using photolithography to create a plurality of polyimide layer protrusions positioned between a pair of metal features and extending away from the semiconductor die ( 1012 ). Fig.11F Shown Fig.11E The structure of FIG. 1 is different in that the second polyimide layer 1100 has been patterned using photolithography into a plurality of polyimide layer protrusions 302 as described herein.

[0053] The method 1000 includes coupling a pair of metal members to the conductive terminals and covering the die, the metal members, the first passivation layer, the first polyimide layer, and the protrusions with a molding compound (1014). Fig.11GShown Fig.11F The structure of FIG. 1 is different in that a solder member 208, a metal bump 210, an RDL 212, and a molding compound 214 are added.

[0054] In this description, the term "coupled" may encompass connections, communications, or signal paths that enable a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B through a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B, so that device B is controlled by device A through the control signal generated by device A.

[0055] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the described function when manufactured by a manufacturer, and / or may be configurable (or reconfigurable) by a user after manufacture to perform the described function and / or other additional or alternative functions. Configuration may be achieved through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnections, or a combination thereof.

[0056] In this specification, unless otherwise stated, "about," "approximately," or "substantially" preceding a parameter means within + / - 10% of the parameter. Modifications are possible in the described examples, and other examples are possible within the scope of the claims.

Claims

1. A package comprising: a semiconductor die having a device side having circuitry formed thereon; a first metal member and a second metal member coupled to the device side and extending away from the device side; a passivation layer contacting the device side, at least a portion of the passivation layer being positioned between the first metal component and the second metal component, the passivation layer including a top surface facing away from the semiconductor die; as well as A plurality of passivation layer protrusions PLP are coupled to the top surface and extend away from the top surface, the plurality of PLP having a height ranging from 0.5 micrometers to 50 micrometers. 2 . The package of claim 1 , wherein the plurality of PLPs form a lattice pattern on the top surface. 3 . The package of claim 1 , wherein the plurality of PLPs have a width ranging from 0.5 microns to 50 microns. 4 . The package of claim 1 , wherein the plurality of PLPs have a length ranging from 0.5 microns to 50 microns. 5 . The package of claim 1 , wherein the plurality of PLPs form a barrier to direct line of sight between the first metal member and the second metal member. The package of claim 1 , wherein a pitch between the plurality of PLPs is in a range of 0.5 μm to 10 μm. 7 . The package of claim 1 , wherein the plurality of PLPs have a cross-section shaped into a star shape, a rectangle, or an arc shape.

8. The package of claim 1, wherein the plurality of PLPs are oriented differently in space.

9. The package of claim 1, further comprising a polyimide layer contacting the top surface of the passivation layer, the polyimide layer having a top polyimide surface facing away from the semiconductor die, the top polyimide surface having a plurality of additional PLPs extending away from the top polyimide surface.

10. The package of claim 9, wherein the plurality of additional PLPs have a height ranging from 0.5 microns to 50 microns, a width ranging from 0.5 microns to 50 microns, and a length ranging from 0.5 microns to 50 microns. 11 . The package of claim 1 , wherein top surfaces of the first and second metal members are not covered by the passivation layer.

12. The package of claim 1, wherein the passivation layer is comprised of a first material and the plurality of PLPs are comprised of a second material different from the first material.

13. The package of claim 1, wherein the package is a wafer chip scale package.

14. A package comprising: a semiconductor die having a device side having circuitry formed thereon; a first metal member and a second metal member coupled to the device side; a passivation layer contacting the device side, at least a portion of the passivation layer being positioned between the first metal component and the second metal component, the passivation layer comprising a first top surface facing away from the semiconductor die, the first metal component and the second metal component extending away from the device side and extending beyond the first top surface; a plurality of passivation layer protrusions arranged in a lattice pattern on the first top surface and extending away from the first top surface, the plurality of passivation layer protrusions having a height ranging from 0.5 micrometers to 50 micrometers, a width ranging from 0.5 micrometers to 50 micrometers, a length ranging from 0.5 micrometers to 50 micrometers, and a pitch ranging from 0.5 micrometers to 10 micrometers; a polyimide layer contacting the first top surface, at least a portion of the polyimide layer being positioned between the first metal member and the second metal member, the polyimide layer including a second top surface facing away from the semiconductor die; as well as A plurality of polyimide layer protrusions are arranged in a lattice pattern on the second top surface and extend away from the second top surface, wherein the plurality of polyimide layer protrusions have a height ranging from 0.5 microns to 50 microns, a width ranging from 0.5 microns to 50 microns, a length ranging from 0.5 microns to 50 microns, and a spacing ranging from 0.5 microns to 10 microns. 15 . The package of claim 14 , wherein the plurality of passivation layer protrusions have a density ranging from 1 unit / square micron to 100 units / square micron, and the plurality of polyimide layer protrusions have a density ranging from 1 unit / square micron to 100 units / square micron. The package of claim 14 , wherein the plurality of passivation layer protrusions are formed of a material different from that of the passivation layer. The package of claim 14 , wherein the plurality of polyimide layer protrusions are formed of a material different from that of the polyimide layer.

18. The package of claim 14, wherein the plurality of passivation layer protrusions are oriented differently in space, and wherein the plurality of polyimide layer protrusions are oriented differently in space.

19. A method for manufacturing a package, comprising: applying a first passivation layer on a device side of a semiconductor die, the device side including circuitry and a pair of metal features extending away from the device side; applying a second passivation layer on the first passivation layer; as well as The second passivation layer is patterned using photolithography to produce a plurality of passivation layer protrusions positioned between the pair of metal components and extending away from the semiconductor die, the plurality of passivation layer protrusions having a height ranging from 0.5 microns to 50 microns and a density ranging from 1 unit / square micron to 100 units / square micron.

20. The method of claim 19, further comprising: applying a first polyimide layer on the second passivation layer; applying a second polyimide layer on the first polyimide layer; as well as The second polyimide layer is patterned using photolithography to produce a plurality of polyimide layer protrusions positioned between the pair of metal features and extending away from the semiconductor die.

21. The method of claim 19, wherein the plurality of passivation layer protrusions have a pitch ranging from 0.5 microns to 10 microns.

22. The method of claim 19, wherein the plurality of passivation layer protrusions have a length ranging from 0.5 microns to 50 microns and a width ranging from 0.5 microns to 50 microns.

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