Interconnect clamp for vertically stacked die arrangements

Abstract

An electrical interconnect jig includes a die interface portion adapted to fit between two vertically stacked semiconductor dies, and a carrier connection portion configured to electrically connect the two vertically stacked semiconductor dies with a carrier, where the die interface portion is adapted to fit between the two vertically stacked semiconductor dies, and the carrier connection portion is configured to electrically connect the two vertically stacked semiconductor dies with the carrier. The die interface portion includes a lower mating surface, an upper mating surface opposite the lower mating surface, and a solder retention feature formed by one or more grooves in the upper mating surface, the one or more grooves are spaced apart from an outer edge side of the electrical interconnect clip and surround a die attachment area of the upper mating surface.

Description

Background Art

[0001] Many applications, such as automotive and industrial applications, utilize semiconductor packages to accommodate high voltage loads. These semiconductor packages can be configured as discrete components, or can be configured as power converter circuits, such as single-phase and multi-phase half-wave rectifiers, single-phase and multi-phase full-wave rectifiers, voltage regulators, etc. These semiconductor packages can include power devices, such as diodes, IGBTs (insulated gate bipolar transistors), MOSFETs (metal oxide semiconductor field effect transistors), HEMTs (high electron mobility transistors), etc. Thermal and electrical properties have played an increasingly important role in the development of semiconductor packages. Many power semiconductor packages require electrical connections with low resistance and high current capacity that can be reliably and inexpensively formed. Summary of the invention

[0002] An electrical interconnect fixture is disclosed. According to an embodiment, the electrical interconnect fixture comprises a die interface portion and a carrier connection portion, the die interface portion being adapted to be mated between two vertically stacked semiconductor dies, the carrier connection portion being configured to electrically connect the two vertically stacked semiconductor dies to a carrier, wherein the die interface portion comprises a lower mating surface, an upper mating surface opposite to the lower mating surface, and a solder retention feature formed by one or more grooves in the upper mating surface, the one or more grooves being spaced apart from an outer edge side of the electrical interconnect fixture and forming a boundary of a die attachment area surrounding the upper mating surface.

[0003] A method for forming a semiconductor package is disclosed. According to an embodiment, the method includes: providing a carrier including a die pad and a plurality of leads; providing a first semiconductor die and a second semiconductor die, each of the first semiconductor die and the second semiconductor die being configured as a vertical power device, providing an electrical interconnect fixture, the electrical interconnect fixture including a die interface portion and a carrier connection portion; providing a stacked die arrangement on the die pad, the stacked die arrangement including the die interface portion of the electrical interconnect fixture arranged between the first semiconductor die and the second semiconductor die, and the carrier connection portion contacting the carrier; providing solder material between the second semiconductor die and the die interface portion of the electrical interconnect fixture; and performing a soldering process, the soldering process liquefies the solder material, wherein the electrical interconnect fixture includes a solder retaining feature forming a boundary at least partially surrounding the second semiconductor die, and wherein the solder retaining feature interacts with the liquefied solder during the soldering process by retaining the solder material within a confined space surrounding the second semiconductor die, thereby preventing floating movement of the second semiconductor die.

[0004] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The elements of the drawings are not necessarily to scale relative to each other. Similar reference numerals indicate corresponding similar parts. Unless mutually exclusive, the features of the various illustrative embodiments can be combined. The embodiments are illustrated in the drawings and described in detail in the following detailed description.

[0006] Figure 1A , 1B , 1C and 1D show an electrical interconnection fixture according to an embodiment. Figure 1A The electrical interconnect fixture is shown from a plan view perspective, Figure 1B The electrical interconnect fixture is shown from a side view perspective viewed along the width direction, Figure 1C The electrical interconnect fixture is shown from a side view perspective along the length direction, Figure 1D along Figure 1A The identified cross-section line II' shows the electrical interconnect fixture.

[0007] Figure 2 A semiconductor package assembly including a plurality of stacked die arrangements having an electrical interconnect fixture forming electrical connections between the stacked die and a carrier is shown.

[0008] Figure 3A , 3B 3C and 3C illustrate electrical interconnect fixtures according to various embodiments. DETAILED DESCRIPTION

[0009] Disclosed herein are embodiments of an electrical interconnect fixture, a method for forming a semiconductor package using the electrical interconnect fixture, and a corresponding semiconductor package. The semiconductor package includes a stacked die arrangement, wherein two semiconductor dies are stacked on each other and mounted on a carrier. The electrical interconnect fixture is inserted between the two semiconductor dies and forms an electrical connection with terminals from both the die and the carrier. The electrical interconnect fixture advantageously includes a solder retention feature formed by a groove or a set of grooves surrounding the die attachment area of ​​the upper semiconductor die. The solder retention feature receives and retains excess solder that flows out of the upper semiconductor die during the soldering process. Retaining the excess solder material in this way prevents the floating movement of the upper semiconductor die when the solder material is in a liquefied state, thereby maintaining the position of the upper semiconductor die in its desired position. Providing a solder retention feature can eliminate the need to provide a special plating on the electrical interconnect fixture, thereby reducing costs.

[0010] refer to Figures 1A-1D, an electrical interconnect fixture 100 is shown. The electrical interconnect fixture 100 is an electrical interconnect fixture for forming a low resistance electrical connection in a semiconductor package. The electrical interconnect fixture 100 can be formed from an original flat sheet of a base material, which is similar to or equivalent to a metal sheet used to form a lead frame. The geometric features of the electrical interconnect fixture 100 described herein can be generated by performing metal processing, such as perforating, coining, stamping, etching, bending, cutting, etc. The electrical interconnect fixture 100 can be formed from an electrically conductive and thermally conductive base material, such as copper, aluminum, and alloys thereof. The electrical interconnect fixture 100 can be plated with additional metals, such as Ni, Ag, Au, Pd, Pt, Ni, etc., which can act as an adhesion promoter, an anti-corrosion layer, etc. However, in an embodiment, these plating layers can be omitted, thereby exposing the base material.

[0011] The electrical interconnect fixture 100 includes a die interface portion 102 and a carrier connection portion 104. The die interface portion 102 is adapted to fit between two vertically stacked semiconductor dies. That is, the die interface portion 102 is configured to form an interface with a semiconductor die below it and a semiconductor die above it. To this end, the die interface portion 102 includes a lower mating surface 106 and an upper mating surface 107 opposite to the lower mating surface 106. The lower mating surface 106 and the upper mating surface 107 are both substantially planar surfaces that can be arranged flush with the semiconductor die. The carrier connection portion 104 corresponds to the exterior of the electrical interconnect fixture 100, which facilitates electrical connection to an external carrier. The carrier connection portion 104 forms a vertical transition between the die interface portion 102 and the outer end of the carrier connection portion 104 below the die interface portion 102 and for contacting the external carrier. As shown, the carrier connection portion 104 includes a vertical transition, which can correspond to a punched hole in the metal. More generally, the carrier connection portion 104 may include different geometries, such as curved transitions, rounded corners, and the like.

[0012] The die interface portion 102 of the electrical interconnect fixture 100 includes a solder retention feature 108 formed by a recess 110 in the upper mating surface 107. The recess 110 is an artificially formed groove-like structure that extends inward from the upper mating surface 107 of the electrical interconnect fixture 100 toward the lower mating surface 106. The recess 110 can be generated by processing an initially planar metal using a metal processing technique, such as coining, etching, cutting, stamping, etc., to remove metal or portions that would otherwise disturb the surface planarity. The recess 110 is spaced apart from the outer edge side of the electrical interconnect fixture 100. That is, the recess 110 is completely confined within the inner area of ​​the upper mating surface 107. The separation distance between the recess 110 and the outer edge side of the electrical interconnect fixture 100 can be between 25 μm and 100 μm, for example. The recess 110 surrounds the die attach area of ​​the upper mating surface 107.

[0013] According to an embodiment, the solder retention feature 108 is formed by a continuous groove 110 that forms an enveloping shape around the die attach area 112 in the upper mating surface 107 . That is, the solder retention feature 108 completely surrounds the die attach area 112 on the upper mating surface 107 . Figures 1A-1D One example of such an embodiment is shown. In this embodiment, the recess 110 forms a rectangle around the die attach area 112 of the upper mating surface 107. As will be explained in more detail below, other geometries are possible.

[0014] According to an embodiment, the depth of the groove 110 is between 10 μm and 50 μm. In a specific embodiment, the depth of the groove 110 is about 20-25 μm. The depth refers to the distance between the upper mating surface 107 and the lowest point of the groove 110 closest to the lower mating surface 106 .

[0015] According to an embodiment, the groove 110 has a v-shaped cross-sectional geometry. Figure 1D An example of a groove 110 having a v-shaped cross-sectional geometry is shown. A v-shaped cross-sectional geometry refers to a geometry in which the walls of the groove 110 are planar and intersect each other at acute angles. According to an embodiment, the angle of intersection between the side walls of the groove 110 is between 50° and 70°. In a particular embodiment, the angle of intersection between the side walls of the groove 110 having a v-shaped cross-sectional geometry is approximately 60°. Other cross-sectional geometries are also possible. For example, the groove 110 can have a u-shaped cross-sectional geometry, a trapezoidal cross-sectional geometry, a flat bottom cross-sectional geometry, a fully curved cross-sectional geometry, a cross-sectional geometry with flat sidewalls, a cross-sectional geometry with a convex or concave outer wall, or a cross-sectional geometry in which the outer wall forms a rounded transition with the bottom and / or upper mating surface 107 of the groove 110.

[0016] refer to Figure 2, according to an embodiment, an exploded view of an assembly 200 for forming a semiconductor package is shown. Assembly 200 includes a carrier, which includes a die pad 202 and a plurality of leads 204. According to an embodiment, the carrier is provided by a metal lead frame. For example, such a lead frame can be formed by one or more conductive metals such as Cu, Ni and / or Ag. In addition, the features of the lead frame can include or be plated with, for example, Cu, Ni, Ag, Au, Pd, Pt, NiV, NiP, NiNiP, NiP / Pd, Ni / Au, NiP / Pd / Au or NiP / Pd / AuAg. The lead frame can be provided by a planar sheet metal of uniform thickness and processed by metal processing techniques, such as stamping, cutting, etching, etc. Instead of a metal lead frame, the carrier can correspond to an insulating electronic substrate. Examples of insulating electronic substrates include PCBs (printed circuit boards) or power electronic device carriers, such as DCB (direct copper bonding) substrates, IMS (insulated metal) substrates, or AMB (active metal brazing) substrates. In that case, the carrier may additionally comprise one or more electrically insulating regions formed of, for example, ceramic, FR-4 or the like, on which the structured metal layer is arranged.

[0017] The assembly 200 includes a plurality of semiconductor dies mounted on a die pad portion of a carrier. The semiconductor dies include pairs of vertical power device dies 206 mounted in a vertical stacking arrangement. The vertical power device dies 206 are discrete power devices rated to accommodate a voltage of at least 100V (volts), for example, 600V, 1200V or greater, and / or rated to accommodate a current of at least 1A, for example, 10A, 50A, 100A or greater. Examples of vertical power device dies 206 include diodes, transistors, thyristors, junction field effect transistors, and the like. In a specific example, the vertical power device dies 206 are configured as MOSFETs (metal oxide semiconductor field effect transistors), IGBTs (insulated gate bipolar transistors), or HEMTs (high electron mobility transistors). The term vertical refers to the fact that the power device die conducts current in a vertical direction between a first load terminal disposed on a main surface and a second load terminal disposed on a back surface opposite to the main surface. For a MOSFET, the first and second load terminals may correspond to source and drain terminals, respectively (or vice versa), for an IGBT, the first and second load terminals may correspond to emitter and collector terminals, respectively (or vice versa), etc. The assembly 200 additionally includes an additional logic device die 208 mounted on a low voltage plane separate from the vertical stacking arrangement. The logic device die 208 may be an integrated circuit, such as a silicon logic die.

[0018] According to an embodiment, the vertical stacking arrangement of semiconductor dies is configured as a half-bridge circuit. A half-bridge circuit refers to a circuit topology used in a power conversion circuit, such as a DC to DC converter, a DC to AC converter, etc. In a half-bridge circuit, one load terminal (e.g., source / emitter) of a high-side switch is connected to a first DC voltage (e.g., a positive potential), one load terminal (e.g., drain / collector) of a low-side switch is connected to a second DC voltage (e.g., a negative potential or ground), and the remaining two load terminals (e.g., drain / collector of a high-side switch and source / emitter of a low-side switch) are connected together to form an output or switch (SW) of the half-bridge circuit. The control (gate) terminals of the high-side and low-side switches can be switched according to a power control scheme (e.g., pulse width modulation) to produce a desired voltage and frequency at the output of the half-bridge circuit. For example, the first of the vertical power device dies 206 mounted directly on the die pad 202 can correspond to the high-side switch of the half-bridge circuit, and the second of the vertical power device dies 206 mounted above the first of the vertical power device dies 206 can correspond to the low-side switch of the half-bridge circuit. The logic device die 208 can be configured to provide switching signals to the control terminals of the high-side switch and the low-side switch. The electrical interconnection between the logic device die 208 and the vertical stacking arrangement of the semiconductor die can be provided by additional electrical interconnection elements not shown in the drawings, such as bonding wires, clamps, tapes, etc. As shown, the semiconductor package assembly 200 includes three of the vertical stacking arrangements of semiconductor dies. This configuration can be used to generate a full-bridge arrangement, wherein each of the vertical stacking arrangements of the semiconductor dies forms a phase of the full-bridge arrangement.

[0019] Each of the vertical stacked arrangements is mounted in the following manner. A first of the vertical power device dies 206 is mounted on the die pad 202, with a first load terminal (e.g., source terminal) facing the die pad 202 and a second load terminal (e.g., drain terminal) facing away from the die pad 202. A die interface portion 102 of an electrical interconnect fixture is disposed over the first of the vertical power device dies 206, with a lower mating surface 106 facing the second load terminal of the first vertical power device die 206. A second of the vertical power device dies 206 is mounted on the die interface portion 102 of the electrical interconnect fixture 100, with a first load terminal (e.g., drain terminal) facing the electrical interconnect fixture 100 and a second load terminal (e.g., source terminal) facing away from the electrical interconnect fixture 100. A second electrical interconnect fixture 210 is disposed over the second vertical power device die 206 and mated with the second load terminal of the second power device die 206. In this arrangement, a first load terminal of the first vertical power device die 206 is electrically connected to the die pad 202, which in turn is connected to the lead 204, a second load terminal of the second vertical power device die 206 is electrically connected to the lead 204 via the second electrical interconnect fixture 210, and both the second load terminal of the first vertical power device die 206 and the first load terminal of the second vertical power device die 206 are electrically connected to the lead 204 via the electrical interconnect fixture 100. In a half-bridge configuration, the connection provided by the die pad 202 to the first vertical power device die 206 may correspond to a first DC voltage connection, the connection provided by the second electrical interconnect fixture 210 to the second vertical power device die 206 may correspond to a second DC voltage connection, and the connection provided between the first and second vertical power device dies 206 and the electrical interconnect fixture 100 may correspond to a phase connection.

[0020] Forming a semiconductor package may include one or more welding processes. These welding processes include welding the first load terminal of the second vertical power device die 206 to the die interface portion 102 of the electrical interconnect fixture 100, thereby electrically connecting the two together. According to this process, a solder material is provided between the upper mating surface 107 of the electrical interconnect fixture 100 and the load terminal of the second vertical power device die 206. This solder material can be a solder paste, including, for example, a tin-based and / or lead-free solder material. The solder material can be initially applied to one or both of the upper mating surface 107 of the electrical interconnect fixture 100 and the second vertical power device die 206, for example, as a preform, a solder ball, etc. When the second vertical power device die 206 is complete and located at the desired position on the electrical interconnect fixture 100, a heating process is performed, wherein the temperature of the solder material is increased to melt the material and induce a reaction, thereby forming a stable solder joint. The peak temperature of this heating process occurs during the reflow phase of this heating process. The reflow temperature for this soldering process may be in the range of, for example, 200° C. to 300° C. This heating process may also form additional solder joints, including any solder joints necessary to form the electrical connections described above.

[0021] During the above-mentioned soldering step, the solder holding feature 108 advantageously maintains the position of the second vertical power device die 206. More specifically, the solder holding feature 108 forms a boundary around the second vertical power device die 206 and interacts with the liquefied solder by keeping the solder material within the constrained space around the second vertical power device die 206 during the heating process. As a result, the liquefied solder material gathers at the boundary around the periphery of the second vertical power device die 206 and prevents the floating movement of the second vertical power device die 206 during the reflow process. The liquefied solder material is collected in the solder holding feature 108 to form a curved liquid surface, which prevents the second vertical power device die 206 from freely moving (floating) on ​​the liquefied solder material. Specifically, the second vertical power device die 206 is prevented from rotating from a plan view perspective. In comparison, a rotational movement of 5 degrees or more was observed in an electrical interconnect fixture that does not include the solder holding feature 108 described herein, which may potentially lead to problematic failures and / or semiconductor die extending above the edge side of the electrical interconnect fixture.

[0022] Advantageously, the solder retention features 108 can eliminate the need for special plating on the electrical interconnect fixture, such as Ag plating, which can be used to prevent floating movement of the semiconductor die, but increases cost and complexity. Therefore, according to an embodiment, the surface of the electrical interconnect fixture 100, especially the die attach area 112, can be an exposed base material metal, such as a surface of bare copper, bare aluminum, and alloys thereof.

[0023] After the die is mounted and the electrical interconnections are formed, an encapsulation process may be performed to cover the carrier, the semiconductor die, and the associated electrical connections. At the same time, the outer ends of the leads 204 remain exposed from the electrically insulating encapsulant body, thereby forming package terminals that are accessible from the outside. The encapsulation process may include, for example, forming an electrically insulating molding compound by injection molding, transfer molding, compression molding, etc. A dicing process may be performed to form a complete semiconductor package.

[0024] refer to Figures 3A-3C , an additional embodiment of the electrical interconnect fixture 100 is shown. The illustrated embodiment represents a potential alternative configuration for the solder retention feature 108. Figure 3A and 3B In the embodiments of the present invention, the solder retention feature 108 is formed by a plurality of grooves 110. In each case, the grooves 110 together form a boundary around the die attach area 112 of the upper mating surface 107 and therefore around the semiconductor die mounted thereon. The plurality of grooves 110 operate similarly to the single continuous groove 110 in the above-described embodiments in that they form a boundary that holds the solder material within a constrained space around the semiconductor die mounted thereon, thereby preventing floating movement of this semiconductor die. The interruption size between each of the grooves 110 is sufficiently small that the liquefied solder material gathers around the periphery of the semiconductor die mounted thereon and forms a meniscus that prevents floating movement of the semiconductor die mounted thereon during the soldering process. For example, the plurality of grooves 110 may occupy at least 90%, at least 80%, or at least 75% of the total length of the closed shape around the die attach area 112 and provide the necessary interaction with the liquefied solder to hold the position of the die. Independently or in combination, the plurality of grooves 110 may occupy at least 50% of the length of each side of the closed shape around the die attach area 112 and provide the necessary interaction with the liquefied solder to hold the die in place. Figure 3A and 3B Only two potential configurations are shown, and more generally, small interruptions may be provided at any location. Figure 3C A solder retention feature 108 is shown formed by a continuous groove 110 that forms a closed shape around the upper mating surface 107, wherein the closed shape has rounded corners. Different types of corner geometries and / or different closed shape geometries are also possible. In addition, the size of the groove 110 can be adapted to a specific die size. Preferably, the footprint of the groove 110 is slightly larger than the specific die to be mounted on the electrical interconnect fixture 100.

[0025] As used herein, the term surrounding includes completely continuous geometric shapes that form a closed shape as well as discontinuous geometric shapes that form a closed shape with interruptions. For example, a rectangle with partial interruptions is a geometric shape that surrounds an interior region, provided that at least a portion of the interior region is bordered by the rectangle on all four sides.

[0026] The semiconductor die disclosed herein may be formed by a wide range of device technologies utilizing a wide range of semiconductor materials. Examples of such materials include, but are not limited to, elemental semiconductor materials (e.g., silicon (Si) or germanium (Ge)), Group IV compound semiconductor materials (e.g., silicon carbide (SiC) or silicon germanium (SiGe)), binary, ternary, or quaternary Group III-V semiconductor materials (e.g., gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN), or indium gallium arsenide phosphide (InGaAsP), etc.).

[0027] The semiconductor die disclosed herein can be configured as a vertical device, which refers to a device that conducts a load current between the oppositely facing main surface and the back surface of the die. Alternatively, the semiconductor die can be configured as a lateral device, which refers to a device that conducts a load current parallel to the main surface of the die.

[0028] Spatially relative terms such as "under", "below", "lower", "above", "upper", etc. are used for convenience of description to explain the positioning of one element relative to another element. These terms are intended to cover different device orientations other than the orientation shown in the drawings. In addition, terms such as "first", "second", etc. are also used to describe various elements, regions, parts, etc., and are not intended to be limiting. Similar terms throughout the specification indicate similar elements.

[0029] As used herein, the terms "having", "containing", "including", "comprising" and the like are open terms that indicate the presence of stated elements or features, but do not exclude additional elements or features. The articles "a", "an" and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0030] Although the present disclosure is not so limited, one or more aspects of the present disclosure are presented below by way of numbered examples.

[0031] Example 1. An electrical interconnect fixture comprises: a die interface portion and a carrier connection portion, the die interface portion being adapted to be mated between two vertically stacked semiconductor dies, the carrier connection portion being configured to electrically connect the two vertically stacked semiconductor dies to a carrier, wherein the die interface portion comprises a lower mating surface, an upper mating surface opposite to the lower mating surface, and a solder retention feature formed by one or more grooves in the upper mating surface, the one or more grooves being spaced apart from an outer edge side of the electrical interconnect fixture and surrounding a die attachment area of ​​the upper mating surface.

[0032] Example 2. The electrical interconnect fixture of Example 1, wherein the solder retention feature is formed by one of the grooves being a continuous groove, the continuous groove forming a closed shape surrounding the die attach area of ​​the upper mating surface.

[0033] Example 3. The electrical interconnect clamp of Example 2, wherein the one continuous groove of the grooves forms a rectangle surrounding the die attach area of ​​the upper mating surface.

[0034] Example 4. The electrical interconnect clamp of Example 1, wherein the one or more grooves have a v-shaped cross-sectional geometry.

[0035] Example 5. The electrical interconnection clamp of Example 4, wherein an intersection angle between side walls of the one or more grooves is between 50° and 70°.

[0036] Example 6. The electrical interconnect fixture of Example 1, wherein the one or more grooves have a depth between 20 μm and 50 μm.

[0037] Example 7. The electrical interconnect clamp of Example 1, wherein the electrical interconnect clamp is formed of a base metal of copper, aluminum, or alloys thereof, and wherein the die attach area of ​​the upper mating surface is an exposed surface of the base metal.

[0038] Example 8. A semiconductor package comprising the electrical interconnection fixture according to claim 1.

[0039] Example 9. The semiconductor package of Example 8, wherein the semiconductor package includes a first semiconductor die and a second semiconductor die mounted in a stacked die arrangement, the interface portion of the electrical interconnect fixture is arranged between the first semiconductor die and the second semiconductor die, and wherein the one or more grooves of the solder retention feature surround the second semiconductor die.

[0040] Example 10. The semiconductor package of Example 9, wherein the first semiconductor die and the second semiconductor die are each configured as a discrete transistor die, wherein the first semiconductor die and the second semiconductor die are arranged in a half-bridge configuration, and wherein the electrical interconnect fixture forms a phase terminal connection that electrically connects load terminals from the first semiconductor die and the second semiconductor die to one or more leads of the semiconductor package.

[0041] Example 11. A method of forming a semiconductor package, the method comprising: providing a carrier including a die pad and a plurality of leads; providing a first semiconductor die and a second semiconductor die, each semiconductor die being configured as a vertical power device, providing an electrical interconnect fixture, the electrical interconnect fixture comprising a die interface portion and a carrier connection portion; providing a stacked die arrangement on the die pad, the stacked die arrangement comprising the die interface portion of the electrical interconnect fixture arranged between the first semiconductor die and the second semiconductor die, and the carrier connection portion contacting the carrier; providing a solder material between the second semiconductor die and the die interface portion of the electrical interconnect fixture; and performing a soldering process, the soldering process liquefying the solder material, wherein the electrical interconnect fixture comprises a solder retaining feature forming a boundary around the second semiconductor die, and wherein the solder retaining feature interacts with the liquefied solder during the soldering process by retaining the solder material within a confined space surrounding the second semiconductor die, thereby preventing floating movement of the second semiconductor die.

[0042] Example 12. The method of Example 11, wherein the solder retention feature is formed by one or more grooves in the upper mating surface of the die interface portion, the one or more grooves being spaced apart from the outer edge side of the electrical interconnect fixture and forming a boundary of a die attach area around the upper mating surface, and wherein the one or more grooves become at least partially filled with the liquefied solder material during the soldering process.

[0043] Example 13. The method of Example 12, wherein the liquefied solder material filling the one or more recesses forms a meniscus during the soldering process, the meniscus preventing floating movement of the second semiconductor die during the soldering process.

[0044] Example 14. The method of Example 12, wherein the solder retention feature is formed by one of the grooves being a continuous groove, the continuous groove forming a closed shape around the upper mating surface.

[0045] Example 15. The method of Example 12, wherein the one or more grooves have a v-shaped cross-sectional geometry.

[0046] Example 16. The method of Example 15, wherein the angle between the side walls of the one or more grooves is between 50° and 70°.

[0047] Example 17. The method of Example 12, wherein the one or more grooves have a depth between 20 μm and 50 μm.

[0048] Example 18. The method of Example 12, wherein the electrical interconnect clip is formed of a base metal of copper, aluminum, or alloys thereof, and wherein the die attach area of ​​the upper mating surface is an exposed surface of the base metal.

[0049] Example 19. The method of Example 11, wherein the first semiconductor die and the second semiconductor die are each configured as a discrete transistor die, wherein the first semiconductor die and the second semiconductor die are arranged in a half-bridge configuration, and wherein the electrical interconnect fixture forms a phase terminal connection that electrically connects load terminals from the first semiconductor die and the second semiconductor die to one or more of the leads.

[0050] Example 20. The method of Example 19, further comprising providing a second electrical interconnect clamp and electrically connecting a second load terminal of the second semiconductor die to the carrier via the second electrical interconnect clamp.

[0051] In view of the above range of variations and applications, it should be understood that the present invention is not limited by the above description, nor by the accompanying drawings. Instead, the present invention is limited only by the appended claims and their legal equivalents.

Claims

1. An electrical interconnection fixture, comprising: a die interface portion adapted to fit between two vertically stacked semiconductor dies; as well as a carrier connection portion configured to electrically connect the two vertically stacked semiconductor dies to a carrier, Wherein, the tube core interface part comprises: lower mating surface; an upper mating surface opposite the lower mating surface; and A solder retention feature is formed by one or more grooves in the upper mating surface, the one or more grooves being spaced apart from an outer edge side of the electrical interconnect fixture and surrounding a die attach area of ​​the upper mating surface.

2. The electrical interconnection fixture according to claim 1, wherein: The solder retention feature is formed by one of the grooves being a continuous groove that forms a closed shape surrounding the die attach area of ​​the upper mating surface.

3. The electrical interconnection fixture according to claim 2, wherein: The one continuous one of the grooves forms a rectangle surrounding the die attach area of ​​the upper mating surface.

4. The electrical interconnection fixture according to claim 1, wherein: The one or more grooves have a v-shaped cross-sectional geometry.

5. The electrical interconnection fixture according to claim 4, wherein: The intersection angle between the side walls of the one or more grooves is between 50° and 70°.

6. The electrical interconnection fixture according to claim 1, wherein: The one or more grooves have a depth between 20 μm and 50 μm.

7. The electrical interconnection fixture according to claim 1, wherein: The electrical interconnect clip is formed of a base metal of copper, aluminum, or alloys thereof, and wherein the die attach area of ​​the upper mating surface is an exposed surface of the base metal.

8. A semiconductor package comprising the electrical interconnection fixture according to claim 1.

9. The semiconductor package according to claim 8, wherein: The semiconductor package includes a first semiconductor die and a second semiconductor die mounted in a stacked die arrangement, the interface portion of the electrical interconnect fixture is arranged between the first semiconductor die and the second semiconductor die, and wherein the one or more grooves of the solder retention feature surround the second semiconductor die.

10. The semiconductor package according to claim 9, wherein The first semiconductor die and the second semiconductor die are each configured as a discrete transistor die, wherein the first semiconductor die and the second semiconductor die are arranged in a half-bridge configuration, and wherein the electrical interconnect fixture forms a phase terminal connection that electrically connects load terminals from the first semiconductor die and the second semiconductor die to one or more leads of the semiconductor package.

11. A method of forming a semiconductor package, the method comprising: providing a carrier including a die pad and a plurality of leads; providing a first semiconductor die and a second semiconductor die, each semiconductor die being configured as a vertical power device, providing an electrical interconnect fixture comprising a die interface portion and a carrier connection portion; providing a stacked die arrangement on the die pad, the stacked die arrangement comprising the die interface portion of the electrical interconnect fixture disposed between the first semiconductor die and the second semiconductor die, and the carrier connection portion contacting the carrier; providing a solder material between the second semiconductor die and the die interface portion of the electrical interconnect fixture; as well as performing a soldering process that liquefies the solder material, wherein the electrical interconnect fixture includes solder retention features forming a border around the second semiconductor die, and Wherein, the solder retention feature interacts with liquefied solder during the soldering process by retaining the solder material within a confined space surrounding the second semiconductor die, thereby preventing floating movement of the second semiconductor die.

12. The method according to claim 11, wherein: The solder retention feature is formed by one or more grooves in the upper mating surface of the die interface portion, the one or more grooves being spaced apart from the outer edge side of the electrical interconnect fixture and forming a boundary of the die attachment area surrounding the upper mating surface, and wherein the one or more grooves become at least partially filled with liquefied solder material during the soldering process.

13. The method according to claim 12, wherein: The liquefied solder material filling the one or more recesses during the soldering process forms a meniscus that prevents floating movement of the second semiconductor die during the soldering process.

14. The method according to claim 12, wherein: The solder retention feature is formed by one of the grooves being a continuous groove, the one continuous groove forming a closed shape around the upper mating surface.

15. The method according to claim 12, wherein: The one or more grooves have a v-shaped cross-sectional geometry.

16. The method according to claim 15, wherein: The intersection angle between the side walls of the one or more grooves is between 50° and 70°.

17. The method according to claim 12, wherein: The one or more grooves have a depth between 20 μm and 50 μm.

18. The method according to claim 12, wherein: The electrical interconnect clip is formed of a base metal of copper, aluminum, or alloys thereof, and wherein the die attach area of ​​the upper mating surface is an exposed surface of the base metal.

19. The method according to claim 11, wherein: The first semiconductor die and the second semiconductor die are each configured as a discrete transistor die, wherein the first semiconductor die and the second semiconductor die are arranged in a half-bridge configuration, and wherein the electrical interconnect fixture forms a phase terminal connection that electrically connects load terminals from the first semiconductor die and the second semiconductor die to one or more of the leads.

20. The method according to claim 19, further comprising: A second electrical interconnect clip is provided and a second load terminal of the second semiconductor die is electrically connected to the carrier via the second electrical interconnect clip.

Images