Double-sided conductive vias

Abstract

The invention relates to a double-sided conductive via. A method of processing and associated integrated circuit (IC) structures and devices are described herein, the IC structures and devices including one or more conductive vias. In one example, a conductive via is formed from one side of the integrated circuit, and then a portion of the conductive via is widened from a second side of the IC structure opposite the first side. In one example, the resulting IC structure includes a first portion having a first width, a second portion having a second width, and a third portion having a third width, where the third portion is between the first portion and the second portion, and the third width is less than the first width and the second width. In one such example, the conductive via tapers from both ends toward a third portion between the both ends.

Description

Background Art

[0001] Over the past several decades, the scaling of features in integrated circuits (ICs) has been the driving force behind the ever-growing semiconductor industry. Scaling to smaller and smaller features enables an increased density of functional units on the limited real estate of a semiconductor chip. For example, shrinking transistor size allows an increased number of storage or logic devices to be incorporated on a chip, lending to the processing of products with increased capacity. However, the drive for ever-increasing capacity is not without problems. The necessity to optimize the processing and performance of each component (e.g., conductive interconnects for signaling, power delivery, and grounding) is becoming increasingly important. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The embodiments will be easily understood by the following detailed description in conjunction with the accompanying drawings.

[0003] Figures 1A-1C Cross-sectional side views are provided illustrating examples of integrated circuit (IC) structures including double-sided conductive vias according to embodiments of the present disclosure.

[0004] Figure 2 is a flow chart of an exemplary method for processing an IC structure including double-sided conductive vias according to some embodiments.

[0005] Figures 3A-3G According to some embodiments, Figure 2 sectional side views of an exemplary IC structure at various stages in the process of fabricating the exemplary IC structure.

[0006] Figure 4 is a flow chart of an exemplary method for processing an IC structure including double-sided conductive vias according to some embodiments.

[0007] Figures 5A-5H According to some embodiments, Figure 4 sectional side views of an exemplary IC structure at various stages in the process of fabricating the exemplary IC structure.

[0008] Figure 6 is a top view of a wafer and die according to any of the embodiments disclosed herein which may include any of the IC structures disclosed herein.

[0009] Figure 7 is a side cross-sectional view of an IC device according to any of the embodiments disclosed herein, which may include any of the IC structures disclosed herein.

[0010] Figure 8is a side cross-sectional view of an IC package that may include any of the IC structures disclosed herein according to various embodiments.

[0011] Fig. 9 is a side cross-sectional view of an IC device assembly according to any of the embodiments disclosed herein that may include any of the IC structures disclosed herein.

[0012] Fig.10 is a block diagram of an exemplary electrical device that may include any of the IC structures disclosed herein according to any of the embodiments disclosed herein. DETAILED DESCRIPTION

[0013] Disclosed herein is a processing method and associated IC structures and devices that include one or more double-sided conductive vias. The disclosed systems, methods, and devices each have several innovative aspects, no single innovative aspect of which is solely responsible for all of the desirable properties disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the following description and accompanying drawings.

[0014] As briefly described above, shrinking features in ICs has fueled the growth of the semiconductor industry. Smaller features mean more functionality on a chip, increasing capacity. In the pursuit of greater capacity, it is critical to optimize the processing and performance of each individual component. One factor that limits performance is the aspect ratio of the conductive via. Traditionally, vias are patterned in one step, resulting in an etched trench profile in which one side of the via is wider than the other. For example, the via opening may taper from the top of the via opening toward the bottom, resulting in a smaller width at its bottom than at its top. Therefore, conventional vias can have a V-shaped or trapezoidal profile (e.g., the profile of the via may have two parallel sides, one of which is a short side and the other of which is a long side).

[0015] This reduction in width along the entire height of the via trench can result in higher vertical resistance as well as higher contact resistance at the narrower sides (e.g., at the bottom of the via). The increased resistance can be particularly problematic for high aspect ratio vias, which can have one side that is significantly narrower than the other side. The increased resistance in a conductive via can result in a number of undesirable effects that can affect device performance, including increased power consumption and heat dissipation, signal delays, reduced signal integrity, and crosstalk (e.g., unwanted interference between adjacent components).

[0016] Compared to conventional techniques for forming vias, double-sided via processing can achieve the formation of vias with a larger minimum width and a larger total volume of conductive fill material. Unlike conventional vias having a V-shaped profile or a trapezoidal profile, in one example, the double-sided via is wider at both ends than at the portion between the two ends of the via. Therefore, in one example, the double-sided via can have straighter and / or wider sidewalls than conventional vias. In some examples, the double-sided via may have a profile that is similar to an hourglass shape and / or tapers from both ends toward the portion between the two ends. Forming a double-sided via can, for example, involve: forming an opening in one or more layers on a first side of a substrate (e.g., from the front side), flipping the substrate to reveal a second side of the substrate (e.g., the back side), and widening a portion of the opening from the second side. The widened opening can then be filled with a conductive material. For ease of reference, the term "double-sided via" is used herein to refer to a conductive via according to the examples described herein. According to examples herein, the terms via, interconnect, and conductive interconnect may be used to refer to a conductive via.

[0017] The IC structure as described herein (particularly, the IC structure including the double-sided conductive via) can be implemented in one or more components associated with the IC, or / and implemented between various such components. In various embodiments, the components associated with the IC include, for example, transistors, diodes, power supplies, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. The components associated with the IC may include those components mounted on the IC or those components connected to the IC. The IC may be analog or digital, and may be used in many applications (such as microprocessors, optoelectronic devices, logic blocks, audio amplifiers, etc.) according to the components associated with the IC. In some embodiments, the IC structure as described herein may be included in a radio frequency IC (RFIC), which may be included in any component associated with an RF receiver, RF transmitter, or RF transceiver used in telecommunications, such as a base station (BS) or user equipment (UE). Such components may include, but are not limited to, power amplifiers, low noise amplifiers, RF filters (including arrays of RF filters or RF filter banks), switches, up-converters, down-converters, and duplexers. In some embodiments, the IC structure as described herein may be included in a memory device or circuit. In some embodiments, an IC structure as described herein may be used as part of a chipset for performing one or more related functions in a computer.

[0018] For the purpose of explanation, specific quantities, materials and configurations are set forth in order to provide a thorough understanding of illustrative implementations. However, it will be clear to those skilled in the art that the present disclosure may be implemented without specific details, or / and the present disclosure may be implemented using only some of the described aspects. In other instances, well-known features are omitted or simplified to avoid blurring illustrative implementations. As described herein or as known in the art, based on the context of a specific value, the terms "substantially", "close", "approximately", "near..." and "approximately" are generally referred to within + / -10% of the target value, such as within + / -5% of the target value. Similarly, as described herein or as known in the art, based on the context of a specific value, the terms indicating the orientation of various elements (e.g., "coplanar", "vertical", "orthogonal", "parallel" or any other angle between elements) are generally referred to within + / -10% of the target value, such as within + / -5% of the target value.

[0019] In the following description, reference is made to the accompanying drawings, which form a part of this description and in which embodiments that may be implemented are illustrated as diagrams. It should be understood that other embodiments may be used and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be interpreted in a limiting sense.

[0020] In the accompanying drawings, although some schematic illustrations of exemplary structures of various devices and components described herein may be shown with exact right angles and straight lines, this is only for ease of illustration, and embodiments of these components may be curved, rounded, or otherwise irregularly shaped, as dictated by and sometimes unavoidable by the processing used to process semiconductor device components. Therefore, it should be understood that when any of the structures described herein are examined using, for example, scanning electron microscopy (SEM) images or transmission electron microscopy (TEM) images, such schematic illustrations may not reflect the actual process limitations, which may make the features not appear so "ideal." In such images of the actual structure, possible processing defects can also be visible, such as imperfectly straight edges of material, tapered vias or other openings, unintentional rounding of corners or variations in the thickness of different material layers, accidental screw dislocations, edge dislocations, or combined dislocations within a crystal region, and / or accidental dislocation defects of single atoms or clusters of atoms. Other defects not listed here but common in the field of device processing may exist. Examining the layout and mask data using, for example, optical microscopy, TEM or SEM and reverse engineering portions of the device to reconstruct the circuit and / or examining cross-sections of the device using, for example, physical failure analysis (PFA) to detect the shapes and locations of the various device elements described herein will allow determination of the presence of an IC structure with double-sided vias as described herein.

[0021] Various aspects of the illustrative implementations will be described using terms commonly used by those skilled in the art to convey the substance of their work to others skilled in the art. For example, the terms "oxide", "carbide", "nitride", "silicide", etc. refer to compounds containing oxygen, carbon, nitrogen, silicon, etc., respectively; the term "high-k dielectric" refers to a material having a higher dielectric constant than silicon oxide; the term "low-k dielectric" refers to a material having a lower dielectric constant than silicon oxide. Materials mentioned herein using chemical formulas or as compounds cover all materials including elements of the chemical formula or compound, for example, TiSi or titanium silicide may refer to any material including titanium and silicon, WN or tungsten nitride may refer to any material including tungsten and nitrogen, etc. Unless otherwise specified, the term "insulating" means "insulating in an electrical manner", and the term "conductive" means "conductive in an electrical manner". In addition, the term "connected" may be used to describe a direct electrical or magnetic connection between connected things without any intermediate device, and the term "coupled" may be used to describe a direct electrical or magnetic connection between connected things or an indirect connection through one or more passive or active intermediate devices. A first component described as being electrically coupled to a second component means that the first component is in conductive contact with the second component (ie, a conductive path is provided to route electrical signals / power between the first and second components).

[0022] Various operations can be described in turn as multiple discrete actions or operations in a manner that is most helpful for understanding the claimed subject matter. However, the order of description should not be interpreted as implying that these operations must be order-dependent. These operations may not be performed in the order presented. The operations described can be performed in an order different from the described embodiments. In other embodiments, various other operations can be performed, and / or the described operations can be omitted.

[0023] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C). When the term "between" is used with reference to a measurement range, the term "between" includes the endpoints of the measurement range.

[0024] The present description uses the phrases "in one embodiment" or "in an embodiment", which may all refer to one or more embodiments in the same or different embodiments. As used for embodiments of the present disclosure, the terms "including", "comprising", "having", etc. are synonymous. The present disclosure may use angle-based descriptions, such as "above...", "below...", "top", "bottom", and "side"; such descriptions are used to facilitate discussion and are not intended to constrain the application of the disclosed embodiments. The drawings are not necessarily drawn to scale. Unless otherwise specified, the use of ordinal adjectives "first", "second", and "third", etc. to describe common objects only indicates that different instances of similar objects are being referred to, and is not intended to imply that the objects described in this manner must be in a given order in time, space, rank, or in any other manner. Although some materials may be described in singular form, such materials may include multiple materials, for example, a semiconductor material may include two or more different semiconductor materials.

[0025] Figures 1A-1C is a cross-sectional side view illustrating an example of an IC structure including a double-sided conductive via according to an embodiment of the present disclosure. Figure 1A , the conductive via 102A extends through one or more layers to electrically couple conductive elements in layers above and below the conductive via 102A. The conductive via 102A may be used for signaling, power delivery (e.g., a power via), or grounding. The conductive via 102A is surrounded by an insulator material 105, such as any suitable interlayer dielectric (ILD) material. In some embodiments, such insulator material 105 may be a high-k dielectric including various elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used for such purposes may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium oxide silicon, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate. In other embodiments, the insulator material 105 may be a low-k dielectric material. Some examples of low-k dielectric materials include, but are not limited to, silicon dioxide, carbon-doped oxides, silicon nitride, organic polymers (such as perfluorocyclobutane or polytetrafluoroethylene), fused silica glass (FSG), and organosilicates (such as silsesquioxane, siloxane, or organosilicate glass).

[0026] exist Figure 1AIn the example illustrated in FIG, the conductive via 102A is located in a device region 104, which includes one or more devices 106, such as transistors or other IC devices. The conductive via 102A may be located near a transistor of any architecture, such as any non-planar or planar architecture. Non-planar transistors, such as dual-gate transistors, tri-gate transistors, FinFETs, and nanowire / nanobelt / nanosheet transistors, refer to transistors with non-planar architectures. Compared to a planar architecture in which a transistor channel has only one confined surface, a non-planar architecture is any type of architecture in which a transistor channel has more than one confined surface. A confined surface refers to a specific orientation of a channel surface confined by a gate field. Non-planar transistors may improve performance relative to transistors with a planar architecture, such as a single-gate transistor. Due to the potential to form gates on all four sides of the channel material, nanobelt transistors may be particularly beneficial to the continued scaling of complementary metal oxide semiconductor (CMOS) technology nodes (thus, such transistors are sometimes referred to as "all-around gate" transistors).

[0027] exist Figure 1A , the device region 104 and the conductive via 102A through the device region 104 are located between the interconnect layers 103 and 138. Additional interconnect layers may exist above or below the interconnect layers 103 and 138. For example, the IC structure 100A includes an interconnect layer 136 on the interconnect layer 138 and an interconnect layer 108 below the interconnect layer 103. A collection of interconnect layers may be referred to as a "metallization stack" of the IC structure 100A. For example, the metallization stack 119 includes the interconnect layers 103, 108, and the metallization stack 149 includes the interconnect layers 136, 138. Interchangeably, the metallization stacks 119, 149 may be referred to as the "BEOL layer(s)" of the IC structure 100A, and the device region 104 may be referred to as the "FEOL layer(s)" of the IC structure 100A.

[0028] By placing one or more interconnect layers (e.g., Figure 1A 103, 108, 136, and 138), electrical signals (such as power and / or input / output (I / O) signals) can be routed to and / or from devices 106 (e.g., transistors) in device region 104. Interconnect structures 127, 128, 157, and 158 can be arranged within the interconnect layers of metallization stacks 119, 149 to route electrical signals according to a variety of designs (in particular, the arrangement is not limited to the arrangement of Figure 1A ). Although a specific number of interconnect layers 103, 108, 136, 138 are Figure 1AAlthough depicted in FIG. 1 , embodiments of the present disclosure include IC structures having more or fewer interconnect layers than depicted.

[0029] In some embodiments, interconnect structures 127, 128, 157, and 158 may include conductive wires 127, 157 and / or conductive vias 128, 158 filled with a conductive material such as metal. Wires 127, 157 may be arranged to route electrical signals in a direction substantially parallel to the planes of layers 103, 138. For example, Figure 1A , lines 127, 157 may route electrical signals in a direction into and out of the page. Vias 128, 158 may be arranged to route electrical signals in a direction substantially perpendicular to the planes of layers 103, 138. In some embodiments, vias 128, 158 may electrically couple lines of different interconnect layers of corresponding metallization stacks together.

[0030] The interconnect layers 103, 108, 136, 138 may include dielectric materials disposed between interconnect structures, such as Figure 1A For example, interconnect layers 103, 108 include dielectric material 126 between interconnect structures 127, 128, and interconnect layers 136, 138 include dielectric material 156 between interconnect structures 157, 158. In some embodiments, dielectric material 126 between interconnect structures 127, 128 disposed in different ones of interconnect layers 103 and 108 may have different compositions; in other embodiments, the composition of dielectric material 126 between different interconnect layers 103 and 108 may be the same. Similarly, the composition of dielectric material 156 between different interconnect layers 136 and 138 may be different or the same. Although not specifically shown in Figure 1A In some embodiments, however, the IC structure 100A may further include a solder resist material (eg, polyimide or similar material) and one or more conductive contacts formed on the interconnect layers of the metallization stacks 119 and / or 149 .

[0031] Therefore, if Figure 1A As shown in FIG. 1 , IC structure 100A includes: layer 103 including conductive elements (e.g., via 128); second layer 138 including conductive elements (e.g., via 158); and third layer (e.g., one or more layers of device region 104) including conductive via 102A between vias 158 and 128. Conductive via 102A is filled with a conductive material such as a metal (e.g., tungsten or another metal) and electrically couples the conductive elements in layer 103 with the conductive elements in layer 138. Although Figure 1AThe conductive via 102A is depicted as being located between two conductive vias 128 , 158 , but in other examples, the conductive via may be located between other conductive elements, such as conductive contacts (eg, bond pads) or other conductive elements.

[0032] Unlike conventional conductive vias having a V-shaped profile or a trapezoidal cross-section, the conductive via 102A is wider at both ends than between the ends of the conductive via 102A. For example, the conductive via 102A includes a first portion 107A having a width 113A, a second portion 111A having a width 117A, and a third portion 109A having a width 115A, wherein the width 115A is smaller than the widths 113A and 117A, wherein in a plane substantially parallel to the layer 103 (e.g., in an xy plane, wherein the x-axis is shown at Figure 1A and from Figure 1A The width of a given portion of the conductive via 102A is measured at an angle of , with the y-axis in the direction into and out of the page). In one example, the first portion 107A is closer to the first conductive element 128 than the second portion 111A, and is in conductive contact with the first conductive element 128. Similarly, the second portion 111A is closer to the second conductive element 158 ​​than the first portion 107A, and is in conductive contact with the second conductive element 158. Figure 1A In the example illustrated in , the second portion 111A is closer to the device 106 than the portions 109A and 107A.

[0033] exist Figure 1A In the example illustrated in FIG. 1 , the conductive via 102A tapers from both ends toward a portion between the two ends, rather than tapering in one direction like a conventional via. For example, the conductive via tapers from a first portion 107A (e.g., a bottom portion) toward portion 109A and from a second portion 111A (e.g., a top portion) toward portion 109A. In one such example, the conductive via can have a cross-section similar to an hourglass shape (e.g., along the length of the conductive via as shown in FIG. 1 ), in the sense that the conductive via has a narrower portion between two wider portions. Figure 1A 1 and is substantially perpendicular to the cross-section of layer 103). However, the cross-section of the double-sided conductive via may have other shapes or profiles.

[0034] Figure 1A The example illustrated in FIG. 1 shows the narrowest portion of the conductive via 102A near the approximate midpoint of the conductive via 102A, wherein the midpoint of the conductive via 102A between the conductive elements 158, 128 is located at 50% of the length 121A of the conductive via 102A relative to either end of the conductive via 102A. The length 121A of the conductive via 102A is a length that is substantially perpendicular to the layer 103 (e.g., parallel to the z-axis, such as Figure 1A). However, the narrowest portion of the conductive via 102A may not be at or near the midpoint. Additionally, a double-sided conductive via may not have a single "narrowest portion." In one example, the narrowest portion of the conductive via 102A may be located between the midpoint and one end of the conductive via 102A. For example, consider a conductive via such as Figure 1A 102A, the first portion 107A has a first width 113A in a first plane substantially parallel to the layer 103, the second portion 111A has a second width 117A in a second plane substantially parallel to the layer 103, and the third portion 109A has a third width 115A in a third plane substantially parallel to the layer 103. In one such example, the distance between the third plane and the first conductive element 128 is at least 10% of the length 121A and less than 75% of the length 121A of the conductive via 102A. In other examples, the distance between the third plane and the first conductive element 128 is in the range of 25-60% of the length 121A of the conductive via 102A or 30-55% of the length 121A of the conductive via 102A. In one such example, the third plane is closer to the midpoint of the conductive via 102A than to the conductive element 128 (or the third plane is closer to the midpoint than to the second conductive element 158).

[0035] Figure 1A Widths 113A, 115A, and 117A are depicted as being measured at certain points along length 121A of conductive via 102A, however, in other examples, widths of portions 107A, 109A, and 111A can be measured at points different than those depicted. In one example, width 113A of portion 107A can be measured at or near an interface between conductive via 102A and conductive element 128 in a plane substantially parallel to layer 103, or at another point along length 121A of portion 107A that is closer to conductive element 128 than to a midpoint of conductive via 102A along length 121A of conductive via 102A. Similarly, in one example, a width 117A of portion 111A can be measured at or near an interface between conductive via 102A and conductive element 158, or at another point along portion 111A of length 121A of conductive via 102A that is closer to conductive element 158 ​​than to a midpoint along length 121A of conductive via 102A in a plane substantially parallel to layer 103. A width 115A of portion 109A can be measured at any point along length 121A of conductive via 102A between portions 107A, 111A.

[0036] In one example, the double-sided conductive via can have ends (e.g., a top and a bottom) that have substantially the same width, or the other end of the conductive via can be wider than one end. In one example, the width 113A can be approximately the same as or less than the width 114A of the conductive element 128 coupled to the conductive via 102A, where the width 114A is measured in a plane substantially parallel to the layer 103. In one example, the width 113A is substantially the same as the width 114A. In one such example, increasing the width 113A to be greater than the width 114A of the conductive element below the conductive via 102A may not generally improve the contact between the conductive via 102A and the conductive element 128. However, in some examples, the width 113A at the portion 107A may be greater than the width 114A of the conductive element 128 (but not so large as to interfere with or accidentally contact an adjacent conductive element or an adjacent device, such as a sub-fin of an adjacent nanoribbon transistor). In other examples, width 113A is less than width 114A (while still greater than width 115A).

[0037] Figure 1B An example of an IC structure 100B is shown having a conductive via 102B having one end that is wider than the other end. Figure 1A 1 , the conductive via 102A is shown in FIG. 1 , the conductive via 102B includes a first portion 107B having a width 113B, a second portion 111B having a width 117B, and a third portion 109B having a width 115B, wherein the width 115B is less than the widths 113B and 117B, wherein in a plane substantially parallel to the layer 103 (e.g., in an xy plane, wherein the x-axis is shown at Figure 1B and from Figure 1B The width of a given portion of conductive via 102B is measured at an angle of y, with the y-axis in a direction into and out of the page). Like conductive via 102A, conductive via 102B is located between conductive elements 158, 128 and has a length 121B, where length 121B is the dimension of conductive via 102B in a direction substantially perpendicular to layer 103. In addition to portions 107B and 111B having greater widths than portion 109B, portion 107B also has a greater width than portion 111B. In one example, width 113B is 5-20% greater than width 117B. In another example, width 113B is 10-15% greater than width 117B. Although Figure 1B Width 113B is shown as being greater than width 114B of conductive element 128 , but width 113B can be greater than, equal to, or less than width 114B of conductive element 128 .

[0038] In some examples, one end of the via may be closer to an adjacent device and therefore have a stricter limit on the maximum width of the portion of the via near the device to avoid unintended electrical connection with the adjacent device. In one such example, the wider end (e.g., portion 107B) of the conductive via 102B is further away from the device 106 than the opposite end (e.g., portion 111B) of the conductive via 102B. In one such example, the wider end (e.g., portion 107B) is located on the back side of the IC structure 100B, and the opposite end (e.g., portion 111B) is located on the front side of the IC structure 100B.

[0039] Although Figure 1A and 1B The schematic diagram in shows a conductive via with straight sidewalls, but the conductive via can include one or more substantially straight portions, irregular portions, and / or curved or rounded portions, wherein even substantially straight portions can include irregularities and / or defects so that they are not completely straight. Depending on the processing technology used to form the conductive via, the conductive via can include one or more curved protrusions. For example, due to an isotropic etching process (e.g., via an isotropic wet etching process) used to open or widen the opening at that end, the curved protrusion of the conductive via can be formed, which can result in a curved protruding sidewall in the etched area. The curved protruding sidewall can result in a ridge or protrusion in the resulting conductive via.

[0040] For example, Figure 1C An IC structure 100C is shown having a conductive via 102C that includes a curved protrusion 129 near one end of the conductive via 102C. Figure 1A and 1B 102A and 102B, conductive via 102C includes a first portion 107C having a width 113C, a second portion 111C having a width 117C, and a third portion 109C having a width 115C, wherein width 115C is less than widths 113C and 117C, wherein in a plane substantially parallel to layer 103 (e.g., in an xy plane, wherein the x-axis is shown at Figure 1C and from Figure 1C121C, with the y-axis in a direction into and out of the page). Like conductive vias 102A and 102B, conductive via 102C is located between conductive elements 158, 128 and has a length 121C, where length 121C is a dimension of conductive via 102C in a direction substantially perpendicular to layer 103. In one such example, portion 107C at one end of conductive via 102C includes a curved bulge 129 between conductive element 128 and portion 109C. In one example, curved bulge 129 is closer to conductive element 128 than to a midpoint of conductive via 102C along length 121C of conductive via 102C. In one example, the end of conductive via 102C that is farthest from device 106 includes curved bulge 129. In one such example, the end of the conductive via 102C having the curved protrusion 129 is located at the back side of the IC structure 100C (eg, closer to the back side of the IC structure than the opposite end). Figure 1C Width 113C is shown as being greater than width 114C of conductive element 128 , but width 113C can be greater than, equal to, or less than width 114C of conductive element 128 .

[0041] therefore, Figures 1A-1C The figure shows an example of a conductive via that can be processed using the double-sided via processing technology. Figures 1A-1C The device region 104 through which the conductive vias 102A, 102B, and 102C extend in the example illustrated in FIG. 1 is shown as a single layer, but the conductive vias 102A, 102B, and 102C can extend through one or more layers in the device region or other regions of the IC structure. Figures 1A-1C In the example illustrated in , the material surrounding the conductive vias 102A, 102B, and 102C (whether it comprises a single layer or multiple layers) lacks a bonding interface or seam. Therefore, the conductive vias 102A, 102B, and 102C are each a single via through one or more layers, rather than multiple vias bonded together (e.g., not different vias formed in or on separate substrates that are bonded together).

[0042] Figure 2 and 4 is a flow chart of an exemplary method for processing an IC structure including double-sided conductive vias according to some embodiments. Figure 2 and 4 The exemplary method illustrated in involves forming an opening from a first side and widening a portion of the opening from a second side. Figure 2 An exemplary method 200 is illustrated that involves filling an opening with a conductive material from a first side before widening the opening from a second side. Figure 4An exemplary method 400 is illustrated that involves partially filling the opening with a sacrificial material prior to widening the opening from a second side. Figures 3A-3G According to some embodiments, Figure 2 sectional side views of an exemplary IC structure at various stages in the process of fabricating the exemplary IC structure.

[0043] Figures 5A-5H According to some embodiments, Figure 4 sectional side views of an exemplary IC structure at various stages in the process of fabricating the exemplary IC structure.

[0044] Although Figure 2 and 4 The operations of the method are each illustrated once and in a particular order, but the operations may be performed in any suitable order and repeated as desired. For example, one or more operations may be performed in parallel to process multiple IC structures having one or more conductive vias substantially simultaneously. In another example, the operations may be performed in a different order to reflect the structure of the IC device in which the conductive vias will be implemented.

[0045] in addition, Figure 2 and 4 Exemplary processing methods may include those not specifically shown in Figure 2 and 4 Other operations in the process, such as various cleaning or planarization operations as are known in the art, may be performed. For example, in some embodiments, before, after, or during any of the processes in the methods described herein, the support and various other layers of material subsequently deposited thereon may be cleaned to, for example, remove oxides, surface-bound organic and metallic contaminants, and subsurface contamination. In some embodiments, cleaning may be performed using, for example, chemical solutions such as peroxides, and / or using ultraviolet (UV) radiation in combination with ozone, and / or oxidizing the surface (e.g., using thermal oxidation) and then removing the oxide (e.g., using hydrofluoric acid (HF)). In another example, in the process described herein, the support and various other layers of material subsequently deposited thereon may be cleaned to, for example, remove oxides, surface-bound organic and metallic contaminants, and subsurface contamination. In some embodiments, cleaning may be performed using, for example, chemical solutions such as peroxides, and / or using ultraviolet (UV) radiation in combination with ozone, and / or oxidizing the surface (e.g., using thermal oxidation) and then removing the oxide (e.g., using hydrofluoric acid (HF)). Figure 2 and 4 Before, after, or during any process in the method of the present invention, the intermediate IC structure described herein may be planarized, for example, to remove overburden or excess material. In some embodiments, planarization may be performed using a wet or dry planarization process, for example, the planarization is chemical mechanical planarization (CMP), which may be understood as a process that uses a polishing surface, abrasives, and slurries to remove overburden and planarize the surface.

[0046] Steering Figure 2 , method 200 begins with process 202 of forming an opening in one or more layers on a first side of an IC structure. Figure 3AIC structure 300A illustrates an exemplary result of process 202 . IC structure 300A includes support 308 , insulator material 304 , device 306 , and opening 301 in insulator material 304 .

[0047] The support 308 can be, for example, a substrate, a die, a wafer, or a chip. The support 308 can be, for example, Figure 6 The wafer 1500 may be a die (e.g., Figure 6 The support member 308 may be a semiconductor substrate including a semiconductor material system, the semiconductor material system including, for example, an N-type or P-type material system. In one implementation, the semiconductor substrate may be a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In other implementations, the semiconductor substrate may be formed using alternative materials, which may or may not be combined with silicon, including but not limited to germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, aluminum gallium arsenide, aluminum arsenide, indium aluminum arsenide, aluminum indium antimonide, indium gallium arsenide, gallium nitride, indium gallium nitride, aluminum indium nitride or gallium antimonide or other combinations of III-V materials (i.e., materials from III and V groups of the periodic system), II-VI materials (i.e., materials from II and IV groups of the periodic system) or IV materials (i.e., materials from IV groups of the periodic system). In some embodiments, the substrate may be amorphous. In some embodiments, support 308 may be a printed circuit board (PCB) substrate, a package substrate, an interposer, a wafer, or a die. Although some examples of materials from which support 308 may be formed are described herein, any material that may be used as a foundation upon which an IC structure including double-sided vias as described herein may be built falls within the spirit and scope of the present disclosure.

[0048] Insulator material 304 may include any suitable insulator material, for example, one or more of the materials described above with reference to ILD materials. Device 306 can include transistors and / or other devices, such as those described above with reference to Figures 1A-1C106 of the device. In one example, the opening 301 is a trench (e.g., a via trench or a deep trench). The opening 301 is formed from a first side 310 opposite to a second side 312. In one example, the first side 310 is a front side (e.g., a front side of the IC structure 300A or a front side of a support on which the IC structure is processed), and the second side 312 is a back side (e.g., a back side of the IC structure 300A or a back side of a support on which the IC structure is processed). Any suitable etching technique, such as dry etching (such as, for example, radio frequency (RF) reactive ion etching (RIE) or inductively coupled plasma (ICP) RIE), can be used to form the opening 301. In some embodiments, the etching performed in process 202 may include: anisotropic etching, using an etchant in the form of, for example, a chemically active ionized gas (i.e., plasma), using, for example, bromine (Br) and chloride (Cl) based chemicals. In some embodiments, during etching of process 202, the IC structure may be heated to an elevated temperature, for example, to a temperature between approximately room temperature and 200 degrees Celsius (including all values ​​and ranges therein), to facilitate sufficient volatilization of etching byproducts for removal from the surface.

[0049] Refer again Figure 2 , method 200 may then proceed to process 204 where the opening is filled with a conductive material. Figure 3B 300B illustrates an exemplary result of process 204. IC structure 300B includes opening 301 filled with conductive material 314. Conductive material 314 may include any suitable conductive material (such as any of the conductive materials described above) and may be deposited in process 204 using techniques such as atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), or / and physical vapor deposition (PVD) processes (such as sputtering).

[0050] The method 200 may then proceed to process 206 where the IC structure is flipped over to reveal a second side of the IC structure. Figure 3C 300C illustrates an exemplary result of process 206. Specifically, IC structure 300C is identical to IC structure 300B, but is flipped over so that it can be processed from a second side 312 of IC structure 300C. As described above, in one example, second side 312 can be referred to as a back side of IC structure 300C or a back side of support 308.

[0051] Refer again Figure 2 , method 200 may then proceed to process 208 where material from the second side of the IC structure is removed to reveal conductive material at the bottom of the opening. Figure 3D300D illustrates an exemplary result of process 208. Specifically, support 308 (or at least a portion of support 308 on opening 301) has been removed from the second side of IC structure 300D. In process 208, support 308 may be removed using a suitable thinning / polishing process. After removing support 308, conductive material 314 is exposed at one end of opening 301 (e.g., at the bottom of opening 301).

[0052] Refer again Figure 2 The method 200 may then proceed to process 210 where the conductive material is partially removed (eg, recessed) from the opening from the second side of the IC structure. Figure 3E IC structure 300E illustrates an exemplary result of process 210. Any suitable etching technique, such as the techniques described above for process 202, may be used to recess conductive material 314 in opening 301. In one example, conductive material is partially removed to expose sidewalls at the bottom of opening 301 (e.g., sidewalls of opening 301 proximate second side 312). The extent to which conductive material 314 is recessed can depend on many factors, such as minimizing the risk of shorting to adjacent devices, and may be, for example, between 5-75% of the length of opening 301, where the length of opening 301 is the dimension of opening 301 in a direction substantially perpendicular to support 308. In one example, conductive material 314 is removed from a portion of opening 301 extending from the bottom to 25-60% of the length of the opening or from the bottom to 30-55% of the length of the opening, where in this example, the bottom refers to the side of the opening proximate second side 312. In one example, conductive material 314 is recessed to a point where opening 301 begins to taper or taper increases. In one example, the degree to which the conductive material 314 is recessed in the opening affects what percentage of the opening 301 will be widened in a subsequent process. Thus, in one example, the conductive material 314 is recessed to a point that is sufficient to increase the minimum width of the opening 301 using a subsequent process, but not so far as to interfere with or cause unintended contact with an adjacent device 306. In one such example, the conductive material 314 is recessed from the bottom of the opening 301 to a point that is before or near the adjacent device 306.

[0053] Refer again Figure 2 , the method 200 may then proceed to process 212 where a portion of the opening is widened from the second side. Figure 3FIC structure 300F of FIG. 210 illustrates an exemplary result of process 212. Any suitable etching technique, such as the techniques described above, may be used to widen a portion of opening 301. For example, widening a portion of the opening may involve wet etching or dry etching the sidewalls of the opening exposed by partially removing the conductive material. In one example, a wet etching process selective to conductive material 314 is used to etch insulator material 304 on the sidewalls of opening 301.

[0054] In various examples, before widening a portion of the opening 301, a material may be deposited on a top surface 316 (e.g., a surface of the second side 312) of the insulator material 304 or may not be deposited on the top surface 316 to prevent removal of the insulator material 304 from areas other than the sidewalls of the opening 301. In one example, a material (such as titanium nitride (TiN) or other hard mask material) may be deposited on the surface 316 of the insulator material 304. In one such example, before widening the opening 301, the hard mask material is removed from the sidewalls of the opening 301 (e.g., using a dry etching process or other processing technique for removing the hard mask material from the sidewalls). Thus, in some examples, loss of the insulator material 304 from the surface 316 is prevented without requiring additional photolithography and masking processes. In other examples, a portion of the opening 301 is widened without protecting the surrounding insulator material 304, which may result in some loss of the insulator material 304 from the surface 316.

[0055] Different embodiments can vary as to the extent to which a portion of the opening is widened from the second side 312. For example, the opening 301 can be widened from the second side 312 to form a conductive via having substantially the same width at both ends. In another example, the opening 301 can be widened from the second side 312 so as to be wider or narrower than the opposite end (e.g., the end of the via near the first side 310). In some examples, due to the proximity of the device 306 at the first side 310, widening the opening 301 from the second side 312 can achieve an even wider dimension than can be achieved when patterning from the first side 310. Thus, in one such example, the opening 301 can be widened from the second side 312 to have a significantly wider portion near the end of the second side 312 (similar to Figure 1B Depending on the processing technology used, the shape of the opening 301 may have a curved or rounded profile (similar to Figure 1C conductive via 102C), substantially straight sidewalls (similar to Figure 1A conductive via 102A) or other shapes or contours.

[0056] Refer again Figure 2, method 200 may then proceed to process 214 where the opening is refilled with a conductive material from the second side. Figure 3G The IC structure 300G of FIG. 2 illustrates an exemplary result of process 214. Using any suitable process (such as the techniques described above for process 204), the partially filled opening 301 can be filled with a conductive material 314. The resulting conductive via 302 of the IC structure 300G has a larger width on the second side 312 than conventional vias, resulting in reduced resistance and improved performance. The IC structure 300G can then undergo additional processing, such as to form a metallization layer on the first and / or second side of the IC structure 300G to electrically connect the conductive via 302 to other conductive elements and / or devices.

[0057] Now refer to Figure 4 , method 400 is a flow chart of another method for processing an IC structure with double-sided vias, wherein the via opening is partially filled with a sacrificial material prior to metal deposition. Method 400 begins with process 402 of forming an opening in one or more layers on a first side of the IC structure. Figure 5A The IC structure 500A of FIG. 4 illustrates an exemplary result of the process 402. The IC structure 500A includes a support 508, an insulator material 504, a device 506, and an opening 501 in the insulator material 504. The support 508, the insulator material 504, and the device 506 can be connected to the above-mentioned Figure 3A The support 308, insulator material 304, and device 306 are the same or similar. The opening 501 can be a trench (e.g., a via trench or a deep trench) formed from a first side 510 opposite to a second side 512. In one example, the first side 510 is a front side (e.g., a front side of the IC structure 500A or a front side of a support on which the IC structure is processed), and the second side 512 is a back side (e.g., a back side of the IC structure 500A or a back side of a support on which the IC structure is processed). Any suitable etching technique can be used to form the opening 501, such as the technique described above with reference to process 202.

[0058] The method 400 may then proceed to process 404 where the opening is partially filled with a sacrificial material. Figure 5B4. The IC structure 500B of FIG. 400B illustrates an exemplary result of process 404. The IC structure 500B includes an opening 501 partially filled with a sacrificial material 507. The sacrificial material can be any suitable sacrificial material, such as a carbon-based material (e.g., a carbon-based photoresist) or other sacrificial material, and in process 404, the sacrificial material can be deposited using any suitable processing technique (such as, for example, the processing technique described above for process 204). In one example, the extent to which the opening 501 is filled depends on the portion of the opening 501 that is to be widened from the second side 512. For example, the opening 501 can be filled between 5-75% of the length of the opening 501, where the length of the opening 501 is the dimension of the opening 501 in a direction substantially perpendicular to the support 508. In one example, the opening 501 is filled to 25-60% or 30-55% of the length of the opening 501. In one example, the opening 501 is filled until a point at which the opening 501 begins to taper or a point at which the taper increases. In one example, the degree to which the opening 501 is filled affects what percentage of the opening 501 will be widened in a subsequent process. Thus, in one example, the opening 501 is filled to a point that is large enough to increase the minimum width of the opening 501 using a subsequent process, but not so large as to interfere with or cause unintended contact with an adjacent device 506. In one such example, the opening 501 is filled to a point below or near an adjacent device 506.

[0059] The method 400 may then proceed to process 405 where the partially filled opening is filled with a conductive material over the sacrificial material. Figure 5C IC structure 500C illustrates an exemplary result of process 405. Conductive material 514 may include any suitable conductive material, such as any of the conductive materials described above, and may be deposited in process 405 using any suitable processing technique, such as the processing techniques described above for process 204.

[0060] The method 400 may then proceed to process 406 where the IC structure is flipped over to reveal a second side of the IC structure. Figure 5D IC structure 500D illustrates an exemplary result of process 406. Specifically, IC structure 500D is identical to IC structure 500C, but is flipped over to enable processing of second side 512 of IC structure 500D.

[0061] Refer again Figure 4 The method 400 may then proceed to process 408 where material from the second side of the IC structure is removed to reveal the sacrificial material at the bottom of the opening. Figure 5E4 shows an exemplary result of process 408. Specifically, support 508 (or at least a portion of support 508 on opening 501) has been removed from second side 512 of IC structure 500E. In process 408, support 508 may be removed using a suitable thinning / polishing process. After removing support 508, sacrificial material 507 is exposed at one end of opening 501 (e.g., at the bottom of opening 501).

[0062] Refer again Figure 4 The method 400 may then proceed to process 410 where the sacrificial material is removed from the opening from the second side of the IC structure. Fig. 5F IC structure 500F illustrates an exemplary result of process 410. Any suitable technique may be used to remove the sacrificial material, such as an ashing or etching technique, such as the techniques described above for process 202. In one example, the sacrificial material is removed to expose the sidewalls at the bottom of opening 501 (e.g., at the end of opening 501 proximate second side 512).

[0063] Refer again Figure 4 , the method 400 may then proceed to process 412 where a portion of the opening is widened from the second side. Figure 5G IC structure 500G illustrates an exemplary result of process 412. Widening a portion of opening 501 may involve the same process described above with respect to Figure 2 The same or similar techniques as those described in process 212 of (e.g., any suitable etching technique (such as, the techniques described above) may be used to widen a portion of the opening 501). For example, widening a portion of the opening 501 may involve wet etching or dry etching the sidewalls of the opening 501 exposed by removing the sacrificial material. Prior to widening the opening 501, the exposed surface of the insulator material 504 other than the exposed sidewalls of the opening 501 may be protected (e.g., as described above, using a hard mask material) or remain exposed. In addition, depending on the processing technology used, the shape of the opening 501 after widening may have a curved or rounded profile in the widened portion proximate the second side 512 (similar to Figure 1C conductive via 102C), substantially straight sidewalls (similar to Figure 1A The conductive via 102A and Figure 1B conductive via 102B) or another shape or contour.

[0064] Refer again Figure 4 , the method 400 may then proceed to process 414 where the opening is filled with a conductive material from the second side. Figure 5H4. The IC structure 500H of FIG. 4 illustrates an exemplary result of process 414. Using any suitable process (such as the techniques described above for process 204), the opening 501 can be filled with a conductive material 514. The resulting conductive via 502 of the IC structure 500H has a greater width on the second side 512 than conventional vias, resulting in reduced resistance and improved performance. The IC structure 500H can then undergo additional processing, such as to form a metallization layer on the first and / or second side of the IC structure 500H, thereby electrically connecting the conductive via 502 to other conductive elements and / or devices.

[0065] Thus, method 400 is another method for processing an IC structure with a double-sided via in which a sacrificial material is used. In one example, the sacrificial material can then be removed (e.g., ashed away) after backside polishing to reveal the portion of the via opening that is to be widened. Using a sacrificial material can eliminate the problems associated with recessing the conductive material (e.g., in Figure 2 of method 200).

[0066] Execution of method 200 or 400 may result in several features in the final IC structure that are characteristic of the use of methods 200 and 400. For example, one such feature is illustrated in Figure 1A In the IC structure 100A shown in FIG. 1 , the width 115A of the portion 109A is smaller than the widths 113A and 117A of the portions 107A and 111A, respectively. In another example, the width of the conductive via at the end farther from the adjacent device can be wider than the end closer to the adjacent device. For example, Figure 1B The IC structure 100B shown in FIG. 1 has a width 113B of the portion 107B that is wider than a width 117B of the portion 111B. In another example, the conductive via may have a curved protrusion near the end that is further away from the adjacent device. For example, Figure 1C The IC structure 100C shown in FIG. 1 has a curved protrusion 129. Regardless of the exact width or shape, a conductive via first formed from one side of the IC structure and then widened from the opposite side can have a wider dimension than a conventional via, which can result in reduced resistance and improved performance.

[0067] Figure 61 is a top view of a wafer 1500 and die 1502 that may include one or more IC structures with conductive vias according to any of the embodiments disclosed herein. Wafer 1500 may include semiconductor material and may include one or more die 1502 having IC structures formed on a surface of wafer 1500. Each of die 1502 may be a repeating unit of a semiconductor product including any suitable IC. After processing of the semiconductor product is completed, wafer 1500 may undergo a singulation process in which die 1502 are separated from one another to provide discrete "chips" of semiconductor products. Die 1502 may include Figures 1A-1C One or more IC structures of the IC structures 100A, 100B and / or 100C, Figure 3E-3G or Figure 5E-5H Any of the IC structures shown in or any combination of such IC structures and / or supporting circuits for routing electrical signals to transistors of these IC structures and any other IC components. In some embodiments, wafer 1500 or die 1502 may include memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Multiple of these devices may be combined on a single die 1502. For example, a memory array formed by multiple memory devices may be formed on a chip with a processing device (e.g., Fig.10 The processor 1802 or other logic on the same die 1502 may be configured to store information in a memory device or execute instructions stored in a memory array.

[0068] Figure 7 is a side cross-sectional view of an IC device 1600 that may include one or more IC structures having conductive vias according to any of the embodiments disclosed herein. One or more of the IC devices 1600 may be included in one or more dies 1502. The IC device 1600 may include a device region 1604 that includes one or more IC structures 1602, wherein any of the IC structures 1602 may include any of the IC structures having conductive vias according to the examples disclosed herein, e.g., Figures 1A-1C One or more IC structures of the IC structures 100A, 100B and / or 100C, Figure 3E-3G or Figure 5E-5HDevice region 1604 may also include electrical contacts for gates and S / D contacts of transistors included in device region 1604 .

[0069] By placing one or more interconnect layers (in the device area 1604 Figure 7 1604), electrical signals (such as power and / or input / output (I / O) signals) may be routed to and / or from devices (e.g., transistors) of device region 1604. For example, conductive features of device region 1604 (e.g., gate electrode materials, conductive materials, and conductive materials of IC structure 1602) may be electrically coupled to interconnect structures 1628 of interconnect layers 1606, 1608, and 1610. The one or more interconnect layers 1606, 1608, and 1610 may form a metallization stack (also referred to as an "ILD stack") 1619 of IC device 1600.

[0070] Interconnect structures 1628 may be arranged within interconnect layers 1606, 1608, and 1610 to route electrical signals according to various designs (particularly, the arrangement is not limited to Figure 7 1606, 1608, and 1610 in the specific configuration of the interconnect structure 1628 depicted in FIG. 1606. Figure 7 Although depicted in FIG. 1 , embodiments of the present disclosure include IC structures having more or fewer interconnect layers than depicted.

[0071] In some embodiments, interconnect structure 1628 may include wires 1628a and / or vias 1628b filled with a conductive material such as a metal. One or more of vias 1628b can include double-sided vias according to examples described herein. Wires 1628a may be arranged to route electrical signals in a direction substantially parallel to a plane of a surface of a support on which device region 1604 is formed. For example, from Figure 7 1606, 1608, and 1610. In some embodiments, vias 1628b may electrically couple lines 1628a of different interconnect layers 1606, 1608, and 1610 together.

[0072] Interconnect layers 1606, 1608, and 1610 may include dielectric material 1626 disposed between interconnect structures 1628, such as Figure 7In some embodiments, the dielectric material 1626 disposed between the interconnect structures 1628 in different interconnect layers 1606, 1608, and 1610 may have different compositions; in other embodiments, the composition of the dielectric material 1626 between different interconnect layers 1606, 1608, and 1610 may be the same.

[0073] First interconnect layer 1606 may be formed over device region 1604. In some embodiments, first interconnect layer 1606 may include wires 1628a and / or vias 1628b, as shown. Wires 1628a of first interconnect layer 1606 may be coupled to contacts of device region 1604.

[0074] The second interconnect layer 1608 may be formed over the first interconnect layer 1606. In some embodiments, the second interconnect layer 1608 may include vias 1628b to couple the lines 1628a of the second interconnect layer 1608 with the lines 1628a of the first interconnect layer 1606. Although the lines 1628a and the vias 1628b are structurally delineated with lines within each interconnect layer (e.g., within the second interconnect layer 1608) for clarity, in some embodiments, the lines 1628a and the vias 1628b may be structurally and / or materially continuous (e.g., filled simultaneously during a dual damascene process).

[0075] The third interconnect layer 1610 (and additional interconnect layers, as desired) may be subsequently formed on the second interconnect layer 1608 according to similar techniques and configurations as described in connection with the second interconnect layer 1608 or the first interconnect layer 1606. In some embodiments, the interconnect layers that are "higher" (i.e., further away from the device region 1604) in the metallization stack 1619 in the IC device 1600 may be thicker.

[0076] IC device 1600 may include solder resist material 1634 (e.g., polyimide or a similar material) and one or more conductive contacts 1636 formed on interconnect layers 1606, 1608, and 1610. Figure 7 , the conductive contact 1636 is illustrated as being in the form of a bonding pad. The conductive contact 1636 may be electrically coupled to the interconnect structure 1628 and configured to route electrical signals of the transistor(s) of the device region 1604 to other external devices. For example, a solder joint may be formed on one or more conductive contacts 1636 to mechanically and / or electrically couple a chip including the IC device 1600 to another component (e.g., a circuit board). The IC device 1600 may include additional or alternative structures to route electrical signals from the interconnect layers 1606, 1608, and 1610; for example, the conductive contact 1636 may include other similar features (e.g., pillars) that route electrical signals to external components.

[0077] Figure 8 is a side cross-sectional view of an exemplary IC package 1650 that may include one or more IC structures with conductive vias according to any of the embodiments disclosed herein. In some embodiments, IC package 1650 may be a system-in-package (SiP).

[0078] Package substrate 1652 may be formed of a dielectric material (e.g., ceramic, a laminate film, an epoxy film having filler particles therein, glass, an organic material, an inorganic material, a combination of organic and inorganic materials, an embedded portion formed of different materials, etc.), and may have conductive paths extending through the dielectric material between surface 1672 and surface 1674 or between different locations on surface 1672 and / or between different locations on surface 1674. These conductive paths may be formed using the above-mentioned reference Figure 7 Any form of interconnect 1628 discussed.

[0079] The packaging substrate 1652 may include conductive contacts 1663, which are coupled to conductive paths (not shown) through the packaging substrate 1652, allowing the circuits within the tube core 1656 and / or the inserter 1657 to be electrically coupled to various conductive contacts 1664 in the conductive contacts 1664 (or to devices included in the packaging substrate 1652, not shown).

[0080] IC package 1650 may include interposer 1657 coupled to package substrate 1652 via conductive contacts 1661 of interposer 1657 , first level interconnects 1665 , and conductive contacts 1663 of package substrate 1652 . Figure 8 The first level interconnects 1665 illustrated in FIG. 1 are solder bumps, but any suitable first level interconnects 1665 may be used. In some embodiments, no interposer 1657 may be included in IC package 1650; instead, die 1656 may be coupled directly to conductive contacts 1663 at face 1672 via first level interconnects 1665. More generally, one or more dies 1656 may be coupled to package substrate 1652 via any suitable structure (e.g., a silicon bridge, an organic bridge, one or more waveguides, one or more interposers, wire bonding, etc.).

[0081] IC package 1650 may include one or more dies 1656 coupled to interposer 1657 via conductive contacts 1654 of die 1656, first level interconnects 1658, and conductive contacts 1660 of interposer 1657. Conductive contacts 1660 may be coupled to conductive pathways (not shown) through interposer 1657, allowing circuitry within die 1656 to be electrically coupled to various ones of conductive contacts 1661 (or to other devices included in interposer 1657, not shown). Figure 8 The first level interconnect 1658 illustrated in FIG is a solder bump, but any suitable first level interconnect 1658 may be used. As used herein, a "conductive contact" may refer to a portion of a conductive material (e.g., metal) that serves as an interface between different components; a conductive contact may be recessed into, flush with, or extend away from a surface of a component, and may take any suitable form (e.g., a conductive pad or socket).

[0082] In some embodiments, an underfill material 1666 may be disposed around the first level interconnect 1665 between the package substrate 1652 and the interposer 1657, and a mold compound 1668 may be disposed around the die 1656 and the interposer 1657 and in contact with the package substrate 1652. In some embodiments, the underfill material 1666 may be the same as the mold compound 1668. An exemplary material that may be used for the underfill material 1666 and the mold compound 1668 is an epoxy molding material as desired. The second level interconnect 1670 may be coupled to the conductive contact 1664. Figure 8 The second level interconnects 1670 illustrated in FIG. 1 are solder balls (e.g., for a ball grid array arrangement), but any suitable second level interconnects 1670 may be used (e.g., pins in a pin grid array arrangement or contacts in a contact grid array arrangement). The second level interconnects 1670 may be used to couple the IC package 1650 to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as is known in the art and as described below with reference to Fig. 9 discussed.

[0083] Die 1656 may take the form of any of the embodiments of die 1502 discussed herein (e.g., may include any of the embodiments of IC device 1600). In embodiments where IC package 1650 includes multiple dies 1656, IC package 1650 may be referred to as a multi-chip package (MCP). Die 1656 may include circuitry to perform any desired functionality. For example, one or more of die 1656 may be logic dies (e.g., silicon-based dies), and one or more of die 1656 may be memory dies (e.g., high bandwidth memory).

[0084] Although Figure 8 The IC package 1650 illustrated in FIG. 1 is a flip chip package, but other package architectures may be used. For example, the IC package 1650 may be a ball grid array (BGA) package, such as an embedded wafer level ball grid array (eWLB) package. In another example, the IC package 1650 may be a wafer level chip scale package (WLCSP) or a panel fan-out (FO) package. Although two dies 1656 are illustrated in FIG. Figure 8 1650, but IC package 1650 may include any desired number of dies 1656. IC package 1650 may include additional passive components, such as surface mount resistors, capacitors, and inductors disposed on first side 1672 or second side 1674 of package substrate 1652 or disposed on either side of interposer 1657. More generally, IC package 1650 may include any other active or passive components known in the art.

[0085] Fig. 9 1700 is a side cross-sectional view of an IC device assembly 1700 according to any of the embodiments disclosed herein, the IC device assembly 1700 may include one or more IC packages or other electronic components (e.g., dies) that include one or more IC structures having conductive vias. The IC device assembly 1700 includes a number of components mounted on a circuit board 1702 (the circuit board 1702 may be, for example, a motherboard). The IC device assembly 1700 includes components mounted on a first side 1740 of the circuit board 1702 and an opposing second side 1742 of the circuit board 1702; typically, the components may be mounted on one or both sides 1740 and 1742. Any of the IC packages discussed below with reference to the IC device assembly 1700 may be employed with reference to the above. Figure 7 The form of any of the embodiments of the IC package 1650 discussed (eg, may include one or more IC structures having conductive vias according to the examples described herein).

[0086] In some embodiments, circuit board 1702 may be a PCB that includes multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals between components coupled to circuit board 1702 (optionally in conjunction with other metal layers). In other embodiments, circuit board 1702 may be a non-PCB substrate.

[0087] Fig. 9 The IC device assembly 1700 illustrated in FIG. 1 includes an interposer package structure 1736 coupled to a first side 1740 of a circuit board 1702 via a coupling component 1716. The coupling component 1716 may electrically and mechanically couple the interposer package structure 1736 to the circuit board 1702 and may include solder balls (e.g., Fig. 9 ), male and female portions of a socket, adhesive, bottom fill material, and / or any other suitable electrical and / or mechanical coupling structure.

[0088] Package-on-interposer structure 1736 may include IC package 1720 coupled to package interposer 1704 via coupling component 1718. Coupling component 1718 may take any suitable form for the application, such as those discussed above with reference to coupling component 1716. Although a single IC package 1720 is shown in Fig. 9 1704; in fact, additional interposers may be coupled to package interposer 1704. Package interposer 1704 may provide an intermediate substrate for bridging circuit board 1702 and IC package 1720. IC package 1720 may be or include, for example, a die ( Figure 6 1502), IC devices (e.g., Figure 7 IC device 1600) or any other suitable component. Typically, package inserter 1704 can expand connections to a wider spacing or reroute connections to different connections. For example, package inserter 1704 can couple IC package 1720 (e.g., die) to a set of BGA conductive contacts for coupling to coupling component 1716 of circuit board 1702. Fig. 9 , IC package 1720 and circuit board 1702 are attached to opposite sides of package interposer 1704; in other embodiments, IC package 1720 and circuit board 1702 may be attached to the same side of package interposer 1704. In some embodiments, three or more components may be interconnected via package interposer 1704.

[0089] In some embodiments, the package inserter 1704 may be formed as a PCB, which includes multiple metal layers separated from each other by dielectric material layers and interconnected by conductive vias. In some embodiments, the package inserter 1704 may be formed of epoxy, glass fiber reinforced epoxy, epoxy with inorganic filler, ceramic material, or polymer material (such as polyimide). In some embodiments, the package inserter 1704 may be formed of alternative rigid or flexible materials, which may include the same materials described above for semiconductor substrates, such as silicon, germanium, and other III-V and IV materials. The package inserter 1704 may include metal lines 1710 and vias 1708, including but not limited to through silicon vias (TSVs) 1706. Vias 1706 and 1708 may be according to the examples described herein. The package inserter 1704 may also include embedded devices 1714, including both passive devices and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices (such as RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices) may also be formed on the package interposer 1704. The package-on-interposer structure 1736 may take the form of any package-on-interposer structure known in the art.

[0090] IC device assembly 1700 may include an IC package 1724 coupled to first side 1740 of circuit board 1702 via coupling component 1722. Coupling component 1722 may take the form of any of the embodiments discussed above with reference to coupling component 1716, and IC package 1724 may take the form of any of the embodiments discussed above with reference to IC package 1720.

[0091] Fig. 9 1700 includes a package-on-package structure 1734 coupled to a second side 1742 of a circuit board 1702 via a coupling component 1728. The package-on-package structure 1734 may include an IC package 1726 and an IC package 1732 coupled together via a coupling component 1730 such that the IC package 1726 is disposed between the circuit board 1702 and the IC package 1732. The coupling components 1728 and 1730 may take the form of any of the embodiments of the coupling component 1716 discussed above, and the IC packages 1726 and 1732 may take the form of any of the embodiments of the IC package 1720 discussed above. The package-on-package structure 1734 may be configured according to any of the package-on-package structures known in the art.

[0092] Fig.10 1 is a block diagram of an exemplary electrical device 1800 that may include one or more IC structures with conductive vias according to any of the embodiments disclosed herein. For example, any suitable component of the components of the electrical device 1800 may include one or more of the IC device assembly 1700, IC package 1650, IC structure 1600, or die 1502 disclosed herein. Many components are described in detail in detail. Fig.10 1800, but any one or more of these components may be omitted or doubled as required by the application. In some embodiments, some or all of the components included in the electrical device 1800 may be attached to one or more motherboards. In some embodiments, some or all of these components are processed onto a single system-on-chip (SoC) die.

[0093] Additionally, in various embodiments, the electrical device 1800 may not include Fig.10 1800, but the electrical device 1800 may include interface circuitry for coupling to the one or more components. For example, the electrical device 1800 may not include the display device 1806, but may include display device interface circuitry (e.g., connectors and drive circuitry) to which the display device 1806 may be coupled. In another set of examples, the electrical device 1800 may not include the audio input device 1824 or the audio output device 1808, but may include audio input or output device interface circuitry (e.g., connectors and support circuitry) to which the audio input device 1824 or the audio output device 1808 may be coupled.

[0094] The electrical device 1800 may include a processing device 1802 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that can be stored in registers and / or memory. The processing device 1802 may include one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (special processors that execute encryption algorithms in hardware), server processors, or any other suitable processing devices. The electrical device 1800 may include a memory 1804, which may itself include one or more memory devices, such as volatile memory (e.g., dynamic RAM (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard drive. In some embodiments, the memory 1804 may include a memory that shares a die with the processing device 1802. Such a memory may be used as a cache memory and may include embedded dynamic RAM (eDRAM) or spin transfer torque magnetic RAM (STT-MRAM).

[0095] In some embodiments, the electrical device 1800 may include a communication chip 1812 (e.g., one or more communication chips). For example, the communication chip 1812 may be configured to manage wireless communications for transferring data to and from the electrical device 1800. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transmit data through a non-solid medium using modulated electromagnetic radiation. The term does not mean that the associated devices do not contain any wires, but in some embodiments, they may not contain any wires.

[0096] The communication chip 1812 may implement any of a number of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards (including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment)), Long Term Evolution (LTE) projects and any modifications, updates and / or revisions (e.g., Advanced LTE projects, Ultra Mobile Broadband (UMB) projects (also known as "3GPP2"), etc.). IEEE 802.16-compatible broadband wireless access (BWA) networks are commonly referred to as WiMAX networks (an acronym standing for Worldwide Interoperability for Microwave Access), which is a certification mark for products that have passed conformance and interoperability testing of the IEEE 802.16 standards. The communication chip 1812 may operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 1812 may operate according to Enhanced Data GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1812 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO) and its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and higher. In other embodiments, the communication chip 1812 may operate according to other wireless protocols. The electrical device 1800 may include an antenna 1822 to facilitate wireless communications and / or receive other wireless communications (such as AM or FM radio transmissions).

[0097] In some embodiments, the communication chip 1812 may manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 1812 may include multiple communication chips. For example, the first communication chip 1812 may be dedicated to short-range wireless communications (such as Wi-Fi or Bluetooth), and the second communication chip 1812 may be dedicated to long-range wireless communications (such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO or other). In some embodiments, the first communication chip 1812 may be dedicated to wireless communications, and the second communication chip 1812 may be dedicated to wired communications.

[0098] The electrical device 1800 may include a battery / power circuit 1814. The battery / power circuit 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuits for coupling components of the electrical device 1800 to an energy source separate from the electrical device 1800 (e.g., AC line power).

[0099] Electrical device 1800 may include display device 1806 (or corresponding interface circuitry, as discussed above). Display device 1806 may include any visual indicator, such as a heads-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0100] The electrical device 1800 may include an audio output device 1808 (or corresponding interface circuitry, as discussed above). The audio output device 1808 may include any device that produces an audible indicator, such as a speaker, headphones, or earbuds.

[0101] The electrical device 1800 may include an audio input device 1824 (or corresponding interface circuitry, as discussed above). The audio input device 1824 may include any device that produces a signal representative of sound, such as a microphone, a microphone array, or a digital instrument (e.g., an instrument with a Musical Instrument Digital Interface (MIDI) output).

[0102] The electrical device 1800 may include a GPS device 1818 (or corresponding interface circuitry, as discussed above). The GPS device 1818 may communicate with a satellite-based system and may receive the location of the electrical device 1800, as is known in the art.

[0103] The electrical device 1800 may include another output device 1810 (or corresponding interface circuitry, as discussed above). Examples of the other output device 1810 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or another storage device.

[0104] The electrical device 1800 may include another input device 1820 (or a corresponding interface circuit, as discussed above). Examples of the other input device 1820 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device (such as a mouse, a stylus, a touch pad), a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0105] The electrical device 1800 may have any desired form factor, such as a handheld or mobile electrical device (e.g., a cellular phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop electrical device, a server device or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electrical device. In some embodiments, the electrical device 1800 may be any other electronic device that processes data.

[0106] The following paragraphs provide various examples of the embodiments disclosed herein.

[0107] Example 1 provides an IC structure, the IC structure comprising: a first layer, comprising a first conductive element (e.g., a conductive via, a conductive contact, or other conductive element); a second layer, located on the first layer, the second layer comprising a second conductive element; and a third layer, located between the first layer and the second layer. The third layer comprises a conductive interconnect (e.g., a via) between the first conductive element and the second conductive element. The conductive interconnect comprises: a first portion having a first width in a first plane substantially parallel to the first layer; a second portion having a second width in a second plane substantially parallel to the first layer; and a third portion having a third width in a third plane substantially parallel to the first layer, wherein the third portion is located between the first portion and the second portion, and the third width is less than the first width and the second width.

[0108] Example 2 provides the IC structure of Example 1, wherein the conductive interconnect tapers from the first portion toward the third portion.

[0109] Example 3 provides the IC structure of Example 1 or 2, wherein the conductive interconnect tapers from the second portion toward the third portion.

[0110] Example 4 provides the IC structure of any of Examples 1-3, wherein the conductive interconnect includes a curved protrusion (eg, a bump or ridge) between the first conductive element and the third portion.

[0111] Example 5 provides the IC structure of any of Examples 1-4, wherein the first width is greater than the second width.

[0112] Example 6 provides an IC structure as described in any of Examples 1-5, wherein the distance between the third plane and the first conductive element is at least 10% of the length of the conductive interconnect, wherein the length of the conductive interconnect is a dimension of the conductive interconnect in a direction substantially perpendicular to the first layer.

[0113] Example 7 provides the IC structure of any of Examples 1-6, wherein a distance between the third plane and the first conductive element is less than 75% of a length of the conductive via.

[0114] Example 8 provides the IC structure of any of Examples 1-7, wherein the conductive interconnect includes a midpoint between the first conductive element and the second conductive element, and the third plane is closer to the midpoint of the conductive interconnect than to the first conductive element and the second conductive element.

[0115] Example 9 provides an IC structure, the IC structure comprising: a first layer including a first conductive interconnect; a second layer located on the first layer, the second layer including a second conductive interconnect; and a conductive via located between the first conductive interconnect and the second conductive interconnect. The conductive via comprises: a bottom portion having a first width in a first plane substantially parallel to the first layer; a top portion having a second width in a second plane substantially parallel to the first layer; and a third portion having a third width in a third plane substantially parallel to the first layer, wherein the third portion is located between the top portion and the bottom portion, and the third width is less than the first width and the second width.

[0116] Example 10 provides the IC structure of Example 9, wherein the conductive via tapers from the bottom portion toward the third portion.

[0117] Example 11 provides the IC structure of Example 9 or 10, wherein the conductive via tapers from the top portion toward the third portion.

[0118] Example 12 provides the IC structure of any of Examples 9-11, wherein the bottom portion includes a curved protrusion.

[0119] Example 13 provides the IC structure of any of Examples 9-12, wherein the first width is greater than the second width.

[0120] Example 14 provides an IC structure as described in any of Examples 9-13, wherein the distance between the third plane and the first conductive interconnect is at least 10% of the length of the conductive via, and wherein the length of the conductive via is a dimension of the conductive via in a direction substantially perpendicular to the first layer.

[0121] Example 15 provides the IC structure of any of Examples 9-14, wherein a distance between the third plane and the first conductive interconnect is less than 75% of a length of the conductive via.

[0122] Example 16 provides the IC structure of any of Examples 9-15, wherein the conductive via includes a midpoint between the first conductive element and the second conductive element, and the third plane is closer to the midpoint of the conductive via than to the first conductive element and the second conductive element.

[0123] Example 17 provides the IC structure of any of Examples 1-16, wherein the IC structure includes a central processing unit, or is a portion of a central processing unit.

[0124] Example 18 provides the IC structure of any of Examples 1-17, wherein the IC structure includes a memory device or is a portion of a memory device.

[0125] Example 19 provides the IC structure of any of Examples 1-18, wherein the IC structure includes a logic circuit or is a portion of a logic circuit.

[0126] Example 20 provides the IC structure of any of Examples 1-19, wherein the IC structure includes, or is a portion of, an input / output circuit.

[0127] Example 21 provides the IC structure of any of Examples 1-20, wherein the IC structure includes, or is a portion of, a field programmable gate array transceiver.

[0128] Example 22 provides the IC structure of any of Examples 1-21, wherein the IC structure includes, or is a portion of, field programmable gate array logic.

[0129] Example 23 provides the IC structure of any of Examples 1-22, wherein the IC structure includes, or is part of, a power delivery circuit.

[0130] Example 24 provides an IC package, the IC package comprising: a package substrate including a first conductive contact; and an IC die. The IC die comprises: a first layer including a first conductive element coupled to the first conductive contact; a second layer located on the first layer, the second layer including a second conductive element; and a conductive via located between the first conductive element and the second conductive element, wherein the conductive via is wider at both ends than between the two ends of the conductive via.

[0131] Example 25 provides the IC package of Example 24, wherein the conductive via tapers from both ends of the conductive via toward a portion between the two ends.

[0132] Example 26 provides the IC package of Example 24 or 25, wherein the conductive via includes a curved protrusion at one of the two ends.

[0133] Example 27 provides an IC package as described in any of Examples 24-26, wherein both ends of the conductive via include a first end and a second end, wherein the first end is closer to the first conductive contact than the second end, and wherein the first end is wider than the second end.

[0134] Example 28 provides an IC package as described in any of Examples 24-27, wherein the conductive via includes a midpoint between the two ends, and wherein a portion between the two ends of the conductive via that is narrower than the two ends of the conductive via is closer to the midpoint than to the two ends of the conductive via.

[0135] Example 29 provides an IC package, comprising: an IC die including the IC structure as described in any of Examples 1-23; and another IC component coupled to the IC die.

[0136] Example 30 provides the IC package of Example 29, wherein the other IC component includes a package substrate.

[0137] Example 31 provides the IC package of Example 29, wherein the other IC component includes an interposer.

[0138] Example 32 provides the IC package of Example 29, wherein the other IC component includes another IC die.

[0139] Example 33 provides a computing device comprising a carrier substrate and an IC structure coupled to the carrier substrate, wherein the IC structure is the IC structure as described in any one of Examples 1-23, or the IC structure is included in an IC package as described in any one of Examples 24-32.

[0140] Example 34 provides the computing device of Example 33, wherein the computing device is a wearable or handheld computing device.

[0141] Example 35 provides a computing device as described in Example 33 or 34, wherein the computing device further includes one or more communication chips.

[0142] Example 36 provides a computing device as described in any of Examples 33-35, wherein the computing device further comprises an antenna.

[0143] Example 37 provides the computing device of any of Examples 33-36, wherein the carrier substrate is a motherboard.

[0144] Example 38 provides a method of processing an IC structure, the method comprising: forming an opening (e.g., a via trench) in one or more layers on a first side (e.g., on a front side) of the IC structure; at least partially filling the opening with a first material (e.g., partially filling the opening with a sacrificial material or filling the opening with a conductive material); flipping the IC structure to expose a second side (e.g., a back side) of the IC structure; and removing material from the second side of the substrate to reveal the first material at a bottom of the opening. The method involves: at least partially removing the first material from the opening from the second side (e.g., removing the sacrificial material or partially recessing the conductive material); widening a portion of the opening from the second side; and filling the opening with a conductive material from the second side.

[0145] Example 39 provides a method as described in method 38, wherein widening a portion of an opening includes widening a portion of the opening at a bottom of the opening or near the bottom of the opening (e.g., near the second side) to a width greater than a second portion of the opening at a top of the opening or near the top of the opening (e.g., near the first side).

[0146] Example 40 provides the method of Example 38 or 39, wherein at least partially removing the first material from the bottom of the opening comprises removing the first material from a portion of the opening extending from the bottom to 5-75% of the length of the opening.

[0147] Example 41 provides the method of any of Examples 38-40, wherein removing material from the second side includes polishing the second side to reveal the first material at a bottom of the opening.

[0148] Example 42 provides a method as in any of Examples 38-41, wherein widening a portion of the opening comprises wet etching or dry etching a sidewall of the opening exposed by at least partially removing the first material.

[0149] Example 43 provides a method as in any of Examples 38-42, further comprising depositing a hard mask material on the second side before wet etching or dry etching the sidewalls.

[0150] Example 44 provides a method as in any of Examples 38-43, wherein the first material comprises a conductive material (such as, Figure 2 ), and wherein at least partially filling the opening with the first material includes filling the opening with a conductive material.

[0151] Example 45 provides the method of Example 44, wherein at least partially removing the first material from the bottom of the opening comprises dry etching the conductive material from the bottom of the via trench.

[0152] Example 46 provides the method of any of Examples 38-43, wherein at least partially filling the opening with the first material includes partially filling the opening with a sacrificial material (such as, for example, Figure 4 400).

[0153] Example 47 provides a method as described in Example 46, wherein the sacrificial material includes a carbon-based material.

[0154] Example 48 provides the method of Example 46 or 47, further comprising: filling the partially filled via trench with a conductive material on the sacrificial material.

[0155] Example 49 provides the method of any of Examples 46-48, wherein at least partially removing the first material from the opening comprises removing the first material using an ashing process.

[0156] Example 50 provides the method of any one of Examples 38-49, wherein the IC structure is the IC structure of any one of Examples 1-23.

[0157] The above description of the illustrated implementation of the present disclosure (including the content described in the summary) is not intended to be exhaustive or to limit the present disclosure to the precise form disclosed. Although specific implementations and examples of the present disclosure are described herein for illustration purposes, as will be appreciated by those skilled in the relevant art, various equivalent modifications are possible within the scope of the present disclosure. In view of the above detailed description, these modifications may be made to the present disclosure.

Claims

1. An integrated circuit (IC) structure, comprising: A first layer including a first conductive element; a second layer, located on the first layer, the second layer comprising a second conductive element; and A third layer is located between the first layer and the second layer, the third layer includes a conductive interconnection between the first conductive element and the second conductive element, the conductive interconnection includes: a first portion having a first width in a first plane substantially parallel to the first layer, a second portion having a second width in a second plane substantially parallel to the first layer, and A third portion has a third width in a third plane substantially parallel to the first layer, wherein the third portion is located between the first portion and the second portion, and the third width is smaller than the first width and the second width.

2. The IC structure of claim 1, wherein: The conductive interconnect tapers from the first portion toward the third portion.

3. The IC structure of claim 2, wherein: The conductive interconnect tapers from the second portion toward the third portion.

4. The IC structure of claim 1, wherein: The conductive interconnect includes a curved protrusion between the first conductive element and the third portion.

5. The IC structure of claim 1, wherein: The first width is greater than the second width.

6. The IC structure of any one of claims 1 to 5, wherein: The distance between the third plane and the first conductive element is at least 10% of the length of the conductive interconnect, Wherein the length of the conductive interconnect is a dimension of the conductive interconnect in a direction substantially perpendicular to the first layer.

7. The IC structure of claim 6, wherein: The distance between the third plane and the first conductive element is less than 75% of the length of the conductive interconnect.

8. The IC structure of any one of claims 1 to 5, wherein: The conductive interconnect includes a midpoint between the first conductive element and the second conductive element; and The third plane is closer to the midpoint of the conductive interconnect than to the first conductive element and the second conductive element.

9. An integrated circuit (IC) structure comprising: a first layer including a first conductive interconnect; a second layer disposed on the first layer, the second layer comprising a second conductive interconnect; and A conductive via, located between the first conductive interconnect and the second conductive interconnect, the conductive via comprising: a bottom portion having a first width in a first plane substantially parallel to the first layer, a top portion having a second width in a second plane substantially parallel to the first layer, and A third portion has a third width in a third plane substantially parallel to the first layer, wherein the third portion is located between the top portion and the bottom portion, and the third width is smaller than the first width and the second width.

10. The IC structure of claim 9, wherein: The conductive via tapers from the bottom portion toward the third portion.

11. The IC structure of claim 10, wherein: The conductive via tapers from the top portion toward the third portion.

12. The IC structure of claim 9, wherein: The bottom portion includes a curved convex portion.

13. The IC structure of any one of claims 9 to 12, wherein: The first width is greater than the second width.

14. The IC structure of claim 9, wherein: The distance between the third plane and the first conductive interconnect is at least 10% of the length of the conductive via, Wherein the length of the conductive via is a dimension of the conductive via in a direction substantially perpendicular to the first layer.

15. The IC structure of claim 14, wherein: The distance between the third plane and the first conductive interconnect is less than 75% of the length of the conductive via.

16. An integrated circuit (IC) package, comprising: a package substrate including a first conductive contact; and IC die, including: a first layer comprising a first conductive element coupled to the first conductive contact, a second layer disposed on the first layer, the second layer comprising a second conductive element, and A conductive via is located between the first conductive element and the second conductive element, wherein the conductive via is wider at both ends than a portion between the two ends of the conductive via.

17. The IC package of claim 16, wherein: The conductive via gradually tapers from both ends of the conductive via toward a portion between the two ends.

18. The IC package of claim 16, wherein: The conductive via includes a bent protruding portion at one of the two ends.

19. The IC package of claim 16, wherein: The two ends of the conductive via include a first end and a second end, wherein the first end is closer to the first conductive contact than the second end; and The first end is wider than the second end.

20. The IC package of any one of claims 16 to 19, wherein: The conductive via includes a midpoint between two ends; and A portion between the two ends of the conductive via, which is narrower than the two ends of the conductive via, is closer to the midpoint than to the two ends of the conductive via.

21. A method of processing an integrated circuit (IC) structure, the method comprising: forming a via trench in one or more layers on a first side of the substrate; at least partially filling the via trench with a material; flipping the substrate to expose a second side of the substrate; removing another material from the second side of the substrate to reveal the material at the bottom of the via trench; removing the material from the via trench at least partially from the second side; widening a portion of the via trench from the second side; and The via trench is filled with a conductive material from the second side.

22. The method of claim 21, wherein: Widening a portion of the via trench includes widening a portion of the via trench at or near the bottom to a greater width than a second portion of the via trench at or near the top of the via trench.

23. The method of claim 21 or 22, wherein: At least partially removing the material from the bottom of the via trench includes removing the material from a portion of the via trench extending from the bottom to 5-75% of the length of the via trench.

24. The method of claim 21 or 22, wherein: Removing another material from the second side of the substrate includes polishing the second side of the substrate to reveal the material at the bottom of the via trench.

25. The method of claim 21 or 22, wherein: Widening a portion of the via trench includes wet etching or dry etching a sidewall of the via trench exposed by at least partially removing the material.

Images