Semiconductor test structure and test method thereof

Abstract

The invention provides a semiconductor test structure and a test method thereof. The semiconductor test structure is arranged on a scribing channel of a wafer, and comprises a transistor which comprises a substrate, a source electrode, a drain electrode and a grid electrode; the electric fuse comprises a first end and a second end; wherein the source electrode is electrically connected to the first bonding pad through a first metal wire, the second end of the electric fuse is electrically connected to the second bonding pad through a second metal wire, the drain electrode, the substrate and the first end of the electric fuse are electrically connected to the third bonding pad through corresponding third metal wires, and the grid electrode is electrically connected to the fourth bonding pad through a fourth metal wire. Voltage is applied to the first bonding pad, the second bonding pad, the third bonding pad and the fourth bonding pad by adopting a preset rule so as to test the resistance of the electric fuse and the performance of the transistor. According to the technical scheme, the resistance of the electric fuse and the performance of the transistor can be simultaneously monitored in the line in the wafer manufacturing process, the process is rapidly adjusted, and the flexibility of the process is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a semiconductor test structure and a test method thereof. Background Art

[0002] Polysilicon electric fuses (Poly Fuse) are small-density embedded one-time programmable components and are widely used in integrated circuits. According to the electromigration theory, electric fuse technology stores information by whether the electric fuse is blown by current. The resistance of polysilicon electric fuses is very small before they are blown. After continuous large current blows, the resistance can be regarded as infinite, and the broken state of the electric fuse will be permanently maintained. Electric fuse technology has been widely used in redundant circuits to improve chip failure problems or chip numbering, basic code of equipment, etc., to replace small-capacity one-time programmable memory.

[0003] As for the performance verification of Fuse Programming, wafer testing (CP) is usually performed after wafer manufacturing is completed, which is often time-consuming and inflexible. Therefore, how to optimize the Fuse testing method and save testing time is a problem that needs to be solved at present. Summary of the invention

[0004] The technical problem to be solved by the present invention is how to optimize the electric fuse testing method and save testing time, and to provide a semiconductor testing structure and a testing method thereof.

[0005] In order to solve the above problems, the present invention provides a semiconductor test structure, which is arranged on a dicing path of a wafer, and includes: a transistor, including a substrate, a source, a drain and a gate; an electric fuse, including a first end and a second end; wherein the source is electrically connected to a first pad through a first metal wire, the second end of the electric fuse is electrically connected to a second pad through a second metal wire, the drain, the substrate and the first end of the electric fuse are electrically connected to a third pad through corresponding third metal wires, respectively, and the gate is electrically connected to a fourth pad through a fourth metal wire. By applying voltage to the first pad, the second pad, the third pad and the fourth pad using preset rules, it is possible to test the resistance of the electric fuse and test the performance of the transistor.

[0006] In order to solve the above problems, the present invention provides a semiconductor testing method, comprising the following steps: providing a semiconductor testing structure, wherein the semiconductor testing structure adopts the semiconductor testing structure described in the present invention; applying voltage to the first pad, the second pad, the third pad, and the fourth pad using preset rules to test the resistance of the electric fuse and test the performance of the transistor.

[0007] The above technical solution can realize in-line monitoring of the resistance of the electric fuse and the performance of the transistor during wafer manufacturing by setting the semiconductor test structure on the wafer dicing path and connecting the electric fuse and the transistor to the pads respectively, so as to quickly adjust the process and improve the flexibility of the process. By setting multiple pads to split the burning circuit and separate the electric fuse from the transistor, it is convenient to control variables, test the performance of each component separately by structure, and improve the flexibility and accuracy of the test. The semiconductor test structure short-circuits the drain, substrate and the first end of the electric fuse to the same pad, reduces the number of pads in the semiconductor test, optimizes the circuit layout of the semiconductor test structure, and then reduces the area of ​​the semiconductor test structure, saving wafer space.

[0008] It should be understood that the above general description and the detailed description below are exemplary and explanatory only and cannot limit the present invention. The techniques, methods and devices known to ordinary technicians in the relevant field may not be discussed in detail, but where appropriate, the techniques, methods and devices should be considered as part of the authorization specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following is a brief introduction to the drawings required for the description of the specific embodiments. Obviously, the drawings described below are only some specific embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0010] Figure 1 It is a structural schematic diagram of an embodiment of the semiconductor test structure of the present invention.

[0011] Figure 2 The figure is a flowchart of one embodiment of the semiconductor testing method of the present invention. DETAILED DESCRIPTION

[0012] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0013] Since the performance test of the electric fuse programming is usually conducted during wafer testing after wafer manufacturing is completed, it cannot be monitored in real time, and the lag in adjusting the process is strong. Therefore, the present application proposes a semiconductor test structure, which is arranged on the scribe lane of the wafer, and can realize inline monitoring during the wafer manufacturing process, thereby quickly adjusting the process, and the flexibility is greatly improved.

[0014] See also Figure 1 , which is a schematic diagram of the structure of an embodiment of the semiconductor test structure of the present invention. The semiconductor test structure is arranged on a wafer dicing road, such as Figure 1 As shown, the semiconductor test structure includes: a transistor 11 and an electric fuse 12. The transistor 11 includes a substrate 111, a source 112, a drain 113 and a gate 114. The electric fuse 12 includes a first end 121 and a second end 122. The source 112 is electrically connected to a first pad 141 through a first metal line 131, the second end 122 of the electric fuse 12 is electrically connected to a second pad 142 through a second metal line 132, the drain 113, the substrate 111 and the first end 121 of the electric fuse 12 are electrically connected to a third pad 143 through corresponding third metal lines 133, respectively, and the gate 114 is electrically connected to a fourth pad 144 through a fourth metal line 134. Voltages are applied to the first pad 141, the second pad 142, the third pad 143 and the fourth pad 144 using a preset rule to test the resistance of the electric fuse 12 and the performance of the transistor 11.

[0015] The above technical solution can realize inline monitoring of the resistance of the electric fuse and the performance of the transistor in the wafer manufacturing process by setting the semiconductor test structure on the wafer dicing path and connecting the electric fuse and the transistor to the pads respectively, so as to quickly adjust the process and improve the flexibility of the process. By setting multiple pads to split the burning circuit and separate the electric fuse from the transistor, it is convenient to control variables, test the performance of each component separately by structure, and improve the flexibility and accuracy of the test. The semiconductor test structure short-circuits the drain, substrate and the first end of the electric fuse to the same pad, reduces the number of pads in the semiconductor test, optimizes the circuit layout of the semiconductor test structure, and then reduces the area of ​​the semiconductor test structure, saving wafer space.

[0016] In some embodiments, the preset rules include: before programming, applying a test voltage to the second pad 142 and the third pad 143 to test the resistance of the electric fuse 12, and applying a test voltage to the first pad 141, the third pad 143 and the fourth pad 144 to test the performance of the transistor 11; and / or after programming, applying a test voltage to the second pad 142 and the third pad 143 to test the resistance of the electric fuse 12, and applying a test voltage to the first pad 141, the third pad 143 and the fourth pad 144 to test the performance of the transistor 11.

[0017] In some embodiments, the electric fuse 12 reaches a predetermined resistance state after programming. The predetermined resistance state is to set the required resistance value or resistance shape according to the programming purpose. In this embodiment, the predetermined resistance state is a preset resistance value; a test voltage is applied to the first pad 141, the second pad 142 and the fourth pad 144 to allow a predetermined current to pass through the electric fuse 12, so that self-aligned silicide electromigration or silicon melting occurs inside the electric fuse 12, and the resistance value of the electric fuse 12 is increased. The electric fuse 12 is burned until the resistance value of the electric fuse 12 reaches the preset resistance value, thereby writing information on the electric fuse 12 (i.e., programming). Specifically, the resistance state of the electric fuse 12 before programming is used as information "0", and the resistance state of the electric fuse 12 after programming is used as information "1".

[0018] In some embodiments, the first metal line 131 , the second metal line 132 , the third metal line 133 , and the fourth metal line 134 are formed by patterning the same metal layer.

[0019] In this embodiment, an active region is defined in the substrate 111, the source 112 and the drain 113 are formed in the active region, the gate 114 is located on the surface of the active region, and the source 112 and the drain 113 are located on both sides of the gate 114. A gate dielectric layer is also formed between the gate 114 and the active region.

[0020] In this embodiment, the material of the electrical fuse 12 is polysilicon.

[0021] Based on the same inventive concept, an embodiment of the present invention further provides a semiconductor testing method.

[0022] See also Figure 2 , which is a flow chart of steps of an embodiment of the semiconductor testing method of the present invention. Figure 2As shown, the semiconductor testing method includes the following steps: step S21, providing a semiconductor testing structure, and the semiconductor testing structure adopts the semiconductor testing structure described in the present invention; step S22, applying voltage to the first pad, the second pad, the third pad and the fourth pad using preset rules to test the resistance of the electric fuse and test the performance of the transistor.

[0023] Please refer to Figure 1 And step S21, providing a semiconductor test structure, the semiconductor test structure adopts the present invention Figure 1 The semiconductor test structure shown. Figure 1 The semiconductor test structure shown can realize in-line monitoring of the electric fuse burning performance and the performance of the transistor during the wafer manufacturing process, and by optimizing the burning circuit layout, the number of pads used is reduced and the cost is lower. At the same time, the area of ​​the semiconductor test structure can be reduced, saving wafer space.

[0024] Please refer to Figure 1 And step S22 , applying voltage to the first pad 141 , the second pad 142 , the third pad 143 and the fourth pad 144 according to a preset rule to test the resistance of the electrical fuse 12 and the performance of the transistor 11 .

[0025] In some embodiments, the method further includes the following step: applying a programming voltage to the first pad 141 , the second pad 142 , and the fourth pad 144 to program the electrical fuse 12 .

[0026] In some embodiments, the preset rules include: before programming, applying a test voltage to the second pad 142 and the third pad 143 to test the resistance of the electric fuse 12, and applying a test voltage to the first pad 141, the third pad 143 and the fourth pad 144 to test the performance of the transistor 11; and / or after programming, applying a test voltage to the second pad 142 and the third pad 143 to test the resistance of the electric fuse 12, and applying a test voltage to the first pad 141, the third pad 143 and the fourth pad 144 to test the performance of the transistor 11.

[0027] In some embodiments, the performance of the transistor 11 is a threshold voltage or a saturation current of the transistor 11 .

[0028] Specifically, in this embodiment, before programming, a test voltage of 0.2V to 0.5V is applied to the second pad 142, a ground voltage is applied to the third pad 143, and the current at the third pad 143 is obtained to test the resistance of the electrical fuse 12. The current at the third pad 143 is controlled to be in the range of 1μA to 1mA to obtain the accurate resistance of the electrical fuse 12. By monitoring the resistance of the electrical fuse 12 inline during the wafer manufacturing process, the process can be quickly adjusted to improve the flexibility of the test.

[0029] In addition, before programming, a test voltage of 2V to 2.5V is applied to the first pad 141, a test voltage of 2V to 2.5V is applied to the fourth pad 144, a ground voltage is applied to the third pad 143, and a current at the third pad 143 is obtained to test the performance of the transistor 11. In this embodiment, the voltages applied to the first pad 141 and the fourth pad 144 are equal.

[0030] After testing the resistance of the electric fuse 12 and the performance of the transistor 11, the electric fuse 12 is programmed. In some embodiments, the electric fuse 12 reaches a predetermined resistance state after programming. The predetermined resistance state is to set the required resistance value or resistance shape according to the programming purpose. In this embodiment, the predetermined resistance state is a preset resistance value; specifically, a programming voltage of 2V to 2.5V is applied to the second pad 142, a programming voltage of 2V to 2.5V is applied to the fourth pad 144, and a ground voltage is applied to the first pad 141, so that a predetermined current passes through the electric fuse 12, so that self-aligned silicide electromigration or silicon melting occurs inside the electric fuse 12, and the resistance value of the electric fuse 12 is increased, and the electric fuse 12 is burned until the resistance value of the electric fuse 12 reaches the preset resistance value, thereby writing information on the electric fuse 12 (i.e., programming). The resistance state of the electric fuse 12 before programming is regarded as information "0", and the resistance state of the electric fuse 12 after programming is regarded as information "1".

[0031] After programming, a test voltage of 0.2V to 0.5V is applied to the second pad 142, a ground voltage is applied to the third pad 143, and the current at the third pad 143 is obtained to test the resistance of the programmed electric fuse 12. The current range at the third pad 143 is controlled to be 1μA to 1mA to obtain the resistance of the electric fuse 12 after accurate programming. If the difference between the resistance of the programmed electric fuse 12 and the preset resistance value is less than a preset threshold value, it is determined that the electric fuse 12 after burning meets the process requirements. If the difference between the resistance of the electric fuse 12 after burning and the preset resistance value is greater than the preset threshold value, it is determined that the electric fuse 12 after burning does not meet the process requirements, and further adjustment of process parameters is required to improve the process.

[0032] In addition, after programming, a test voltage of 2V to 2.5V is applied to the first pad 141, a test voltage of 2V to 2.5V is applied to the fourth pad 144, a ground voltage is applied to the third pad 143, and a current at the third pad 143 is obtained to test the performance of the programmed transistor 11. In this embodiment, the voltages applied to the first pad 141 and the fourth pad 144 are equal.

[0033] Theoretically, the performance of the transistor 11 after programming should be consistent with the performance of the transistor 11 before programming. If the performance of the transistor 11 after programming is too different from the performance of the transistor 11 before programming, the parameters of the programming process need to be adjusted to meet the process requirements.

[0034] The above technical solution can realize in-line monitoring of the resistance of the electric fuse and the performance of the transistor during wafer manufacturing by setting the semiconductor test structure on the wafer dicing path and connecting the electric fuse and the transistor to the pads respectively, so as to quickly adjust the process and improve the flexibility of the process. By setting multiple pads to split the burning circuit and separate the electric fuse from the transistor, it is convenient to control variables, test the performance of each component separately by structure, and improve the flexibility and accuracy of the test. The semiconductor test structure short-circuits the drain, substrate and the first end of the electric fuse to the same pad, reduces the number of pads in the semiconductor test, optimizes the circuit layout of the semiconductor test structure, and then reduces the area of ​​the semiconductor test structure, saving wafer space.

[0035] It should be noted that references in the specification to "an embodiment", "an embodiment", "an exemplary embodiment", "some embodiments", etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it is within the knowledge of a technician in the relevant art to implement such feature, structure, or characteristic in conjunction with other embodiments.

[0036] Typically, a term can be understood at least in part from usage in context. For example, the term "one or more" as used herein depends at least in part on the context and can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or features in a plural sense. Similarly, terms such as "one", "a" or "the" can also be understood to express singular usage or to express plural usage, depending at least in part on the context. In addition, the term "based on" can be understood to not necessarily be intended to express a set of exclusive factors, but can alternatively, also at least in part depending on the context, allow for the presence of other factors that are not necessarily explicitly described. It should also be noted in this specification that "connected / coupled" refers not only to the direct coupling of one component to another component, but also to the indirect coupling of one component to another component through an intermediate component.

[0037] It should be noted that the terms "including" and "having" and their variations involved in the documents of the present invention are intended to cover non-exclusive inclusions. The terms "first", "second", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Unless the context clearly indicates otherwise, it should be understood that the data used in this way can be interchanged under appropriate circumstances. In addition, the embodiments of the present invention and the features in the embodiments can be combined with each other unless there is a conflict. In addition, in the above description, the description of well-known components and technologies is omitted to avoid unnecessary confusion of the concepts of the present invention. In the above embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to each other.

[0038] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A semiconductor test structure, characterized in that: The semiconductor test structure is arranged on a dicing path of a wafer, and includes: A transistor, including a substrate, a source, a drain and a gate; an electrical fuse including a first end and a second end; The source is electrically connected to the first pad through a first metal wire, the second end of the electric fuse is electrically connected to the second pad through a second metal wire, the drain, the substrate and the first end of the electric fuse are electrically connected to the third pad through corresponding third metal wires, respectively, and the gate is electrically connected to the fourth pad through a fourth metal wire. Voltage is applied to the first pad, the second pad, the third pad and the fourth pad by adopting preset rules to test the resistance of the electric fuse and test the performance of the transistor.

2. The semiconductor test structure according to claim 1, characterized in that: The preset rule includes: before programming, applying a test voltage to the second pad and the third pad to test the resistance of the electric fuse, and applying a test voltage to the first pad, the third pad and the fourth pad to test the performance of the transistor; and / or After programming, a test voltage is applied to the second pad and the third pad to test the resistance of the electric fuse, and a test voltage is applied to the first pad, the third pad and the fourth pad to test the performance of the transistor.

3. The semiconductor test structure according to claim 2, characterized in that: The electrical fuse reaches a predetermined resistance state after being programmed.

4. The semiconductor test structure according to claim 1, characterized in that: The first metal line, the second metal line, the third metal line and the fourth metal line are formed by patterning a same metal layer.

5. The semiconductor test structure according to claim 1, characterized in that: The material of the electric fuse is polysilicon.

6. A semiconductor testing method, characterized in that: The steps include: Providing a semiconductor test structure, wherein the semiconductor test structure adopts the semiconductor test structure as claimed in claim 1; A voltage is applied to the first pad, the second pad, the third pad, and the fourth pad according to a preset rule to test the resistance of the electrical fuse and the performance of the transistor.

7. The method according to claim 6, characterized in that The method further comprises the steps of: A programming voltage is applied to the first pad, the second pad, and the fourth pad to program the electrical fuse.

8. The method according to claim 7, characterized in that The preset rules include: Before programming, applying a test voltage to the second pad and the third pad to test the resistance of the electric fuse, and applying a test voltage to the first pad, the third pad and the fourth pad to test the performance of the transistor; and / or After programming, a test voltage is applied to the second pad and the third pad to test the resistance of the electric fuse, and a test voltage is applied to the first pad, the third pad, and the fourth pad to test the performance of the transistor.

9. The method according to claim 7, characterized in that: The electrical fuse reaches a predetermined resistance state after programming.

10. The method according to claim 6, characterized in that The performance of the transistor is a threshold voltage or a saturation current of the transistor.

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