Control circuit and power factor correction circuit thereof

Abstract

The embodiment of the invention provides a control circuit and a power factor correction circuit thereof. The control circuit comprises a control signal generation module for generating a switching tube control signal; the comparison module is used for generating a protection trigger signal when the received sampling signal exceeds a preset first threshold value; the leading edge blanking module is used for shielding the protection trigger signal appearing in the preset shielding time; and the overcurrent protection module is used for outputting a first overcurrent protection signal and a second overcurrent protection signal to turn off the first switching tube. The over-current protection module calculates the period number of switching periods in which abnormal states occur continuously; when the period number reaches a preset second threshold value, continuously outputting a second overcurrent protection signal; and when the duration of the second over-current protection signal reaches a preset third threshold value, stopping generating the second over-current protection signal, and resetting the accumulated period number. On the premise of not sacrificing a design margin, reliable protection of the converter can be realized, and the realization cost is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of overcurrent protection, and in particular to a control circuit and a power factor correction circuit thereof. Background Art

[0002] In voltage converter applications, topologies such as Buck, Boost, Buck / Boost, Cuk, Zeta, and Sepic are the basic circuit forms for realizing DC-DC power conversion. These converters all use inductors as key energy storage components and realize periodic energy transfer by controlling the on and off of the switch tube.

[0003] However, when the converter is actually running, the inductor current may rise rapidly due to abnormal factors such as input voltage fluctuations or load changes. When the inductor current exceeds its rated value, the core material will enter the saturation region. Such inductor saturation phenomenon will cause the switch tube to be subjected to excessive current stress, resulting in device damage, inductor heating and aging, and a series of problems such as reduced system efficiency and increased electromagnetic interference.

[0004] To ensure reliable operation of the converter, a cycle-by-cycle current protection function is usually added to the power converter to monitor and limit the inductor current value in real time during each switching cycle, thereby avoiding converter damage caused by inductor saturation.

[0005] Figure 1 The system block diagram of a typical power factor correction (PFC) circuit is shown. Figure 1 As shown in the figure, the AC input voltage Vac is rectified by the EMI filter and the rectifier bridge Bridge to obtain the unprocessed input voltage Vi. Based on the sampled input voltage, output voltage and inductor current information, the control circuit generates a control signal through the PWM modulation circuit, and drives the main switch tube S of the converter after level conversion and isolation by the drive circuit. By accurately controlling the on and off timing of the switch tube S, the input current waveform follows the input voltage waveform, and at the same time, a stable DC voltage Vo is output under the action of the LC filter network to achieve harmonic correction of the input current waveform and power factor optimization.

[0006] In order to ensure the safe operation of the converter, the control circuit also integrates a cycle-by-cycle overcurrent protection function. When the converter is running, the inductor current is detected in real time through the sampling resistor Rcs, and the current signal is converted into a corresponding sampling voltage Vs. In each switching cycle, the comparator compares the current sampling voltage Vs with the internally preset overcurrent threshold V OCP_TH1 When the sampling voltage Vs rises to V OCP_TH1When the overcurrent protection signal is triggered, the comparator outputs a corresponding control signal to turn off the switch tube S, ensuring that the inductor current is limited to a safe range. The protection mechanism restarts in the next switching cycle, thus achieving cycle-by-cycle overcurrent protection.

[0007] To ensure reliable operation, the converter usually also implements the minimum on-time limit and leading edge blanking function. The leading edge blanking (LEB) function is used to suppress the parasitic ringing at the moment of switch S turning on and interfere with overcurrent detection. The setting of the minimum on time (Minimum On Time) takes into account the switching characteristics of the power switch tube (such as gate charging time) and the transmission delay of the drive circuit.

[0008] The combination of the above two factors results in that in each switching cycle, the switch tube S must maintain a certain conduction time before responding to the overcurrent protection signal. Under normal working conditions, this design will not affect the reliability of the overcurrent protection.

[0009] However, when the converter is in an abnormal state (such as the output diode D2 is short-circuited or the output terminal Vo is short-circuited), the excitation voltage of the inductor L is equal to the input voltage Vi and the demagnetization voltage is almost zero. Therefore, even a very short switch on time will cause the inductor current to accumulate rapidly. In this case, the cycle-by-cycle overcurrent protection mechanism of the control circuit may not be able to curb the current rise in time, which may eventually lead to inductor saturation or device damage. Summary of the invention

[0010] The control circuit and power factor correction circuit provided in the embodiments of the present application are intended to solve at least some of the defects in the existing converter overcurrent protection mechanism.

[0011] In a first aspect, an embodiment of the present application provides a control circuit. The control circuit includes: a control signal generating module, configured to generate a switch control signal, wherein the switch control signal is used to control a first switch of a converter; a comparison module, configured to generate a protection trigger signal when a received sampling signal exceeds a preset first threshold; the sampling signal comes from the converter; a leading edge blanking module, configured to shield a protection trigger signal that appears within a preset shielding time; an overcurrent protection module, configured to output a first overcurrent protection signal when receiving an unshielded protection trigger signal; wherein the overcurrent protection module is further configured to calculate the number of switching cycles in which an abnormal state occurs continuously, wherein the switching cycle in the abnormal state is: the protection trigger signal is received along with the opening of the first switch; when the number of cycles reaches a preset second threshold, the second overcurrent protection signal is continuously output; when the duration of the second overcurrent protection signal reaches a preset third threshold, the second overcurrent protection signal is stopped from being generated, and the accumulated number of cycles is cleared; the switch control module is further configured to generate a switch control signal for controlling the first switch to turn off when the first overcurrent protection signal or the second overcurrent protection signal is received.

[0012] In a second aspect, an embodiment of the present application provides a power factor correction circuit. The power factor correction circuit includes: a converter, the converter includes: a first switch tube and an inductor; the control circuit as described above; a sampling circuit, the sampling circuit is respectively connected to the control circuit and the converter, and is configured to: provide a sampling signal for the control circuit; and a driving circuit, the driving circuit is respectively connected to the control circuit and the first switch tube, and is configured to: convert the switch tube control signal provided by the control circuit into a control signal that drives the first switch tube to turn off or on.

[0013] At least one advantageous aspect of the control circuit provided in the embodiment of the present application is that by detecting whether a protection trigger signal appears when the switch tube is turned on to determine whether the converter is in an abnormal state, reliable protection of the converter can be achieved without sacrificing the design margin, thereby reducing the implementation cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0015] Figure 1 It is a system block diagram of a typical power factor correction circuit;

[0016] Figure 2 A system block diagram of another power factor correction circuit is shown, showing a situation where a secondary overcurrent protection is set;

[0017] Figure 3 A schematic diagram of a control circuit provided in an embodiment of the present application;

[0018] Figure 4 A waveform diagram of the leading edge blanking module provided in an embodiment of the present application;

[0019] Figure 5 A flow chart of a method for generating a second overcurrent protection signal by an overcurrent protection module provided in an embodiment of the present application;

[0020] Figure 6 A functional block diagram of an overcurrent protection module provided in an embodiment of the present application;

[0021] Figure 7 A functional block diagram of an overcurrent protection module provided in an embodiment of the present application, showing a situation where an anti-jitter circuit and a detection window setting unit are set;

[0022] Figure 8 A waveform diagram of the debouncing circuit provided in an embodiment of the present application;

[0023] Fig. 9 A circuit schematic diagram of an overcurrent protection module provided in an embodiment of the present application;

[0024] Fig.10 The waveform diagram of each signal of the control circuit provided in the embodiment of the present application when the converter is in a normal working state;

[0025] Fig.11 The waveform diagram of each signal of the control circuit provided in the embodiment of the present application during cycle-by-cycle overcurrent protection;

[0026] Fig.12 for Fig.11 The control circuit shown is a waveform diagram of each signal when the converter is in an abnormal state;

[0027] Fig.13 A circuit schematic diagram of an overcurrent protection module provided in another embodiment of the present application;

[0028] Fig.14 for Fig.13 The control circuit shown is a waveform diagram of each signal when the converter is in an abnormal state;

[0029] Fig.15 A schematic diagram of a power factor correction circuit provided in an embodiment of the present application, showing a situation in which a sampling circuit collects inductor current;

[0030] Fig.16A schematic diagram of a power factor correction circuit provided in an embodiment of the present application, showing a situation in which a sampling circuit collects the current of a first switch tube;

[0031] Fig.17 A schematic diagram of a power factor correction circuit provided in an embodiment of the present application, showing a situation where the first switch tube is a high-side drive switch tube of a buck converter;

[0032] Fig.18 The schematic diagram of the power factor correction circuit provided in the embodiment of the present application shows a situation where the first switch tube is a low-side drive switch tube of a buck converter. DETAILED DESCRIPTION

[0033] In order to facilitate the understanding of the present application, the present application is described in more detail below in conjunction with the accompanying drawings and specific embodiments.

[0034] It should be noted that when an element is referred to as being "disposed on" another element, it may be directly on the other element or there may be an intermediate element. When an element is considered to be "connected" to another element, it may be directly connected to the other element or there may be an intermediate element at the same time, or it may mean that the two elements are interactively connected through signals. When an element is considered to be "coupled" / "coupled to" another element, it may be directly coupled to the other element or there may be an intermediate element at the same time, or it may mean that the two elements interact through signals.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The terms "and / or" and "and / or" used herein include any and all combinations of one or more related listed items.

[0036] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0037] Figure 2 Another power factor correction circuit is shown. Figure 1 There is a defect that, under certain abnormal conditions, the cycle-by-cycle over-current protection mechanism fails, and the inductor current continues to increase as the number of switching cycles increases.

[0038] like Figure 2 As shown, relative to Figure 1 For the current comparison module, an additional current comparison module is added to form a two-level overcurrent protection. The newly added comparator uses another preset threshold voltage V OCP_TH2Among them, the threshold voltage V used by the newly added comparator OCP_TH2 is greater than the threshold voltage V used by the other comparator OCP_TH1 .

[0039] When a similar abnormal state occurs (for example, the diode D2 is short-circuited or the output terminal Vo is short-circuited), the inductor current will gradually increase as the number of switching cycles increases until it reaches another larger threshold value V OCP_TH2 When the additional comparator generates a second level protection signal accordingly, the control circuit outputs a corresponding control signal to control the main switch tube S to be continuously turned off for a period of time.

[0040] After the main switch tube S is continuously turned off for a period of time, the inductor current has enough time to recover to a smaller value, so that the inductor current will not increase further.

[0041] However, the applicant noticed during the implementation of this application: Figure 2 The control circuit shown in the figure adopts a two-stage overcurrent protection method. The threshold value V used by the second stage overcurrent protection is OCP_TH2 Relative to the threshold V used for the first level overcurrent protection OCP_TH1 For example, sufficient margin should be reserved (for example, V OCP_TH2 =V OCP_TH1 *150% or other higher values). Therefore, when selecting circuit components, it is necessary to consider that the current margin also increases (for example, the saturation current of the inductor), and components with better tolerance performance need to be used, which makes the solution implementation cost higher.

[0042] In order to solve the problem of high implementation cost mentioned above, the applicant has found that: based on the cycle-by-cycle current protection, it is possible to indirectly determine whether the converter is in an abnormal state by detecting whether the comparator generates a corresponding overcurrent protection signal at the time when the switch tube is turned on in each switching cycle.

[0043] Furthermore, when the detection results of two or more consecutive switching cycles show an abnormal state, the second overcurrent protection signal is continuously output for a period of time to make the main switch tube have a sufficiently long shutdown time, so that the inductor current will not continue to increase with the increase in the number of switching cycles, thereby achieving the same technical effect as the secondary overcurrent protection.

[0044] This method of judging the abnormal state of the switching cycle and triggering the overcurrent protection signal by counting the number of cycles can achieve the effect of suppressing the gradual increase of current inductance with the increase in the number of switching cycles when only using the first-level overcurrent protection module, thereby fundamentally solving the problem of rising costs caused by the second-level overcurrent protection.

[0045] According to the inventive concept provided by the embodiment of the present application, it can be generally applied to the control circuit of the converter to achieve overcurrent protection at a low cost. Figure 3 The present application is described by way of example to fully illustrate the design ideas and implementation methods provided by the present application.

[0046] Figure 3 Schematic diagram of a control circuit provided in an embodiment of the present application. Figure 3 As shown, the control circuit 100 includes: a control signal generating module 10, a comparison module 20, a leading edge blanking module 30 and an overcurrent protection module 40.

[0047] The control signal generating module 10 is a functional circuit unit configured to generate a switch control signal, and controls the first switch of the converter to turn on or off by generating a switch control signal drv.

[0048] The specific switch tube control signal drv and the control signal generating module 10 used can be selected or configured according to the needs of the actual situation, and are not specifically limited here. For example, the control signal generating module 10 can be a PWM signal generating circuit. It generates a corresponding pulse width modulation signal as a switch tube control signal (when the PWM signal is at a high level, the first switch tube is controlled to be turned on, and when the PWM signal is at a low level, the first switch tube is controlled to be turned off), and controls the on-time of the first switch tube by adjusting the duty cycle of the PWM signal.

[0049] Furthermore, the converter controlled by the control circuit may be a topology of a boost type (Boost), a buck type (Buck), a buck-boost type (Buck-Boost), a flyback type (Flyback), a forward type (Forward), etc. Correspondingly, the first switch tube may also be any type of switch tube in the converter, for example, a main power switch tube in a boost converter, a high-side drive switch tube or a low-side drive switch tube in a buck converter, etc. The present application does not limit the specific topology of the converter and the specific type of the first switch tube.

[0050] The comparison module 20 is configured to perform a comparison between the sampling signal Vs and the first threshold V OCP_TH1 The comparison function can compare the size between the received sampling signal and the preset first threshold, and generate a protection trigger signal when the sampling signal reaches the first threshold.

[0051] Specifically, the comparison module 20 can be implemented by a comparator. The two input terminals of the comparator are respectively connected to the sampling signal Vs and the first threshold V OCP_TH1 When the level of the sampling signal Vs exceeds the first threshold V OCP_TH1When the comparator output is inverted, the protection trigger signal is generated.

[0052] It should be noted that, in addition to the implementation method of using a single comparator, the comparison module 20 may also include other functional units such as a signal conditioning circuit and a hysteresis comparison circuit, and is not limited to those shown in the drawings of the present application specification.

[0053] The sampling signal Vs is an electrical signal from the converter and is associated with the inductor current in the converter. It can be any type of electrical signal, depending on the sampling circuit used. For example, the sampling signal Vs can be a voltage signal proportional to the inductor current, or a voltage signal proportional to the first switch tube current.

[0054] The leading edge blanking module 30 is configured as a functional circuit to implement the leading edge blanking function. It can shield the protection trigger signal that appears within the preset shielding time starting from the opening moment of the first switch tube. The size of the preset shielding time can be configured by the technician according to the actual needs, and is not specifically limited here.

[0055] The overcurrent protection module 40 is a functional circuit configured to generate an overcurrent protection signal so that the control signal generation module 10 can timely control the first switch tube to turn off and realize overcurrent protection. It can generate a first overcurrent protection signal ocp1 or a second overcurrent protection signal ocp2. When the switch tube control module 10 receives any one of the first overcurrent protection signal ocp1 or the second overcurrent protection signal ocp2, it generates a switch tube control signal to control the first switch tube to turn off.

[0056] The first overcurrent protection signal ocp1 is an overcurrent protection signal output by the overcurrent protection module 40 each time it receives an unshielded protection trigger signal, and is used to implement a cycle-by-cycle overcurrent protection function for the converter.

[0057] For example, Figure 4 The waveform diagram of the leading edge blanking function is shown. Among them, drv represents the switch control signal output by the control circuit. LEB represents the pulse signal generated by the leading edge blanking module, and the width of the pulse signal is Tblank. cmp_flag represents the protection trigger signal output by the comparison module. ocp1 represents the first overcurrent protection signal output by the overcurrent protection module.

[0058] like Figure 4As shown, the pulse signal provided by the leading edge blanking module (the shielding time is determined by the pulse width Tblank of the pulse signal) shields the protection trigger signal generated within a period of time after the first switch tube is turned on (the shielded protection trigger signal is marked as cmp_flag1). The shielded protection trigger signal cmp_flag1 will not cause the first overcurrent protection signal ocp1 of the overcurrent protection module.

[0059] In addition, in addition to the above-mentioned first overcurrent protection signal ocp1, the overcurrent protection module 40 will also detect whether the converter is in an abnormal state, and when the detection result meets the preset judgment standard, it will output a second overcurrent protection signal ocp2 that lasts for a period of time, and control the first switch tube to be turned off for a period of time to suppress the continuous increase of the inductor current and avoid the failure of the overcurrent protection function.

[0060] Figure 5 4 is a flow chart of a method for the overcurrent protection module 40 to generate the second overcurrent protection signal ocp2 provided in an embodiment of the present application. Figure 5 As shown, the method for generating the second overcurrent protection signal includes:

[0061] S41. Calculate the number of switching cycles in which abnormal conditions occur continuously.

[0062] The switching cycle of the abnormal state refers to the situation that the protection trigger signal is received along with the opening of the first switch tube. "Accompanying" means that the time interval between the opening moment of the first switch tube and the moment of receiving the protection trigger signal generated by the comparison module 20 is short, or that the protection trigger signal is detected within a detection window of a specific time length with the opening moment of the first switch tube as the detection starting point.

[0063] S42: Determine whether the number of cycles reaches a preset second threshold value. If yes, execute step S43; if no, return to step S41.

[0064] The second threshold is a value set by technicians according to actual needs, and is not specifically limited here. For example, the second threshold can be set to 2.

[0065] When the switching period of the continuous abnormal state does not reach the set second threshold, it indicates that no converter has the above abnormal situation at this time, and there is no need to output the second overcurrent protection signal, and the process returns to step S41.

[0066] S43. Output a second overcurrent protection signal.

[0067] The second overcurrent protection signal may be any suitable type of electrical signal, as long as it is a switch tube control signal that can instruct the switch tube control module 10 to control the first switch tube to turn off.

[0068] S44: When the duration of the second over-current protection signal reaches a preset third threshold, stop generating the second over-current protection signal and clear the accumulated number of cycles.

[0069] The third threshold value defines the duration of the second overcurrent protection signal. It is also an empirical value and can be set by technicians according to actual needs. "Reset" refers to the operation of restoring the current number of cycles to zero. After the number of cycles is restored to zero, the process can return to step S41 to recalculate the number of switch cycles in abnormal state.

[0070] It should be understood that the above steps S41 to S44 are exemplary descriptions of the functions to be implemented by the overcurrent protection module 40 from the perspective of method steps. The specific implementation of the overcurrent protection module 40 is not limited to a specific circuit structure.

[0071] Based on the exemplary description of steps S41 to S44, those skilled in the art can implement different forms of specific circuits for the overcurrent protection module 40 using one or more circuit elements such as a counter, a sequential logic circuit, and a combinational logic circuit according to actual needs. Any circuit implementation that can generate a second overcurrent protection signal that lasts for a certain period of time based on the number of switching cycles in which an abnormal state occurs continuously falls within the protection scope of the overcurrent protection module 40 of this embodiment.

[0072] Figure 6 Schematic diagram of an overcurrent protection module 40 provided in an embodiment of the present application. Figure 6 As shown, the overcurrent protection module 40 includes: a first indication signal generating unit 41 , a second indication signal generating unit 42 , a counting control unit 43 , a cycle number counting unit 44 and an overcurrent protection signal generating unit 45 .

[0073] The first indication signal generating unit 41 is configured to generate a first indication signal drv_ppulse indicating the turn-on time of the first switch tube according to the received switch tube control signal drv. The second indication signal generating unit 42 is configured to generate a second indication signal drv_npulse indicating the turn-off time of the first switch tube according to the received switch tube control signal.

[0074] The first indication signal generating unit 41 and the second indication signal generating unit 42 can be implemented by selecting appropriate types of circuits according to the actual needs. For example, when the switch control signal is a PWM signal, the first indication signal generating unit can be a latch circuit that captures the rising edge, and when the PWM signal has a rising edge, a PWM pulse is output as the first indication signal. The second indication signal generating unit can be a latch circuit that captures the falling edge, and when the PWM signal has a falling edge, a PWM pulse is output as the second indication signal.

[0075] The counting control unit 43 continuously outputs a counting signal cnt_en corresponding to whether an abnormal state occurs in each switching cycle based on the reception of the first indication signal drv_ppulse, the second indication signal drv_npulse and the protection trigger signal cmp_flag. By outputting different counting signals cnt_en, it can control the functional circuit of the subsequent cycle number counting unit 44 to perform cycle number accumulation or cycle number clearing action.

[0076] Specifically, the counting control unit 43 detects and determines whether an abnormal state occurs in the current switching cycle at the start time of a certain switching cycle (i.e., when the first indication signal appears), and maintains the detected state. According to the maintained state, at the update time of the current cycle (i.e., when the second indication signal appears), the counting signal cnt_en is updated until the second indication signal of the next switching cycle. Then, according to the detection result of the abnormal state at the start time of the next switching cycle, the output counting signal cnt_en is updated.

[0077] In the present application, a first counting signal is used to represent a counting signal output when it is determined that an abnormal state occurs in the current switching cycle, and a second counting signal is used to represent a counting signal output when no abnormal state occurs in the current switching cycle.

[0078] The cycle number counting unit 44 is a functional circuit configured to calculate the cycle number and determine whether it reaches the second threshold value. When receiving the first counting signal, it performs the cycle number accumulation operation, when receiving the second indication signal drv_npulse, it adds one to the cycle number, and when receiving the second counting signal, it performs the cycle number clearing operation to clear the current cycle number.

[0079] Therefore, the cycle number counting unit 44 uses the judgment result of whether the switch unit is in an abnormal state provided by the counting control unit 43 to count the number of switching cycles in which abnormal states occur continuously, and clears the number of cycles when there is no switching cycle in an abnormal state.

[0080] Furthermore, the cycle number counting unit 44 also has a preset second threshold value, and is configured to output a first trigger signal cnt_flag when the cycle number reaches the second threshold value. Of course, after the first trigger signal cnt_flag is output, the cycle number is also cleared.

[0081] The overcurrent protection signal generating unit 45 is configured to output a second overcurrent protection signal, which may be triggered by the first trigger signal cnt_flag output by the cycle number counting unit 44, and continuously output the second overcurrent protection signal ocp2 after being triggered until a preset duration is reached.

[0082] In the present application, the preset duration is the third threshold mentioned above, which can be configured by technical personnel according to the needs of actual conditions and is not specifically limited here.

[0083] As described above, whether an abnormal state occurs in each switching cycle is detected and determined when the first indication signal drv_ppulse is received, and the counting signal cnt_en corresponding to whether the abnormal state occurs is updated when the second indication signal drv_npulse is received, and then continuously output until the next switching cycle is updated.

[0084] Therefore, in order to realize the conversion between the detection result and the continuously output counting signal, in some embodiments, please continue to refer to Figure 6 The counting control unit 43 may include a state determination subunit 431 and a state latch subunit 432. The continuous output of the counting signal is achieved through the cooperation of these two subunits.

[0085] The state judgment subunit 431 is configured to detect whether an abnormal state occurs and generate a corresponding detection signal. It is connected to the first indication signal generating unit 41, and upon receiving the first indication signal drv_ppulse, detects whether a protection trigger signal cmp_deb occurs, and generates a corresponding detection signal based on the detection result.

[0086] In the present application, for the sake of distinction, the first detection signal is used to represent the detection signal output when the protection trigger signal is detected, and the second detection signal is used to represent the detection signal output when the protection trigger signal is not detected.

[0087] The first detection signal and the second detection signal can be selected to use any suitable type of electrical signal or combination of electrical signals according to actual needs, as long as two different detection results can be distinguished.

[0088] The state latch subunit 432 is configured to convert the detection signal into a continuously output counting signal and is connected to the state judgment subunit 431 to latch the detection signal provided by the state judgment subunit 431, thereby converting it into a continuously output counting signal cnt_en in the entire switching cycle.

[0089] For details, please continue to refer to Figure 6 The state latch subunit 432 includes: a first latch circuit 4321 and a second latch circuit 4322 .

[0090] The first latch circuit 4321 is configured to perform a latching function of the detection signal, and is connected to the state judgment subunit 431, and can record the state information of the detection signal by updating its latching state when the detection signal arrives.

[0091] The second latch circuit 4322 is configured to sample the latch state of the first latch circuit 4321. It is connected to the first latch circuit 4321 and the second indication signal generating unit 42 respectively, and in response to the triggering of the second indication signal drv_npulse, samples and holds the current latch state of the first latch circuit 4321, thereby generating a corresponding counting signal.

[0092] Specifically, the second latch circuit 4322 generates a first count signal when sampling the detection signal latched by the first latch circuit as a first detection signal, and generates a second count signal when sampling the detection signal latched by the first latch circuit as a second detection signal.

[0093] Therefore, through the cooperation between the first latch circuit 4321 and the second latch circuit 4322, the detection signal obtained at the turn-on moment of the first switch tube in one switching cycle can be converted into a continuous counting signal.

[0094] On the basis of the functional units described in one or more of the above embodiments, the overcurrent protection module 40 of the embodiment of the present application can also selectively add one or more functional circuits to solve technical problems that may be encountered in specific application scenarios, thereby further improving its use effect. These added functional circuits can be used alone or in any combination according to actual needs to obtain the superposition of corresponding technical effects. The following will be combined with specific embodiments to exemplify the functional circuits that can be optionally added to the overcurrent protection module 40 and their technical effects.

[0095] In some embodiments, when the received sampling signal is close to the first threshold set by the comparison module, the protection trigger signal output by the comparison module may contain some high-frequency jitter glitches.

[0096] In order to overcome the adverse effects caused by these jitter glitches and avoid interfering with the detection results of whether the switching cycle has an abnormal state, such as Figure 7 As shown, the overcurrent protection module 40 may further include: a debouncing circuit 47 .

[0097] The de-jitter circuit 47 is a functional circuit configured to provide a specific pulse width. It is arranged between the output end of the comparison module 20 and the counting control unit 43, and filters out the jitter burrs of the protection trigger signal output by the comparison module by pulse width superposition, thereby forming a stable protection trigger signal.

[0098] For example, Figure 8 The signal waveform of the debouncing circuit is shown. Among them, Vs represents the sampling signal proportional to the inductor current, cmp_flag represents the protection trigger signal output by the comparison module, and cmp_deb represents the protection trigger signal after being processed by the debouncing circuit.

[0099] like Figure 8 As shown, when the sampling signal Vs is at the first threshold V OCP_TH1 When the comparison module outputs a protection trigger signal cmp_flag, the protection trigger signal output by the comparison module will have high-frequency jitter glitches. After being processed by the de-jitter circuit, these jitter glitches are eliminated to form a stable protection trigger signal cmp_deb.

[0100] In other embodiments, considering that at the time of turning on the first switch tube, a certain amount of settling time is usually required to obtain a stable and accurate sampling signal. Figure 7 The overcurrent protection module may further include: a detection window setting unit 48.

[0101] The detection window setting unit 48 is a functional circuit for controlling the detection time window. It is arranged between the first indication signal generating unit 41 and the counting control unit 43, so that the first indication signal drv_ppulse generated by the first indication signal generating unit 41 is provided to the counting control unit 43 after a preset window time has passed, so as to detect whether an abnormal state occurs in the switching cycle.

[0102] Specifically, the preset window time can be reasonably set to ensure that the sampling signal is stable while not affecting the detection of whether an abnormal state occurs in the switching cycle, thereby avoiding false triggering of the second overcurrent protection signal.

[0103] For example, the establishment time of the sampling signal is usually in the order of 100ns (i.e., after about 100ns, the sampling signal begins to stabilize), and in the switching cycle without abnormal conditions, the time between receiving the first indication signal and the protection trigger signal is usually in the order of us (i.e., if the difference between the first indication signal and the protection trigger signal exceeds 1us or more, it can be considered that it does not belong to the above-mentioned "accompanying" situation). Therefore, when the preset window time is controlled between 100ns and 1us (such as 300ns), it can ensure that a stable sampling signal is obtained and avoid false triggering of the second overcurrent protection signal.

[0104] To facilitate understanding and explanation of the technical solutions of the embodiments of the present application, the functional units are functionally divided and named in the drawings of the specification. However, those skilled in the art should understand that the division of the functional units is only exemplary and not a specific limitation on the actual circuit implementation.

[0105] In actual implementation, the functional units described in one or more of the above embodiments may be integrated into the same circuit component according to specific requirements, or a certain functional unit may be dispersed in multiple independent circuit components, or any combination of the above methods may be adopted. No specific limitation is made here.

[0106] The following combination Fig. 9 The circuit schematic diagram shown describes in detail the specific circuit implementation of each functional unit in the above-mentioned overcurrent protection module.

[0107] like Fig. 9 As shown, the state judgment subunit 431 includes: a first logic gate circuit and1, a second logic gate circuit and2, and an inverter inv. The first logic gate circuit and1 and the second logic gate circuit and2 are both AND gates.

[0108] The first input end of the first logic gate circuit and1 is connected to the output end of the comparison module through the inverter inv, and receives the protection trigger signal cmp_deb that is stabilized after being processed by the debouncing circuit 47. The second input end of the first logic gate circuit and1 is connected to the output end of the first indication signal generating unit 41, and receives the first indication signal drv_ppulse.

[0109] The first input terminal of the second logic gate circuit and2 is connected to the output terminal of the comparison module, and receives the protection trigger signal cmp_deb stabilized after being processed by the debouncing circuit 47. The second input terminal of the second logic gate circuit and2 is connected to the output terminal of the first indication signal generating unit, and also receives the first indication signal drv_ppulse.

[0110] Therefore, when the first indication signal drv_ppulse is received, the output ends of the first logic gate circuit and1 and the second logic gate circuit and2 will form different electrical signal combinations as the first detection signal and the second detection signal according to whether the protection trigger signal is detected.

[0111] For example, if the protection trigger signal cmp_deb is detected when the first indication signal drv_ppulse is received, the output of the first logic gate circuit and1 is "0", and the output of the second logic gate circuit and2 is "1". Conversely, if the protection trigger signal cmp_deb is not detected when the first indication signal drv_ppulse is received, the output of the first logic gate circuit and1 is "1", and the output of the second logic gate circuit and2 is "0".

[0112] Please continue reading Fig. 9 The first latch circuit includes: an SR latch SR. The second latch circuit includes: a D-type latch DQ.

[0113] The input terminal R of the SR latch is connected to the output of the first logic gate circuit and1, and the input terminal S of the SR latch is connected to the output of the second logic gate circuit and2. The output terminal Q of the SR latch is connected to the data input terminal D of the D-type latch. The clock input terminal CLK of the D-type latch is connected to the output terminal of the second indication signal generating unit 42, and is used to receive the second indication signal drv_npulse.

[0114] Thus, the SR latch SR can be in different latching states based on different electrical signal combinations formed by the outputs of the first logic gate circuit and1 and the second logic gate circuit and2, and output different logic levels at the output terminal Q.

[0115] For example, when the output of the first logic gate circuit and1 is "0" and the output of the second logic gate circuit and2 is "1", the SR latch output terminal Q will output a logic level representing "1". When the output of the first logic gate circuit and1 is "1" and the output of the second logic gate circuit and2 is "0", the SR latch output terminal Q will output a logic level representing "0".

[0116] Each time the D-type latch DQ receives the second indication signal drv_npulse, it samples the latch state of the SR latch and outputs the sampling result from the output terminal Q of the D-type latch to form a corresponding counting signal.

[0117] For example, when the SR latch output terminal Q outputs "1", the D-type latch output terminal Q will output the sampling result "1" as the first counting signal. Conversely, when the SR latch output terminal Q outputs "0", the D-type latch output terminal Q will output the sampling result "0" as the second counting signal.

[0118] It should be understood that, depending on the specific composition of the state judgment subunit 431, the specific connection configuration between the input end of the SR latch and the output end of the state judgment subunit 431 can also be appropriately adjusted and replaced, as long as the SR latch can be in different latch states based on different detection signals, without limitation. Fig. 9 shown.

[0119] Please continue reading Fig. 9 The cycle number counting unit 44 includes: a counter Ncount. The overcurrent protection signal generating unit 45 includes: a timer Tcount.

[0120] The enable terminal of the counter Ncount is connected to the output terminal Q of the D-type latch to receive the count signal. The input terminal of the counter Ncount is connected to the output terminal of the second indication signal generating unit 42. The output terminal of the counter Ncount is connected to the enable terminal of the timer Tcount, and the output terminal of the timer Tcount is used to output the second overcurrent protection signal ocp2.

[0121] The counter Ncount performs a counting operation or a clearing operation according to the different counting signals received at the enable terminal. For example, when the output terminal Q of the D-type latch outputs a logic level indicating "1", the counter Ncount receives the second indication signal drv_npulse at the input terminal, and adds 1 to the current number of cycles. When the output terminal Q of the D-type latch outputs a logic level indicating "0", the counter Ncount clears the current number of cycles.

[0122] The counter Ncount is set with a counting upper limit. After the number of counted cycles reaches the counting upper limit, its output terminal will output the corresponding first trigger signal cnt_flag. The timer Tcount is triggered after receiving the first trigger signal cnt_flag, and continuously outputs the second overcurrent protection signal ocp2 at the output terminal.

[0123] The timer Tcount is also set with an upper limit of duration. After the duration of outputting the second overcurrent protection signal reaches the upper limit of duration, the timer Tcount stops outputting the second overcurrent protection signal and waits for the next trigger.

[0124] Furthermore, the output end of the timer Tcount is also connected to the SR latch SR and the D-type latch, so that when the timer Tcount outputs the second overcurrent protection signal, the SR latch SR and the D-type latch are reset to the initial state (RST) and the next cycle number is counted again.

[0125] It should be understood that, depending on the specific composition of the state latch subunit 432, the specific connection configuration between the enable end of the counter Ncount and the output end of the counting control unit can be appropriately adjusted and replaced (as long as the enable end of the counter Ncount can receive the counting signal), and the specific connection configuration between the output end of the timer Tcount and the state latch subunit 432 can also be appropriately adjusted and replaced (as long as the state latch subunit 432 can be reset to the initial state when the second overcurrent protection signal appears), without limitation. Fig. 9 shown.

[0126] The following combination Figures 10 to 12 The signal waveform diagram shown in the figure is described in detail Fig. 9 The actual operation process of the control circuit shown in different states.

[0127] Fig.10 It shows the waveforms of various signals of the control circuit when the converter is in normal working state.

[0128] Wherein, drv represents the switch control signal output by the control circuit, which is a PWM signal for controlling the on and off of the first switch tube. Vs represents the sampling signal. cmp_flag represents the output of the comparator. ocp1 represents the first overcurrent protection signal. ocp2 represents the second overcurrent protection signal.

[0129] In the normal working state of the converter, when the rising edge of the switch control signal drv arrives, the first switch is turned on, and the sampling signal Vs starts to rise linearly, but always remains at the preset first threshold value V OCP_TH1 When the switch tube control signal drv turns to a low level, the first switch tube is controlled to be turned off, and the sampling signal Vs decreases accordingly until the next switching cycle.

[0130] like Fig.10 As shown, since the sampling signal Vs does not exceed the first threshold V OCP_TH1 Therefore, the output of the comparison module continues to maintain a low level, and no protection trigger signal is output. Correspondingly, the two output signals ocp1 and ocp2 of the overcurrent protection module are also maintained at a low level state, and the first overcurrent protection signal and the second overcurrent protection signal are not output, and there is no need to trigger the overcurrent protection.

[0131] Fig.11The waveform diagram of each signal of the control circuit when the cycle-by-cycle overcurrent protection is triggered is shown. Among them, drv represents the switch control signal output by the control circuit. Vs represents the sampling signal. cmp_flag represents the output of the comparator. ocp1 represents the first overcurrent protection signal. ocp2 represents the second overcurrent protection signal.

[0132] In each switching cycle, when the rising edge of the switch control signal drv arrives, the first switch is turned on and the sampling signal Vs starts to rise linearly. When the sampling signal Vs reaches the preset first threshold V OCP_TH1 When , the comparator outputs the protection trigger signal cmp_flag.

[0133] With the generation of the protection trigger signal cmp_flag, the overcurrent protection module outputs the first overcurrent protection signal ocp1. In response to the generation of the first overcurrent protection signal ocp1, the switch control signal drv switches to a low level to turn off the first switch, and the sampling signal Vs decreases until the next switching cycle.

[0134] Therefore, in each switching cycle, once an overcurrent phenomenon is detected, the protection trigger signal cmp_flag can be responded to in time and the first switch tube can be turned off, thereby effectively controlling the inductor current not to exceed a safe range.

[0135] Fig.12 The waveform diagram of each signal of the control circuit when the converter is in an abnormal state is shown. Among them, cmp_flag represents the output of the comparator. ocp1 represents the first overcurrent protection signal. Vs represents the sampling signal. cmp_deb represents the protection trigger signal after debouncing. drv_ppulse represents the first indication signal generated with the appearance of the rising edge of the switch tube control signal drv. drv_npulse represents the second indication signal generated with the appearance of the falling edge of the switch tube control signal drv, and cnt represents the count value of the counter. ocp2_state represents the output of the SR latch. cnt_en represents the count signal output by the D-type latch. cnt_flag represents the first trigger signal output by the counter. ocp2 represents the second overcurrent protection signal.

[0136] When the rising edge of the switch control signal drv triggers the first switch to turn on, the sampling signal Vs starts to rise linearly. OCP_TH1 When the comparator outputs the protection trigger signal cmp_flag, the overcurrent protection module is triggered to generate the first overcurrent protection signal ocp1, so that drv turns to a low level to control the first switch tube to turn off. However, since the converter is in an abnormal state, the short off time of the first switch tube causes the sampling signal Vs to only slightly decrease.

[0137] In the subsequent switching cycle, since the sampling signal Vs is still at a high level, once the first switch tube is turned on, the comparator will be triggered to output the protection signal cmp_flag immediately. However, as mentioned above, in each switching cycle, the overcurrent protection module needs to output the ocp1 signal after a very short conduction time Ton to control the first switch tube to turn off.

[0138] In this process, the SR latch outputs the first detection signal (ocp2_state is high) when it detects cmp_deb at each drv rising edge (drv_ppulse). The D-type latch samples it at the corresponding drv falling edge (drv_npulse) and outputs the corresponding first count signal (cnt_en is high) to the counter. Accordingly, the counter increases the count value cnt at each drv_npulse.

[0139] When cnt reaches the second threshold ( Fig.12 As shown in the example, when the second threshold is 2), the counter outputs the first trigger signal cnt_flag. The timer then generates a second overcurrent protection signal ocp2 with a duration of Tocp2 to turn off the first switch tube. Since the duration Tocp2 is a relatively long time, it is sufficient to completely release the energy of the inductor and reduce the sampling signal Vs to a safe level, thereby realizing the overcurrent protection function of the converter in an abnormal state.

[0140] Finally, when the duration of the second over-current protection signal ocp2 reaches Tocp2, the timer is reset and stops outputting, and the control circuit resumes normal control.

[0141] In some embodiments, Fig.13 As shown, the detection window setting unit 48 includes: a pulse signal generator Gen and a third logic gate circuit and3.

[0142] The input end of the pulse signal generator Gen is connected to the output end of the first indication signal generating unit 41 to receive the first indication signal drv_ppulse. The output end of the pulse signal generator Gen is connected to one of the input ends of the third logic gate circuit and3, and the other input end of the third logic gate circuit and3 receives the switch control signal drv. The output end of the third logic gate circuit and3 is connected to the second input end of the first logic gate circuit and1 to provide the first indication signal drv_ppulse2 after the preset window time for the first logic gate circuit and1.

[0143] Specifically, the preset window time can be set by configuring the pulse width of the pulse generated by the pulse signal generator Gen.

[0144] Fig.14Shows Fig.13 The waveform diagram of each signal of the control circuit shown. Among them, cmp_flag represents the protection trigger signal output by the comparator, ocp1 represents the first overcurrent protection signal output by the overcurrent protection module, and cmp_deb represents the protection trigger signal after debouncing. drv_ppulse represents the first indication signal generated with the appearance of the rising edge of the switch tube control signal drv, drv_ppulse2 represents the pulse signal formed after the first indication signal drv_ppulse is processed by the detection window setting unit, drv_npulse represents the second indication signal generated with the appearance of the falling edge of the switch tube control signal drv, and cnt represents the count value of the counter. ocp2_state represents the output state of the SR latch, cnt_en represents the count signal output by the D-type latch, cnt_flag represents the first trigger signal output by the counter, and ocp2 represents the second overcurrent protection signal output by the timer.

[0145] When the rising edge of the switch control signal drv triggers the first switch to turn on, the sampling signal Vs starts to rise linearly. When the sampling signal Vs exceeds the preset first threshold value Vocp_th, the comparator outputs the protection trigger signal cmp_flag, which in turn triggers the overcurrent protection module to generate the first overcurrent protection signal ocp1, so that drv turns to a low level to control the first switch to turn off. However, since the converter is in an abnormal state, the short off time of the first switch causes the sampling signal Vs to only slightly decrease.

[0146] In the subsequent switching cycle, since the sampling signal Vs is still at a high level, the protection signal cmp_flag will be triggered immediately once the first switch tube is turned on. Considering that the first switch tube needs to be turned on for at least a period of time in each switching cycle, the overcurrent protection module will output the first overcurrent protection signal ocp1 to control the first switch tube to turn off after waiting for a period of time.

[0147] In this process, the first indication signal drv_ppulse is processed by the detection window setting unit to form a corresponding pulse signal drv_ppulse2. When receiving each pulse signal drv_ppulse2, the SR latch detects whether there is a protection trigger signal cmp_deb after debouncing. When the protection trigger signal cmp_deb is detected, the first detection signal is output (that is, ocp2_state is high). The D-type latch samples the corresponding drv falling edge (drv_npulse) and outputs a first counting signal (that is, cnt_en is high). Counter. Accordingly, the counter increases the count value cnt at each drv_npulse.

[0148] When cnt reaches the second threshold ( Fig.14The counter outputs the first trigger signal cnt_flag when the second threshold is 2). The timer then generates a second overcurrent protection signal ocp2 with a duration of Tocp2, so that the first switch tube is turned off for a period of time, so that the sampling signal Vs drops to a safe level, thereby realizing the overcurrent protection function of the converter in an abnormal state.

[0149] Based on the control circuit provided in one or more of the above embodiments, the present application further provides a power factor correction circuit (PFC) using the above control circuit to fully describe the specific control process of the control circuit on the converter during actual use.

[0150] like Fig.15 As shown, the power factor correction circuit includes: the control circuit 100, the converter 200, the sampling circuit 300 and the driving circuit 400 as described above.

[0151] The converter 200 is a power converter for implementing voltage conversion. The converter 200 may be a converter of any suitable topology type. For example, Fig.15 The boost converter 200 includes a first switch tube S1 as a main switch tube, a boost inductor L, a boost diode D1 and an output capacitor and other electronic devices, and can provide good power factor correction capability.

[0152] Alternatively, if Fig.17 and Fig.18 As shown, the converter 200 may also be a step-down (Buck) converter. The first switch tube S1 may be a high-side drive switch tube or a low-side drive switch tube.

[0153] The sampling circuit 300 is a functional circuit for collecting sampling signals, which is connected to the converter 200 and the control circuit 100 respectively, collects one or more relevant parameters of the converter 200 during operation, and provides them to the control circuit 100 .

[0154] The sampling circuit 300 may be implemented in any suitable circuit form. For example, Fig.15 and Fig.16 2 shows a case where the sampling resistor Rcs is used as the sampling circuit 300 .

[0155] Alternatively, in addition to using a sampling circuit, the sampling circuit 300 may also use a current sensor or other suitable types of current sampling circuits.

[0156] The driving circuit 400 is a functional circuit for converting the switch control signal drv output by the control circuit 100 into a driving signal DRV sufficient to drive the switch of the converter to turn on and off. It is connected to the control circuit 100 and the first switch S1 respectively, and after converting the switch control signal provided by the control circuit into a control signal for driving the first switch to turn off or on, it drives the first switch to turn on and off.

[0157] In some embodiments, the sampling circuit 300 may be a sampling circuit for collecting the inductor current of the converter. Fig.15 As shown, the sampling circuit RS1 can generate a first voltage signal proportional to the inductor current and provide it to the control circuit 100, so that the control circuit 100 can implement the overcurrent protection function described in one or more of the above embodiments.

[0158] Alternatively, the sampling circuit 300 may also be a sampling circuit for collecting the current of the first switch tube. Fig.16 As shown, the sampling circuit RS2 can generate a second voltage signal proportional to the current of the first switch tube and provide it to the control circuit 100, so that the control circuit 100 can implement the overcurrent protection function described in one or more of the above embodiments.

[0159] In the present application, for the convenience of description, a first sampling circuit is used to represent a sampling circuit for collecting inductor current, and a second sampling circuit is used to represent a sampling circuit for collecting first switch tube current.

[0160] It should be understood that, based on one or more embodiments disclosed in the present application, those skilled in the art can, in actual applications, adapt different types of sampling circuits and converters of different topologies by adjusting and configuring the control circuit 100 (e.g., the first threshold) according to different application scenarios.

[0161] For example, when different sampling circuits are used to collect electrical signals, or when applied to converters of different topological structures, the control circuit 100 can achieve the same overcurrent protection function by adjusting the configuration (such as the first threshold) accordingly. The control circuit provided in the present application has good versatility and applicability, and can adopt an adaptive parameter configuration according to the actual application scenario.

[0162] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Under the concept of the present application, the technical features in the above embodiments or different embodiments may also be combined, the steps may be implemented in any order, and there are many other changes in different aspects of the present application as described above, which are not provided in detail for the sake of simplicity. Although the present application has been described in detail with reference to the aforementioned embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A control circuit, characterized in that: include: A control signal generating module is configured to: generate a switch tube control signal, wherein the switch tube control signal is used to control a first switch tube of the converter; A comparison module is configured to: generate a protection trigger signal when the received sampling signal exceeds a preset first threshold; the sampling signal comes from the converter; The leading edge blanking module is configured to: shield the protection trigger signal appearing within a preset shielding time; The overcurrent protection module is configured to: output a first overcurrent protection signal when receiving an unshielded protection trigger signal; The overcurrent protection module is further configured to: calculate the number of switching cycles in which an abnormal state occurs continuously, and the switching cycle of the abnormal state is: the protection trigger signal is received along with the opening of the first switch tube; When the number of cycles reaches a preset second threshold, continuously outputting a second overcurrent protection signal; When the duration of the second over-current protection signal reaches a preset third threshold, stop generating the second over-current protection signal and clear the accumulated number of cycles; The switch tube control module is further configured to generate a switch tube control signal for controlling the first switch tube to turn off when receiving the first overcurrent protection signal or the second overcurrent protection signal.

2. The control circuit according to claim 1, characterized in that: The overcurrent protection module comprises: A first indication signal generating unit is configured to: generate a first indication signal indicating a start time of the first switch tube according to a received switch tube control signal; A second indication signal generating unit is configured to: generate a second indication signal indicating a turn-off moment of the first switch tube according to a received switch tube control signal; A counting control unit, configured to: continuously output a corresponding counting signal in each switching cycle according to the received first indication signal, the second indication signal and the protection trigger signal, wherein the counting signal includes: a first counting signal indicating that an abnormal state occurs in the current switching cycle and a second counting signal indicating that no abnormal state occurs in the current switching cycle; The cycle number counting unit is configured to: if the received counting signal is the first counting signal, increase the current cycle number by 1 each time the second indication signal is received; if the received counting signal is the second counting signal, clear the accumulated cycle number to zero; The cycle number counting unit is further configured to: output a first trigger signal when the cycle number reaches a preset second threshold; The overcurrent protection signal generating unit is configured to: when receiving the first trigger signal, continuously output the second overcurrent protection signal, and when the duration of the second overcurrent protection signal reaches a preset third threshold, stop generating the second overcurrent protection signal.

3. The control circuit according to claim 2, characterized in that: The counting control unit comprises: a state judgment subunit and a state latch subunit; The state judgment subunit is connected to the first indication signal generating unit and is configured to: generate a corresponding detection signal each time the first indication signal is received, the detection signal comprising: a first detection signal for detecting the protection trigger signal and a second detection signal for not detecting the protection trigger signal; The state latch subunit is connected to the state judgment subunit, and is configured to convert the detection signal into a corresponding counting signal that is continuously output during the current switching cycle.

4. The control circuit according to claim 3, characterized in that: The state latch subunit comprises: a first latch circuit and a second latch circuit; Wherein, the first latch circuit is connected to the state judgment subunit and is configured to: latch the detection signal each time the detection signal is received; The second latch circuit is connected to the first latch circuit and the second indication signal generating unit respectively, and is configured to: sample the detection signal latched by the first latch circuit each time the second indication signal is received to form a corresponding counting signal.

5. The control circuit according to claim 4, characterized in that: The first latch circuit includes: an SR latch; the second latch circuit includes: a D-type latch; The input end of the SR latch is connected to the state judgment subunit to receive the detection signal, and the output end of the SR latch is connected to the data input end of the D-type latch to output a logic level corresponding to the detection signal; The clock input end of the D-type latch is connected to the output end of the second indication signal generating unit for receiving the second indication signal; the output end of the D-type latch is connected to the cycle quantity counting unit for outputting the counting signal.

6. The control circuit according to claim 3, characterized in that: The state judgment subunit includes: a first logic gate circuit, a second logic gate circuit and an inverter; Wherein, the first input end of the first logic gate circuit is connected to the output end of the comparison module through the inverter; the second input end of the first logic gate circuit is connected to the output end of the first indication signal generating unit, for receiving the first indication signal; The first input end of the second logic gate circuit is connected to the output end of the comparison module, and the second input end of the second logic gate circuit is connected to the output end of the first indication signal generating unit, for receiving the first indication signal; The detection signal is composed of electrical signals output by the first logic gate circuit and the second logic gate circuit, and both the first logic gate circuit and the second logic gate circuit are AND gates.

7. The control circuit according to claim 2, characterized in that: The cycle number counting unit includes: a counter; the overcurrent protection signal generating unit includes: a timer; The enable terminal of the counter is connected to the counting control unit, the input terminal of the counter is connected to the output terminal of the second indication signal generating unit, and the counter is configured as follows: When the enabling end receives the first counting signal, the number of times the second indication signal is received is calculated as the number of cycles; When the number of cycles reaches a preset second threshold, the first trigger signal is output, and When receiving the second counting signal, clearing the number of cycles; The enable end of the timer is connected to the output end of the counter, the output end of the timer is connected to the control signal generating module, and the timer is configured to: output the second overcurrent protection signal when receiving the first trigger signal; When the output duration of the second over-current protection signal reaches a preset third threshold, the output of the second over-current protection signal is stopped.

8. The control circuit according to claim 2, characterized in that: The overcurrent protection module further includes: a detection window setting unit; The detection window setting unit is connected to the output end of the first indication signal generating unit, and is configured to control the first indication signal to be provided to the counting control unit after a preset window time has passed.

9. The control circuit according to any one of claims 2 to 8, characterized in that: The overcurrent protection module further includes: an anti-jitter circuit; The de-jitter circuit is connected to the output end of the comparison module and is configured to filter out jitter glitches of the protection trigger signal output by the comparison module.

10. A power factor correction circuit, characterized in that: include: A converter, the converter comprising: a first switch tube and an inductor; The control circuit according to any one of claims 1 to 9; a sampling circuit, the sampling circuit being connected to the control circuit and the converter respectively, and being configured to: provide a sampling signal to the control circuit; and A driving circuit is connected to the control circuit and the first switch tube respectively, and is configured to: convert a switch tube control signal provided by the control circuit into a control signal that drives the first switch tube to turn off or on.

11. The power factor correction circuit according to claim 10, characterized in that: The sampling circuit includes: a first sampling circuit configured to: form a first voltage signal proportional to the inductor current.

12. The power factor correction circuit according to claim 10, characterized in that: The sampling circuit includes: a second sampling circuit configured to: form a second voltage signal proportional to the current of the first switch tube.

13. The power factor correction circuit according to claim 10, characterized in that: The converter includes: a boost converter or a buck converter; the first switch tube includes: a high-side drive switch tube or a low-side drive switch tube.

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