Control circuit and power factor correction circuit thereof

Abstract

The embodiment of the invention provides a control circuit and a power factor correction circuit thereof. The control circuit comprises a switch control module for generating a switch tube control signal, and a first protection module and a second protection module for generating an overcurrent protection signal. The second protection module is used for determining a first cumulative number of the first period and generating an overload signal when the first cumulative number reaches a first threshold value; a second cumulative number of second cycles is determined and an overload protection signal is generated when a second threshold is reached. When the switch control module receives an overcurrent protection signal or an overload protection signal, the switch control module controls the first switch tube to be switched off. The overload protection function is realized by multiplexing the overcurrent protection mechanism of the control circuit, and the circuit area and the implementation cost are effectively reduced.

Description

Technical Field

[0001] The present application relates to the technical field of overload protection, and in particular to a control circuit and a power factor correction circuit thereof. Background Art

[0002] In the actual application of voltage converters, there are many basic circuit forms implemented by topologies such as Buck, Boost, Buck / Boost, Cuk, Zeta, Sepic, etc. These voltage converters all use inductors as key energy storage elements and realize periodic energy transfer by controlling the on and off of the switch tube.

[0003] During actual operation of the voltage converter, in order to prevent the voltage converter from operating in an overload state for a long time, causing problems such as overheating and damage of the converter's electronic components, an overload protection function is usually added to the voltage converter to monitor and limit the input power in real time.

[0004] Figure 1 The system block diagram of a typical power factor correction (PFC) circuit is shown. Figure 1 As shown in the figure, the AC input voltage Vac is rectified by the EMI filter and the rectifier bridge Bridge to obtain the unprocessed input voltage Vi. Based on the sampled input voltage, output voltage and inductor current information, the control circuit generates a control signal through the PWM modulation circuit, and drives the main switch tube S of the converter after level conversion and isolation by the drive circuit. By accurately controlling the on and off timing of the switch tube S, the input current waveform follows the input voltage waveform, and at the same time, a stable DC voltage Vo is output under the action of the LC filter network to achieve harmonic correction of the input current waveform and power factor optimization.

[0005] The control circuit collects the input voltage and the inductor current through the input sampling circuit and the current sampling circuit respectively, multiplies the two to obtain the corresponding input power, and compares the input power with the preset power threshold Volp_th. When the input power reaches the preset power threshold Volp_th, the output of the comparator cmp1 triggers the overload protection signal, and the control circuit outputs the corresponding control signal to turn off the switch tube S to prevent the voltage converter from operating in an overload state.

[0006] However, the above operation of multiplying the input voltage and the inductor current requires the use of a fast analog multiplier, which occupies a large circuit area and has a high implementation cost. Summary of the invention

[0007] The control circuit and power factor correction circuit provided in the embodiments of the present application are intended to solve at least some of the defects in the existing converter overload protection mechanism.

[0008] In the first aspect, an embodiment of the present application provides a control circuit. The control circuit includes: a switch control module, configured to: generate a switch control signal, the switch control signal is used to control the first switch of the converter; a first protection module, configured to: generate an overcurrent protection signal when the received sampling signal reaches a preset overcurrent protection threshold; a second protection module, configured to: determine the first cumulative number of the first cycle, and generate an overload signal when the first cumulative number reaches a preset first threshold; determine the second cumulative number of the second cycle, and generate an overload protection signal when the second cumulative number reaches a preset second threshold; wherein the first cycle is a switching cycle in which the overcurrent protection signal appears; the second cycle is a detection cycle in which the overload signal appears; the detection cycle is greater than or equal to half of the power frequency cycle; the switch control module is also configured to: generate a switch control signal to control the first switch to turn off when the overcurrent protection signal or the overload protection signal is received.

[0009] In a second aspect, an embodiment of the present application provides a power factor correction circuit. The power factor correction circuit includes: a converter, the converter includes: a first switch tube and an inductor; the control circuit as described above; a current sampling circuit, the current sampling circuit is respectively connected to the control circuit and the converter; and a drive circuit, the drive circuit is respectively connected to the control circuit and the first switch tube, and is configured to: convert the switch tube control signal provided by the control circuit into a control signal that drives the first switch tube to turn off or on.

[0010] At least one advantageous aspect of the control circuit provided in the embodiment of the present application is that the overcurrent protection mechanism for the converter in the multiplexed control circuit realizes the overload protection function of the converter through a two-level counting method for the switching cycle and the detection cycle, thereby effectively reducing the circuit area and implementation cost required for overload protection. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0012] Figure 1 It is a system block diagram of a typical power factor correction circuit;

[0013] Figure 2 A schematic diagram of a control circuit provided in an embodiment of the present application;

[0014] Figure 3 A signal waveform diagram of a leading edge blanking circuit provided in an embodiment of the present application;

[0015] Figure 4 A flow chart of a method for generating an overload protection signal provided in an embodiment of the present application;

[0016] Figure 5 A functional block diagram of a control circuit provided in an embodiment of the present application;

[0017] Figure 6 A schematic diagram of a second protection module provided in another embodiment of the present application;

[0018] Figure 7 A schematic diagram of a state maintainer provided in an embodiment of the present application;

[0019] Figure 8 A signal waveform diagram of a state maintainer provided in an embodiment of the present application;

[0020] Fig. 9 A schematic diagram of a first state maintainer provided in an embodiment of the present application;

[0021] Fig.10 A schematic diagram of a second state maintainer provided in an embodiment of the present application;

[0022] Fig.11 A signal waveform diagram of a first state maintainer provided in an embodiment of the present application;

[0023] Fig.12 A signal waveform diagram of a second state maintainer provided in an embodiment of the present application;

[0024] Fig.13 A schematic diagram of a second protection module provided in another embodiment of the present application;

[0025] Fig.14 A schematic diagram of a second protection module provided in another embodiment of the present application, showing a specific implementation of the first reset control unit and the second reset control unit;

[0026] Fig.15 A schematic diagram of a power factor correction circuit provided in an embodiment of the application, showing a situation in which a sampling circuit collects inductor current;

[0027] Fig.16 A schematic diagram of a power factor correction circuit provided in an embodiment of the application, showing a situation in which a sampling circuit collects the current of a first switch tube;

[0028] Fig.17 A schematic diagram of a power factor correction circuit provided in an embodiment of the present application, showing a case where the converter is a buck converter;

[0029] Fig.18 The waveform diagram of the input AC voltage and the detection reference signal provided in the embodiment of the present application. DETAILED DESCRIPTION

[0030] In order to facilitate the understanding of the present application, the present application is described in more detail below in conjunction with the accompanying drawings and specific embodiments.

[0031] It should be noted that when an element is referred to as being "disposed on" another element, it may be directly on the other element or there may be an intermediate element. When an element is considered to be "connected" to another element, it may be directly connected to the other element or there may be an intermediate element at the same time, or it may mean that the two elements are interactively connected through signals. When an element is considered to be "coupled" / "coupled to" another element, it may be directly coupled to the other element or there may be an intermediate element at the same time, or it may mean that the two elements interact through signals.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0033] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0034] Please continue reading Figure 1 In order to avoid using a fast analog multiplier, in some control circuits, the inductor current collected over a period of time is averaged to obtain the average inductor current of the time period, and then multiplied by the input voltage to calculate the input power monitoring result.

[0035] However, the applicant has noticed in the process of implementing the present application that the above-mentioned method of using inductor current averaging requires the use of a filter with a relatively large time constant, which also occupies a relatively large circuit area and still has the defect of high implementation cost.

[0036] In order to solve the problem of high implementation cost mentioned above, the applicant has found through research that: based on the overcurrent protection mechanism provided by the control circuit, a two-stage counting method can be used to indirectly determine whether the input power of the converter exceeds the set power threshold by respectively calculating the periodic count values ​​of the overcurrent protection signal that appears continuously in the switching cycle and the overload signal that appears continuously in the industrial frequency half-wave cycle, thereby realizing the overload protection function of the converter.

[0037] Such an overload protection method does not need to directly calculate the input power of the converter, which effectively reduces the occupied circuit area and reduces the implementation cost of the control circuit.

[0038] According to the above invention ideas, the control circuit provided in the embodiment of the present application can be generally applied to the control circuit of the converter to realize the overload protection of the converter at a low cost. Figure 2 The specific implementation of the control circuit provided in the embodiment of the present application is described by way of example.

[0039] Figure 2 Schematic diagram of a control circuit provided in an embodiment of the present application. Figure 2 As shown, the control circuit 100 includes: a switch control module 10 , a first protection module 20 and a second protection module 30 .

[0040] The switch control module 10 is a functional circuit unit for generating a switch control signal. It controls the operation of the first switch of the converter by generating a switch control signal drv. The specific switch control signal drv used can be selected or configured according to the actual needs, and is not specifically limited here.

[0041] For example, the switch control module 10 is a PWM signal generating circuit, which generates a corresponding pulse width modulation signal as a switch tube control signal (when the PWM signal is at a high level, the first switch tube is controlled to be turned on, and when the PWM signal is at a low level, the first switch tube is controlled to be turned off), and controls the on-time of the first switch tube in each switching cycle by adjusting the duty cycle of the PWM signal.

[0042] Furthermore, the converter controlled by the control circuit may be a topology of a boost type (Boost), a buck type (Buck), a buck-boost type (Buck-Boost), a flyback type (Flyback), a forward type (Forward), etc. Correspondingly, the first switch tube may also be any type of switch tube in the converter, for example, a main power switch tube in a boost converter, a high-side drive switch tube or a low-side drive switch tube in a buck converter, etc. The present application does not limit the specific topology of the converter and the specific type of the first switch tube.

[0043] The first protection module 20 is a functional circuit unit for implementing overcurrent protection. It monitors the inductor current of the converter in real time during actual operation by receiving a sampling signal from the converter, and generates an overcurrent protection signal accordingly when the preset overcurrent protection threshold is reached. The overcurrent protection signal is provided to the switch control module 10 so that it can control the first switch tube to be turned off in time by generating a corresponding switch tube control signal.

[0044] The sampling signal Vs is an electrical signal associated with the inductor current in the converter. It can be any type of electrical signal, depending on the sampling circuit used. For example, the sampling signal Vs is a voltage signal proportional to the inductor current, or a voltage signal proportional to the first switch tube current.

[0045] For details, please continue to refer to Figure 2 The first protection module 20 includes a comparator cmp. The two input terminals of the comparator cmp are respectively connected to the sampling signal Vs and the overcurrent protection threshold V OCP_TH When the level of the sampling signal Vs is greater than the overcurrent protection threshold V OCP_TH When the output terminal of comparator cmp is turned on, the level is reversed, thus generating an over-current protection signal.

[0046] Better yet, please continue reading Figure 2 The first protection module 20 may further include: a leading edge blanking circuit LEB. The leading edge blanking circuit LEB can shield the overcurrent protection signal generated by the comparator cmp within a period of time after the first switch tube is turned on. The specific shielding time is configured by the technician according to the actual needs and is not specifically limited here.

[0047] For example, Figure 3 The waveform diagram of the leading edge blanking circuit is shown. Among them, drv represents the switch control signal output by the control circuit. T-LEB represents the pulse signal generated by the leading edge blanking circuit, and the width of the pulse signal is Tblank. cmp_flag represents the output of the comparator. ocp_flag represents the overcurrent protection signal output by the first protection module 20.

[0048] like Figure 3 As shown, the pulse signal provided by the leading edge blanking circuit (the shielding time is determined by the pulse width Tblank of the pulse signal) will shield the output of the comparator cmp for a period of time after the first switch tube is turned on, so that the first protection module will not generate a corresponding over-current protection signal ocp_flag, thereby suppressing the interference of the over-current protection in the case of parasitic ringing at the moment when the first switch tube is turned on, and avoiding the over-current protection from being triggered incorrectly.

[0049] The second protection module 30 is a functional circuit unit for implementing overload protection. Based on the overcurrent protection signal generated by the first protection module 20, it performs secondary counting of the switching cycle and the detection cycle, and indirectly determines whether to output the overload protection signal olp_flag according to the cycle counting result.

[0050] Figure 4 1 is a flow chart of a method for generating an overload protection signal by the second protection module 30 provided in an embodiment of the present application. Figure 4As shown, the method for overload protection signal includes:

[0051] S301. Determine a first accumulated number of a first cycle according to a generation condition of an overcurrent protection signal.

[0052] The "first cycle" indicates a switching cycle in which an overcurrent protection signal appears. In other words, the second protection module 30 continuously detects whether an overcurrent protection signal appears in each switching cycle of the first switch tube during operation to determine whether the first cycle exists.

[0053] The "first cumulative number" refers to the result of counting the number of occurrences in the first cycle according to the set cumulative calculation rule. The specific cumulative calculation rule used can be set according to the actual needs.

[0054] For example, the first cumulative number is continuously increased only when the first cycle appears continuously, and when the overcurrent protection signal does not appear in a certain switching cycle, the first cumulative number is cleared. Alternatively, the accumulation calculation rule may also be: when the overcurrent protection signal does not appear in a certain switching cycle, the first cumulative number is kept unchanged or reduced, and the first cumulative number is cleared until the overcurrent protection signal does not appear for multiple consecutive switching cycles.

[0055] S302: Determine whether the first cumulative number reaches a preset first threshold. If yes, execute step S303; if no, return to step S301 to continue monitoring the first cumulative number.

[0056] The first threshold is a value pre-set by a technician, and can be set according to different actual application situations, so that the converter can obtain a relatively consistent overload protection threshold under different input voltages. For example, the first threshold and the overcurrent protection threshold can be configured accordingly according to different input voltages of the converter.

[0057] S303: Generate an overload signal.

[0058] When the first accumulated number reaches the first threshold, it can be determined that an overload has occurred in the current half-wave cycle of the power frequency, thereby generating a corresponding overload signal to indicate that the converter has been overloaded.

[0059] S304: Determine a second accumulated number of a second cycle according to the generation of the overload signal.

[0060] The "second cycle" is a detection cycle in which an overload signal appears. In other words, in addition to counting the switching cycles, the second protection module 30 also continuously detects whether an overload signal appears in each detection cycle to determine whether a second cycle exists.

[0061] Specifically, the detection period needs to be set to be greater than or equal to half of the power frequency period to ensure that the detection range can cover half of the complete power frequency period.

[0062] The "second cumulative number" refers to the result of counting the number of occurrences of the second cycle according to the set cumulative calculation rule. The specific cumulative calculation rule used can be set according to the actual needs, and can use the same cumulative calculation rule as the first cumulative number, or a different cumulative calculation rule, which is not specifically limited here.

[0063] S305: Determine whether the second cumulative number reaches a preset second threshold value. If yes, execute step S306; if no, return to step S304 to continue monitoring the second cumulative number.

[0064] The second threshold is a value pre-set by the technicians, which reflects the balance between the triggering speed and the triggering stability of the overload protection in the control circuit. For example, a smaller second threshold can provide a faster triggering speed of the overload protection, respond to the overload situation more promptly and turn off the first switch tube in time, while a larger second threshold can provide better triggering stability, making the overload protection action more stable and not easily triggered by mistake in some specific states or extreme situations.

[0065] S306: Generate an overload protection signal.

[0066] When the second accumulated number reaches the second threshold, it means that the converter has been running in the overload state for a long time. Therefore, a corresponding overload protection signal is generated and provided to the switch control module 10, so as to timely control the first switch tube to be turned off for a period of time.

[0067] Specifically, the duration of the overload protection signal can be preset and configured by a technician according to actual needs.

[0068] It can be understood that the above steps S301 to S306 are exemplary descriptions of the functions to be implemented by the second protection module 30 from the perspective of method steps. The specific implementation of the second protection module 30 is not limited to a specific circuit structure.

[0069] Based on the exemplary description of steps S301 to S306, those skilled in the art can use one or more circuit elements such as a counter, a sequential logic circuit, a combinational logic circuit, etc. according to actual needs to implement the second protection module 30 in a variety of different circuit forms. These different circuit implementation forms all fall within the protection scope of the second protection module 30 provided by the present application.

[0070] Figure 5 is a schematic diagram of a second protection module provided in an embodiment of the present application. Figure 5 As shown, the second protection module 30 includes: a first detection unit 31 , a first counting unit 32 , a detection cycle generating unit 33 , a second detection unit 34 and a second counting unit 35 .

[0071] The first detection unit 31 is a functional unit for detecting whether an overcurrent protection signal appears in each switching cycle. It is connected to the switch control module 10 and the first protection module 20 respectively, and can receive the switch tube control signal and the overcurrent protection signal, and output the corresponding switch cycle detection signal accordingly.

[0072] The first counting unit 32 is a functional unit for updating the first accumulated quantity according to a set accumulation rule, and is connected to the first detection unit 31 to update the first accumulated quantity according to the received switching cycle detection signal.

[0073] In addition, the first counting unit 32 will also output an overload signal when the first accumulated number reaches the aforementioned first threshold value, which serves as the basis for counting the next stage of detection cycle. The overload signal may also be any suitable electrical signal type.

[0074] The detection cycle generation unit 33 is a functional unit for generating a detection reference signal. The detection reference signal is an electrical signal for defining the aforementioned detection cycle. Any suitable electrical signal type may be selected and used, and no specific limitation is made here. For example, the detection cycle generation unit 33 is a pulse generation circuit that outputs a PWM signal with a pulse width greater than half a power frequency cycle as the detection reference signal.

[0075] The second detection unit 34 is a functional unit for detecting whether an overload signal appears in each detection cycle. The logic judgment steps to be performed are similar to those of the first detection unit 31, and are respectively connected to the detection cycle generation unit 33 and the first counting unit 32, and can receive the detection reference signal and the overload signal, and output the corresponding detection cycle detection signal accordingly.

[0076] The second counting unit 35 is a functional unit that updates the second cumulative number according to the set cumulative rule. It is connected to the second detection unit 34, updates the second cumulative number according to the received detection cycle detection signal, and generates and outputs an overload protection signal to the switch control module 10 when the second cumulative number reaches the aforementioned second threshold value, so as to turn off the first switch tube.

[0077] Thus, the first detection unit 31 and the first counting unit 32 constitute a first-level counting performed on the scale of the switching cycle, and when the first accumulated number reaches the first threshold, an overload signal is output to complete the contents of the aforementioned steps S301 to S303.

[0078] The second detection unit 34 and the second counting unit 35 constitute a second level of counting performed on the scale of the detection cycle. They further count based on the output of the first counting unit 32, and when the second accumulated number reaches the second threshold, they output an overload protection signal to complete the above steps S304 to S306.

[0079] In some embodiments, the first detection unit 31 or the second detection unit 34 is implemented by a state maintainer capable of maintaining or sustaining a detection signal. The state maintainer can form a detection signal according to whether a target signal is detected, and can also maintain such a detection signal so that it can be continuously output to a subsequent counting unit to complete the counting of the first cycle or the second cycle.

[0080] For example, taking the first detection unit 31 as an example, Figure 6 As shown, the first detection unit 31 includes: a first state maintainer Sig_Latch1. The first state maintainer Sig_Latch1 has a detection input terminal set1, a time input terminal time1, a state output terminal cnt_rst1 and a counting output terminal cnt_pulse1. The switching cycle detection signal provided by it includes: a first counting signal, a first reset signal and a first counting pulse.

[0081] Among them, the detection input terminal set1 is connected to the first protection module 20 to detect whether an overcurrent protection signal appears. The time input terminal time1 is connected to the switch control module 10 to receive the switch tube control signal and determine the switching cycle accordingly. The state output terminal cnt_rst1 is used to output a first counting signal (indicating that an overcurrent protection signal appears in the current switching cycle) or a first reset signal (indicating that an overcurrent protection signal does not appear in the current switching cycle). The counting output terminal cnt_pulse1 is used to output a first counting pulse in each switching cycle.

[0082] Based on the input of the detection input terminal set1 and the time input terminal time1, the specific manner in which the corresponding switching cycle detection signal is formed at the state output terminal cnt_rst1 and the counting output terminal cnt_pulse1 of the first state maintainer Sig_Latch1 is as follows:

[0083] Firstly, the first state maintainer Sig_Latch1 determines the start time and the stop time of the first switch tube according to the level change of the switch tube control signal received by the time input terminal time1.

[0084] For example, when a PWM signal is used as a switch control signal, the moment when the PWM signal has a rising edge and switches from a low level to a high level can be considered as the turn-on moment. Conversely, the moment when the PWM signal has a falling edge and switches from a high level to a low level can be considered as the turn-off moment.

[0085] Secondly, the first state maintainer Sig_Latch1 is set to switch between two states (hereinafter referred to as the first state and the second state). When the detection input terminal set1 receives a valid signal (i.e., an overcurrent protection signal), the first state maintainer Sig_Latch1 switches from the first state to the second state, and at each turn-on moment of the first switch tube, the first state maintainer Sig_Latch1 is reset to the first state.

[0086] It can be understood that, under such a state setting mode, the first state indicates that the detection result of the overcurrent protection signal does not appear in the current switching cycle, while the second state indicates that the detection result of the overcurrent protection signal appears in the current switching cycle. Moreover, after the first switch tube is turned on again and enters a new switching cycle, it is reset to the first state, thereby starting to detect whether the overcurrent protection signal appears in the new switching cycle.

[0087] Finally, the current state of the first state maintainer Sig_Latch1 is obtained at the closing time, and the output of the state output terminal cnt_rst1 is determined accordingly. The counting output terminal cnt_pulse1 outputs a first counting pulse at each closing time.

[0088] Specifically, when the first state maintainer is in the first state at the off time, the state output terminal cnt_rst1 continuously outputs the first reset signal, and when the first state maintainer is in the second state at the off time, the state output terminal cnt_rst1 continuously outputs the first counting signal.

[0089] The term "update" indicates that the output of the state output terminal cnt_rst1 is determined by the state of the first state maintainer sampled at the closing time, and is not affected by the state change time of the first state maintainer. In other words, the output of the state output terminal cnt_rst1 is maintained after the last closing time and before the next closing time.

[0090] The first reset signal and the first counting signal are any type of electrical signals as long as they can be distinguished by the first counting unit. For example, the first reset signal can be a low level signal, and the first counting signal can be a high level signal.

[0091] In some other embodiments, the second detection unit 34 also uses similar logic steps as the first detection unit 31 to implement detection of the second cycle.

[0092] Please continue reading Figure 6 The second detection unit 34 includes a second state maintainer Sig_Latch2. The second state maintainer Sig_Latch2 performs substantially the same logical steps as the first state maintainer Sig_Latch1, and also has a time input terminal time2, a detection input terminal set2, a state output terminal cnt_rst2, and a count output terminal cnt_pulse2. The detection cycle detection signal provided by the second state maintainer Sig_Latch2 includes: a second count signal, a second reset signal, and a second count pulse.

[0093] Among them, the time input terminal time2 of the second state maintainer is connected to the detection cycle generation unit 33, and is used to receive the detection reference signal and determine the detection cycle accordingly. The detection input terminal set2 of the second state maintainer is connected to the output terminal of the first counting unit 32, and is used to determine whether the first counting unit 32 outputs an overload signal. The state output terminal cnt_rst2 of the second state maintainer is used to output a second counting signal (indicating that an overload signal appears in the current detection cycle) or a second reset signal (indicating that an overload signal does not appear in the current detection cycle). The counting output terminal cnt_pulse2 of the second state maintainer is used to output a second counting pulse in each detection cycle.

[0094] In actual operation, the second state maintainer Sig_Latch2 determines the start time and the end time of the detection cycle through the received detection reference signal.

[0095] The second state maintainer Sig_Latch2 is also configured to switch between the first state and the second state. At the start of each detection cycle, the second state maintainer Sig_Latch2 is reset to the first state and enters a new detection cycle for detection. When the overload signal output by the first counting unit 12 is received, the second state maintainer Sig_Latch2 switches to the second state.

[0096] At the end of each detection cycle, the output of the state output terminal cnt_rst2 is updated according to the current state of the second state maintainer (when the current state is the second state, the second counting signal is output, and when the current state is the first state, the second reset signal is output), and the output of the updated state output terminal cnt_rst2 is maintained before the next update moment.

[0097] In addition, at the end of each detection cycle, the counting output terminal cnt_pulse2 of the second state maintainer Sig_Latch2 also outputs a second counting pulse, which is provided to the second counting unit 35 .

[0098] In order to fully describe the first state maintainer and the second state maintainer of the present application, the embodiment of the present application also provides a specific implementation of the state maintainer, which can be applied to the aforementioned first state maintainer or the second state maintainer to implement one or more of the aforementioned logical steps and form the required switching cycle detection signal or detection cycle detection signal.

[0099] Figure 7 Schematic diagram of a state maintainer provided in an embodiment of the present application. Figure 7 As shown, the state maintainer includes: a rising edge detector RiseEdge, a falling edge detector FallEdge, an SR latch SR and a D-type latch DQ.

[0100] The input terminals of the rising edge detector RiseEdge and the falling edge detector FallEdge are connected to the time input terminal time of the state maintainer, and the output terminal of the falling edge detector FallEdge is connected to the counting output terminal cnt_pulse of the state maintainer.

[0101] The reset input terminal R of the SR latch SR is connected to the output of the rising edge detector RiseEdge. The set input terminal S of the SR latch is connected to the detection input terminal set of the state maintainer. The non-inverting output terminal Q of the SR latch SR is connected to the data input terminal Q of the D-type latch DQ.

[0102] The sampling terminal CLK of the D-type latch DQ is connected to the output of the falling edge detector FallEdge. Connected to the state output terminal cnt_rst of the state maintainer.

[0103] The SR latch SR and the D-type latch DQ are also connected to the reset terminal rst of the state maintainer. When the reset terminal rst of the state maintainer receives a reset signal, the SR latch SR and the D-type latch DQ are both reset.

[0104] The following combination Figure 8The signal waveform diagram shown in the figure is described in detail Figure 7 The actual operation process of the state maintainer shown in FIG. Among them, time_pulse represents the electrical signal input to the time input terminal, pos_pulse represents the detection pulse generated by the rising edge detector RiseEdge, neg_pulse represents the counting pulse generated by the falling edge detector FallEdge, set_pulse represents the electrical signal received by the detection input terminal, set_state represents the output of the SR latch, cnt_rst represents the output of the state output terminal, cnt_pulse represents the output of the counting output terminal, and ret represents the electrical signal received by the reset terminal.

[0105] like Figure 8 As shown, when the rising edge of the input signal at the time input terminal time arrives, the rising edge detector RiseEdge generates a detection pulse pos_pulse.

[0106] When the rising edge detector RiseEdge outputs the detection pulse pos_pulse, the detection pulse pos_pulse acts on the reset terminal R of the SR latch SR to reset the SR latch SR, and the output set_pulse of the non-inverting output terminal Q of the SR latch is low level.

[0107] When a valid electrical signal set_pulse is input to the detection input terminal of the state maintainer, the SR latch SR is set through the set terminal S of the SR latch SR, so that the output set_pulse of the non-inverting output terminal Q of the SR latch is turned to a high level.

[0108] When the falling edge of the input signal at the time input terminal time arrives, the falling edge detector FallEdge generates a counting pulse neg_pulse. At this time, the counting output terminal cnt_pulse of the state maintainer will output a counting pulse accordingly.

[0109] When the D-type latch DQ receives the count pulse neg_pulse, the output state of the non-inverting output terminal Q of the SR latch SR is sampled, and the output state of the non-inverting output terminal Q of the D-type latch DQ is sampled. Output the corresponding output signal cnt_rst.

[0110] By way of example, the following provides Figure 7 The state maintainer shown in the figure includes a first state maintainer and a second state maintainer. Fig. 9 A schematic diagram of a first state maintainer provided in an embodiment of the present application. Fig.10 A schematic diagram of a second state maintainer provided in an embodiment of the present application.

[0111] like Fig. 9As shown, the first state maintainer includes: a first rising edge detector RiseEdge1, a first falling edge detector FallEdge1, a first SR latch SR1 and a first D-type latch DQ1.

[0112] In response to the occurrence of a rising edge of the switch control signal, the first rising edge detector RiseEdge1 generates a first detection pulse, and in response to the occurrence of a falling edge of the switch control signal, the first falling edge detector FallEdge1 generates a first counting pulse.

[0113] The reset input terminal R of the first SR latch SR1 is connected to the first rising edge detector RiseEdge1 for receiving the first detection pulse. The set input terminal S of the first SR latch SR1 is connected to the first protection module 10 for receiving the overcurrent protection signal. The non-inverting output terminal Q of the first SR latch SR1 is connected to the data input terminal D of the first D-type latch DQ1.

[0114] The sampling terminal CLK of the first D-type latch DQ1 is connected to the first falling edge detector FallEdge1 for receiving the first counting pulse. The first falling edge detector FallEdge1 is connected to the state output terminal cnt_rst1 of the first state maintainer, and the output terminal of the first falling edge detector FallEdge1 is connected to the counting output terminal cnt_pulse1 of the first state maintainer.

[0115] like Fig.10 As shown, the second state maintainer includes: a second rising edge detector RiseEdge2, a second falling edge detector FallEdge2, a second SR latch SR2 and a second D-type latch DQ2.

[0116] In response to the occurrence of a rising edge of the detection reference signal, the second rising edge detector RiseEdge2 generates a second detection pulse, and in response to the occurrence of a falling edge of the detection reference signal, the second falling edge detector FallEdge2 generates a second counting pulse.

[0117] The reset input terminal R of the second SR latch SR2 is connected to the second rising edge detector RiseEdge2 for receiving the second detection pulse. The set input terminal S of the second SR latch SR2 is connected to the detection input terminal set2 for receiving the overload signal. The non-inverting output terminal Q of the second SR latch SR2 is connected to the data input terminal of the second D-type latch DQ2.

[0118] The sampling terminal CLK of the second D-type latch DQ2 is connected to the second falling edge detector FallEdge2 for receiving the second counting pulse. The output terminal of the second falling edge detector is connected to the state output terminal cnt_rst2 of the second state maintainer. The output terminal of the second falling edge detector is connected to the count output terminal cnt_pulse2 of the second state maintainer.

[0119] In some embodiments, based on the switching cycle detection signal output by the first state maintainer and the detection cycle detection signal output by the second state maintainer, the first counting unit and the second counting unit count the number of cycles and output a valid signal through a comparison counter.

[0120] For example, please refer to Figure 6 The first counting unit 32 includes a first counter Count1. The first counter Count1 has a reset signal terminal cnt1_rst, a counting signal terminal cnt1_pulse and an output terminal cnt1_flag, and is used to count the clock pulses received by the counting signal terminal cnt1_pulse, and output an overload signal at the output terminal cnt1_flag when the count value reaches a preset first threshold.

[0121] The reset signal terminal cnt1_rst of the first counter Count1 is connected to the state output terminal cnt_rst1 of the first state maintainer Sig_Latch1, so that the output of the state output terminal cnt_rst1 of the first state maintainer Sig_Latch1 can realize the reset control of the first counter Count1. The count signal terminal cnt1_pulse of the first counter Count1 is connected to the count output terminal cnt_pulse1 of the first state maintainer Sig_Latch1, so as to receive the first count pulse and count.

[0122] Specifically, when the first counter Count1 receives the first counting signal at the reset signal terminal cnt1_rst, it performs a counting function, counts the received first counting pulses, and increases the count value (i.e., the first cumulative number) as the first counting pulses are received. When the first counter Count1 receives the first reset signal at the reset signal terminal cnt1_rst, it performs a reset function, clears the current count value, and counts again.

[0123] The following combination Fig.11 The signal waveform diagram shown in the figure is described in detail. Figure 6 The actual operation process of the first counter shown in FIG. 1 is shown in FIG. 1 . Wherein, drv represents the switch control signal, Vs represents the sampling signal, V OCP_THrepresents the overcurrent protection threshold, cmp_flag represents the output of the comparator, ocp_flag represents the overcurrent protection signal output by the first protection module 10, cnt1_rst represents the electrical signal received by the reset signal end, cnt1_pulse represents the electrical signal received by the counting signal end, Cnt1 represents the first cumulative number, and cnt1_flag represents the output of the first counter.

[0124] like Fig.11 As shown, for the triggering of the overcurrent protection signal:

[0125] During the period when the switch control signal drv=1, the first switch is turned on, and the inductor current and the corresponding sampling signal rise accordingly until V S >V OCP_TH When the output level of the comparator flips (cmp_flag=1), the first protection module 10 generates an overcurrent protection signal (ie, ocp_flag has a positive pulse). With the generation of the overcurrent protection signal, the switch tube control signal drv=0, controlling the first switch tube to turn off.

[0126] Please continue reading Fig.11 , for the first cycle, count the number of cycles:

[0127] During the period when the switch control signal drv=1, the state output terminal of the first state maintainer Sig_Latch1 outputs the first counting signal (i.e., cnt1_rst=0) to the reset signal terminal of the first counter. The first counter starts counting. The count value Cnt1 of the first counter is increased by 1 each time a counting pulse is received until it reaches the pre-configured first threshold N. When the count value Cnt1 reaches N, the output overload signal of the first counter (i.e., cnt1_flag=1) is output, and the count value is reset to 0, and counting starts again.

[0128] In other embodiments, please refer to Figure 6 The second counting unit 34 includes: a second counter Count2 and a timer Tcount.

[0129] The second counter Count2 performs substantially the same logic steps as the aforementioned first counter Count1, and also has a reset signal terminal cnt2_rst, a counting signal terminal cnt2_pulse, and an output terminal cnt2_flag.

[0130] The reset signal terminal cnt2_rst of the second counter is connected to the state output terminal cnt_rst2 of the second state maintainer, and the count signal terminal cnt2_pulse of the second counter is connected to the count output terminal cnt_pulse2 of the second state maintainer. It counts the clock pulses received by the count signal terminal cnt2_pulse, and outputs a valid signal at the output terminal flag2 when the count value reaches a preset second threshold.

[0131] Specifically, when the second counter Count2 receives the second counting signal at the reset signal terminal cnt2_rst, the counting function is executed to count the second counting pulses received at the counting signal terminal cnt2_pulse, so that the count value (i.e., the second cumulative number) is accumulated as the second counting pulses are received. When the second counter Count2 receives the second reset signal at the reset signal terminal cnt2_rst, the reset function is executed to clear the current count value to zero and count again.

[0132] The timer Tcount is a functional circuit that can realize timing control and change the output state when a specific time condition is reached. The timing trigger end of the timer Tcount is connected to the output end flag2 of the second counter Count2. The output end of the timer Tcount is connected to the switch control module 10.

[0133] When the timing trigger end of the timer Tcount receives a valid signal, it starts timing and keeps outputting the overload protection signal olp_flag at the output end until the timing reaches a preset time threshold, at which time the timer Tcount automatically resets and stops outputting the overload protection signal olp_flag at the output end.

[0134] In other embodiments, please refer to Figure 6 The output end of the timer Tcount is also connected to the reset end rst1 of the first state maintainer Sig_Latch1 and the reset end rst2 of the second state maintainer Sig_Latch2.

[0135] Therefore, when the overload protection signal is generated at the output end of the timer Tcount, the reset ends of the first state maintainer Sig_Latch1 and the second state maintainer Sig_Latch2 receive the overload protection signal and are reset to the initial state.

[0136] The following combination Fig.12 The signal waveform diagram shown in the figure is described in detail Figure 6The actual operation process of the second counter and timer shown in the figure. Among them, drv represents the switch control signal, Vs represents the sampling signal, and Vac represents the input AC voltage; cmp_flag represents the output of the comparator, cnt1_flag represents the output of the first counter, line_pulse represents the detection reference signal, Tline represents the detection cycle length defined by the detection reference signal, cnt2_rst represents the electrical signal received by the reset signal end, cnt2_pulse represents the electrical signal received by the counting signal end, Cnt2 represents the second cumulative number, cnt2_flag represents the output of the second counter, olp_flag represents the overcurrent protection signal output by the timer, and Tolp represents the time threshold length pre-configured by the timer.

[0137] like Fig.12 As shown, the detection cycle length Tline is greater than or equal to half of the power frequency cycle, thereby completely including half of the power frequency cycle of the input AC voltage. During the detection reference signal line_pulse=1, the second state maintainer Sig_Latch2 latches the output signal of the first counter to provide a detection result of whether an overload signal (i.e. cnt1_flag=1) occurs within a detection cycle.

[0138] When the state output terminal of the second state maintainer Sig_Latch2 outputs the second counting signal (i.e., cnt2_rst=0) to the reset signal terminal of the second counter, the second counter starts to count pulses. Its count value Cnt2 is increased by 1 each time a counting pulse is received (the count value is equivalent to calculating the number of half-waves of the power frequency when the overload signal appears) until the pre-configured second threshold M is reached.

[0139] When the count value Cnt2=M, the second counter outputs a valid signal (i.e., cnt2_flag=1), and resets the second counter, and the count value Cnt2 is cleared to zero. The valid signal output by the second counter triggers the timer Tcount to start timing and maintain the output state, outputting an overload protection signal (i.e., olp_flag=1), until the preset time threshold Tolp is reached, the timer Tcount stops outputting the overload protection signal (i.e., olp_flag=0).

[0140] During the overload protection signal output period, the switch control signal drv=0, and the first switch is turned off. After the overload protection signal output ends, the switch control signal drv returns to a normal control state.

[0141] Figure 6The second protection module shown in the figure counts the number of consecutive first and second cycles when calculating the first cumulative number and the second cumulative number. When the first cycle or the second cycle interval occurs, as described above, the first counter or the second counter will clear the current count value due to the reset signal terminal receiving the first reset signal or the second reset signal.

[0142] In some embodiments, in order to further increase the control flexibility of the first counter and the second counter during counting and resetting, a comparison counter with more pulse counting modes may be used, and an additional reset control unit may be added.

[0143] For example, taking the first counter as an example, Fig.13 As shown, the second protection module 30 further includes: a first reset control unit 36. Accordingly, in the first counting unit 32, the third counter Count3 is used to replace the first counter Count1.

[0144] The first reset control unit 36 ​​is a functional circuit for determining the third cumulative number of consecutive third cycles according to the switching cycle detection signal. It also has a comparison function, comparing the third cumulative number with a pre-configured third threshold, and generating a corresponding first reset control signal or a second reset control signal according to the comparison result.

[0145] Specifically, the third cycle refers to a switching cycle in which no overcurrent protection signal appears. The first reset control signal is a signal output when the third cumulative number does not reach a preset third threshold. The second reset control signal is a signal output when the third cumulative number reaches the third threshold.

[0146] The third counter Count3 has a count mode selection terminal cnt3_dis in addition to a reset signal terminal cnt3_rst, a count signal terminal cnt3_pulse and an output terminal cnt3_flag, and has different pulse counting modes based on different signals received by the count mode selection terminal cnt3_dis.

[0147] Specifically, the reset signal terminal cnt3_rst of the third counter is connected to the output terminal of the first reset control unit 36. The count signal terminal cnt3_pulse of the third counter is connected to the count output terminal cnt_pulse1 of the first state maintainer. The count mode selection terminal cnt3_dis of the third counter is connected to the state output terminal cnt_rst1 of the first state maintainer Sig_Latch1.

[0148] When the counting mode selection terminal cnt3_dis of the third counter Count3 receives the first counting signal and the reset signal terminal cnt3_rst receives the first reset control signal, it is in a forward counting state. In this state, as the counting signal terminal cnt3_pulse receives the first counting pulse each time, the first accumulated number increases by 1.

[0149] When the counting mode selection terminal cnt3_dis of the third counter Count3 receives the first reset signal and the reset signal terminal cnt3_rst receives the first reset control signal, it is in a reverse counting state. In this state, as the counting signal terminal cnt3_pulse receives the first counting pulse each time, the first accumulated number decreases by 1 accordingly.

[0150] Alternatively, in the reverse counting state, the third counter Count3 may also be configured to keep the first accumulated number unchanged, that is, each time the counting signal terminal cnt3_pulse receives the first counting pulse, the first accumulated number remains unchanged.

[0151] When the reset signal terminal cnt3_rst of the third counter Count3 receives the second reset control signal, the reset function is executed to clear the first accumulated number and recalculate.

[0152] In addition, the third counter Count3 also has a comparison function, which can compare the first accumulated number with a pre-configured first threshold, and output an overload signal when the first accumulated number reaches the first threshold.

[0153] Therefore, through the above-mentioned first reset control unit and the third counter, when the first cycle interval occurs, the third counter can switch the pulse counting mode, and update the first cumulative number by subtracting the count value or keeping the count value unchanged. Only when the number of cycles in the interval of the first cycle (that is, the cumulative number of the third cycle) reaches the set third threshold, the reset processing is performed.

[0154] Such a flexible counting method helps to improve the control stability of overload protection and avoid the immediate clearing of the first cumulative number due to the first cycle interval. It is closer to the actual application scenario and reduces the impact of short-term fluctuations.

[0155] In other embodiments, please refer to Fig.13 The second protection module further includes: a second reset control unit 37. Accordingly, in the second counting unit 35, a fourth counter Count4 is used to replace the second counter Count2.

[0156] The second reset control unit 37 is connected to the second state maintainer Sig_Latch2, and determines the fourth cumulative number of consecutive fourth cycles according to the detection cycle detection signal output by the second reset control unit 37. The second reset control unit 37 also compares the fourth cumulative number with a pre-selected fourth threshold value, thereby generating a corresponding third reset control signal or a fourth reset control signal according to the comparison result.

[0157] Specifically, the fourth cycle refers to a detection cycle in which no overload signal appears. The third reset control signal is a signal output when the fourth cumulative number does not reach a preset fourth threshold. The fourth reset control signal is a signal output when the fourth cumulative number reaches a fourth threshold.

[0158] The fourth counter Count4 also has a reset signal terminal cnt4_rst, a counting mode selection terminal cnt4_dis, a counting signal terminal cnt4_pulse and an output terminal cnt4_flag. It separates the reset and clearing and the addition and subtraction control of the count value, and also has a comparison function, and outputs a valid signal when the second accumulated number reaches the second threshold.

[0159] Specifically, the reset signal terminal cnt4_rst of the fourth counter is connected to the output terminal of the second reset control unit 37. The count signal terminal cnt4_pulse of the fourth counter is connected to the count output terminal cnt_pulse2 of the second state maintainer. The count mode selection terminal cnt4_dis of the fourth counter is connected to the state output terminal cnt_rst2 of the second state maintainer Sig_Latch2.

[0160] When the counting mode selection terminal cnt4_dis of the fourth counter Count4 receives the second counting signal and the reset signal terminal cnt4_rst receives the third reset control signal, it is in a forward counting state. In this state, as the counting signal terminal cnt4_pulse receives the second counting pulse each time, the second accumulated number increases by 1.

[0161] When the counting mode selection terminal cnt4_dis of the fourth counter Count4 receives the second reset signal and the reset signal terminal cnt4_rst receives the third reset control signal, it is in a reverse counting state. In this state, as the counting signal terminal cnt4_pulse receives the second counting pulse each time, the second accumulated number decreases by 1 or remains unchanged.

[0162] When the reset signal terminal cnt4_rst of the fourth counter Count4 receives the fourth reset control signal, the reset function is executed to clear the second accumulated number and recalculate.

[0163] Also, please continue to read Fig.13 , the timing trigger end of the timer Tcount is connected to the output end cnt4_flag of the fourth counter Count4. When the timing trigger end receives the valid signal output by the fourth counter Count4, the timer Tcount starts timing and keeps outputting the overload protection signal to the switch control module 10 at the output end until the timing reaches the preset time threshold, the timer Tcount automatically resets, and stops outputting the overload protection signal olp_flag at the output end.

[0164] Therefore, through the above-mentioned second reset control unit and the fourth counter, when the second cycle interval occurs, the fourth counter can switch the pulse counting mode, and update the second cumulative number by subtracting the count value or keeping the count value unchanged. Only when the number of cycles in the interval between the second cycles (that is, the cumulative number of the fourth cycle) reaches the set fourth threshold, the reset processing is performed.

[0165] Such a flexible counting method helps to improve the control stability of overload protection and avoid the immediate clearing of the second cumulative number due to the second cycle interval. It is closer to the actual application scenario and reduces the impact of short-term fluctuations.

[0166] The embodiment of the present application also provides a specific implementation of the first reset control unit 36 ​​and the second reset control unit 37. Such a reset control unit can implement one or more of the aforementioned logic steps and form a corresponding reset control signal according to the received switching cycle detection signal or detection cycle detection signal.

[0167] like Fig.14 As shown, the first reset control unit 36 ​​includes: a first inverter inv1, a fifth counter Count5 and a third SR latch SR3.

[0168] The reset signal terminal cnt5_rst of the fifth counter Count5 is connected to the state output terminal cnt_rst1 of the first state maintainer through the first inverter inv1. The count signal terminal cnt5_pulse of the fifth counter Count5 is connected to the count output terminal cnt_pulse1 of the first state maintainer.

[0169] The set input terminal S of the third SR latch SR3 is connected to the output terminal cnt5_flag of the fifth counter. The reset input terminal R of the third SR latch SR3 is also connected to the state output terminal cnt_rst1 of the first state maintainer through the first inverter inv1. The non-inverting output terminal Q of the third SR latch SR3 is connected to the reset signal terminal cnt3_rst of the third counter.

[0170] During actual operation, when the state output terminal cnt_rst1 of the first state maintainer provides a first reset signal (indicating that no overcurrent protection signal is detected in the current switching cycle), the fifth counter Count5 starts to count pulses, and based on the first counting pulse received by the counting signal terminal cnt5_pulse, the third cumulative number is accumulated until the third cumulative number reaches a pre-configured third threshold value, and the fifth counter Count5 outputs a valid signal at the output terminal cnt5_flag.

[0171] When the valid signal output by the output terminal cnt5_flag of the fifth counter Count5 and the state output terminal cnt_rst1 of the first state maintainer provide a first reset signal to act on the third SR latch SR3 through the first inverter inv1, the non-inverting output terminal Q of the third SR latch SR3 outputs a second reset control signal to reset the third counter Count3.

[0172] In other embodiments, please refer to Fig.14 The second reset control unit 37 includes: a second inverter inv2, a sixth counter Count6 ​​and a fourth SR latch SR4.

[0173] The reset signal terminal cnt6_rst of the sixth counter Count6 ​​is connected to the state output terminal cnt_rst2 of the second state maintainer through the second inverter inv2. The count signal terminal cnt6_pulse of the sixth counter Count6 ​​is connected to the count output terminal cnt_pulse2 of the second state maintainer.

[0174] The set input terminal S of the fourth SR latch SR4 is connected to the output terminal cnt6_flag of the sixth counter. The reset input terminal R of the fourth SR latch SR4 is also connected to the state output terminal cnt_rst2 of the second state maintainer through the second inverter inv2. The non-inverting output terminal Q of the fourth SR latch SR4 is connected to the reset signal terminal cnt4_rst of the fourth counter.

[0175] During actual operation, when the state output terminal cnt_rst2 of the second state maintainer provides a second reset signal (indicating that no overload signal is detected in the current detection cycle), the sixth counter Count6 ​​starts to count pulses, and based on the second counting pulse received by the counting signal terminal cnt6_pulse, the fourth cumulative number is accumulated until the fourth cumulative number reaches the pre-configured fourth threshold value, and the sixth counter Count6 ​​outputs a valid signal at the output terminal cnt6_flag.

[0176] When the valid signal output by the output terminal cnt6_flag of the sixth counter Count6 ​​and the state output terminal cnt_rst2 of the second state maintainer provide a second reset signal to act on the fourth SR latch SR4 through the second inverter inv2, the non-inverting output terminal Q of the fourth SR latch SR4 outputs a fourth reset control signal to reset the fourth counter Count4.

[0177] Based on the control circuit provided by one or more of the above embodiments, the present application further provides a power factor correction circuit (PFC) using the above control circuit.

[0178] like Fig.15 As shown, the power factor correction circuit includes: the control circuit 100, the converter 200, the sampling circuit 300 and the driving circuit 400 as described above.

[0179] The converter 200 is a power converter for implementing voltage conversion. The converter 200 may be a converter of any suitable topology type. For example, Fig.15 The boost converter 200 includes a first switch tube S1 as a main switch tube, a boost inductor L, a boost diode D1, and an output capacitor, and other electronic devices, which can provide good power factor correction capability. Alternatively, as Fig.17 As shown, the converter 200 may also be a step-down (Buck) converter.

[0180] The sampling circuit 300 is a functional circuit for collecting sampling signals, which is connected to the converter 200 and the control circuit 100 respectively, collects one or more relevant parameters of the converter 200 during operation, and provides them to the control circuit 100 .

[0181] The sampling circuit 300 may be implemented in any suitable circuit form. For example, Fig.15 and Fig.16 2 shows a case where the sampling resistor Rcs is used as the sampling circuit 300 .

[0182] Alternatively, in addition to using a sampling circuit, the sampling circuit 300 may also use a current sensor or other suitable types of current sampling circuits.

[0183] The driving circuit 400 is a functional circuit for converting the switch control signal drv output by the control circuit 100 into a driving signal DRV sufficient to drive the switch of the converter to turn on and off. It is connected to the control circuit 100 and the first switch S1 respectively, and after converting the switch control signal provided by the control circuit into a control signal for driving the first switch to turn off or on, it drives the first switch to turn on and off.

[0184] In some embodiments, the sampling circuit 300 is a sampling circuit for collecting the inductor current of the converter. Fig.15 As shown, the sampling circuit RS1 can form a first voltage signal proportional to the inductor current and provide it to the control circuit 100, so that the control circuit 100 can implement the overload protection and overcurrent protection functions described in one or more of the above embodiments.

[0185] Alternatively, the sampling circuit 300 is a sampling circuit for collecting the current of the first switch tube. Fig.16 As shown, the sampling circuit RS2 can generate a second voltage signal proportional to the current of the first switch tube and provide it to the control circuit 100, so that the control circuit 100 can implement the overload protection and overcurrent protection functions described in one or more of the above embodiments.

[0186] In the present application, for the convenience of description, a first sampling circuit is used to represent a sampling circuit for collecting inductor current, and a second sampling circuit is used to represent a sampling circuit for collecting first switch tube current.

[0187] In some other embodiments, the power factor correction circuit further includes: an input voltage sampling circuit. The input voltage sampling circuit is a functional circuit for collecting the AC input voltage, and can form a third voltage signal corresponding to the AC input voltage of the power factor correction circuit.

[0188] In the case where the power factor correction circuit includes an input voltage sampling circuit or has an input voltage sampling function, such as Fig.18 As shown, the control circuit 100 receives the third voltage signal vin_sns corresponding to the AC input voltage, and obtains the detection reference signal line_pulse whose detection period is synchronized with the half-wave period of the AC input voltage. This setting does not require the use of the detection period generation unit 33 described in one or more of the above embodiments, and the detection period generation unit 33 is omitted.

[0189] It should be understood that based on one or more embodiments disclosed in the present application, those skilled in the art can, in practical applications, adapt different types of sampling circuits and converters of different topologies by adjusting and configuring the control circuit 100 according to different application scenarios.

[0190] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Under the concept of the present application, the technical features in the above embodiments or different embodiments may also be combined, the steps may be implemented in any order, and there are many other changes in different aspects of the present application as described above, which are not provided in detail for the sake of simplicity. Although the present application has been described in detail with reference to the aforementioned embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A control circuit, characterized in that: include: A switch control module is configured to: generate a switch control signal, wherein the switch control signal is used to control a first switch of the converter; The first protection module is configured to: generate an overcurrent protection signal when the received sampling signal reaches a preset overcurrent protection threshold; A second protection module is configured to: determine a first cumulative number of a first cycle, and generate an overload signal when the first cumulative number reaches a preset first threshold; determining a second accumulated number of a second cycle, and generating an overload protection signal when the second accumulated number reaches a preset second threshold; Wherein, the first cycle is the switching cycle in which the overcurrent protection signal appears; the second cycle is the detection cycle in which the overload signal appears; the detection cycle is greater than or equal to half of the power frequency cycle; The switch control module is further configured to generate a switch tube control signal for controlling the first switch tube to turn off when receiving the overcurrent protection signal or the overload protection signal.

2. The control circuit according to claim 1, characterized in that: The second protection module comprises: The first detection unit is configured to: receive the switch tube control signal, and output a corresponding switch cycle detection signal according to the detection result of the overcurrent protection signal in each switch cycle; A first counting unit is configured to: update the first accumulated number according to the received switching cycle detection signal, and generate the overload signal when the first accumulated number reaches the first threshold; A detection period generating unit is configured to: generate a detection reference signal; the detection period is defined by the detection reference signal; The second detection unit is configured to: receive the detection reference signal, and output a corresponding detection cycle detection signal according to the detection result of the overload signal in each detection cycle; The second counting unit is configured to: update the second accumulated number according to the received detection cycle detection signal, and generate the overload protection signal when the second accumulated number reaches the second threshold.

3. The control circuit according to claim 2, characterized in that: The switching cycle detection signal includes: a first counting signal, a first reset signal and a first counting pulse; the first detection unit includes: a first state maintainer; Wherein, the detection input end of the first state maintainer is connected to the first protection module, the time input end of the first state maintainer is connected to the switch control module, and the state output end and the counting output end of the first state maintainer are both connected to the first counting unit; The first state maintainer is configured to: determine the opening time and closing time of the first switch tube according to the switch tube control signal received by the time input terminal; At the start-up time, resetting to the first state; When the detection input terminal receives the overcurrent protection signal, switching to the second state; At the closing time, acquiring the current state of the first state maintainer, and outputting a first counting pulse at the counting output terminal; When the current state is the first state, continuously outputting the first reset signal at the state output terminal; When the current state is the second state, the first counting signal is continuously outputted at the state output terminal.

4. The control circuit according to claim 3, characterized in that: The first counting unit comprises: a first counter; Wherein, the reset signal terminal of the first counter is connected to the state output terminal of the first state maintainer, and the count signal terminal of the first counter is connected to the count output terminal of the first state maintainer; The first counter is configured to: when the first counting signal is received at the reset signal terminal, control the first accumulated number to increase as the first counting pulse is received; When the reset signal terminal receives the first reset signal, clearing the first accumulated number; When the first accumulated number reaches the first threshold, the overload signal is output and the first accumulated number is cleared.

5. The control circuit according to claim 3, characterized in that: The detection cycle detection signal includes: a second counting signal, a second reset signal and a second counting pulse; the second detection unit includes: a second state maintainer; Wherein, the detection input terminal of the second state maintainer is connected to the first counting unit, the time input terminal of the second state maintainer is connected to the detection cycle generating unit, and the state output terminal and the counting output terminal of the second state maintainer are both connected to the second counting unit; The second state maintainer is configured to: determine the start time and the end time of the detection cycle according to the detection reference signal received by the time input terminal; At the starting time, resetting to the first state; When the detection input terminal receives the overload signal, switching to the second state; At the end time, acquiring the current state of the second state maintainer, and outputting a second counting pulse at the counting output terminal; When the current state is the first state, continuously outputting the second reset signal at the state output terminal; When the current state is the second state, the second counting signal is continuously outputted at the state output terminal.

6. The control circuit according to claim 5, characterized in that: The second counting unit includes: a second counter and a timer; Wherein, the reset signal terminal of the second counter is connected to the state output terminal of the second state maintainer, and the count signal terminal of the second counter is connected to the count output terminal of the second state maintainer; The output end of the second counter is connected to the timing trigger end of the timer, the output end of the timer is connected to the switch control module, and the output end of the timer is also connected to the reset ends of the first state maintainer and the second state maintainer; The second counter is configured to: when the reset signal terminal receives the second counting signal, control the second accumulated number to increase each time the counting signal terminal receives the second counting pulse; When the reset signal terminal receives the second reset signal, clearing the second accumulated number to zero; and When the second accumulated number reaches the second threshold, outputting the overload trigger signal; The timer is configured to: output the overload protection signal when the timing trigger end receives the overload trigger signal, and stop outputting the overload protection signal when the output time of the overload protection signal reaches a preset time threshold; The first state maintainer and the second state maintainer are further configured to reset to the first state when the reset end receives the overload protection signal.

7. The control circuit according to claim 5, characterized in that: The first state maintainer includes: a first rising edge detector, a first falling edge detector, a first SR latch and a first D-type latch; the second state maintainer includes: a second rising edge detector, a second falling edge detector, a second SR latch and a second D-type latch; Wherein, the first rising edge detector generates a first detection pulse in response to the occurrence of a rising edge of the switch tube control signal; the first falling edge detector generates a first counting pulse in response to the occurrence of a falling edge of the switch tube control signal; The second rising edge detector generates a second detection pulse in response to the occurrence of a rising edge of the detection reference signal; the second falling edge detector generates a second counting pulse in response to the occurrence of a falling edge of the detection reference signal; The reset input terminal of the first SR latch is connected to the first rising edge detector for receiving the first detection pulse; the set input terminal of the first SR latch is connected to the first protection module for receiving the overcurrent protection signal; The non-inverting output terminal of the first SR latch is connected to the data input terminal of the first D-type latch; the sampling terminal of the first D-type latch is connected to the first falling edge detector for receiving the first counting pulse; The inverting output terminal of the first D-type latch is connected to the state output terminal of the first state maintainer; the output terminal of the first falling edge detector is connected to the counting output terminal of the first state maintainer; The reset input terminal of the second SR latch is connected to the second rising edge detector for receiving the second detection pulse; the set input terminal of the second SR latch is connected to the output terminal of the first counter for receiving the overload signal; The non-inverting output terminal of the second SR latch is connected to the data input terminal of the second D-type latch; the sampling terminal of the second D-type latch is connected to the second falling edge detector for receiving the second counting pulse; The inverting output terminal of the second D-type latch is connected to the state output terminal of the second state maintainer; and the output terminal of the second falling edge detector is connected to the counting output terminal of the second state maintainer.

8. The control circuit according to claim 5, characterized in that: The second protection module further includes: a first reset control unit and a second reset control unit; the first counting unit includes: a third counter; the second counting unit includes: a fourth counter and a timer; The first reset control unit is connected to the state output terminal and the count output terminal of the first state maintainer, the count mode selection terminal of the third counter is connected to the state output terminal of the first state maintainer, the count signal terminal of the third counter is connected to the count output terminal of the first state maintainer; the reset signal terminal of the third counter is connected to the output terminal of the first reset control unit; The second reset control unit is connected to the state output terminal and the count output terminal of the second state maintainer, the count mode selection terminal of the fourth counter is connected to the state output terminal of the second state maintainer, the count signal terminal of the fourth counter is connected to the count output terminal of the second state maintainer; the reset signal terminal of the fourth counter is connected to the output terminal of the second reset control unit The output end of the fourth counter is connected to the timing trigger end of the timer, the output end of the timer is connected to the switch control module, and the output end of the timer is also connected to the reset ends of the first state maintainer and the second state maintainer; The first reset control unit is configured as follows: Determine, according to the switching cycle detection signal, a third cumulative number of consecutive occurrences of a third cycle, wherein the third cycle is a switching cycle in which the overcurrent protection signal does not appear; When the third accumulated number does not reach a preset third threshold, output a first reset control signal, and when the third accumulated number reaches the third threshold, output a second reset control signal; The second reset control unit is configured as follows: determining, according to the detection cycle detection signal, a fourth cumulative number of consecutive occurrences of a fourth cycle, wherein the fourth cycle is a detection cycle in which the overload signal does not appear; When the fourth accumulated number does not reach a preset fourth threshold, output a third reset control signal, and when the fourth accumulated number reaches the fourth threshold, output a fourth reset control signal; The third counter is configured as: When the reset signal terminal receives the first reset control signal and the counting mode selection terminal receives the first counting signal, controlling the first accumulated number to increase as the first counting pulse is received; When the reset signal terminal receives the first reset control signal and the counting mode selection terminal receives the first reset signal, controlling the first accumulated number to decrease or remain unchanged as the first counting pulse is received; When the reset signal terminal receives the second reset control signal, clearing the first accumulated number; When the first accumulated number reaches the first threshold, the overload signal is output and the first accumulated number is cleared. The fourth counter is configured as: When the reset signal terminal receives the third reset control signal and the counting mode selection terminal receives the second counting signal, controlling the second accumulated number to increase as the second counting pulse is received; When the reset signal terminal receives the third reset control signal and the counting mode selection terminal receives the second reset signal, controlling the second accumulated number to decrease or remain unchanged as the second counting pulse is received; When the reset signal terminal receives the fourth reset control signal, clearing the second accumulated number; When the second accumulated number reaches the second threshold, outputting an overload trigger signal; The timer is configured to: output the overload protection signal when the timing trigger end receives the overload trigger signal, and stop outputting the overload protection signal when the output time of the overload protection signal reaches a preset time threshold; The first state maintainer and the second state maintainer are further configured to reset to the first state when the reset end receives the overload protection signal.

9. The control circuit according to claim 8, characterized in that: The first reset control unit includes: a first inverter, a fifth counter and a third SR latch; the second reset control unit includes: a second inverter, a sixth counter and a fourth SR latch; Wherein, the reset signal terminal of the fifth counter is connected to the state output terminal of the first state maintainer through the first inverter; the count signal terminal of the fifth counter is connected to the count output terminal of the first state maintainer; The set input terminal of the third SR latch is connected to the output terminal of the fifth counter; the reset input terminal of the third SR latch is also connected to the state output terminal of the first state maintainer through the first inverter; the non-inverting output terminal of the third SR latch is connected to the reset signal terminal of the third counter; The reset signal terminal of the sixth counter is connected to the state output terminal of the second state maintainer through the second inverter; the count signal terminal of the sixth counter is connected to the count output terminal of the second state maintainer; The set input terminal of the fourth SR latch is connected to the output terminal of the sixth counter; the reset input terminal of the fourth SR latch is also connected to the state output terminal of the second state maintainer through the second inverter; the non-inverting output terminal of the fourth SR latch is connected to the reset signal terminal of the fourth counter.

10. A power factor correction circuit, characterized in that: include: A converter, the converter comprising: a first switch tube and an inductor; The control circuit according to any one of claims 1 to 9; a current sampling circuit, the current sampling circuit being connected to the control circuit and the converter respectively; and A driving circuit is connected to the control circuit and the first switch tube respectively, and is configured to: convert a switch tube control signal provided by the control circuit into a control signal that drives the first switch tube to turn off or on.

11. The power factor correction circuit according to claim 10, characterized in that: The current sampling circuit includes: a first current sampling circuit configured to: form a first voltage signal proportional to the inductor current.

12. The power factor correction circuit according to claim 10, characterized in that: The current sampling circuit includes: a second current sampling circuit configured to: form a second voltage signal proportional to the current of the first switch tube.

13. The power factor correction circuit according to claim 10, characterized in that: The converter includes: a boost converter or a buck converter; the first switch tube includes: a high-side drive switch tube or a low-side drive switch tube.

14. The power factor correction circuit according to claim 10, characterized in that: Also included is: an input voltage sampling circuit configured to: form a third voltage signal corresponding to the AC input voltage of the power factor correction circuit; Wherein, the input voltage sampling circuit is connected to the control circuit so that the detection cycle of the control circuit is synchronized with the half-wave cycle of the AC input voltage.

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