DC-DC converter based on ripple control

Abstract

The invention provides a DC-DC converter based on ripple control. The DC-DC converter comprises an output circuit, a ripple voltage generation circuit, a PWM logic circuit, a fixed conduction time control circuit, a driving circuit and a ripple compensation circuit. Wherein the ripple compensation circuit can calculate the amplitude of the ripple and generate two paths of current in direct proportion to the amplitude of the ripple, the current enters the loop to respectively adjust the gain of the amplifier in the voltage loop and the gain of the amplifier in the ripple loop, and when the amplitude of the ripple becomes large, the gain of the amplifier in the voltage loop becomes large, and the gain of the amplifier in the ripple loop becomes small. When the ripple amplitude becomes small, the gain of the amplifier in the voltage loop becomes small, and the gain of the amplifier in the ripple loop becomes large. Changes in gain of the amplifiers in the voltage loop and the ripple loop can adjust changes in ripple amplitude. Therefore, the amplitude of the equivalent ripples entering the loop is relatively stable, so that the stability of the converter is optimized. And meanwhile, the transient response and the Jitter effect can be improved due to the relatively stable ripple amplitude.

Description

Technical Field

[0001] The present application relates to the technical field of DC-DC (direct current to direct current) converters, and in particular to a DC-DC converter based on ripple control. Background Art

[0002] DC-DC (direct current to direct current) converters have been widely used in many technical fields such as automotive electronics, industrial control, smart home, new energy, medical equipment, aerospace, etc., providing buck, boost and buck-boost functions for various circuits. DC-DC circuits with fixed on-time or off-time control based on ripple control are popular because of their fast response speed and simple control loop.

[0003] In a ripple control loop technology known to the applicant, a ripple control signal is generated based on the input voltage and the output voltage. The input voltage is generated by a resistor Rripple connected to SW (the SW voltage is substantially equal to the input after the first transistor is turned on) and connected to the control loop, or the input voltage and the output voltage are connected to the control loop through a transconductance amplifier. When the input voltage and the output voltage change, the current through the resistor Rripple changes or the output current of the transconductance amplifier connected to the input voltage and the output voltage changes. This current charges the capacitor when PWM is high and discharges the capacitor when PWM is low. The charging current is proportional to the difference between the input voltage and the output voltage, and the discharge current is proportional to the output voltage.

[0004] This technology is widely used because the circuit is simple and easy to implement, but the amplitude of the ripple will change with the input voltage and output voltage. When the ripple voltage is too low, the control loop bandwidth becomes larger, and the system noise and high-frequency poles enter the loop, causing system instability. If the ripple voltage is too high, the control loop bandwidth becomes smaller, the loop phase margin also becomes smaller, and there are also system stability problems. At the same time, the smaller bandwidth will cause the transient response to deteriorate. It is not expected to see the ripple amplitude is too small, too large or too small. When the ripple amplitude is too small, the noise and high-frequency poles will produce greater jitter and make the system more unstable; when the ripple amplitude is too large, the phase margin of the control loop will decrease, and the loop stability will also be reduced. As mentioned earlier, the ripple amplitude is affected by the input voltage and output voltage, and it is also difficult to optimize the transient response and jitter. In order to ensure a small ripple amplitude in the worst case, the transient response performance deteriorates when the ripple amplitude increases. Summary of the invention

[0005] In view of this, the present application proposes a DC-DC converter based on ripple control to solve at least one technical problem mentioned in the background technology. The converter effectively improves the stability and transient response of the ripple control loop.

[0006] The first aspect of the embodiment of the present application provides a DC-DC converter based on ripple control, including an output circuit, a ripple voltage generating circuit, a PWM logic circuit, a fixed on-time control circuit, a driving circuit, and a ripple compensation circuit, wherein the ripple compensation circuit further includes a voltage loop, a ripple loop, a ripple calculation circuit, and a comparator. The output circuit is used to convert the input voltage into an output voltage, and includes a voltage input terminal VIN, a voltage output terminal VOUT, a first transistor M1, a second transistor M2, an inductor L, and a capacitor COUT. The ripple voltage generating circuit is used to sample the current of the inductor L in the output circuit to generate a ripple voltage. Exemplarily, the voltage output terminal VIN charges the capacitor CRN and Cripple through VSW (M1 is turned on) to generate a ripple voltage. The PWM logic circuit is used to generate and output a PWM signal. The fixed on-time control circuit forms a loop with the PWM logic circuit, which is used to generate and provide a fixed on-time control signal to the PWM logic circuit to control the PWM logic circuit to output a low level. The driving circuit is used to generate a first driving signal and a second driving signal according to the high level and the low level of the input of the PWM logic circuit, and the first driving signal and the second driving signal respectively drive the first transistor M1 and the second transistor M2 to be alternately turned on and off. The ripple calculation circuit is used to generate a first gain current GAINA*IB_ADJ and a second gain current GAINB*IB_ADJ based on the input voltage VIN and the output voltage VOUT, and input the first gain current GAINA*IB_ADJ to the voltage loop, and input the second gain current GAINB*IB_ADJ to the ripple loop. A voltage loop, comprising a first transconductance amplifier GMripple connected to a ripple voltage generating circuit; a ripple loop, comprising a second transconductance amplifier GMFB connected to a control voltage VC and a feedback voltage VFB; wherein the first transconductance amplifier GMripple and the second transconductance amplifier GMFB are respectively used to connect a first tail current source IBP1 and a second tail current source IBP2, the first tail current source IBP1 is suitable for superimposing with the first gain current GAINA*IB_ADJ to output a first current IB1 at the output end of the voltage loop, and the second tail current source IBP2 is suitable for superimposing with the second gain current GAINB*IB_ADJ to output a second current IB2 at the output end of the ripple loop; a comparator, one input end of which is connected to the output ends of the voltage loop and the ripple loop, the other input end is grounded, and the output end of which is connected to the PWM logic circuit, and is used to control the PWM logic circuit to output the high level.

[0007] In a possible implementation, the ripple calculation circuit includes a first transconductance circuit and a second transconductance circuit, which are respectively connected to the voltage input terminal VIN and the voltage output terminal VOUT, and are used to generate a first related current I_AJ1 and a second related current I_AJ2 based on the input voltage and the output voltage, respectively; a minimum current selection circuit, which is connected to the first transconductance circuit and the second transconductance circuit, and is used to select the minimum current I_MIN between the first related current I_AJ1 and the second related current I_AJ2; and a current correction circuit, which is connected to the minimum current selection circuit, and is used to correct the minimum current I_MIN to generate and output the first gain current GAINA*IB_ADJ and the second gain current GAINB*IB_ADJ.

[0008] It also includes an error amplifier gain circuit, which is used to generate a first voltage and a second voltage based on the first current IB1 and the second current IB2 and provide them to the error amplification signal comparator; the error amplification signal comparator outputs a high-level signal to generate a control PWM signal based on the first voltage and the second voltage, and provides it to the set terminal S of the PWM logic circuit.

[0009] In a possible implementation manner, the first transconductance circuit includes a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6 and a fourth resistor R4; wherein the fourth resistor R4 is connected between the sources of the third transistor M3 and the fourth transistor M4, the gate of the third transistor M3 is connected to the voltage input terminal VIN, the gate of the fourth transistor M4 is connected to the voltage output terminal VOUT, the drains of the fifth transistor M5 and the sixth transistor M6 are respectively connected to the two ends of the fourth resistor R4, the drains of the third transistor M3 and the fourth transistor M4 and the gates and drains of the fifth transistor M5 and the sixth transistor M6 are respectively grounded through current sources I3 and I4; the second transconductance circuit includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10 and a fifth resistor R5; wherein the fifth resistor R5 is connected between the sources of the seventh transistor M7 and the eighth transistor M8, the gate of the seventh transistor M7 is connected to the voltage output terminal VOUT, the gate of the eighth transistor M8 is grounded, the drains of the tenth transistor M10 and the ninth transistor M9 are respectively connected to the two ends of the fifth resistor R5, the drains of the seventh transistor M7 and the eighth transistor M8 and the gates and drains of the tenth transistor M10 and the ninth transistor M9 are respectively grounded through current sources I7 and I8; the drain currents of the sixth transistor M6 and the ninth transistor M9 are respectively the first related current I_AJ1 and the second related current I_AJ2.

[0010] In a possible implementation, the minimum current selection circuit includes an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, and a fourteenth transistor M14; wherein, the gates of the eleventh transistor M11 and the fourteenth transistor M14 are connected to the gate of the sixth transistor M6, the gates of the twelfth transistor M12 and the thirteenth transistor M13 are connected to the gate of the ninth transistor M9, the source of the eleventh transistor M11 is connected to the drain of the thirteenth transistor M13, and the source of the twelfth transistor M12 is connected to the drain of the fourteenth transistor M14; the minimum current selection circuit is used to select the minimum current I_MIN from the first related current I_AJ1 and the second related current I_AJ2.

[0011] In a possible implementation, the current correction circuit includes a first mirror circuit and a second mirror circuit; wherein the first mirror circuit includes a fifteenth transistor M15, a sixteenth transistor M16 and a nineteenth transistor M19 whose gates are connected, the sources of the fifteenth transistor M15, the sixteenth transistor M16 and the nineteenth transistor M19 are all connected to a power supply, the drain of the fifteenth transistor M15 is connected to the drains of the eleventh transistor M11 and the twelfth transistor M12, and the drain of the nineteenth transistor M19 is used to output the first gain current GAINA*IB_ADJ; wherein the second mirror circuit includes a seventeenth transistor M17 and an eighteenth transistor M18 whose sources are both grounded; the gates of the seventeenth transistor M17 and the eighteenth transistor M18 and the drain of the seventeenth transistor M17 are all connected to the drain of the sixteenth transistor M16, and the drain of the eighteenth transistor M18 is used to output the second gain current GAINB*IB_ADJ.

[0012] In a possible implementation, the voltage loop includes a twentieth transistor M20 and a twenty-first transistor M21 whose sources are connected to the drain of the nineteenth transistor M19 and the first tail current source IBP1, and the gates of the twentieth transistor M20 and the twenty-first transistor M21 are respectively used to obtain the feedback voltage VFB and the control voltage VC, and the drains of the twentieth transistor M20 and the twenty-first transistor M21 are respectively grounded through the sixth resistor R6 and the seventh resistor R7; the ripple loop includes a twenty-second transistor M22 and a twenty-third transistor M23 whose sources are connected to the drain of the eighteenth transistor M18 and the second tail current source IBP2, and the gates of the twenty-second transistor M22 and the twenty-third transistor M23 are respectively used to obtain the a ripple voltage VRN and a second ripple voltage VRP, wherein the ripple loop obtains the first ripple voltage VRN from between the second resistor RRN and the first capacitor CRN, and obtains the second ripple voltage VRP from between the first resistor Rripple and the second capacitor Cripple; the DC-DC converter also includes an error amplifier gain circuit and a comparison error amplification signal comparator, the error amplifier gain circuit includes a sixth resistor R6 and a seventh resistor R7 grounded, two input ends of the comparison error amplification signal comparator are respectively connected to the drain of the twenty-third transistor M23 and the twenty-second transistor M22, the drain of the twenty-second transistor M22 and the twenty-first transistor M21, and its output end is connected to the S end of the PWM logic circuit.

[0013] In a possible implementation manner, the ripple voltage generating circuit includes a first resistor Rripple, a second resistor R RN , the first capacitor C RN and a second capacitor Cripple, wherein the first resistor Rripple, the second resistor R RN and the first capacitor C RN The first resistor Rripple is connected in series and then grounded. The first resistor Rripple is also connected to the source of the first transistor M1. The second capacitor Cripple is connected to the second resistor R RN and the first capacitor C RN Connect in parallel and then ground.

[0014] In a possible implementation, the ripple loop is used to generate a voltage from the second resistor R RN and the first capacitor C RN Get the first ripple voltage V RN , and obtaining a second ripple voltage V between the first resistor Rripple and the second capacitor Cripple RP , and based on the first ripple voltage V RN and the second ripple voltage V RP The second current IB2 is generated.

[0015] In a possible implementation, the fixed on-time control circuit includes a second comparator, a first input terminal of which is connected to the voltage output terminal VOUT, and an output terminal of which is connected to the R terminal of the PWM logic circuit, a second input terminal of the second comparator is connected to the voltage input terminal, and the second input terminal is also connected to the Q' terminal of the PWM logic circuit through a control loop; the control loop includes a switch controlled by the Q' terminal, a first terminal of the switch and a second input terminal of the second comparator are connected to the voltage input terminal through a current source of K*VIN, a first terminal of the switch is connected to the second input terminal of the second comparator, the second terminal is grounded, and the third capacitor CTON is connected in parallel with the switch S1.

[0016] In a possible implementation manner, the S terminal of the PWM logic circuit is connected to the comparator output terminal, and the Q terminal of the PWM logic circuit is connected to the driving circuit.

[0017] Compared with the prior art, the embodiment of the present application adds a brand-new ripple compensation circuit. The ripple compensation circuit can calculate the ripple amplitude and generate two currents proportional to the ripple amplitude (i.e., the first gain current GAINA*IB_ADJ and the second gain current GAINB*IB_ADJ). The first gain current GAINA*IB_ADJ and the second gain current GAINB*IB_ADJ will be respectively included in the voltage loop and the ripple loop to adjust the gains of the two loops. Among them, when the ripple amplitude increases, the adjustment gain in the voltage loop increases, and the adjustment gain in the ripple loop decreases; when the ripple amplitude decreases, the adjustment gain in the voltage loop decreases, and the adjustment gain in the ripple loop increases. The changes in the gains in the voltage loop and the ripple loop can further adjust the changes in the ripple amplitude. Therefore, the loop stability within the range of the applied input voltage VIN and the output voltage VOUT can be guaranteed, as well as a good transient response.

[0018] The ripple compensation circuit in the embodiment of the present application can calculate the ripple amplitude under different input voltage VIN and output voltage VOUT configurations, and compensate for the change of the ripple amplitude in the loop. The ripple amplitude is fixed, which is conducive to improving the loop stability of the converter, and does not affect the transient response of the system, and can effectively avoid the Jitter phenomenon to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present application and the technical solutions in the prior art, the drawings required for use in the embodiments and the description of the prior art will be briefly introduced below. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0020] Figure 1 A circuit diagram of a ripple control loop of a DC-DC converter according to an embodiment of the present application; Figure 2 A circuit diagram of a ripple calculation circuit in one embodiment of the present application; Figure 3 A circuit diagram of a part of the ripple compensation circuit in one embodiment of the present application; Figure 4 In one embodiment of the present application, a curve showing the relationship between the ripple amplitude and the input voltage VIN and VOUT, and a curve showing the relationship between the compensated current and the input voltage and output voltage VOUT. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Generally, the components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0022] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0023] The present application shall prevail for matters that are clearly stated in the present application specification, or that can be concluded or inferred without doubt based on the present application specification. For matters that are not elaborated in detail in the present application specification, those skilled in the art may refer to the prior art or known technology in the field for understanding, which does not require creative thinking or labor.

[0024] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not require further definition and explanation in subsequent drawings.

[0025] In addition, the terms "first", "second", etc., if used, are merely used to distinguish and describe, and should not be understood as indicating or implying relative importance.

[0026] It should be noted that, in the absence of conflict, the features in the embodiments of the present application can be combined with each other.

[0027] like Figure 1, which is a circuit diagram of a DC-DC converter based on ripple control provided by an embodiment of the present application. As shown in the figure, the circuit includes an output circuit 110, a ripple voltage generating circuit 120, a PWM logic circuit 130, a fixed on-time control circuit 140, a driving circuit 150, and a ripple compensation circuit 160, wherein the ripple compensation circuit 160 further includes a voltage loop 162, a ripple loop 164, a ripple calculation circuit 166, and a comparator 168.

[0028] The output circuit 110 is used to convert an input voltage into an output voltage, and includes a voltage input terminal VIN, a voltage output terminal VOUT, a first transistor M1, a second transistor M2, an inductor L, and a capacitor COUT.

[0029] The ripple voltage generating circuit 120 is used to generate a ripple voltage related to the input voltage and the output voltage. Specifically, it is used to sample the input voltage and the output voltage of the voltage input terminal VIN and the voltage output terminal VOUT in the output circuit 110 to generate a ripple voltage. The PWM logic circuit 130 is used to generate and output a PWM signal.

[0030] The fixed on-time control circuit 140 forms a loop with the PWM logic circuit 130 for generating and providing a fixed on-time control signal to the PWM logic circuit 130 to control the PWM logic circuit 130 to output a low level.

[0031] The driving circuit 150 is used to generate a first driving signal and a second driving signal according to the high level and the low level of the input of the PWM logic circuit, and the first driving signal and the second driving signal respectively drive the first transistor M1 and the second transistor M2 to be alternately turned on and off.

[0032] The ripple compensation circuit 160 includes a ripple calculation circuit 166, a voltage loop 162, a ripple loop 164 and a comparator 168.

[0033] The ripple calculation circuit 166 is used to generate a first gain current GAINA*IB_ADJ and a second gain current GAINB*IB_ADJ based on the input voltage and the output voltage, and input the first gain current GAINA*IB_ADJ to the voltage loop and the second gain current GAINB*IB_ADJ to the voltage loop and the ripple loop.

[0034] The voltage loop 162 includes a first transconductance amplifier GMripple connected to a ripple voltage generating circuit; the ripple loop 164 includes a second transconductance amplifier GMFB connected to a control voltage VC and a feedback voltage VFB; wherein the first transconductance amplifier GMripple and the second transconductance amplifier GMFB are respectively used to connect to a first tail current source IBP1 and a second tail current source IBP2, the first tail current source IBP1 is suitable for superimposing with a first gain current GAINA*IB_ADJ to output a first current IB1 at the output end of the voltage loop, and the second tail current source IBP2 is suitable for superimposing with a second gain current GAINB*IB_ADJ to output a second current IB2 at the output end of the ripple loop.

[0035] One input terminal of the comparator 168 is connected to the output terminals of the voltage loop and the ripple loop, the other input terminal is grounded, and the output terminal is connected to the PWM logic circuit to control the PWM logic circuit to output a high level. Figure 1-3 , and the following description of the ripple compensation circuit 160 and the comparator 168. Compared with the prior art, the embodiment of the present application adds a brand-new ripple compensation circuit. The ripple compensation circuit can calculate the ripple amplitude and generate two currents proportional to the ripple amplitude (i.e., the first gain current GAINA*IB_ADJ and the second gain current GAINB*IB_ADJ). The first gain current GAINA*IB_ADJ and the second gain current GAINB*IB_ADJ will be respectively included in the voltage loop and the ripple loop to adjust the gains of the two loops respectively. Among them, when the ripple amplitude increases, the adjustment gain in the voltage loop increases, and the adjustment gain in the ripple loop decreases; when the ripple amplitude decreases, the adjustment gain in the voltage loop decreases, and the adjustment gain in the ripple loop increases. The changes in the gains in the voltage loop and the ripple loop can further adjust the changes in the ripple amplitude. Therefore, the loop stability within the range of the applied input voltage VIN and the output voltage VOUT can be guaranteed, as well as a good transient response.

[0036] The ripple compensation circuit in the embodiment of the present application can calculate the ripple amplitude under different input voltage VIN and output voltage VOUT configurations, and compensate for the change of the ripple amplitude in the loop. The ripple amplitude is fixed, which is conducive to improving the loop stability of the converter, and does not affect the transient response of the system, and can effectively avoid the Jitter phenomenon to a certain extent.

[0037] Continue reading Figure 1 The ripple voltage generating circuit 120 includes a first resistor Rripple, a second resistor R RN , the first capacitor C RN and the second capacitor Cripple, wherein the first resistor Rripple, the second resistor R RN and the first capacitor CRN The first resistor Rripple is also connected to the source of the first transistor M1, and the second capacitor Cripple is connected to the second resistor R RN and the first capacitor C RN Connect in parallel and then ground.

[0038] The ripple loop 164 is used to generate a voltage from the second resistor R RN and the first capacitor C RN Get the first ripple voltage V RN , and obtain a second ripple voltage V between the first resistor Rripple and the second capacitor Cripple RP , and based on the first ripple voltage V RN and the second ripple voltage V RP Generate a second tail current source IBP2. Specifically, based on the first ripple voltage V RN and the second ripple voltage V RP The difference generates the tail current flow.

[0039] The voltage loop 162 is used to generate the first tail current source IBP1 based on the difference between the control voltage VC and the output voltage VOUT. Specifically, the control voltage VREF and the feedback voltage VFB are connected to a comparator, which outputs the control voltage VC, and then the control voltage VC and the output voltage VOUT are input to the voltage loop 162.

[0040] In the embodiment shown in the figure, the voltage loop 162 and the ripple loop 164 respectively include a second transconductance amplifier GMFB and a first transconductance amplifier GMripple, a control voltage VC and an output voltage VOUT, a first ripple voltage V RN and the second ripple voltage V RP They are their respective input terminals, and their output terminals output the aforementioned first tail current source IBP1 and second tail current source IBP2.

[0041] The first gain current GAINA*IB_ADJ and the second gain current GAINB*IB_ADJ are respectively connected to the output ends of the first transconductance amplifier GMripple and the second transconductance amplifier GMFB, and the first gain current GAINA*IB_ADJ and the second gain current GAINB*IB_ADJ are respectively superimposed on the tail currents output by the two transconductance amplifiers to generate the first current IB1 and the second current IB2.

[0042] The voltage loop 162 and the ripple loop 164 are connected to the same input terminal of the comparator 168 through the output terminals of the first transconductance amplifier GMripple and the second transconductance amplifier GMFB.

[0043] The PWM logic circuit includes two input terminals, S and R, and two output terminals, Q and Q'. The S terminal of the PWM logic circuit 130 is connected to the output terminal of the comparator 168, and the Q terminal of the PWM logic circuit 130 is connected to the driving circuit 150. The Q terminal outputs a corresponding signal based on the signal obtained from the comparator 168 and the fixed on-time control circuit 140 to control the driving circuit to output a high level or a low level.

[0044] The fixed on-time control circuit 140 includes a second comparator, a first input terminal of which is connected to the voltage output terminal VOUT, and an output terminal of which is connected to the R terminal of the PWM logic circuit. The second input terminal of the second comparator is connected to the voltage input terminal, and the second input terminal is also connected to the Q' terminal of the PWM logic circuit through the control loop; the control loop includes a switch controlled by the Q' terminal, a first terminal of the switch is connected to the second input terminal of the second comparator, a second terminal of the switch is grounded, and a third capacitor CTON is connected in parallel with the switch S1.

[0045] like Figure 2 FIG. 1 is a schematic diagram of a ripple calculation circuit 166 in one embodiment of the present application. Figure 2 As shown, the ripple calculation circuit 166 includes a first transconductance circuit 1661 , a second transconductance circuit 1662 , a minimum current selection circuit 1663 and a current correction circuit 1664 .

[0046] The first transconductance circuit 1661 and the second transconductance circuit 1662 are connected to the voltage input terminal VIN and the voltage output terminal VOUT, respectively, and are used to generate the first related current I_AJ1 and the second related current I_AJ2 based on the input voltage and the output voltage, respectively. The minimum current selection circuit 1663 is connected to the first transconductance circuit 1661 and the second transconductance circuit 1662, and is used to select the minimum current I_MIN in the first related current I_AJ1 and the second related current I_AJ2. The current correction circuit 1664 is connected to the minimum current selection circuit 1663, and is used to correct the minimum current I_MIN to generate and output the first gain current GAINA*IB_ADJ and the second gain current GAINB*IB_ADJ.

[0047] In a possible implementation, the first transconductance circuit 1661 includes a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6 and a fourth resistor R4; wherein the fourth resistor R4 is connected between the sources of the third transistor M3 and the fourth transistor M4, the gate of the third transistor M3 is connected to the voltage input terminal VIN, the gate of the fourth transistor M4 is connected to the voltage output terminal VOUT, the drains of the fifth transistor M5 and the sixth transistor M6 are respectively connected to the two ends of the fourth resistor R4, the drains of the third transistor M3 and the fourth transistor M4 are respectively grounded through current sources I7 and I8, and the sources of the fifth transistor M5 and the sixth transistor M6 are grounded.

[0048] In a possible implementation, the second transconductance circuit 1662 includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10 and a fifth resistor R5; wherein the fifth resistor R5 is connected between the sources of the seventh transistor M7 and the eighth transistor M8, the gate of the seventh transistor M7 is connected to the voltage output terminal VOUT, the gate of the eighth transistor M8 is grounded, the drains of the tenth transistor M10 and the ninth transistor M9 are respectively connected to the two ends of the fifth resistor R5, the drains of the seventh transistor M7 and the eighth transistor M8 are respectively grounded through the current sources I7 and I8, and the sources of the tenth transistor M10 and the ninth transistor M9 are grounded.

[0049] In a possible implementation manner, drain currents of the sixth transistor M6 and the ninth transistor M9 are respectively a first related current I_AJ1 and a second related current I_AJ2.

[0050] In a possible implementation, the minimum current selection circuit 1663 includes an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, and a fourteenth transistor M14; wherein, the gates of the eleventh transistor M11 and the fourteenth transistor M14 are connected to the gate of the sixth transistor M6, the gates of the twelfth transistor M12 and the thirteenth transistor M13 are connected to the gate of the ninth transistor M9, the source of the eleventh transistor M11 is connected to the drain of the thirteenth transistor M13, and the source of the twelfth transistor M12 is connected to the source of the fourteenth transistor M14; the minimum current selection circuit 1663 is used to select the minimum current I_MIN from the first related current I_AJ1 and the second related current I_AJ2.

[0051] In a possible implementation, the current correction circuit 1664 includes a first mirror circuit 16641 and a second mirror circuit 16642; wherein the first mirror circuit 16641 includes a fifteenth transistor M15, a sixteenth transistor M16 and a nineteenth transistor M19 whose gates are connected, the sources of the fifteenth transistor M15, the sixteenth transistor M16 and the nineteenth transistor M19 are all connected to the source of the third transistor M3, the drain of the fifteenth transistor M15 is connected to the drains of the eleventh transistor M11 and the twelfth transistor M12, and the drain of the nineteenth transistor M19 is used to output the first gain current GAINA*IB_ADJ; wherein the second mirror circuit 16642 includes a seventeenth transistor M17 and an eighteenth transistor M18 whose sources are both grounded, the gates of the seventeenth transistor M17 and the eighteenth transistor M18 and the drain of the seventeenth transistor M17 are all connected to the drain of the sixteenth transistor M16, and the drain of the eighteenth transistor M18 is used to output the second gain current GAINB*IB_ADJ.

[0052] Below Figure 2 Taking the illustrated implementation as an example, some principles of the present application are briefly described. First, in the first transconductance circuit 1661, the voltage of the input voltage VIN is level-shifted (increasing a VGS3) to one end of the resistor R4 through the third transistor M3, and the output voltage VOUT is level-shifted (increasing VGS4, VGS3=VGS4) to the other end of R4 through the fourth transistor M4, then the current of R4 is (input voltage VIN-output voltage VOUT) / R4. Similarly, in the second transconductance circuit 1662, the current of the resistor R5 is (output voltage VOUT-ground voltage GND) / R5, ensuring that the current I2=current I4=current I6=current I8, then the drain current of the sixth transistor M6 is equal to the current flowing through the resistor R4, and the current of the ninth transistor M9 is equal to the current flowing through the resistor R5. Then there is the following relationship: the first related current I_AJ1=(input voltage VIN-output voltage VOUT) / resistor R4, the second related current I_AJ2=(output voltage VOUT-ground voltage) / resistor R5.

[0053] The first related current I_AJ1 and the second related current I_AJ2 will be connected to the minimum current selection circuit 1663. In the minimum current selection circuit 1663, the eleventh transistor M11 and the fourteenth transistor M14 are connected to the gate of the sixth transistor M6, the gates of the twelfth transistor M12 and the thirteenth transistor M13 are connected to the ninth transistor M9, the source of the eleventh transistor M11 is connected to the drain of the thirteenth transistor M13, and the source of the twelfth transistor M12 is connected to the source of the fourteenth transistor M14. The circuit composed of the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, and the fourteenth transistor M14 will select the smaller current of the first related current I_AJ1 and the second related current I_AJ2, which is recorded as the minimum current I_MIN.

[0054] The minimum current I_MIN is connected to the current correction circuit 1664. The minimum current I_MIN is mirrored through the fifteenth transistor M15 and the sixteenth transistor M16, and is mirrored into a first gain current GAINA*IB_ADJ through the nineteenth transistor M19, and is mirrored into a second gain current GAINB*IB_ADJ through the seventeenth transistor M17 and the eighteenth transistor M18. The first gain current GAINA*IB_ADJ and the second gain current GAINB*IB_ADJ are added to the transconductance amplifier of the loop to adjust the tail current size.

[0055] like Figure 3 , which is a circuit diagram of a part of the ripple compensation circuit of an embodiment of the present application, specifically illustrates possible implementations of the voltage loop 162, the ripple loop 164, the comparator 168 and other related circuits.

[0056] In a possible implementation, the voltage loop 162 increases the first gain current GainA*IB_ADJ.

[0057] The voltage loop 162 includes a twentieth transistor M20 and a twenty-first transistor M21 whose sources are connected to the drain of the nineteenth transistor M19 and the first tail current source IBP1, and the gates of the twentieth transistor M20 and the twenty-first transistor M21 are used to obtain a feedback voltage and a control voltage, respectively, and the drains of the twentieth transistor M20 and the twenty-first transistor M21 are grounded through a sixth resistor R6 and a seventh resistor R7, respectively.

[0058] In a possible implementation, the ripple loop 164 reduces the second gain current GainB*IB_ADJ.

[0059] In this embodiment, the first current IB1 is the difference between the drain currents of the 20th transistor M20 and the 21st transistor M21, and the second current IB2 is the difference between the drain currents of the 22nd transistor M22 and the 23rd transistor M23. After the first current IB1 and the second current are superimposed by the error amplifier gain circuit 167, a comparison error amplification signal is generated as an input to the comparator 169.

[0060] The ripple loop 164 includes a source connected to the drain of the eighteenth transistor M18 and the second tail current source IBP2, and a source of the twenty-second transistor M22 and the source of the twenty-third transistor M23 are connected, and the gates of the twenty-second transistor M22 and the twenty-third transistor M23 are connected to the ripple voltage V RN and V RP The drains of the twenty-first transistor M21 and the twenty-second transistor M22 and the drains of the twentieth transistor M20 and the twenty-third transistor M23 are connected to the two input terminals of the comparison error amplification signal comparator 169 respectively.

[0061] In a possible implementation, the DC-DC converter 100 further includes an error amplifier gain circuit 167 and a comparison error amplification signal comparator 169. The error amplifier gain circuit is used to generate a first voltage and a second voltage based on the first current IB1 and the second current IB2 and provide them to the error amplification signal comparator; the error amplification signal comparator outputs a high-level signal for generating a control PWM signal based on the first voltage and the second voltage, and provides it to the set terminal S of the PWM logic circuit. The error amplifier gain circuit 167 includes a sixth resistor R6 and a seventh resistor R7 connected to ground. The two input terminals of the comparison error amplification signal comparator 169 are respectively connected to the drain of the twenty-third transistor M23 and the drain of the twenty-second transistor M22 and the drain of the twenty-first transistor M21, and the output terminal is connected to the S terminal of the PWM control circuit (130).

[0062] It should be noted that, in a possible implementation, the error amplifier gain circuit 167 and the comparison error amplified signal comparator 169 may be equivalent to the comparator 168 mentioned above in this article. In this case, the comparator 168 may be omitted.

[0063] Figure 4 It is a curve showing the relationship between the ripple amplitude and the input voltage VIN and VOUT, and the relationship between the compensated current and the input voltage and the output voltage VOUT in the implementation effect of the embodiment of the present application. Among them, (a) is a curve showing the relationship between the ripple amplitude and the input voltage VIN and the output voltage VOUT, and (b) is a curve showing the relationship between the compensated gain current and the amplitude of the input voltage VIN and the output voltage VOUT. It can be seen from the figure that the change in ripple amplitude caused by the change in input voltage VIN and output voltage VOUT is consistent with the change in compensation current. Therefore, the ripple compensation circuit that calculates the ripple amplitude information due to the change in ripple amplitude caused by VIN and VOUT is added to the control loop, which can effectively compensate for the change in ripple amplitude, thereby obtaining a stable ripple amplitude. Effectively improve the stability and transient response of the loop of the ripple-based DC / DC converter.

[0064] The embodiments of the present application take a step-down DC / DC converter as an example to illustrate the present invention, but those skilled in the art will appreciate that the solution of the present invention may also be directly applied, or applied to a step-up or step-down converter after adaptive adjustment based on the embodiments of the present application, which is also within the scope of protection requested by the applicant.

[0065] The embodiments of the present application do not impose specific restrictions on the types and parameters of various devices. Under the guidance of the embodiments of the present application, those skilled in the art can implement the solutions of the embodiments of the present application after making simple common sense or choices based on specific needs.

[0066] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A DC-DC converter based on ripple control, characterized in that: include: An output circuit (110), used for converting an input voltage into an output voltage, comprising a voltage input terminal VIN, a voltage output terminal VOUT, a first transistor M1, a second transistor M2, an inductor L and a capacitor COUT; A ripple voltage generating circuit (120) is used to sample the input voltage and output voltage of the voltage input terminal VIN and the voltage output terminal VOUT in the output circuit (110) to generate a ripple voltage; A PWM logic circuit (130), used to generate and output a PWM signal; A fixed on-time control circuit (140) forms a loop with the PWM logic circuit (130) and is used to generate and provide a fixed on-time control signal to the PWM logic circuit (130) to control the PWM logic circuit (130) to output a low level; A driving circuit (150) for generating a first driving signal and a second driving signal according to the high level and the low level of the input of the PWM logic circuit, wherein the first driving signal and the second driving signal respectively drive the first transistor M1 and the second transistor M2 to be alternately turned on and off; And, a ripple compensation circuit (160), the ripple compensation circuit (160) further comprising: a ripple calculation circuit (166), configured to generate a first gain current GAINA*IB_ADJ and a second gain current GAINB*IB_ADJ based on the input voltage VIN and the output voltage VOUT, and input the first gain current GAINA*IB_ADJ to a voltage loop, and input the second gain current GAINB*IB_ADJ to a ripple loop; The voltage loop (162) comprises a first transconductance amplifier GMripple connected to the ripple voltage generating circuit (120); the ripple loop (164) comprises a second transconductance amplifier GMFB connected to the control voltage VC and the feedback voltage VFB; wherein the first transconductance amplifier GMripple and the second transconductance amplifier GMFB are respectively used to connect to a first tail current source IBP1 and a second tail current source IBP2, the first tail current source IBP1 is suitable for being superimposed with the first gain current GAINA*IB_ADJ to output a first current IB1 at the output end of the voltage loop (162), and the second tail current source IBP2 is suitable for being superimposed with the second gain current GAINB*IB_ADJ to output a second current IB2 at the output end of the ripple loop (164); A comparator (168) has one input end connected to the output ends of the voltage loop and the ripple loop, another input end connected to ground, and an output end connected to the PWM logic circuit, for controlling the PWM logic circuit to output the high level.

2. The DC-DC converter according to claim 1, characterized in that: The ripple calculation circuit (166) includes A first transconductance circuit (1661) and a second transconductance circuit (1662) are respectively connected to the voltage input terminal VIN and the voltage output terminal VOUT, and are used to generate a first related current I_AJ1 and a second related current I_AJ2 based on the input voltage and the output voltage respectively; a minimum current selection circuit (1663), connected to the first transconductance circuit (1661) and the second transconductance circuit (1662), for selecting a minimum current I_MIN between the first related current I_AJ1 and the second related current I_AJ2; and The current correction circuit (1664) is connected to the minimum current selection circuit (1663) and is used to correct the minimum current I_MIN to generate and output the first gain current GAINA*IB_ADJ and the second gain current GAINB*IB_ADJ.

3. The DC-DC converter according to claim 1, characterized in that: It also includes an error amplifier gain circuit (167) for generating a first voltage and a second voltage based on the first current IB1 and the second current IB2 and providing the first voltage and the second voltage to an error amplification signal comparator (169); the error amplification signal comparator (169) outputs a high-level signal for generating a control PWM signal based on the first voltage and the second voltage, and provides the high-level signal to the set terminal S of the PWM logic circuit (130).

4. The DC-DC converter according to claim 2, characterized in that: The first transconductance circuit (1661) comprises a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6 and a fourth resistor R4; wherein the fourth resistor R4 is connected between the sources of the third transistor M3 and the fourth transistor M4, the gate of the third transistor M3 is connected to the voltage input terminal VIN, the gate of the fourth transistor M4 is connected to the voltage output terminal VOUT, the drains of the fifth transistor M5 and the sixth transistor M6 are respectively connected to the two ends of the fourth resistor R4, the drain of the third transistor M3 and the gate of the fifth transistor M5 are connected to the current source I3, the drain of the fourth transistor M4 and the gate of the sixth transistor M6 are connected to the current source I4, and the sources of the fifth transistor M5 and the sixth transistor M6 are grounded; The second transconductance circuit (1662) comprises a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10 and a fifth resistor R5; wherein the fifth resistor R5 is connected between the sources of the seventh transistor M7 and the eighth transistor M8, the gate of the seventh transistor M7 is connected to the voltage output terminal VOUT, the gate of the eighth transistor M8 is grounded, the drains of the tenth transistor M10 and the ninth transistor M9 are respectively connected to the two ends of the fifth resistor R5, the drain of the seventh transistor M7 and the gate of the tenth transistor M10 are connected to the current source I7, the drain of the eighth transistor M8 and the gate of the ninth transistor M9 are connected to the current source I8, and the sources of the ninth transistor M9 and the tenth transistor M10 are grounded; The drain currents of the sixth transistor M6 and the ninth transistor M9 are respectively the first related current I_AJ1 and the second related current I_AJ2.

5. The DC-DC converter according to claim 4, characterized in that: The minimum current selection circuit (1663) comprises an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13 and a fourteenth transistor M14; wherein the gates of the eleventh transistor M11 and the fourteenth transistor M14 are connected to the gate of the sixth transistor M6, the gates of the twelfth transistor M12 and the thirteenth transistor M13 are connected to the gate of the ninth transistor M9, the source of the eleventh transistor M11 is connected to the drain of the thirteenth transistor M13, and the source of the twelfth transistor M12 is connected to the drain of the fourteenth transistor M14; The minimum current selection circuit (1663) is used to select the minimum current I_MIN from the first related current I_AJ1 and the second related current I_AJ2.

6. The DC-DC converter according to claim 4, characterized in that: The current correction circuit (1664) comprises a first mirror circuit (16641) and a second mirror circuit (16642); Wherein, the first mirror circuit (16641) comprises a fifteenth transistor M15, a sixteenth transistor M16 and a nineteenth transistor M19 whose gates are connected to each other, the sources of the fifteenth transistor M15, the sixteenth transistor M16 and the nineteenth transistor M19 are connected to a power supply, the source of the third transistor M3 is connected to a current source via a current source I1, the drain of the fifteenth transistor M15 is connected to the drains of the eleventh transistor M11 and the twelfth transistor M12, and the drain of the nineteenth transistor M19 is used to output the first gain current GAINA*IB_ADJ; The second mirror circuit (16642) includes a seventeenth transistor M17 and an eighteenth transistor M18, both of which have their sources grounded, the gates of the seventeenth transistor M17 and the eighteenth transistor M18, and the drain of the seventeenth transistor M17 are connected to the drain of the sixteenth transistor M16, and the drain of the eighteenth transistor M18 is used to output the second gain current GAINB*IB_ADJ.

7. The DC-DC converter according to claim 6, characterized in that: The voltage loop (162) comprises a twentieth transistor M20 and a twenty-first transistor M21, whose sources are connected to the drain of the nineteenth transistor M19 and the first tail current source IBP1, the gates of the twentieth transistor M20 and the twenty-first transistor M21 are respectively used to obtain the feedback voltage VFB and the control voltage VC, and the drains of the twentieth transistor M20 and the twenty-first transistor M21 are respectively grounded through a sixth resistor R6 and a seventh resistor R7; The ripple loop (164) comprises a source of a twenty-second transistor M22 and a source of a twenty-third transistor M23 connected to the drain of the eighteenth transistor M18 and the second tail current source IBP2, and the gates of the twenty-second transistor M22 and the twenty-third transistor M23 are respectively used to obtain a first ripple voltage V RN and the second ripple voltage V RP , wherein the ripple loop (164) is connected from the second resistor R RN and the first capacitor C RN The first ripple voltage V RN , and obtaining the second ripple voltage V between the first resistor Rripple and the second capacitor Cripple RP The DC-DC converter further comprises an error amplifier gain circuit (167) and a comparison error amplification signal comparator (169), wherein the error amplifier gain circuit (167) comprises the sixth resistor R6 and the seventh resistor R7 which are grounded, wherein two input terminals of the comparison error amplification signal comparator (169) are respectively connected to the drains of the twenty-third transistor M23 and the twenty-second transistor M22, and the drains of the twenty-second transistor M22 and the twenty-first transistor M21, and an output terminal thereof is connected to the S terminal of the PWM logic circuit (130).

8. The DC-DC converter according to claim 1, characterized in that: The ripple voltage generating circuit (120) comprises a first resistor Rripple, a second resistor R RN , the first capacitor C RN and a second capacitor Cripple, wherein the first resistor Rripple, the second resistor R RN and the first capacitor C RN They are connected in series and then grounded. The first resistor Rripple is also connected to the source of the first transistor M1. The second capacitor Cripple is connected in parallel with the second resistor RRN and the first capacitor CRN connected in series and then grounded.

9. The DC-DC converter according to claim 1, characterized in that: The ripple loop (164) is used to generate a voltage from the second resistor R RN and the first capacitor C RN Get the first ripple voltage V RN , and obtaining a second ripple voltage V between the first resistor Rripple and the second capacitor Cripple RP , and based on the first ripple voltage V RN and the second ripple voltage V RP The second current IB2 is generated.

10. The DC-DC converter according to claim 1, characterized in that: The fixed on-time control circuit (140) comprises a second comparator, a first input terminal of which is connected to the voltage output terminal VOUT, an output terminal of which is connected to the R terminal of the PWM logic circuit, a second input terminal of the second comparator is connected to the voltage input terminal via a current source of K*VIN, and the second input terminal is also connected to the Q' terminal of the PWM logic circuit; the control loop comprises a switch S1 controlled by the Q' terminal, a first terminal of the switch S1 is connected to the second input terminal, a second terminal of the switch is grounded and connected in parallel to a third capacitor CTON, and a first terminal of the switch is connected to the second input terminal.

11. The DC-DC converter according to claim 1, characterized in that: The S end of the PWM logic circuit (130) is connected to the output end of the comparator (168), and the Q end of the PWM logic circuit (130) is connected to the drive circuit (150).

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