Multi-interruption time sequence adjustment method in arc discharge sampling process, arc discharge detection method and photovoltaic system

Abstract

The invention relates to a multi-interruption time sequence adjustment method in an arc discharge sampling process, an arc discharge detection method and a photovoltaic system. The multi-interrupt time sequence adjusting method in the arc discharge sampling process comprises the steps that the time sequence of a first number of analog-to-digital converter (ADC) interruptions to be started at a first frequency is determined, and the ADC interruptions are used for obtaining sampling data obtained after ADC conversion is conducted on arc discharge parameters; determining a time sequence of interruption of a timer started at a second frequency, wherein the second frequency is smaller than the first frequency; and based on the relative relationship between the time sequence of the timer interrupt and the time sequence of the ADC interrupt, adjusting the trigger position of the timer interrupt on the time sequence to be between two adjacent ADC interrupts. According to the time sequence adjustment method, the condition that the detection value is abnormal in the arc discharge detection process can be optimized.

Description

Technical Field

[0001] The present application relates to the technical field of arc detection, and in particular to a multi-interrupt timing adjustment method for an arc sampling process, an arc detection method, and a photovoltaic system. Background Art

[0002] In the prior art, many fires in electrical systems are mainly caused by arcs. In order to improve the safety of electrical systems, existing electrical systems are usually equipped with arc detection devices to perform arc detection on electrical signals on the DC side of the electrical system.

[0003] The photovoltaic system includes structures such as solar photovoltaic panels, photovoltaic cables and photovoltaic inverters. The solar photovoltaic panels are exposed outdoors to collect solar energy and perform photoelectric conversion, thereby realizing photovoltaic power generation. When an arc is generated on the DC side of the photovoltaic system, it is very easy to cause a fire. In related technologies, arc fault detection technology mainly detects whether an arc fault has occurred by analyzing the differences in time-frequency domain characteristics of the parameters before and after the arc fault occurs. If the sampling period and sampling value used for arc fault analysis are deviated, it is easy to cause the arc fault analysis results to deviate and cause false alarms. Summary of the invention

[0004] In order to overcome the problems existing in the related art, the embodiments of the present application disclose a multi-interrupt timing adjustment method, an arc detection method and a photovoltaic system in an arc sampling process to optimize the problem of abnormal detection values ​​in the arc detection process.

[0005] According to a first aspect of an embodiment of the present application, a method for adjusting the timing of multiple interruptions in an arc sampling process is provided, the method comprising: determining the timing of a first number of digital-to-analog converter (ADC) interrupts to be turned on at a first frequency, wherein the ADC interrupt is used to obtain sampled data after ADC conversion of the arc parameter; determining the timing of a timer interrupt turned on at a second frequency, wherein the second frequency is less than the first frequency; and adjusting the trigger position of the timer interrupt in the timing to between two adjacent ADC interrupts based on the relative relationship between the timing of the timer interrupt and the timing of the ADC interrupt.

[0006] According to a second aspect of an embodiment of the present application, an arc detection method is provided, the method comprising: turning on the ADC interrupt and the timer interrupt according to the timing determined by any timing adjustment method in the present application; and performing arc algorithm processing on the sampling data obtained through the ADC interrupt.

[0007] According to a third aspect of an embodiment of the present application, a photovoltaic system is provided, comprising: a sampling device for collecting arcing parameters in the system; and a processor for executing the steps of any arcing detection method in the present application.

[0008] The technical solution provided by the embodiments of the present application may include the following beneficial effects: based on the relative relationship between the timing of the timer interrupt and the timing of the ADC interrupt, the present application adjusts the trigger position of the timer interrupt in the timing to between two adjacent ADC interrupts, thereby avoiding discontinuous current sampling caused by inserting a timer interrupt during the execution of the ADC interrupt, thereby optimizing the abnormal detection value during the arc detection process.

[0009] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0011] Figure 1 is a structural diagram of a photovoltaic system according to an exemplary embodiment of the present application.

[0012] Figure 2 It is a flowchart of a method for adjusting multiple interrupt timing in an arc sampling process according to an exemplary embodiment of the present application.

[0013] Figure 3 4 is a diagram showing the relative relationship between the trigger position of the delayed Time0 interrupt and the trigger positions of two adjacent ADC interrupts according to an exemplary embodiment of the present application.

[0014] Figure 4 It is a relative relationship diagram between the timing of ADC interrupt and the timing of timer interrupt detected by completing the arc board program upgrade after the timing adjustment.

[0015] Figure 5 It is a flow chart of an arc detection method according to an exemplary embodiment of the present application.

[0016] Figure 6 It is a timing relationship diagram showing how to allocate tasks executed in the Time0 interrupt to the subsequent ADC interrupt execution according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0017] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0018] Figure 1 FIG. 1 is a photovoltaic system structure diagram according to an exemplary embodiment of the present application. Figure 1 As shown, the photovoltaic system 100 includes structures such as photovoltaic panel PV 101, current transformer CT 102, photovoltaic inverter 103 and power grid 104. The photovoltaic panel 101 converts the received solar energy into electrical energy through the photoelectric effect and outputs photovoltaic current. CT 102 monitors the current change in the photovoltaic system 100 in real time, controls the magnitude and direction of the current, and ensures the safe operation of the photovoltaic system 100. The photovoltaic inverter 103 converts the direct current output by the photovoltaic panel 101 into alternating current and outputs it to the power grid 104. The photovoltaic inverter 103 also uses an arcing board to sample and detect arcing parameters such as photovoltaic current monitored by CT 102 to determine whether an arc is generated in the photovoltaic system 100. Among them, the arcing board is a circuit board that can perform arcing detection. The arcing board can be set in products such as photovoltaic inverters as part of the equipment to realize the arcing detection function, or it can be independently realized outside the equipment.

[0019] In some embodiments, the arc detection process may include an arc parameter acquisition phase and an arc algorithm processing phase. In the arc parameter acquisition phase, the processor of the arc board obtains the sampled data of the arc parameters monitored by CT 102 after A / D conversion through a series of ADC interrupts. In the arc algorithm processing phase, the arc algorithm is used to process the collected arc parameters to obtain the arc detection results. More specifically, after completing the initialization procedure, the arc board performs the following processing to obtain the arc parameters and complete the arc detection:

[0020] 1) Enter the arc parameter sampling stage, turn on the ADC interrupt, and complete the sampling of the arc parameters at 1024 sampling points through 1024 ADC interrupts.

[0021] 2) Turn off the ADC interrupt, process the collected arc parameters with the arc algorithm, and determine whether an arc is generated.

[0022] 3) Repeat the above steps 1) and 2) to perform the next round of arc parameter detection.

[0023] In the related art, after the arc board is upgraded on the cloud platform with programs such as ARM (Advanced RISC Machine) / DCAC (DC-to-AC) / DCDC (DC-to-DC) / ARC (Advanced Renewable Computing), the problem of abnormal arc detection value occurs. Generally speaking, the normal value of arc is less than 200, and the arc threshold is set at 400. However, after the arc board program is upgraded, the arc detection value fluctuates greatly, even reaching 3900.

[0024] In response to the above problems, the inventor analyzed and tested the photovoltaic system from the aspects of hardware, software, structure, grounding, load, battery pack, etc. and found that the abnormal arc detection value after upgrading the arc board program may be caused by the long frame in the communication or other reasons that cause the current sampling point to shift. Therefore, the inventor of this application proposed a solution to adjust the trigger position of the timer interrupt in the arc board program in the timing sequence to between two adjacent ADC interrupts.

[0025] Figure 2 is a flowchart of a method for adjusting the timing of multiple interruptions in an arc sampling process according to an exemplary embodiment of the present application. Figure 2 The steps shown are explained.

[0026] In step 11, the timing of a first number of digital-to-analog converter (ADC) interrupts to be turned on at a first frequency is determined, wherein the ADC interrupts are used to obtain sampled data after ADC conversion of the arcing parameters.

[0027] Here, the first frequency can be 250kHz, and the corresponding period is 4us, that is, the interval between the triggering times of two adjacent ADC interrupts is 4us. The first frequency can also be other values ​​that meet the arc detection requirements, such as 220kHz, 280kHz, etc. The first number is usually 1024 times, or it can be other numbers that meet the detection accuracy, such as 512 times, etc. In short, the first frequency and the first number can be reasonably set based on the detection requirements, and are not limited to the above values ​​​​cited in this application. The following is an example in which the first frequency can be 250kHz.

[0028] In some embodiments, the processor of the arc panel turns on ADC interrupt at a first frequency to obtain the photovoltaic current output by the photovoltaic panel 101 as sampling data. The timing of ADC interrupt can be obtained based on the first frequency to determine whether there is an overlap with the timer interrupt in timing.

[0029] In step 12, a timing of a timer interrupt started at a second frequency is determined, wherein the second frequency is less than the first frequency.

[0030] In some embodiments, there are timer interrupts such as Time0 interrupts in the arc drawing board system program. Time0 interrupts can generate a time base signal with a period of 2ms in the system program, that is, the interval between the triggering times of two adjacent Time0 interrupts is 2ms. It can be understood that in the process of the processor using the ADC interrupt to obtain sampled data, the Time0 interrupt also continues at a second frequency in the system program to perform tasks such as communication between chips. The second frequency is usually less than the first frequency, for example, it can be 500Hz, 450Hz, 400Hz, etc.

[0031] Since the cycle of each ADC interrupt is about 4us, one round of ADC interrupt, i.e. 1024 ADC interrupts, may take about 4.1ms. Therefore, at least 2 Time0 interrupts will be inserted in the whole process of one round of ADC interrupt from opening to closing. If the inserted Time0 interrupt overlaps with any of the 1024 ADC interrupts in timing and interferes with the ADC interrupt, the cycle of the ADC interrupt may be extended, resulting in detection point offset and abnormal arc parameter detection.

[0032] In step 13, based on the relative relationship between the timing of the timer interrupt and the timing of the ADC interrupt, the trigger position of the timer interrupt in the timing is adjusted to between two adjacent ADC interrupts.

[0033] As mentioned above, if the Time0 interrupt interferes with a certain ADC interrupt, it may cause abnormal arc parameter detection. The timing adjustment method described in the embodiment of the present application is usually performed before each round of acquisition phase is started. After adjusting the trigger position of the Time0 interrupt according to the above timing adjustment method, the ADC interrupt and Time0 interrupt of this round are turned on, and the arc algorithm is processed for the sampled data obtained through the ADC interrupt.

[0034] In the embodiment of the present application, before a round of ADC interruption is started, the timing of the round of ADC interruption and the timing of Time0 interruption are determined first, and based on the relative timing relationship between the two, the trigger position of Time0 interruption that may cause interference is adjusted to between two adjacent ADC interruptions in the timing to avoid the interference of Time0 interruption on ADC interruption. In this way, the discontinuity of current sampling caused by the insertion of timer interruption during the execution of ADC interruption is prevented, thereby optimizing the abnormality of detection value during arc detection.

[0035] Here, the Time0 interrupt that interferes with the ADC interrupt is the Time0 interrupt that overlaps with the ADC interrupt in terms of timing relationship. For example, the trigger position of the Time0 interrupt may be before, after, or both are triggered at the same time as the trigger position of a certain ADC interrupt, that is, any trigger position that causes the Time0 interrupt to have a synchronous execution duration with a certain ADC interrupt. For another example, if the priority of the ADC interrupt is defined as higher than the Time0 interrupt, the trigger position of the Time0 interrupt is before the ADC interrupt is triggered.

[0036] In some embodiments, based on the relative relationship between the timing of the timer interrupt and the timing of the ADC interrupt, the trigger position of the timer interrupt in the timing is adjusted to between two adjacent ADC interrupts, including: based on the timing of the Time0 interrupt and the timing of the ADC interrupt, determining whether each inserted Time0 interrupt in the process of the round of ADC interrupts interferes with a certain ADC interrupt in the timing, for example, interferes with the Nth ADC interrupt, where N is a natural number greater than or equal to 1. In the case of interference, the processor delays triggering the Time0 interrupt so that each Time0 interrupt runs between the Nth ADC interrupt and the N+1th ADC interrupt. Preferably, the trigger position of the Time0 interrupt is delayed to the interval period after the end of the Nth ADC interrupt and before the triggering of the N+1th ADC interrupt.

[0037] By determining the triggering positions of all Time0 interrupts that occur during a round of ADC interrupts and delaying the Time0 interrupt that may interfere with a certain ADC interrupt to be triggered during the interval between two adjacent ADC interrupts, the influence of Time0 interrupts on ADC interrupts can be better prevented.

[0038] Figure 3 FIG. 1 is a diagram showing the relative relationship between the trigger position of the delayed Time0 interrupt and the trigger positions of two adjacent ADC interrupts according to an exemplary embodiment of the present application. Figure 3, the cycle of ADC interrupt is 4us, and the execution time of each ADC interrupt is about 0.8us. Therefore, the interval period after the end of the Nth ADC interrupt and before the triggering of the N+1th ADC interrupt is about 3.2us. The expected position of the delayed triggering of the Time0 interrupt is taken as the control target. Preferably, the control target is set to 0.8us after the end of the Nth ADC interrupt. If the execution time of the Time0 interrupt is 1.6us, the N+1th ADC interrupt is triggered 0.8us after the end of the Time0 interrupt. At this time, the Time0 interrupt is triggered 0.8us after the end of the Nth ADC interrupt and ends 0.8us before the triggering of the N+1th ADC interrupt. Its execution time is exactly in the middle of the interval period between the Nth ADC interrupt and the N+1th ADC interrupt. In other words, controlling the Time0 interrupt to be triggered 1.6us later than the triggering position of the Nth ADC interrupt will present Figure 3 The timing relationship is shown.

[0039] Therefore, the time for delaying the triggering of the Time0 interrupt can be determined based on the expected position of the delayed triggering of the Time0 interrupt. In some embodiments, since the clock cycles of the Time0 interrupt and the ADC interrupt are consistent, both are 60 MHz, delaying the triggering of the corresponding Time0 interrupt so that the Time0 interrupt runs between the Nth ADC interrupt and the N+1th ADC interrupt may include:

[0040] Get the first clock cycle number temp1 from the current trigger position of the Time0 interrupt at this time; get the second clock cycle number temp2 from the trigger position of the Nth ADC interrupt at this time; then (temp2-temp1) is the number of clock cycles required to adjust the Time0 interrupt to be triggered simultaneously with the Nth ADC interrupt. The value of N is determined by dividing temp1 by the cycle of the ADC interrupt, thereby determining the trigger position of the Nth ADC interrupt.

[0041] Determine the third clock cycle number temp3 from the expected position of the delayed trigger of the Time0 interrupt to the trigger position of the Nth ADC interrupt, then (temp2-temp1+temp3) is the number of clock cycles required to delay the Time0 interrupt to the expected position. Preferably, temp3 is not less than the execution time of the Nth ADC interrupt, so that the delayed Time0 interrupt can be triggered after the Nth ADC interrupt ends, rather than during the execution.

[0042] Through the above calculation method, the number of clock cycles for delaying the Time0 interrupt can be determined to ensure that the triggering time of the Time0 interrupt can be located in the interval period between the two ADC interrupts.

[0043] like Figure 3 As shown in the figure, if the control target is that the Time0 interrupt is triggered 1.6us later than the Nth ADC interrupt, the Time0 interrupt needs to be delayed by (temp2-temp1+temp3) clock cycles, then the theoretical value of temp3 is 96 clock cycles, corresponding to 1.6us. However, in the process of obtaining temp1 and temp2, when assigning values ​​to TIM.all, the program runs synchronously, and EPwm1Regs.TBCTR and TIM.all are both decreasing or increasing. Therefore, the theoretical value of temp3 cannot be used directly, and needs to be measured through debugging waveforms.

[0044] In some embodiments, the debugging process may be: first, a value assignment test is performed on temp3 with 110 clock cycles, and the test result is that the Time0 interrupt is started 1.4us after the ADC interrupt ends; then, a value assignment test is performed on temp3 with 170 clock cycles, and the test result is that the Time0 interrupt is started 2.36us after the ADC interrupt ends. The test results are consistent with the theoretical relationship that 60 clock cycles correspond to 1us.

[0045] Then, based on the test results of temp3 being 110 clock cycles and Time0 interrupt being started 1.4us after the ADC interrupt ends, if the expected position of the delayed trigger of Time0 interrupt is 0.8us after the ADC interrupt ends, that is, 0.6us earlier than 1.4us, the test theoretical value of temp3 is 110-60*0.6us=74 clock cycles. It can be concluded that the test theoretical value of temp3 is 74 clock cycles. When temp4=44 or 74 is measured, Time0 interrupt is started 0.88us after the ADC interrupt ends, indicating that a certain interrupt jump time is required before Time0 interrupt starts.

[0046] Therefore, based on the test results, the test theoretical value of temp3 corresponding to the delay of the Time0 interrupt to the expected position trigger is determined, and the test theoretical value is determined as temp3, and the calculation result of (temp2-temp1+temp3) is determined as the number of clock cycles required to delay the Time0 interrupt to the expected position. Based on the number of clock cycles to delay the Time0 interrupt, the number of clock cycles of the Time0 interrupt delay can be adjusted based on the actual state of the program running in the system, so that in the actual state of the system program running, the Time0 interrupt can be adjusted to trigger in the interval period between two adjacent ADC interrupts, thereby avoiding the interference of the Time0 interrupt with the ADC interrupt.

[0047] Figure 4The relative timing relationship diagram between the timing of the ADC interrupt detected by the arc drawing board program upgrade and the timing of the timer interrupt is shown after the above timing adjustment is completed. As shown in the figure, channel 1 is the timing of the ADC interrupt, and the high level in channel 1 indicates that the ADC interrupt is running; channel 2 is the timing of the timer interrupt, and the low level in channel 2 indicates that the Time0 interrupt is running, and channel 3 is the timing of 485 communication in the photovoltaic system. After the timing adjustment, the arc drawing board program upgrade is completed. The interval from the end of the ADC interrupt to the triggering of the Time0 interrupt is 0.8us, and the sampling period of the ADC is still about 4us, which is basically the same as before the upgrade, and no obvious changes are found. It can be seen that after the timing adjustment described in this application, the measured data is indeed optimized.

[0048] Figure 5 The present invention is an arc detection method according to an exemplary embodiment of the present invention. The detection method comprises the following steps:

[0049] In step 21, according to the timing determined by the timing adjustment method described in the present application, the ADC interrupt and the timer interrupt are enabled.

[0050] As mentioned above, based on the relative relationship between the timing of the Time0 interrupt and the timing of the ADC interrupt, the trigger position of the Time0 interrupt that interferes with the ADC interrupt is adjusted to between two adjacent ADC interrupts. After this adjustment, the cycle of the ADC interrupt is restored to the normal duration before the program upgrade, and accordingly, the abnormality of the arc detection value is optimized. Therefore, based on the adjusted timing, the ADC interrupt and the Time0 interrupt are turned on to enter the arc parameter collection stage.

[0051] In step 22, the sampling data obtained through ADC interruption is processed by an arc-drawing algorithm.

[0052] After completing the arc parameter sampling in step 21, the arc algorithm processing stage is entered, and the arc algorithm processing is performed on the sampled data obtained through the ADC interrupt. In some embodiments, the arc algorithm processing may include: performing Fourier transform on the current parameter to obtain the spectrum corresponding to the current parameter; taking the modulus of the amplitude of each frequency point in the spectrum to obtain the characteristic value of the arc; and determining whether an arc is generated based on the characteristic value of the arc and the set arc threshold.

[0053] Since the ADC interrupt and timer interrupt are turned on according to the timing determined by the timing adjustment method of the present application, based on the arc detection method described in the present application, even if the arc board program is upgraded, abnormal arc detection values ​​will not occur after the upgrade.

[0054] In addition, the inventors found in their research that executing communication reception tasks such as reading FIFO in the Time0 interrupt will cause the execution time of the Time0 interrupt to be prolonged, which may still cause the interval between the triggering times of adjacent ADC interrupts to exceed 4us, resulting in abnormal arc detection values. The time data of the arc test board in actual work shows that the execution time of the Time0 interrupt is too long, which may cause the interval between the triggering times of two adjacent ADC interrupts to reach 4.7us. Therefore, reducing the running time of the Time0 interrupt can also optimize the phenomenon of abnormal arc detection values.

[0055] In some embodiments, part of the tasks executed in the Time0 interruption are deployed to be executed in at least one ADC interruption after the Time0 interruption ends, so as to shorten the execution time of the Time0 interruption.

[0056] In an embodiment of the present application, based on the timing of the Time0 interrupt and the timing of the ADC interrupt, it is determined whether the execution of each Time0 interrupt causes the cycle of the Mth ADC interrupt to be extended, wherein the trigger time of the timer Time0 interrupt is located after the Mth ADC interrupt and before the trigger time of the M+1th ADC interrupt. The cycle of the Mth ADC interrupt is extended, specifically, the trigger time of the timing of the Time0 interrupt is located in the cycle of the Mth ADC interrupt, and the end time of the timing of the Time0 interrupt is located after the predetermined trigger time of the M+1th ADC interrupt, where M is a natural number greater than or equal to 1.

[0057] As mentioned above, in the process of each round of ADC interrupt, Time0 interrupt may be inserted. If the triggering time of the Time0 interrupt is close to the ADC interrupt triggered subsequently, or there are too many tasks executed in the Time0 interrupt and the execution time is too long, then the triggering time of the ADC interrupt immediately after the Time0 interrupt will be postponed. In this case, the cycle of the ADC interrupt is prolonged. Therefore, it is necessary to judge whether the execution of each Time0 interrupt will cause the cycle of a certain ADC interrupt (for example, the Mth ADC interrupt) in the round to be prolonged according to the relative relationship between the timing of the ADC interrupt and the timing of the Time0 interrupt. In the case that the cycle of the ADC interrupt is prolonged, some tasks of the Time0 interrupt are deployed to the subsequent ADC interrupt for execution.

[0058] The specific process of task allocation during interruption is further described below based on steps S1301 - S1306 .

[0059] In step S1301, the triggering time of the Mth ADC interrupt is obtained, wherein the period of the Mth ADC interrupt is prolonged due to the insertion of the Time0 interrupt.

[0060] In some embodiments, the Mth ADC interrupt whose cycle is extended is determined by the trigger time and execution duration of the Time0 interrupt. The execution period of the Time0 interrupt in timing can be obtained based on the trigger time and execution duration of the Time0 interrupt. If there is an ADC interrupt in this round of ADC interrupts whose scheduled trigger time falls within the execution period of the Time0 interrupt, it means that the execution of the Time0 interrupt will cause the triggering of the ADC interrupt to be postponed, then the ADC interrupt immediately before the ADC interrupt is the Mth ADC interrupt. The trigger time of the Mth interrupt is used for subsequent task allocation.

[0061] In step S1302, based on the trigger time of the Mth ADC interrupt and the cycle of the ADC interrupt, the first end time of the Time0 interrupt after the task is allocated is determined, wherein the duration from the trigger time of the Mth ADC interrupt to the first end time of the Time0 interrupt after the task is allocated is not greater than the cycle of the ADC interrupt. Here, the cycle of the ADC interrupt is determined based on the first frequency.

[0062] It is understandable that if the Time0 interrupt ends before the M+1th ADC interrupt is triggered, the cycle of the Mth ADC interrupt will not be extended. Therefore, the first end time of the Time0 interrupt is first determined based on this condition, and the first end time makes the execution of the Time0 interrupt not exceed the cycle of the Mth ADC interrupt. Preferably, there is a certain time margin between the first end time and the triggering time of the M+1th ADC interrupt, such as 0.8us or 1us.

[0063] In step S1303, the second end time of the Time0 interruption before the task is allocated is obtained, and the minimum execution duration of the task to be allocated from the Time0 interruption is determined according to the first end time and the second end time.

[0064] Before the task is allocated, the second end time of the Time0 interrupt is after the trigger time of the M+1th ADC interrupt in terms of timing. Therefore, it is necessary to allocate a part of the tasks from the Time0 interrupt so that the Time0 interrupt ends at the first end time before the trigger time of the M+1th ADC interrupt. That is, the execution time of the allocated task cannot be less than the time difference between the second end time and the first end time. This ensures that in the actual operation process, the Time0 interrupt after the task is allocated will not prolong the cycle of the ADC interrupt.

[0065] In step S1304, based on the minimum execution duration, the allocated first task is determined, wherein the execution duration of the first task is not less than the minimum execution duration.

[0066] After obtaining the minimum execution time, it is necessary to select the first task whose execution time is greater than or equal to the minimum execution time from the tasks executed in the Time0 interrupt based on the minimum execution time. If the execution time of the first task allocated is less than the minimum execution time, it is still possible that the Time0 interrupt after the task is allocated will extend the ADC interrupt cycle. Therefore, the allocated tasks cannot be selected arbitrarily, and it is necessary to confirm whether their execution time meets the requirements.

[0067] In step S1305, based on the execution duration of the allocated task, a second number of ADC interrupts required to complete the task is determined, and a second task required to be completed by each ADC interrupt in the second number of ADC interrupts is determined, wherein the first task includes the second task, and the execution duration of the second number of ADC interrupts allocated with the second task is not greater than the period of the ADC interrupt.

[0068] Since the deployed first task needs to be assigned to the ADC interrupt after the Time0 interrupt for execution, and the cycle of the ADC interrupt cannot be lengthened due to task allocation, the deployed first task may need to be assigned to multiple ADC interrupts in order to complete the task while ensuring the normal cycle of the ADC interrupt. In this way, based on the size of the deployed first task, the first task is assigned to a second number of ADC interrupts for execution, and the second number can at least ensure that the cycle of the ADC interrupt that has received the task allocation will not be lengthened. After determining the second number, the second task assigned to each ADC interrupt can be further determined. The ADC interrupt that has received task allocation needs to complete the second task allocated from the Time0 interrupt and the task of obtaining sampled data that it originally needs to complete. It is necessary to limit the execution time of the ADC interrupt that has received task allocation to no more than the cycle of the ADC interrupt, that is, no more than 4us, preferably, it can be 3.2us or 3.8us, etc.

[0069] In step S1306 , starting from the M+1th ADC interrupt immediately after the Time0 interrupt, the tasks allocated from the Time0 interrupt are executed in the second number of ADC interrupts.

[0070] After the adjustment of steps S1301-S1306, the execution duration of the Time0 interrupt is shortened, and there is a timing gap between its end time and the triggering time of the subsequent ADC interrupt, which will not affect the subsequent ADC interrupt being triggered according to the predetermined period.

[0071] Figure 6 FIG. 1 is a timing diagram showing how to deploy tasks executed in the Time0 interrupt to be executed in the subsequent ADC interrupt according to an exemplary embodiment of the present application. Figure 6As shown in the figure, after some tasks in the Time0 interrupt are deployed, the maximum execution time of the Time0 interrupt is shortened to 0.63us. Under normal circumstances, the maximum execution time of the ADC interrupt is 1.33us. Since the Nth ADC interrupt immediately before the Time0 interrupt is executed normally, the Time0 interrupt is started about 0.76us after the end of the Nth ADC interrupt. Therefore, after the execution of the Time0 interrupt ends, there is still a margin of (4us-1.33us-0.63us-0.76us=) 1.28us from the trigger time of the N+1th ADC interrupt. In other words, the triggering and ending time of the Time0 interrupt are both in the execution interval between the Nth ADC interrupt and the N+1th ADC interrupt, which will not interfere with the ADC interrupt and cause abnormal arc detection.

[0072] Accordingly, the ADC interrupt after the Time0 interrupt is extended because the task originally executed in the Time0 interrupt is allocated. Since the interval between the triggering times of two adjacent ADC interrupts cannot exceed 4us, the execution time of the ADC interrupt to which the task is allocated will also be limited. The task needs to be allocated to multiple ADC interrupts to shorten the execution time of the Time0 interrupt to an appropriate time. The N+1th ADC interrupt immediately after the Time0 interrupt ends and the subsequent ADC interrupts may be extended. For example, the first ADC interrupt after the Time0 interrupt, that is, the maximum execution time of the N+1th ADC interrupt will reach 3.2us, and the execution time of the subsequent ADC interrupts will also be extended one by one, even up to 3.85us, until the last ADC interrupt to which the task is allocated is executed and the ADC interrupt returns to its normal execution time.

[0073] As described above, according to the embodiment of the present application, when the execution time of the Time0 interrupt is too long and the cycle of the ADC interrupt is prolonged, some tasks in the Time0 interrupt are adjusted to the subsequent ADC interrupt for execution to shorten the execution time of the Time0 interrupt, so that the Time0 interrupt can be terminated before the next ADC interrupt is triggered, thus avoiding the abnormal arc detection caused by the prolonged cycle of the ADC interrupt. In addition, the tasks allocated from the Time0 interrupt are allocated to multiple ADC interrupts for execution to ensure that the execution time of the ADC interrupt that has been allocated does not exceed the cycle of the ADC interrupt.

[0074] It should be noted that since the period of Time0 interrupt is 2ms, there may be hundreds of ADC interrupts between two adjacent Time0 interrupts. Therefore, there is no need to worry that a new Time0 interrupt will appear and require task allocation before the last ADC with a scheduled task is completed. In other words, there will be enough ADC interrupts to accept task allocation after the Time0 interrupt, and there will be no situation where a new Time0 interrupt is adjacent to the previous ADC interrupt with a longer execution time.

[0075] In the arcing algorithm processing phase after the arcing parameter acquisition phase is completed, the Time0 interrupt will continue to be executed at the second frequency. Since there is no data acquisition task in this phase, in some embodiments, the ADC interrupt is turned off in the arcing algorithm processing phase.

[0076] In some other embodiments, during the arc drawing algorithm processing stage, the ADC interrupt is not completely disabled. For example, at least one ADC interrupt is started after the Time0 interrupt, and some tasks executed in the Time0 interrupt are deployed to the ADC interrupt started after the Time0 interrupt ends.

[0077] The number of ADC interrupts started is determined based on the size of the deployed task. In some embodiments, during the arc drawing algorithm processing, each time the Time0 interrupt is executed, the number of ADC interrupts required to complete the deployed task is determined based on the size of the task deployed from the Time0 interrupt, and the corresponding ADC interrupt is started based on the determined number of ADC interrupts. The execution frequency of the ADC interrupt can be the first frequency, or other suitable frequency required by the system task, without limitation.

[0078] The arc-pulling algorithm processing phase usually lasts about 5.2ms. According to the cycle of the Time0 interrupt, 2 to 3 Time0 interrupts may be executed during this period. After each Time0 interrupt is executed, a certain number of ADC interrupts are started to execute the tasks allocated from the Time0 interrupt.

[0079] Through the above task allocation processing, it is possible to avoid the execution time being too long due to too many or too large tasks of the Time0 interrupt. By shortening the execution time of the Time0 interrupt, the time interval between ADC interrupts is kept within 4us, thereby optimizing the resulting arc detection anomaly.

[0080] In addition to the above reasons, the reason for the abnormal arc detection may also be that after entering the arc parameter acquisition stage, the time interval between the first ADC interrupt and the second ADC interrupt is random, which may cause the first ADC sampling data to be abnormal.

[0081] As mentioned above, the arc detection process is cyclic. After a round of arc parameter sampling, the arc algorithm is processed for the sampled arc parameters and the result of whether an arc is generated is obtained. Then a new round of arc parameter sampling is started, and arc detection is continuously performed in the photovoltaic system. During the cyclic execution of arc detection, the triggering and ending of the ADC interrupt is controlled by setting the ADC interrupt register in the arc board circuit.

[0082] In some embodiments, the ADC interrupt register has an enable bit (Enable Bit) and a trigger bit (TreggerBit). Among them, setting the enable bit in the ADC interrupt register can allow or enable the interrupt line, so that the ADC interrupt can be triggered. Setting the trigger bit in the interrupt register can directly trigger the ADC interrupt, so that the processor responds to the interrupt request. Each round of ADC interrupt is enabled based on the setting of the enable bit, and is repeatedly set at a time interval of 4us through the trigger bit, so that the ADC interrupt is periodically triggered at a time interval of 4us after it is enabled, forming a process of sampling arc parameters at multiple sampling points at a frequency of 250kHz. After completing a predetermined number of ADC interrupts, such as 1024 times, the enable bit is cleared, and the round of ADC interrupts is closed.

[0083] In the system program, the enable bit of the interrupt register is set after the previous round of arcing algorithm processing phase ends and when entering a new round of arcing parameter sampling phase. Since the processing time of the previous round of arcing algorithm is determined by the completion status of the task in the system program (usually around 5.2ms), that is, the actual processing time of each round of arcing algorithm processing phase cannot be predicted, the start time of the ADC interrupt cannot be predetermined, and accordingly, the trigger time of the first ADC interrupt cannot be determined. However, the trigger bit of the interrupt register will be repeatedly set at a predetermined time interval and thereby trigger subsequent ADC interrupts, that is, the trigger time is determined from the second ADC interrupt to the 1024th ADC interrupt. Therefore, in each round of arcing parameter sampling phase, the interval between the trigger time of the first ADC interrupt and the second ADC interrupt is uncontrollable. This may also cause abnormal arcing detection.

[0084] Based on this, in an embodiment of the present application, after using a data sampling device such as a current sensor to start collecting the arc parameters at a preset time interval, the first arc parameter collected is discarded and not put into the sampling data group, and starting from the second arc parameter, the collection of 1024 arc parameters in this round is performed, that is, the sampling of the arc parameters is performed one more time in the future. This can further optimize the abnormal situation of arc detection. In some embodiments, after turning on the ADC interrupt, the ADC interrupt of this round is turned off after executing 1025 interrupts. The sampled data obtained from the 2nd to 1025th ADC interrupts in this round of ADC interrupts are used for data processing in the arc algorithm processing stage, and the arc result is judged.

[0085] After the arc detection process is adjusted in the above manner according to the embodiment of the present application, a simulation test is performed on the arc detection process, and the detection results of the simulation test are compared with the detection results before the above adjustment to verify the optimization effect after the adjustment. The data comparison before and after the adjustment is described in detail below.

[0086] Before the improvement is performed in the manner described in the embodiment of the present application, the timing relationship between the ADC interrupt and the Time0 interrupt is detected, and Table 1 records the relevant time data of the ADC interrupt and the Time0 interrupt in the detection.

[0087] Table 1

[0088]

[0089] It can be seen from Table 1 that the execution duration of the Time0 interrupt overlaps with the execution duration of the ADC interrupt, the ADC interrupt is triggered with a delay, and the ADC interrupt cycle is extended to about 6us.

[0090] It can be seen that before the timing adjustment method of the embodiment of the present application is performed, the sampling period of the ADC interrupt exceeds the expected sampling period of 4us by about 2us.

[0091] After improvement according to the method described in the embodiment of the present application, the timing relationship between the ADC interrupt and the Time0 interrupt is detected, and Table 2 records the relevant time data of the ADC interrupt and the Time0 interrupt in the detection.

[0092] Table 2

[0093]

[0094] It can be seen from the data recorded in Table 2 that after the timing adjustment method of the embodiment of the present application is performed, the sampling period of the ADC interrupt is 4us, which is basically the same as the expected sampling period and meets the requirements for the ADC interrupt sampling period. This proves that the timing adjustment method of the embodiment of the present application can indeed optimize the abnormal situation of the arc detection result.

[0095] The multi-interrupt timing adjustment method and arc detection method in the arc sampling process disclosed in this application can be used in the arc detection of photovoltaic systems. In an embodiment of the present application, the photovoltaic system includes: a sampling device for collecting arc parameters in the system; a processor for executing the steps of any arc detection method disclosed in this application. In some embodiments, the photovoltaic system includes a photovoltaic panel, a photovoltaic inverter and a power grid, and the timing adjustment method and arc detection method can be specifically used in the arc panel of the photovoltaic inverter.

[0096] It should be understood that "some embodiments", "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiments are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the sequence number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned sequence numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments.

[0097] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0098] The above is only an implementation method of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims

1. A method for adjusting the multi-interrupt timing of an arc sampling process, characterized in that: The method comprises: Determine the timing of a first number of digital-to-analog converter (ADC) interrupts to be turned on at a first frequency, wherein the ADC interrupts are used to obtain sampled data after the arcing parameter is converted by ADC; determining a timing of a timer interrupt that is turned on at a second frequency, wherein the second frequency is less than the first frequency; Based on the relative relationship between the timing of the timer interrupt and the timing of the ADC interrupt, the trigger position of the timer interrupt in the timing is adjusted to between two adjacent ADC interrupts.

2. The method according to claim 1, characterized in that The step of adjusting the trigger position of the timer interrupt to between two adjacent ADC interrupts based on the relative relationship between the timing of the timer interrupt and the timing of the ADC interrupt comprises: Based on the timing of the timer interrupt and the timing of the ADC interrupt, determining whether each of the timer interrupts and the Nth ADC interrupt interferes with each other in timing, where N is a natural number greater than or equal to 1; In the case that there is a timing interference between the timer interrupt and the Nth ADC interrupt, the corresponding timer interrupt is triggered with delay, so that each timer interrupt runs between the Nth ADC interrupt and the N+1th ADC interrupt.

3. The method according to claim 2, characterized in that The delay triggers the corresponding timer interrupt so that the timer interrupt runs between the Nth ADC interrupt and the N+1th ADC interrupt, including: Get the first clock cycle number temp1 from the trigger position of the timer interrupt; Get the second clock cycle number temp2 from the Nth ADC interrupt trigger position; Determine a third clock cycle number temp3 from the trigger position of the timer interrupt delay to the trigger position of the Nth ADC interrupt, wherein temp3 is not less than the execution duration of the Nth ADC interrupt; Based on the temp1, the temp2 and the temp3, determine the number of clock cycles temp4 that the timer interrupt needs to be delayed; Based on the temp4, the timer interrupt is triggered with delay.

4. The method according to claim 3, characterized in that: The determining of the distance between the trigger position after the timer interrupt delay and the Nth ADC interrupt trigger position temp3 includes: Assigning a value to the temp3 with a preset first clock cycle number, and performing a delay trigger test of the timer interrupt based on the temp1, the temp2 and the assigned temp3; Based on the actual position of the timer interrupt delay trigger and the expected position of the delay trigger in the test, obtain the test theoretical value of temp3; The test theoretical value is determined as the temp3 to be used for the subsequent determination of the temp4.

5. The method according to any one of claims 1 to 4, characterized in that The method further comprises: During the execution of the first number of ADC interrupts, at least one task executed in the timer interrupt is deployed to be executed in at least one ADC interrupt after the timer interrupt ends, so as to shorten the execution time of the timer interrupt.

6. A method for detecting arcing, characterized in that: The method comprises: According to the timing determined by the method according to any one of claims 1 to 5, enabling the ADC interrupt and the timer interrupt; and The sampling data obtained through the ADC interruption is processed by an arc-drawing algorithm.

7. The method according to claim 6, characterized in that The method further comprises: During the arc drawing algorithm processing, the ADC interrupt is turned off.

8. The method according to claim 6, characterized in that The method further comprises: During the arc drawing algorithm processing, at least one ADC interrupt is executed after the timer interrupt, and at least one task executed in the timer interrupt is deployed to be executed in the at least one ADC interrupt after the timer interrupt ends.

9. The method according to any one of claims 6 to 8, characterized in that: The method further comprises: Using a data collector to collect the arc drawing parameters at preset time intervals; discarding the first arc drawing parameter collected; and Starting from the second arc drawing parameter, the acquisition of the first number of arc drawing parameters is performed.

10. A photovoltaic system, characterized in that: include: A sampling device, used for collecting arc drawing parameters in the system; A processor for executing the steps of the arc detection method according to any one of claims 6 to 9.

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