Millimeter wave radar transmitting method, receiving method and transceiving system based on equivalent sampling

Abstract

The invention discloses a millimeter wave radar transmitting method, a receiving method and a transceiving system based on equivalent sampling, and the transmitting method comprises the steps: generating a single-frame synchronization signal, a multi-frame synchronization signal and a long-frame selection signal according to a system frequency modulation period, a digital-to-analog conversion rate and an equivalent sampling ratio; generating a baseband modulation signal and a delay line selection signal according to the single-frame synchronization signal and the multi-frame synchronization signal; generating an analog voltage control signal according to the baseband modulation signal, and performing delay adjustment on the analog voltage control signal by using a delay line selection signal to generate a delay voltage control signal; regulating and controlling the relative delay of each frame of transmitting signal and the local oscillation signal according to the delay voltage control signal, and generating a target transmitting signal and a frequency multiplication local oscillation signal; according to the invention, the conversion rate requirement of the analog-to-digital converter in the millimeter wave radar is greatly reduced, the maximum detection distance threshold is improved, and the cost and the power consumption are effectively saved.

Description

Technical Field

[0001] The present invention relates to the technical field of millimeter-wave radar, and particularly to a millimeter-wave radar transmitting method, receiving method and transceiver system based on equivalent sampling. Background Art

[0002] Millimeter-wave radar, as a radar operating in the millimeter-wave band for detection, has been widely applied in many fields such as automotive, transportation, security, industry, and medical due to its remarkable characteristics such as high resolution and strong anti-interference ability. In the scope of civilian millimeter-wave radar, cost and power consumption become two key considerations. From the perspective of cost, low cost is the cornerstone for the rapid popularization and large-scale promotion of millimeter-wave radar technology. This can not only effectively expand the market scale, attract more enterprises and institutions to engage in applications, strongly promote the vigorous development of the entire industry, but also attract upstream and downstream enterprises to actively participate in the construction of the industrial chain, improve the scale and specialization of the industry, and then form a virtuous cycle of promoting technological innovation and cost optimization. In terms of power consumption, in devices such as some security monitoring millimeter-wave radar sensors powered by batteries, low power consumption characteristics are crucial. It can greatly extend the battery replacement cycle, significantly reduce the maintenance cost and difficulty, and greatly improve the convenience and reliability of device use. At the same time, low power consumption also helps to reduce the electrical stress on electronic components, reduce the probability of failures, ensure the stable operation of the millimeter-wave radar system under various complex working conditions, and improve its anti-interference ability and working efficiency.

[0003] In a millimeter-wave radar system, the analog-to-digital converter plays an indispensable and crucial role. It is like a bridge connecting analog signals and digital signals, and its cost, power consumption, and technical indicators have a decisive impact on the performance of the entire system. Among them, the sampling rate of the analog-to-digital converter directly relates to the maximum detection distance that the millimeter-wave radar can reach. To expand the maximum detection distance, the system has to design an analog-to-digital converter with a higher sampling rate. However, the increase in the sampling rate is accompanied by a sharp increase in the complexity of circuit design, a significant increase in the interface transmission rate, and a remarkable increase in power consumption. This will undoubtedly directly lead to an increase in system cost and power consumption. Therefore, in the traditional millimeter-wave radar technology system, to achieve a farther detection distance, usually relying on increasing the sampling rate of the analog-to-digital converter, this conventional path will inevitably lead to an increase in the complexity of circuit design and an increase in the interface transmission rate, and then cause the system power consumption and cost to increase accordingly. This sharp contradiction between the sampling rate of the analog-to-digital converter and the system cost and power consumption seriously restricts the further development and wide application of millimeter-wave radar technology.

[0004] In the related art, in the patent application document with publication number CN116436483A, a pulse modulation scheme is proposed to perform single-bit quantization on the baseband waveform and the radio frequency carrier, generating an adjustable-delay radio frequency signal. Its application scope is limited to communication waveform generation systems with relatively low carrier frequencies and low requirements for dynamic range, and it is restricted in the application of low-cost millimeter-wave radars. In the literature "Research and Implementation of High-Speed Signal Acquisition and Transmission Technology Based on ZYNQ, Wang Siwen, Master's Thesis", high conversion rate equivalent sampling is achieved based on the simultaneous parallel operation of multiple analog-to-digital converters, with relatively high costs and hardware complexity. Summary of the Invention

[0005] The technical problem to be solved by the present invention is how to obtain an equivalent improvement in the analog-to-digital conversion rate at relatively low software and hardware costs.

[0006] The present invention solves the above technical problems through the following technical means:

[0007] In a first aspect, the present invention proposes a millimeter-wave radar transmission method based on equivalent sampling, and the method includes:

[0008] Generating a single-frame synchronization signal, a multi-frame synchronization signal, and a long-frame selection signal according to the system frequency modulation period, the digital-to-analog conversion rate, and the equivalent sampling ratio, wherein the period of the single-frame synchronization signal is equal to the frequency modulation signal period, and the period of the multi-frame synchronization signal is a multiple of the single-frame synchronization signal period;

[0009] Generating a baseband modulation signal and a delay line selection signal according to the single-frame synchronization signal and the multi-frame synchronization signal, wherein the sampling time is adjusted by a fractional delay filter when the long-frame selection signal is low, and the sampling time is adjusted by a stepped delay line when the long-frame selection signal is high;

[0010] Generating an analog voltage-controlled signal according to the baseband modulation signal, and performing delay adjustment on the analog voltage-controlled signal by using the delay line selection signal to generate a delayed voltage-controlled signal;

[0011] Regulating the relative delay of each frame of transmitted signal and the local oscillator signal according to the delayed voltage-controlled signal to generate a target transmitted signal and a frequency-doubled local oscillator signal.

[0012] Further, both the single-frame synchronization signal and the multi-frame synchronization signal are periodically repeated pulses, and the period of the multi-frame synchronization signal is equal to the period of the single-frame synchronization signal multiplied by the equivalent sampling ratio.

[0013] Further, the generating a baseband modulation signal and a delay line selection signal according to the single-frame synchronization signal and the multi-frame synchronization signal, wherein the sampling time is adjusted by a fractional delay filter when the long-frame selection signal is low, or the sampling time is adjusted by a stepped delay line when the long-frame selection signal is high, includes:

[0014] Count the rising edge of the single-frame synchronization signal to generate a linear counting sequence;

[0015] Use the multi-frame synchronization signal as the initial clear signal to count the pulses of the single-frame synchronization signal and generate a frame cycle count;

[0016] Perform fractional delay filtering on the linear counting sequence based on the fractional delay value to generate a baseband modulation signal, where the fractional delay value is zero when the long frame selection signal is high and the fractional delay value is the frame cycle count when the long frame selection signal is low;

[0017] Generate a delay line selection signal based on the frame cycle count, where the delay line selection signal is equal to the frame cycle count when the long frame selection signal is high and the delay line selection signal is equal to zero when the long frame selection signal is low.

[0018] Further, the method further includes:

[0019] At T s ≥T dac *2 Bdac The long frame selection signal is high;

[0020] At T s <T dac *2 Bdac The long frame selection signal is low;

[0021] Wherein, T s Is the system frequency modulation period, T dac Is the digital-to-analog conversion period, B dac Is the digital-to-analog conversion accuracy.

[0022] Further, the number of steps of the stepped delay line is equal to the equivalent sampling ratio, and the step size is equal to the reciprocal of the equivalent sampling rate.

[0023] Further, generating an analog voltage-controlled signal according to the baseband modulation signal includes:

[0024] Perform digital-to-analog conversion on the baseband modulation signal to generate an analog voltage signal;

[0025] Perform amplification processing on the analog voltage signal to generate an analog amplified signal;

[0026] Perform low-pass filtering on the analog amplified signal to generate an analog voltage-controlled signal.

[0027] Further, regulating the relative delay of each frame of transmitted signal and the local oscillator signal according to the delay voltage-controlled signal includes:

[0028] Use the delay voltage-controlled signal to modulate a voltage-controlled oscillator to generate a frequency-modulated signal;

[0029] Frequency multiply the FM signal to generate a frequency - multiplied local oscillator signal and send it to the RF front - end;

[0030] Amplify the power of the frequency - multiplied local oscillator signal to generate a transmission signal and send it to the transmitting antenna.

[0031] Further, the coefficients of the fractional delay filter are designed by the maximum - flatness criterion approximation method.

[0032] In a second aspect, the present invention proposes a millimeter - wave radar receiving method based on equivalent sampling. The method includes:

[0033] Mix the received target echo signal based on the frequency - multiplied local oscillator signal to generate an analog intermediate - frequency signal, where the frequency - multiplied local oscillator signal is obtained by adjusting the relative delay of the local oscillator signal according to the delay voltage - controlled signal;

[0034] Perform analog - to - digital conversion on the analog intermediate - frequency signal to generate a digital intermediate - frequency signal;

[0035] Generate read / write address signals based on the single - frame synchronization signal and the multi - frame synchronization signal, where the single - frame synchronization signal and the multi - frame synchronization signal are generated according to the system FM frame length, the analog - to - digital conversion rate, and the equivalent sampling ratio;

[0036] Perform read / write operations on the digital intermediate - frequency signal based on the read / write address signals to generate equivalent sampling data.

[0037] Further, the mixing the received target echo signal based on the frequency - multiplied local oscillator signal to generate an analog intermediate - frequency signal includes:

[0038] Perform low - noise amplification on the target echo signal to generate a low - noise amplified signal;

[0039] Perform power amplification on the frequency - multiplied local oscillator signal to generate a local oscillator amplified signal;

[0040] Mix the low - noise amplified signal and the local oscillator amplified signal to generate a mixed signal;

[0041] Perform band - pass filtering on the mixed signal to generate the analog intermediate - frequency signal.

[0042] Further, the generating read / write address signals based on the single - frame synchronization signal and the multi - frame synchronization signal includes:

[0043] When the odd - numbered multi - frame synchronization signal arrives, the write address after the first single - frame synchronization signal arrives and the write address after the M - th single - frame synchronization signal arrives are corresponding addresses in the first address space;

[0044] When the even - numbered multi - frame synchronization signal arrives, the write addresses after the arrival of the first single - frame synchronization signal and after the arrival of the M - th single - frame synchronization signal are corresponding addresses in the second address space;

[0045] After the odd - numbered multi - frame synchronization signal arrives, the read address fetches one data from the first address space every AR numbers;

[0046] After the even - numbered multi - frame synchronization signal arrives, the read address fetches one data from the second address space every AR numbers;

[0047] Among them, the addresses of the first address space and the second address space are [0 to (M * AR - 1)] and [M * AR to (2 * M * AR - 1)] respectively, and AR is equal to the analog - to - digital conversion rate multiplied by the period of the single - frame synchronization signal.

[0048] Further, the method further includes:

[0049] When the odd - numbered multi - frame synchronization signal arrives, the write address after the arrival of the first single - frame synchronization signal is [0 to (1 * AR - 1)], and the write address after the arrival of the M - th single - frame synchronization signal is [(M - 1) * AR to (M * AR - 1)];

[0050] When the even - numbered multi - frame synchronization signal arrives, the write address after the arrival of the first single - frame synchronization signal is [M * AR to ((M + 1) * AR - 1)], and the write address after the arrival of the M - th single - frame synchronization signal is [(2M - 1) * AR to (2M * AR - 1)].

[0051] Further, the performing the read / write operation on the digital intermediate - frequency signal based on the read / write address signal to generate equivalent sampling data includes:

[0052] Writing the digital intermediate - frequency signal into the first address space or the second address space based on the write address signal;

[0053] Reading out the data in the first address space or the second address space based on the read address signal to generate equivalent sampling data.

[0054] In a third aspect, the present invention also proposes a millimeter - wave radar transmitting device based on equivalent sampling, including:

[0055] A frequency modulation controller, which is used to generate a single-frame synchronization signal, a multi-frame synchronization signal and a long-frame selection signal according to the system frequency modulation period, the digital-to-analog conversion rate and the equivalent sampling ratio, and generate a baseband modulation signal and a delay line selection signal according to the single-frame synchronization signal and the multi-frame synchronization signal. Wherein, the period of the single-frame synchronization signal is equal to the period of the frequency modulation signal, the period of the multi-frame synchronization signal is a multiple of the period of the single-frame synchronization signal, the sampling time is adjusted by a fractional delay filter when the long-frame selection signal is low, and the sampling time is adjusted by a stepped delay line when the long-frame selection signal is high;

[0056] A voltage-controlled signal source, which is used to generate an analog voltage-controlled signal according to the baseband modulation signal;

[0057] A stepped delay line, which is used to delay and adjust the analog voltage-controlled signal by using the delay line selection signal to generate a delayed voltage-controlled signal;

[0058] A frequency modulation source, which is used to regulate the relative delay of each frame of transmitted signal and the local oscillator signal according to the delayed voltage-controlled signal to generate a target transmitted signal and a frequency-multiplied local oscillator signal.

[0059] Further, both the single-frame synchronization signal and the multi-frame synchronization signal are periodically repeated pulses, and the period of the multi-frame synchronization signal is equal to the period of the single-frame synchronization signal multiplied by the equivalent sampling ratio.

[0060] Further, the frequency modulation controller includes:

[0061] A synchronization frame generator, which is used to generate a single-frame synchronization signal, a multi-frame synchronization signal and a long-frame selection signal according to the system frequency modulation period, the digital-to-analog conversion rate and the equivalent sampling ratio;

[0062] A waveform counter, which is used to count the rising edge of the single-frame synchronization signal to generate a linear counting sequence;

[0063] A frame counter, which is used to use the multi-frame synchronization signal as an initial clearing signal to count the pulses of the single-frame synchronization signal to generate a frame cycle count;

[0064] A fractional delay filter, which is used to perform fractional delay filtering on the linear counting sequence based on the fractional delay value to generate a baseband modulation signal, where the fractional delay value is zero when the long-frame selection signal is high, and the fractional delay value is the frame cycle count when the long-frame selection signal is low;

[0065] A data switch, which is used to generate a delay line selection signal based on the frame cycle count, where the delay line selection signal is equal to the frame cycle count when the long-frame selection signal is high, and the delay line selection signal is equal to zero when the long-frame selection signal is low.

[0066] Further, at T s ≥T dac *2 BdacWhen it is, the long frame selection signal is high; at T s <T dac *2 Bdac When it is, the long frame selection signal is low;

[0067] Among them, T s is the system frequency modulation period, T dac is the digital-to-analog conversion period, and B dac is the digital-to-analog conversion accuracy.

[0068] Furthermore, the voltage-controlled signal source includes:

[0069] A digital-to-analog converter for performing digital-to-analog conversion on the baseband modulation signal to generate an analog voltage signal;

[0070] An operational amplifier for amplifying the analog voltage signal to generate an analog amplified signal;

[0071] A low-pass filter for performing low-pass filtering on the analog amplified signal to generate an analog voltage-controlled signal.

[0072] Furthermore, the frequency modulation source includes:

[0073] A voltage-controlled oscillator for modulating the voltage-controlled oscillator using the delayed voltage-controlled signal to generate a frequency modulation signal;

[0074] A frequency multiplier for performing frequency multiplication on the frequency modulation signal to generate a frequency-multiplied local oscillator signal and sending it to the RF front end;

[0075] A power amplifier for amplifying the power of the frequency-multiplied local oscillator signal to generate a transmission signal and sending it to the transmitting antenna.

[0076] Fourthly, the present invention also proposes a millimeter-wave radar receiving device based on equivalent sampling, including:

[0077] An RF front end for mixing the received target echo signal based on the frequency-multiplied local oscillator signal to generate an analog intermediate frequency signal, where the frequency-multiplied local oscillator signal is obtained by adjusting the relative delay of the local oscillator signal according to the delayed voltage-controlled signal;

[0078] An analog-to-digital converter for performing analog-to-digital conversion on the analog intermediate frequency signal to generate a digital intermediate frequency signal;

[0079] A frame processor for generating read / write address signals based on the single-frame synchronization signal and the multi-frame synchronization signal, and performing read / write operations on the digital intermediate frequency signal based on the read / write address signals to generate equivalent sampling data and output it to the signal processor, where the single-frame synchronization signal and the multi-frame synchronization signal are generated according to the system frequency modulation frame length, the digital-to-analog conversion rate, and the equivalent sampling ratio.

[0080] Furthermore, the RF front end includes:

[0081] A low-noise amplifier, which is used to perform low-noise amplification on the target echo signal to generate a low-noise amplified signal;

[0082] A local oscillator amplifier, which is used to perform power amplification on the frequency-multiplied local oscillator signal to generate a local oscillator amplified signal;

[0083] A mixer amplifier, which is used to mix the low-noise amplified signal and the local oscillator amplified signal to generate a mixed signal;

[0084] An anti-aliasing filter, which is used to perform band-pass filtering on the mixed signal to generate the analog intermediate-frequency signal.

[0085] Further, the frame processor includes:

[0086] A write controller, which is used to generate a write address signal based on the single-frame synchronization signal and the multi-frame synchronization signal and output it to the data buffer;

[0087] A read controller, which is used to generate a read address signal based on the single-frame synchronization signal and the multi-frame synchronization signal and output it to the data buffer;

[0088] A data buffer, which is used to perform a write or read operation on the digital intermediate-frequency signal output by the analog-to-digital converter based on the write address signal and the read address signal to generate equivalent sampling data.

[0089] Further, a first address space and a second address space are set in the data buffer, and the addresses are [0 to (M * AR - 1)] and [M * AR to (2 * M * AR - 1)] respectively, where AR is equal to the analog-to-digital conversion rate multiplied by the period of the single-frame synchronization signal;

[0090] The write controller is used to, when the odd-numbered multi-frame synchronization signal arrives, the write addresses after the arrival of the first single-frame synchronization signal and the arrival of the Mth single-frame synchronization signal are the corresponding addresses in the first address space; when the even-numbered multi-frame synchronization signal arrives, the write addresses after the arrival of the first single-frame synchronization signal and the arrival of the Mth single-frame synchronization signal are the corresponding addresses in the second address space;

[0091] The read controller is used to, after the arrival of the odd-numbered multi-frame synchronization signal, the read address is to take out one data from the first address space every AR numbers; after the arrival of the even-numbered multi-frame synchronization signal, the read address is to take out one data from the second address space every AR numbers.

[0092] Further, when the odd-numbered multi-frame synchronization signal arrives, the write address after the arrival of the first single-frame synchronization signal is [0 to (1 * AR - 1)], and the write address after the arrival of the Mth single-frame synchronization signal is [(M - 1) * AR to (M * AR - 1)];

[0093] When the even - numbered multi - frame synchronization signal arrives, the write address after the arrival of the first single - frame synchronization signal is [M*AR~((M + 1)*AR - 1)], and the write address after the arrival of the M - th single - frame synchronization signal is [(2M - 1)*AR~(2M*AR - 1)].

[0094] Fifthly, the present invention also provides a millimeter - wave radar transceiver system based on equivalent sampling, including a transmitting device, a transmitting antenna, a receiving device, and a receiving antenna;

[0095] The transmitting device is used to execute the millimeter - wave radar transmitting method based on equivalent sampling as described above to generate a target transmission signal to the transmitting antenna;

[0096] The receiving device is used to execute the millimeter - wave radar receiving method based on equivalent sampling as described above to process the target echo signal generated by the receiving antenna to generate equivalent sampling data.

[0097] The advantages of the present invention are as follows:

[0098] (1) Different from the traditional equivalent sampling scheme based on a delay - sampled clock, the present invention uses a fractional - delay filter to continuously adjust the sampling time of equivalent sampling to delay the base - band modulation signal. Since the analog voltage - controlled signal, the transmission signal, and the base - band modulation signal are on the same link, the transmission signal is also delayed. The delay accuracy is high, and the timing ambiguity problem caused by phase - shifting the sampling clock in the traditional method is avoided, eliminating the complex timing correction process. Moreover, when the frame length is too large, due to the limited resolution of the digital - to - analog converter for the adjacent distance values of the waveform counter, the fractional - delay accuracy is insufficient. Therefore, a stepped delay line is used to adjust the sampling time of equivalent sampling, thereby expanding the applicable range of the system. In this way, by precisely controlling the relative delay of each frame of the transmission signal and the local oscillator signal, the echo signal can be sampled within multiple frame periods, and then the sampling data is reconstructed to achieve equivalent high - speed sampling at a low original sampling rate. This enables high - speed acquisition to be achieved using a low - speed analog - to - digital converter at the radar receiving end. The system cost based on equivalent sampling is lower than that of a conventional high - speed analog - to - digital conversion system. At the same time, as the conversion rate decreases, the system power consumption also decreases. Therefore, an equivalent improvement in the analog - to - digital conversion rate can be obtained at a relatively low software and hardware cost.

[0099] (2) By mixing the received target echo signal with the frequency-doubled local oscillator signal, the present invention can obtain an intermediate-frequency signal with a lower frequency, reducing the requirement for the conversion rate of the analog-to-digital converter. By sampling the echo signal within multiple frame periods and then performing sampling data reconstruction, equivalent high-speed sampling is achieved at a low original sampling rate. High-speed acquisition can be realized using a low-speed analog-to-digital converter, and the equivalent sampling rate can reach over hundreds of megahertz, still enabling a large detection range. Moreover, the problem of timing ambiguity caused by phase-shifting the sampling clock is avoided, eliminating the complex timing correction process.

[0100] (3) The present invention uses a ping-pong buffer to perform equivalent sampling recovery on the analog-to-digital conversion data, achieving continuous and uninterrupted output of equivalent sampling data with high real-time performance.

[0101] Additional aspects and advantages of the present invention will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present invention. Brief Description of the Drawings

[0102] Figure 1 is a schematic flowchart of a millimeter-wave radar transmitting method based on equivalent sampling proposed in the first embodiment of the present invention;

[0103] Figure 2 is a schematic flowchart of a millimeter-wave radar receiving method based on equivalent sampling proposed in the second embodiment of the present invention;

[0104] Figure 3 is a schematic structural diagram of a millimeter-wave radar transmitting device based on equivalent sampling proposed in the third embodiment of the present invention;

[0105] Figure 4 is a schematic structural diagram of the frequency modulation controller in the third embodiment of the present invention;

[0106] Figure 5 is a schematic structural diagram of the voltage-controlled signal source in the third embodiment of the present invention;

[0107] Figure 6 is a schematic structural diagram of the frequency modulation source in the third embodiment of the present invention;

[0108] Figure 7 is a schematic structural diagram of a millimeter-wave radar receiving device based on equivalent sampling proposed in the fourth embodiment of the present invention;

[0109] Figure 8 is a schematic structural diagram of the radio frequency front end in the fourth embodiment of the present invention;

[0110] Figure 9 is a schematic structural diagram of the frame processor in the fourth embodiment of the present invention;

[0111] Figure 10 It is a schematic structural diagram of a millimeter-wave radar transceiver system based on equivalent sampling proposed in the fifth embodiment of the present invention. Specific implementation manners

[0112] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without making creative efforts shall fall within the protection scope of the present invention.

[0113] Embodiment 1

[0114] As Figure 1 shown, the first embodiment of the present invention proposes a millimeter-wave radar transmission method based on equivalent sampling. The method includes the following steps:

[0115] S101. Generate a single-frame synchronization signal, a multi-frame synchronization signal, and a long-frame selection signal according to the system frequency modulation period, the digital-to-analog conversion rate, and the equivalent sampling ratio. Among them, the period of the single-frame synchronization signal is equal to the frequency modulation signal period, and the period of the multi-frame synchronization signal is a multiple of the single-frame synchronization signal period;

[0116] Specifically, in this embodiment, the equivalent sampling method is adopted. Let the equivalent sampling ratio be M, and the typical value is 8. The single-frame synchronization signal e is a periodically repeated pulse, and its period T s is equal to the system frequency modulation period; the multi-frame synchronization signal f is also a periodically repeated pulse, and the rising edge of the pulse is aligned with the single-frame synchronization signal e, and the period T m is M*T s . Assume that T s is equal to 10 us. If the equivalent sampling ratio is M = 8, then the period T m is M*T s = 80 us.

[0117] S102. Generate a baseband modulation signal and a delay line selection signal according to the single-frame synchronization signal and the multi-frame synchronization signal. Among them, when the long-frame selection signal is low, the sampling time is adjusted through a fractional delay filter, and when the long-frame selection signal is high, the sampling time is adjusted through a stepped delay line;

[0118] It should be noted that corresponding to the equivalent sampling ratio, the stepped delay line has M gears. In this embodiment, when the long frame selection signal is low, a fractional delay filter is used to adjust the sampling time of the equivalent sampling, achieving high precision, and there is no need for a clock phase adjustment circuit in terms of hardware, and the operation is simple and reliable. In some special application scenarios, if the system frequency modulation period is too long, the limited resolution of the digital-to-analog converter will reduce the fractional delay accuracy. In response to this situation, this embodiment uses a stepped delay line to replace the fractional delay filter to implement equivalent sampling, so as to make up for the adverse impact of the quantization bits of the digital-to-analog converter on the delay accuracy, and selects between the fractional delay filter and the stepped delay line according to the system frequency modulation period, thereby expanding the applicable range of the sampling technology.

[0119] S103. Generate an analog voltage-controlled signal according to the baseband modulation signal, and use the delay line selection signal to adjust the delay of the analog voltage-controlled signal to generate a delayed voltage-controlled signal;

[0120] S104. Regulate the relative delay of each frame of transmitted signal and the local oscillator signal according to the delayed voltage-controlled signal to generate a target transmitted signal and a frequency-multiplied local oscillator signal.

[0121] In this embodiment, by accurately regulating the relative delay of each frame of transmitted signal and the local oscillator signal, so as to sample the echo signal within multiple frame periods, and then perform sampling data reconstruction, achieving equivalent high-speed sampling at a low original sampling rate, which enables a low-speed analog-to-digital converter to be used at the radar receiving end to achieve high-speed acquisition. The system cost based on equivalent sampling is lower than that of a conventional high-speed analog-to-digital conversion system. At the same time, as the conversion rate decreases, the system power consumption also decreases. And different from the traditional equivalent sampling scheme based on a delayed sampling clock, it avoids the timing ambiguity problem caused by phase-shifting the sampling clock in the traditional method, eliminates the complex timing correction process, and this equivalent scheme only uses one analog-to-digital converter, with obvious cost advantages. Compared with the prior art, it can obtain an equivalent improvement in the analog-to-digital conversion rate with lower software and hardware costs.

[0122] As a further preferred technical solution, in the step S10, according to the single-frame synchronization signal and the multi-frame synchronization signal, generate the baseband modulation signal and the delay line selection signal, which specifically includes the following steps:

[0123] S11. Count the rising edge of the single-frame synchronization signal to generate a linear counting sequence;

[0124] Specifically, in this embodiment, counting starts from zero based on the rising edge of the single-frame synchronization signal e. In this embodiment, the voltage-controlled signal is a triangular wave, and the maximum count value is T s / T dac -1, so the linear counting sequence e2 is [0, 1, 2,..., 999], the system frequency modulation period T s = 10us, the digital-to-analog conversion period Tdac = 10 ns.

[0125] S12. Use the multi-frame synchronization signal as the initial clear signal to count the pulses of the single-frame synchronization signal and generate a frame cycle count;

[0126] Specifically, use the multi-frame synchronization signal f as the initial clear signal to count the pulses of the single-frame synchronization signal e and generate a frame cycle count e3. Taking the system parameter settings in this embodiment as an example, the frame cycle count e3 is calculated as [0, 1, 2,.., 7].

[0127] S13. Perform fractional delay filtering on the linear count sequence based on the fractional delay value to generate a baseband modulation signal, where the fractional delay value is zero when the long frame selection signal is high, and the fractional delay value is the frame cycle count when the long frame selection signal is low;

[0128] S14. Generate a delay line selection signal based on the frame cycle count, where the delay line selection signal is equal to the frame cycle count when the long frame selection signal is high, and the delay line selection signal is equal to zero when the long frame selection signal is low.

[0129] It should be noted that when the long frame selection signal e1 is high, the delay line selection signal h is equal to the frame cycle count e3, and the fractional delay value e4 is 0; when the long frame selection signal e1 is low, the fractional delay value e4 is equal to the frame cycle count e3, and the delay line selection signal h is 0.

[0130] In this embodiment, a fractional delay filter is used to adjust the sampling time of equivalent sampling, with high implementation accuracy, and the clock phase adjustment circuit is omitted in hardware, and the operation is simple and reliable. When the system frequency modulation period is too long, a stepped delay line is used to replace the fractional delay filter to achieve equivalent sampling, so as to make up for the adverse impact of the quantization bits of the digital-to-analog converter on the delay accuracy, and the robustness is strong.

[0131] Preferably, the coefficients of the fractional delay filter are designed using the maximum flatness criterion approximation method.

[0132] As a further preferred technical solution, the method further includes:

[0133] At T s ≥ T dac * 2 Bdac , the long frame selection signal is high;

[0134] At T s < T dac * 2 Bdac , the long frame selection signal is low;

[0135] Among them, T s is the system frequency modulation period, T dacis the digital-to-analog conversion period, B dac is the digital-to-analog conversion accuracy.

[0136] Specifically, in this embodiment, the system frequency modulation period T s = 10us, the digital-to-analog conversion period T dac = 10ns, the digital-to-analog conversion accuracy Bdac is 16, then the long frame selection signal e1 is low; taking the long frame selection signal e1 being low as an example, according to the fractional delay value e4, the linear counting sequence e2 is subjected to fractional delay filtering, and the absolute delays corresponding to the fractional delay values e4 values [0, 1, 2,.., M-1] are [0, 1, 2,.., M-1] / M / f adc , f adc is the analog-to-digital conversion rate. In this embodiment, the absolute delays implemented by the fractional delay filter are [0, 5, 10,…, 35] ns.

[0137] As a further preferred technical solution, the number of steps of the stepped delay line is equal to the equivalent sampling ratio, and the step size is equal to the reciprocal of the equivalent sampling rate.

[0138] Specifically, taking the minimum sampling rate of a conventional analog-to-digital converter as 200 MHz as an example, the stepped delay line has M gears, M = 8, and the corresponding analog-to-digital conversion rate f adc is 200 / 8 = 25 MHz; taking the upper frequency limit f H of the analog intermediate frequency signal as a typical value of 100 MHz as an example, the delay step between each gear is 1 / (2*f H ) = 5 ns.

[0139] As a further preferred technical solution, the step S103: generating an analog voltage-controlled signal according to the baseband modulation signal specifically includes the following steps:

[0140] S1031. Perform digital-to-analog conversion on the baseband modulation signal to generate an analog voltage signal;

[0141] S1032. Perform amplification processing on the analog voltage signal to generate an analog amplified signal;

[0142] S1033. Perform low-pass filtering processing on the analog amplified signal to generate an analog voltage-controlled signal.

[0143] As a further preferred technical solution, the step S104: regulating the relative delay of each frame of transmitted signal and the local oscillator signal according to the delay voltage-controlled signal specifically includes the following steps:

[0144] S1041. Modulate a voltage-controlled oscillator with the delay voltage-controlled signal to generate a frequency-modulated signal;

[0145] S1042. Perform frequency doubling processing on the frequency-modulated signal to generate a frequency-doubled local oscillator signal and send it to the RF front end;

[0146] S1043. Amplify the frequency-doubled local oscillator signal to generate a transmission signal and send it to the transmitting antenna.

[0147] It should be noted that in this embodiment, based on the fractional delay filter or the stepped delay line, the transmission signal and the received local oscillator are adjusted for stepped delay, so that the echo signal falls into different sampling windows, thus achieving a relatively high equivalent sampling rate. The timing accuracy of the equivalent sampling points is high. For example, if the equivalent sampling ratio is set to 8 or 16, the conversion rate of the analog-to-digital converter can be reduced to the order of ten megahertz. Through data reconstruction between multiple sampling frames, the equivalent sampling rate is above one hundred megahertz, and a relatively large detection range can still be achieved.

[0148] Embodiment 2

[0149] As Figure 2 shown, the second embodiment of the present invention proposes a millimeter-wave radar receiving method based on equivalent sampling. The method includes the following steps:

[0150] S201. Mix the received target echo signal based on the frequency-doubled local oscillator signal to generate an analog intermediate-frequency signal, where the frequency-doubled local oscillator signal is obtained by adjusting the relative delay of the local oscillator signal according to the delay voltage-controlled signal;

[0151] S202. Perform analog-to-digital conversion on the analog intermediate-frequency signal to generate a digital intermediate-frequency signal;

[0152] S203. Generate read / write address signals based on the single-frame synchronization signal and the multi-frame synchronization signal, where the single-frame synchronization signal and the multi-frame synchronization signal are generated according to the system frequency modulation frame length, the analog-to-digital conversion rate, and the equivalent sampling ratio;

[0153] S204. Perform read / write operations on the digital intermediate-frequency signal based on the read / write address signals to generate equivalent sampling data.

[0154] It should be noted that in the above first embodiment, based on the fractional delay filter or the stepped delay line, the transmission signal and the received local oscillator are adjusted for stepped delay, so that the echo signal falls into different sampling windows. In this embodiment, on the radar receiving side, the received target echo signal is mixed based on the frequency-doubled local oscillator signal, and an intermediate-frequency signal with a relatively low frequency can be obtained, reducing the requirement for the conversion rate of the analog-to-digital converter. By sampling the echo signal within multiple frame periods, and then implementing sampling data reconstruction, equivalent high-speed sampling is achieved at a low original sampling rate. A low-speed analog-to-digital converter can be used to achieve high-speed acquisition, and the equivalent sampling rate can reach above one hundred megahertz. A relatively large detection range can still be achieved, and the problem of timing ambiguity caused by phase shifting of the sampling clock is avoided, eliminating the complex timing correction process.

[0155] As a further preferred technical solution, in step S201: the received target echo signal is mixed based on the frequency-doubled local oscillator signal to generate an analog intermediate-frequency signal, which specifically includes the following steps:

[0156] S2011. Perform low-noise amplification on the target echo signal to generate a low-noise amplified signal;

[0157] S2012. Perform power amplification on the frequency-doubled local oscillator signal to generate a locally amplified signal;

[0158] S2013. Mix the low-noise amplified signal and the locally amplified signal to generate a mixed signal;

[0159] S2014. Perform band-pass filtering on the mixed signal to generate the analog intermediate-frequency signal.

[0160] It should be noted that in this embodiment, a linearly frequency-modulated local oscillator is used to mix the echo signal received by the low-noise amplifier, and an intermediate-frequency signal with a lower frequency can be obtained, reducing the requirement for the conversion rate of the analog-to-digital converter. Moreover, power amplification is performed on the frequency-doubled local oscillator signal to generate an amplified signal to compensate for the path loss of the high-frequency local oscillator signal, reducing the power requirement for the frequency-doubled local oscillator signal.

[0161] As a further preferred technical solution, in step S203: a read / write address signal is generated based on the single-frame synchronization signal and the multi-frame synchronization signal, which specifically includes the following steps:

[0162] S2031. When the odd-numbered multi-frame synchronization signal arrives, the write addresses after the arrival of the first single-frame synchronization signal and the Mth single-frame synchronization signal are corresponding addresses in the first address space;

[0163] S2032. When the even-numbered multi-frame synchronization signal arrives, the write addresses after the arrival of the first single-frame synchronization signal and the Mth single-frame synchronization signal are corresponding addresses in the second address space;

[0164] S2033. After the odd-numbered multi-frame synchronization signal arrives, the read address is to take out one data from the first address space every AR numbers;

[0165] S2034. After the even-numbered multi-frame synchronization signal arrives, the read address is to take out one data from the second address space every AR numbers;

[0166] Among them, the addresses of the first address space and the second address space are [0 to (M * AR - 1)] and [M * AR to (2 * M * AR - 1)] respectively, and AR is equal to the analog-to-digital conversion rate multiplied by the period T of the single-frame synchronization signal s , and in this embodiment, it is 25 MHz * 10 us = 250.

[0167] It should be noted that in this embodiment, a ping-pong buffer is used to perform equivalent sampling recovery on the analog-to-digital conversion data, realizing continuous output of equivalent sampling data without interruption and having high real-time performance.

[0168] As a further preferred technical solution, the write address f1 is specifically:

[0169] When the odd-numbered multi-frame synchronization signal arrives, the write address after the arrival of the first single-frame synchronization signal is [0 to (1*AR - 1)], and the write address after the arrival of the Mth single-frame synchronization signal is [(M - 1)*AR to (M*AR - 1)];

[0170] When the even-numbered multi-frame synchronization signal arrives, the write address after the arrival of the first single-frame synchronization signal is [M*AR to ((M + 1)*AR - 1)], and the write address after the arrival of the Mth single-frame synchronization signal is [(2M - 1)*AR to (2M*AR - 1)].

[0171] As a further preferred technical solution, after the odd-numbered multi-frame synchronization signal f arrives, the read address f2 is:

[0172] [M*AR, (M + 1)*AR, (M + 2)*AR, …, (2M - 1)*AR, 1 + M*AR, 1 + (M + 1)*AR, 1 + (M + 2)*AR, …, 1 + (2M - 1)*AR, 2 + M*AR, 2 + (M + 1)*AR, 2 + (M + 2)*AR, …, 2 + (2M - 1)*AR, …, AR - 1 + M*AR, AR - 1 + (M + 1)*AR, AR - 1 + (M + 1)*AR, …, AR - 1 + (2M - 1)*AR];

[0173] After the even-numbered multi-frame synchronization signal f arrives, the read address f2 is:

[0174] [0, AR, 2*AR, …, (M - 1)*AR, 1, 1 + AR, 1 + 2*AR, …, 1 + (M - 1)*AR, 2, 2 + AR, 2 + 2*AR, …, 2 + (M - 1)*AR, …, AR - 1, AR - 1 + AR, AR - 1 + 2*AR, …, AR - 1 + (M - 1)*AR].

[0175] As a further preferred technical solution, the step S204: performing read / write operations on the digital intermediate frequency signal based on the read / write address signals to generate equivalent sampling data includes the following steps:

[0176] S2041. Writing the digital intermediate frequency signal into the first address space or the second address space based on the write address signal;

[0177] S2042. Read the data in the first address space or the second address space based on the read address signal to generate equivalent sampling data.

[0178] It should be noted that in this embodiment, the ping-pong buffer mechanism is adopted to effectively avoid the timing competition problem of simultaneous read and write access to the same address area. The write operation address is continuous, while the read operation takes out one data from the data buffer 4-3 every AR numbers, thus realizing the time-domain rearrangement of M-frame equivalent sampling data and ensuring that the equivalent sampling data d is real-time and continuous in time.

[0179] Embodiment III

[0180] As Figure 3 shown, the third embodiment of the present invention proposes a millimeter-wave radar transmitting device based on equivalent sampling. The transmitting device includes:

[0181] A frequency modulation controller 6, configured to generate a single-frame synchronization signal, a multi-frame synchronization signal, and a long-frame selection signal according to the system frequency modulation period, the digital-to-analog conversion rate, and the equivalent sampling ratio, and generate a baseband modulation signal and a delay line selection signal according to the single-frame synchronization signal and the multi-frame synchronization signal. Among them, the period of the single-frame synchronization signal is equal to the frequency modulation signal period, the period of the multi-frame synchronization signal is a multiple of the single-frame synchronization signal period, adjust the sampling moment through a fractional delay filter when the long-frame selection signal is low, and adjust the sampling moment through a stepped delay line when the long-frame selection signal is high;

[0182] A voltage-controlled signal source 7, configured to generate an analog voltage-controlled signal according to the baseband modulation signal;

[0183] A stepped delay line 8, configured to perform delay adjustment on the analog voltage-controlled signal by using the delay line selection signal to generate a delayed voltage-controlled signal;

[0184] A frequency modulation source 9, configured to regulate the relative delay of each frame of transmitted signal and the local oscillator signal according to the delayed voltage-controlled signal to generate a target transmitted signal and a frequency-doubled local oscillator signal.

[0185] This embodiment is different from the traditional equivalent sampling scheme based on a delayed sampling clock. This scheme uses a fractional delay filter and a delay line to delay the signal, realizes stepped delay adjustment of the transmitted signal and the received local oscillator, makes the echo signal fall into different sampling windows, thereby achieving a higher equivalent sampling rate, and the timing accuracy of the equivalent sampling points is high; and there is no timing ambiguity problem caused by the periodicity of the clock signal, eliminating the complex timing correction process, and obtaining an equivalent improvement in the analog-to-digital conversion rate at a lower software and hardware cost, which is applicable to millimeter-wave radar systems.

[0186] As a further preferred technical solution, as Figure 4As shown, the frequency modulation controller 6 includes a synchronization frame generator 6-1, a waveform counter 6-2, a frame counter 6-3, a data switch 6-4, and a fractional delay filter 6-5;

[0187] Among them, the synchronization frame generator 6-1 is connected to the frame processor 4, the waveform counter 6-2, the frame counter 6-3, and the data switch 6-4. The waveform counter 6-2 is connected to the fractional delay filter 6-5. The frame counter 6-3 is connected to the data switch 6-4. The data switch 6-4 is connected to the fractional delay filter 6-5 and the step delay line 8. The fractional delay filter 6-5 is connected to the voltage-controlled signal source 7.

[0188] The synchronization frame generator 6-1 is used to generate a single-frame synchronization signal e, a multi-frame synchronization signal f, and a long-frame selection signal e1 according to the system frequency modulation frame length, the digital-to-analog conversion rate, and the equivalent sampling ratio, and output the single-frame synchronization signal e to the frame processor 4, the waveform counter 6-2, and the frame counter 6-3, output the multi-frame synchronization signal f to the frame processor 4 and the frame counter 6-3, and output the long-frame selection signal e1 to the data switch 6-4;

[0189] The waveform counter 6-2 is used to count the rising edge of the single-frame synchronization signal e, generate a linear counting sequence e2, and output the linear counting sequence e2 to the fractional delay filter 6-5;

[0190] The frame counter 6-3 is used to use the multi-frame synchronization signal f as an initial clear signal, count the pulses of the single-frame synchronization signal e, generate a frame cycle count e3, and output the frame cycle count e3 to the data switch 6-4;

[0191] The data switch 6-4 is used to output a fractional delay value e4 to the fractional delay filter 6-5 and output a delay line selection signal h to the step delay line 8, where the delay line selection signal h is equal to the frame cycle count e3 when the long-frame selection signal e1 is at a high level, and the delay line selection signal h is equal to zero when the long-frame selection signal e1 is at a low level;

[0192] The fractional delay filter 6-5 is used to perform fractional delay filtering on the linear counting sequence based on the fractional delay value, generate a baseband modulation signal g, and output the baseband modulation signal g to the voltage-controlled signal source 7, where the fractional delay value is zero when the long-frame selection signal e1 is at a high level, and the fractional delay value is the frame cycle count e3 when the long-frame selection signal e1 is at a low level.

[0193] Specifically, the single-frame synchronization signal e is a periodically repeated pulse, and its period T s is equal to the system frequency modulation period, which is 10 us in this embodiment; the multi-frame synchronization signal f is also a periodically repeated pulse, the rising edge of the pulse is aligned with the single-frame synchronization signal e, and the period T m is M*Ts In this embodiment, it is 80 us; the specific value of the long frame selection signal e1 depends on T s , the digital-to-analog conversion period T dac and the digital-to-analog conversion accuracy B dac , at T s <T dac *2 Bdac , the long frame selection signal is low, and the fractional delay filter 6-5 is selected to achieve delay adjustment with high delay accuracy. Considering that the adjacent distance value of the waveform counter is limited by the resolution of the digital-to-analog converter when the frame length is too large, T s ≥T dac *2 Bdac When the time is long, the long frame selection signal e1 is high, and the stepped delay line is selected to achieve delay adjustment. Otherwise, the long frame selection signal e1 is low, and the fractional delay filter is selected to achieve delay adjustment; in this embodiment, T dac = 10 ns, B dac is 16, and the long frame selection signal e1 is low.

[0194] The waveform counter 6-2 starts counting from zero based on the rising edge of the single-frame synchronization signal e. In this embodiment, the voltage control signal is a triangular wave, and the maximum count value is T s / T dac -1, so the linear counting sequence e2 is [0, 1, 2,..., 999]; the frame counter 6-3 uses the multi-frame synchronization signal f as the initial clear signal to count the pulses of the single-frame synchronization signal e and generates the frame cycle count e3. In this embodiment, the frame cycle count e3 is [0, 1, 2,.., 7]; the data switch 6-4 completes the output path switching of the frame cycle count e3 based on the value of the long frame selection signal e1; when the long frame selection signal e1 is high, the delay line selection signal h is equal to the frame cycle count e3, and the fractional delay value e4 is 0; when the long frame selection signal e1 is low, the fractional delay value e4 is equal to the frame cycle count e3, and the delay line selection signal h is 0; the fractional delay filter 6-5 performs fractional delay filtering on the linear counting sequence e2 according to the fractional delay value e4, and the absolute delay corresponding to the fractional delay value e4 value [0, 1, 2,.., M-1] is [0, 1, 2,.., M-1] / M / f adc ; in this embodiment, the absolute delay achieved by the fractional delay filter 6-5 is [0, 5, 10,..., 35] ns, and the fractional delay filter coefficients are designed using the maximum flatness criterion approximation method.

[0195] In this embodiment, a fractional delay filter is used to adjust the sampling time of equivalent sampling, achieving high precision and requiring no clock phase adjustment circuit in terms of hardware, with simple and reliable operation. In some special application scenarios, if the system frequency modulation period is too long, the limited resolution of the digital-to-analog converter will reduce the fractional delay accuracy. In view of this situation, the present invention uses a stepped delay line to replace the fractional delay filter to implement equivalent sampling, so as to make up for the adverse effect of the quantization bits of the digital-to-analog converter on the delay accuracy. The present invention selects between the fractional delay filter and the stepped delay line according to the system frequency modulation period, thereby expanding the applicable range of the sampling technique.

[0196] As a further preferred technical solution, as Figure 5 shown, the voltage-controlled signal source 7 includes a digital-to-analog converter 7-1, an operational amplifier 7-2, and a low-pass filter 7-3; wherein, the digital-to-analog converter 7-1 is respectively connected to the frequency modulation controller 6 and the operational amplifier 7-2, the operational amplifier 7-2 is connected to the low-pass filter 7-3, and the low-pass filter 7-3 is connected to the stepped delay line 8.

[0197] The digital-to-analog converter 7-1 is configured to receive the baseband modulation signal g from the frequency modulation controller 6 and perform digital-to-analog conversion to generate an analog voltage signal g1, and output the analog voltage signal g1 to the operational amplifier 7-2;

[0198] The operational amplifier 7-2 is configured to amplify the analog voltage signal g1 to generate an analog amplified signal g2 and output the analog amplified signal g2 to the low-pass filter 7-3;

[0199] The low-pass filter 7-3 is configured to perform low-pass filtering on the analog amplified signal g2 to generate an analog voltage-controlled signal i and output the analog voltage-controlled signal i to the stepped delay line 8.

[0200] In this embodiment, a voltage-controlled signal source is used to condition the baseband modulation signal g. First, the analog-to-digital converter converts the baseband modulation signal g into an analog signal; then, an operational amplifier is used to expand the voltage range of the analog signal; finally, a low-pass filter is used to improve the linearity of the output signal to meet the usage requirements of the backend voltage-controlled oscillator.

[0201] Specifically, in this embodiment, the recommended conversion rate of the digital-to-analog converter 7-1 is 50 MSPS to 200 MSPS, and the typical value is 100 MSPS, that is, the digital-to-analog conversion period Tdac = 10 ns; the digital-to-analog conversion accuracy Bdac is not less than 14 bits, and the typical value is 16 bits. The operational amplifier 7-2 is used to complete the conversion of the current signal output by the digital-to-analog converter into a voltage signal, and at the same time has functions of amplification and bias adjustment, and the recommended gain-bandwidth product is not less than 500 MHz. The passband frequency of the low-pass filter 7-3 is selected as 40% of the conversion rate of the digital-to-analog converter 7-1, and the typical value is 40 MHz.

[0202] Adjust the gain of the operational amplifier 7-2 to match the analog voltage-controlled signal i with the input level of the stepped delay line 8. Use the low-pass filter 7-3 to filter out the parasitic mirror spectrum output by the digital-to-analog converter 7-1 and improve the output quality of the analog voltage-controlled signal i. The stepped delay line 8 performs stepped delay adjustment on the analog voltage-controlled signal i according to the delay line selection signal h. The total number of steps is equal to the equivalent sampling ratio M, and the adjustment step size is equal to the reciprocal of the equivalent sampling rate. In this embodiment, the total number of steps of the stepped delay line 8 is 8, and the adjustment step size is 5 ns.

[0203] As a further preferred technical solution, as Figure 6 shown, the frequency modulation source 9 includes a voltage-controlled oscillator 9-1, a frequency multiplier 9-2, and a power amplifier 9-3. Among them, the voltage-controlled oscillator 9-1 is respectively connected to the stepped delay line 8 and the frequency multiplier 9-2. The frequency multiplier 9-2 is respectively connected to the RF front-end 2 and the power amplifier 9-3. The power amplifier 9-3 is connected to the transmitting antenna 10.

[0204] The voltage-controlled oscillator 9-1 is configured to receive the delayed voltage-controlled signal j from the stepped delay line 8, modulate the voltage-controlled oscillator using the delayed voltage-controlled signal j, generate a frequency modulation signal j1, and output the frequency modulation signal j1 to the frequency multiplier 9-2.

[0205] The frequency multiplier 9-2 is configured to perform frequency multiplication processing on the frequency modulation signal j1 to generate a frequency-multiplied local oscillator signal k, and output the frequency-multiplied local oscillator signal k to the RF front-end 2 and the power amplifier 9-3.

[0206] The power amplifier 9-3 is configured to perform power amplification on the frequency-multiplied local oscillator signal, generate a target transmission signal l, and send it to the transmitting antenna 10.

[0207] Specifically, the voltage-controlled oscillator 9-1 in this embodiment completes the conversion from the voltage modulation signal to the frequency modulation signal. The frequency multiplier 9-2 is used to multiply the frequency modulation signal j1 to the millimeter-wave frequency band required for the system operation to reduce the design pressure of the voltage-controlled oscillator 9-1. In this embodiment, the frequency multiplication factor is 4. The power amplifier 9-3 is used to perform power amplification on the frequency-multiplied local oscillator signal k to meet the power requirement of the transmitting antenna 10.

[0208] It should be noted that the frequency modulation source 9 in this embodiment has the function of integrally generating a high-frequency local oscillator and a transmission signal. The high-frequency local oscillator and the transmission signal share the same voltage-controlled oscillator, realizing the phase coherence between the two, thereby ensuring the speed detection accuracy of the echo signal. At the same time, by adopting the local oscillator frequency multiplier, the output frequency of the voltage-controlled oscillator is reduced, and thus its design difficulty is reduced.

[0209] It should be noted that other embodiments or specific implementation methods of the millimeter-wave radar transmitting device based on equivalent sampling according to the present invention can refer to the above-mentioned method embodiments, and will not be elaborated here.

[0210] Embodiment 4

[0211] As Figure 7 shown, the fourth embodiment of the present invention proposes a millimeter-wave radar receiving device based on equivalent sampling, including:

[0212] A radio frequency front-end 2, configured to perform mixing processing on the target echo signal output from the receiving antenna 1 based on the frequency-multiplied local oscillator signal to generate an analog intermediate-frequency signal, where the frequency-multiplied local oscillator signal is obtained by adjusting the relative delay of the local oscillator signal according to the delay voltage-controlled signal;

[0213] An analog-to-digital converter 3, configured to perform analog-to-digital conversion on the analog intermediate-frequency signal to generate a digital intermediate-frequency signal;

[0214] A frame processor 4, configured to generate read / write address signals based on the single-frame synchronization signal and the multi-frame synchronization signal, and perform read / write operations on the digital intermediate-frequency signal based on the read / write address signals to generate equivalent sampling data and output it to the signal processor 5, where the single-frame synchronization signal and the multi-frame synchronization signal are generated according to the system frequency modulation frame length, the analog-to-digital conversion rate, and the equivalent sampling ratio.

[0215] In this embodiment, since a low-speed analog-to-digital converter is used to achieve high-speed acquisition, the system cost based on equivalent sampling is lower than that of a conventional high-speed analog-to-digital conversion system. At the same time, as the conversion rate decreases, the system power consumption also decreases. By adopting the equivalent sampling scheme, if the equivalent sampling ratio is set to 8 or 16, the conversion rate of the analog-to-digital converter can be reduced to the order of ten megahertz. Through data reconstruction between multiple sampling frames, the equivalent sampling rate is above one hundred megahertz, and a relatively large detection distance can still be achieved.

[0216] As a further preferred technical solution, as Figure 8 shown, the radio frequency front-end 2 includes a low-noise amplifier 2-1, a local oscillator amplifier 2-2, a mixing amplifier 2-3, and an anti-aliasing filter 2-4; wherein, the low-noise amplifier 2-1 is respectively connected to the receiving antenna 1 and the mixing amplifier 2-2, the local oscillator amplifier 2-2 is respectively connected to the frequency modulation source 9 and the mixing amplifier 2-3, the mixing amplifier 2-3 is connected to the anti-aliasing filter 2-4, and the anti-aliasing filter 2-4 is connected to the analog-to-digital converter 3.

[0217] The low-noise amplifier 2-1 is configured to receive the target echo signal a from the receiving antenna 1 and perform low-noise amplification on the target echo signal a to obtain a low-noise amplified signal a1, and output the low-noise amplified signal a1 to the mixing amplifier 2-2;

[0218] The local oscillator amplifier 2-2 is configured to receive the frequency-multiplied local oscillator signal k from the frequency modulation source 9, perform power amplification on the frequency-multiplied local oscillator signal k to generate a local oscillator amplified signal k1, and output the local oscillator amplified signal k1 to the mixing amplifier 2-3;

[0219] The mixer amplifier 2-3 is used to mix the low-noise amplifier signal a1 and the local oscillator amplified signal k1 to generate a mixed signal a2 and output the mixed signal a2 to the anti-aliasing filter 2-4;

[0220] The anti-aliasing filter 2-4 is used to perform band-pass filtering on the mixed signal a2 to generate the analog intermediate frequency signal b and output the analog intermediate frequency signal b to the analog-to-digital converter 3.

[0221] Specifically, in this embodiment, the low-noise amplifier 2-1 performs low-noise amplification on the target echo signal a to obtain the low-noise amplifier signal a1. The frequency band of the low-noise amplifier signal a1 is the same as the swept frequency range, and the typical value is 76 GHz to 81 GHz; the local oscillator amplifier 2-2 amplifies the frequency-doubled local oscillator signal k to obtain the local oscillator amplified signal k1, and the typical power level is 0 to 10 dBm; the mixer amplifier 2-3 mixes and amplifies the low-noise amplifier signal a1 and the local oscillator amplified signal k1 to obtain the mixed signal a2; the anti-aliasing filter 2-4 performs low-pass filtering on the mixed signal a2. To prevent sampling data aliasing, the cut-off frequency of the filter is fH, and the analog intermediate frequency signal b is obtained after filtering.

[0222] It should be noted that in this embodiment, the radio frequency front end 2 uses a chirp local oscillator to mix the echo signal received by the low-noise amplifier, and a lower-frequency intermediate frequency signal can be obtained, reducing the requirement for the conversion rate of the analog-to-digital converter. The local oscillator amplifier is used to make up for the path loss of the high-frequency local oscillator signal, reducing the power requirement for the frequency-doubled local oscillator signal.

[0223] As a further preferred technical solution, as Figure 9 shown, the frame processor 4 includes: a write controller 4-1, a read controller 4-2, and a data buffer 4-3; the write controller 4-1 is respectively connected to the frequency modulation controller 6 and the data buffer 4-3, the read controller 4-2 is respectively connected to the frequency modulation controller 6 and the data buffer 4-3, and the data buffer 4-3 is connected to the analog-to-digital converter 3 and the signal processor 5.

[0224] The write controller 4-1 receives the single-frame synchronization signal e and the multi-frame synchronization signal f from the frequency modulation controller 6 and outputs a write address signal f1 to the data buffer 4-3; the read controller 4-2 receives the single-frame synchronization signal e and the multi-frame synchronization signal f from the frequency modulation controller 6 and outputs a read address signal f2 to the data buffer 4-3; the data buffer 4-3 receives the digital intermediate frequency signal c from the analog-to-digital converter 3 and outputs equivalent sampling data d to the signal processor 5.

[0225] In this embodiment, the single-frame synchronization signal serves as the start indication signal of a radar waveform frame, used to time the frame start moment of the baseband modulation signal and the frame data read / write input moment of the data buffer; the multi-frame synchronization signal serves as the start indication signal of an equivalent sampling frame, used to determine the switching moment of the delay filter and the selection of the corresponding delay value, and at the same time used to determine the multi-frame data read / write moment of the data buffer.

[0226] As a further preferred technical solution, in the present invention, the data buffer 4-3 is used to temporarily store the data of the analog-to-digital converter, and two consecutive address spaces, namely the first address space and the second address space, are opened up for ping-pong buffering, and the addresses are [0 to (M * AR - 1)] and [M * AR to (2 * M * AR - 1)] respectively; AR is equal to the rate of the analog-to-digital converter multiplied by the period Ts of the single-frame synchronization signal e, which is 25 MHz * 10 us = 250 in this embodiment.

[0227] When the odd-numbered multi-frame synchronization signal f arrives, the write address f1 after the first single-frame synchronization signal e arrives is [0 to (1 * AR - 1)], and the write address f1 after the Mth single-frame synchronization signal e arrives is [(M - 1) * AR to (M * AR - 1)]; when the even-numbered multi-frame synchronization signal f arrives, the write address f1 after the first single-frame synchronization signal e arrives is [M * AR to ((M + 1) * AR - 1)], and the write address f1 after the Mth single-frame synchronization signal e arrives is [(2M - 1) * AR to (2M * AR - 1)].

[0228] After the odd-numbered multi-frame synchronization signal f arrives, the read address f2 is:

[0229] [M * AR, (M + 1) * AR, (M + 2) * AR,..., (2M - 1) * AR, 1 + M * AR, 1 + (M + 1) * AR, 1 + (M + 2) * AR,…, 1 + (2M - 1) * AR, 2 + M * AR, 2 + (M + 1) * AR, 2 + (M + 2) * AR,…, 2 + (2M - 1) * AR,…, AR - 1 + M * AR, AR - 1 + (M + 1) * AR, AR - 1 + (M + 1) * AR,…, AR - 1 + (2M - 1) * AR];

[0230] After the even-numbered multi-frame synchronization signal f arrives, the read address f2 is:

[0231] [0, AR, 2 * AR,…, (M - 1) * AR, 1, 1 + AR, 1 + 2 * AR,…, 1 + (M - 1) * AR, 2, 2 + AR, 2 + 2 * AR,…, 2 + (M - 1) * AR,…, AR - 1, AR - 1 + AR, AR - 1 + 2 * AR,…, AR - 1 + (M - 1) * AR].

[0232] It should be noted that in this embodiment, the single-frame synchronization signal e and the multi-frame synchronization signal f are used to jointly control the initial read and write addresses of the data buffer, and complete the synchronous writing of the digital intermediate-frequency signal and the rearrangement of the read-out data. When the odd-numbered multi-frame synchronization signal f arrives, the write address after the arrival of the first single-frame synchronization signal e increases from zero, ensuring that the data is written into the first half of the storage area of the data buffer; when the even-numbered multi-frame synchronization signal f arrives, the write address after the arrival of the first single-frame synchronization signal e starts to increase from the initial address of the second half of the data buffer. After the odd-numbered multi-frame synchronization signal f arrives, the initial read address points to the initial address of the second half of the data buffer, and then increases at intervals of the equivalent sampling ratio; after the even-numbered multi-frame synchronization signal f arrives, the initial read address points to the initial address of the first half of the data buffer, and then increases at intervals of the equivalent sampling ratio.

[0233] This embodiment adopts the ping-pong buffer mechanism, effectively avoiding the timing competition problem of simultaneous read and write access to the same address area. The address of the write operation is continuous, while the read operation takes out one data from the data buffer 4-3 every AR numbers, thus realizing the time-domain rearrangement of the M-frame equivalent sampling data and ensuring that the equivalent sampling data d is real-time and continuous in time.

[0234] It should be noted that other embodiments or specific implementation methods of the millimeter-wave radar receiving device based on equivalent sampling according to the present invention can refer to the above method embodiments, and will not be elaborated here.

[0235] Embodiment Five

[0236] As Figure 10 shown, the fifth embodiment of the present invention proposes a millimeter-wave radar transceiver system based on equivalent sampling, including a transmitting device, a transmitting antenna, a receiving device, and a receiving antenna;

[0237] The transmitting device adopts the transmitting device proposed in the above third embodiment or is used to execute the millimeter-wave radar transmitting method based on equivalent sampling described in the above first embodiment to generate a target transmission signal to the transmitting antenna;

[0238] The receiving device adopts the receiving device proposed in the above fourth embodiment or is used to execute the millimeter-wave radar receiving method based on equivalent sampling described in the above second embodiment to process the target echo signal generated by the receiving antenna to generate equivalent sampling data.

[0239] Specifically, referring to the above-mentioned third and fourth embodiments, a millimeter-wave radar transceiver system based on equivalent sampling proposed in this embodiment includes a receiving antenna 1, a radio frequency front-end 2, an analog-to-digital converter 3, a frame processor 4, a signal processor 5, a frequency modulation controller 6, a voltage-controlled signal source 7, a stepped delay line 8, a frequency modulation source 9, and a transmitting antenna 10; the receiving antenna 1 is connected to the radio frequency front-end 2, and the receiving antenna 1 outputs a target echo signal a to the radio frequency front-end 2; the radio frequency front-end 2 is respectively connected to the analog-to-digital converter 3 and the frequency modulation source 9, the radio frequency front-end 2 outputs an analog intermediate frequency signal b to the analog-to-digital converter 3, and receives a frequency-doubled local oscillator signal k from the frequency modulation source 9; the analog-to-digital converter 3 is connected to the frame processor 4, and the analog-to-digital converter 3 outputs a digital intermediate frequency signal c to the frame processor 4; the frame processor 4 is connected to the signal processor 5 and the frequency modulation controller 6, the frame processor 4 outputs equivalent sampling data d to the signal processor 5, and receives a single-frame synchronization signal e and a multi-frame synchronization signal f from the frequency modulation controller 6; the frequency modulation controller 6 is connected to the voltage-controlled signal source 7 and the stepped delay line 8, the frequency modulation controller 6 outputs a baseband modulation signal g to the voltage-controlled signal source 7, and the frequency modulation controller 6 outputs a delay line selection signal h to the stepped delay line 8; the voltage-controlled signal source 7 is connected to the stepped delay line 8, and the voltage-controlled signal source 7 outputs an analog voltage-controlled signal i to the stepped delay line 8; the stepped delay line 8 is connected to the frequency modulation source 9, and the stepped delay line 8 outputs a delay voltage-controlled signal j to the frequency modulation source 9; the frequency modulation source 9 is connected to the transmitting antenna 10, and the frequency modulation source 9 outputs a transmission signal l to the transmitting antenna 10.

[0240] Compared with the traditional millimeter-wave radar transceiver system, in order to achieve a larger detection range, the conversion rate of the analog-to-digital converter often reaches more than hundreds of megahertz, with high cost and power consumption, and also has high requirements for the design of the hardware interface. In this embodiment, an equivalent scheme is adopted, and the conversion rate of the analog-to-digital converter can be reduced to the order of ten megahertz, while reducing power consumption and cost, and also reducing the transmission pressure of the data interface.

[0241] Furthermore, the millimeter-wave radar transceiver method based on equivalent sampling implemented by the above system in this embodiment includes the following steps:

[0242] Step 1: The synchronization frame generator 6-1 generates a single-frame synchronization signal e, a multi-frame synchronization signal f, and a long-frame selection signal e1 according to the system frequency modulation frame length, the analog-to-digital conversion rate, and the equivalent sampling ratio; the waveform counter 6-2 starts to generate a linear counting sequence e2 based on the single-frame synchronization signal e; the frame counter 6-3 starts to generate a frame cycle count e3 based on the single-frame synchronization signal e and the multi-frame synchronization signal f; the selector 6-4 sends the frame cycle count e3 as a fractional delay value e4 to the fractional delay filter 6-5 based on the long-frame selection signal e1, and sends the frame cycle count e3 as a delay line selection signal h to the stepped delay line 8; the fractional delay filter 6-5 performs fractional delay filtering on the linear counting sequence e2 based on the fractional delay value e4 to generate a baseband modulation signal g.

[0243] Step 2: The voltage-controlled signal source 7 performs digital-to-analog conversion, amplification, and low-pass filtering on the baseband modulation signal g to generate an analog voltage-controlled signal i.

[0244] Step 3: The step delay line 8 adjusts the delay of the analog voltage-controlled signal i according to the delay line selection signal h to generate a delayed voltage-controlled signal j.

[0245] Step 4: The frequency modulation source 9 uses the delayed voltage-controlled signal j to modulate the voltage-controlled oscillator 9-1 to generate a frequency modulation signal j1; then uses the frequency multiplier 9-2 to perform frequency multiplication on the frequency modulation signal j1 to generate a frequency-multiplied local oscillator signal k; performs power amplification on the frequency-multiplied local oscillator signal k to generate a transmission signal l for the transmitting antenna.

[0246] Step 5: The low-noise amplifier 2-1 performs low-noise amplification on the target echo signal a to generate a low-noise amplified signal a1; the local oscillator amplifier 2-2 performs power amplification on the frequency-multiplied local oscillator signal k to generate a locally amplified signal k1; the mixer amplifier 2-3 mixes the low-noise amplified signal a1 and the locally amplified signal k1 to generate a mixed signal a2; then uses the anti-aliasing filter 2-4 to perform band-pass filtering on the mixed signal a2 to generate an analog intermediate-frequency signal b.

[0247] Step 6: The analog-to-digital converter 3 performs analog-to-digital conversion on the analog intermediate-frequency signal b to generate a digital intermediate-frequency signal c.

[0248] Step 7: The write controller 4-1 generates a write address signal f1 for the data buffer 4-3 based on the single-frame synchronization signal e and the multi-frame synchronization signal f; the read controller 4-2 generates a read address signal f2 for the data buffer 4-3 based on the single-frame synchronization signal e and the multi-frame synchronization signal f; writes the digital intermediate-frequency signal c into the data buffer 4-3 based on the write address signal f1, and reads out the data in the data buffer 4-3 based on the read address signal f2 to generate an equivalent sampling data d.

[0249] In the traditional millimeter-wave radar technology system, to achieve a longer detection range, it usually relies on increasing the sampling rate of the analog-to-digital converter. This conventional path will inevitably lead to an increase in the complexity of circuit design and the interface transmission rate, and then cause the system power consumption and cost to increase accordingly. In this embodiment, a different approach is taken, aiming to build an innovative mechanism. With a carefully designed algorithm and a unique architecture, a low-rate analog-to-digital converter is made to simulate the effect of high-speed sampling. Compared with directly selecting a high-rate analog-to-digital converter, this innovative solution has significant advantages in cost control. The low-rate analog-to-digital converter itself has a lower cost, and because there is no need to match complex high-speed circuits, the overall hardware cost is further reduced. In terms of power consumption, low-rate operation means lower power consumption, effectively alleviating the system's heat dissipation pressure and improving the system's stability and reliability. Whether in the vehicle power supply scenario or in devices such as security monitoring relying on battery power, it greatly enhances the product's practicality and market competitiveness, and is expected to break the current dilemma among the sampling rate of the analog-to-digital converter, system cost, and power consumption, injecting new vitality into the development of millimeter-wave radar technology.

[0250] It should be noted that the logic and / or steps represented in the flowchart or described in other ways herein, for example, can be considered as a definite sequence list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other systems that can fetch instructions from the instruction execution system, apparatus, or device and execute the instructions), or in combination with these instruction execution systems, apparatus, or devices. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection part with one or more wirings (electronic device), a portable computer diskette (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can even be paper or other suitable media on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other media, then editing, interpreting, or otherwise processing it as appropriate, and then storing it in a computer memory.

[0251] It should be understood that various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, any one or a combination of the following technologies well known in the art can be used: discrete logic circuits with logic gate circuits for implementing logical functions on data signals, application specific integrated circuits with suitable combinational logic gate circuits, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.

[0252] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0253] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0254] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A millimeter wave radar transmission method based on equivalent sampling, characterized in that: include: Generate a single-frame synchronization signal, a multi-frame synchronization signal and a long frame selection signal according to the system frequency modulation period, the digital-to-analog conversion rate and the equivalent sampling ratio, wherein the period of the single-frame synchronization signal is equal to the period of the frequency modulation signal, and the period of the multi-frame synchronization signal is a multiple of the single-frame synchronization signal; Generate a baseband modulation signal and a delay line selection signal according to the single-frame synchronization signal and the multi-frame synchronization signal, wherein the sampling time is adjusted by a fractional delay filter when the long frame selection signal is low, and the sampling time is adjusted by a step delay line when the long frame selection signal is high; Generate an analog voltage control signal according to the baseband modulation signal, and use the delay line selection signal to adjust the delay of the analog voltage control signal to generate a delayed voltage control signal; The relative delay of each frame of the transmission signal and the local oscillator signal is adjusted according to the delayed voltage control signal to generate a target transmission signal and a frequency-multiplied local oscillator signal.

2. The millimeter wave radar transmitting method based on equivalent sampling as claimed in claim 1, characterized in that: The single-frame synchronization signal and the multi-frame synchronization signal are both periodic repetitive pulses, and the period of the multi-frame synchronization signal is equal to the period of the single-frame synchronization signal multiplied by the equivalent sampling ratio.

3. The millimeter wave radar transmitting method based on equivalent sampling as claimed in claim 1, characterized in that: The method of generating a baseband modulation signal and a delay line selection signal according to the single-frame synchronization signal and the multi-frame synchronization signal comprises: Count the rising edges of the single-frame synchronization signal to generate a linear counting sequence; Using the multi-frame synchronization signal as the initial clear signal, the pulses of the single-frame synchronization signal are counted to generate a frame cycle count; Perform fractional delay filtering on the linear count sequence based on the fractional delay value to generate a baseband modulation signal, wherein the fractional delay value is zero when the long frame selection signal is high, and the fractional delay value is the frame cycle count when the long frame selection signal is low; A delay line selection signal is generated based on the frame cycle count, wherein the delay line selection signal is equal to the frame cycle count when the long frame selection signal is high, and the delay line selection signal is equal to zero when the long frame selection signal is low.

4. The millimeter wave radar transmitting method based on equivalent sampling as claimed in claim 1, characterized in that: The method further comprises: In T s ≥T dac *2 Bdac When , the long frame selection signal is high; In T s <T dac *2 Bdac When , the long frame selection signal is low; Among them, T s is the system frequency modulation period, T dac is the digital-to-analog conversion period, B dac This is the digital-to-analog conversion accuracy.

5. The millimeter wave radar transmitting method based on equivalent sampling as claimed in claim 1, characterized in that: The number of steps of the step delay line is equal to the equivalent sampling ratio, and the step length is equal to the inverse of the equivalent sampling rate.

6. The millimeter wave radar transmitting method based on equivalent sampling as claimed in claim 1, characterized in that: The step of generating an analog voltage control signal according to a baseband modulation signal comprises: Performing digital-to-analog conversion on the baseband modulation signal to generate an analog voltage signal; Amplifying the analog voltage signal to generate an analog amplified signal; The analog amplified signal is low-pass filtered to generate an analog voltage-controlled signal.

7. The millimeter wave radar transmitting method based on equivalent sampling as claimed in claim 1, characterized in that: The relative delay of each frame transmission signal and the local oscillator signal is adjusted according to the delayed voltage control signal, including: modulating a voltage-controlled oscillator using a delayed voltage-controlled signal to generate a frequency-modulated signal; Perform frequency multiplication on the frequency modulated signal to generate a frequency multiplied local oscillator signal and send it to the RF front end; The frequency-multiplied local oscillator signal is power-amplified to generate a transmit signal and send it to the transmit antenna.

8. The millimeter wave radar transmitting method based on equivalent sampling as claimed in claim 1, characterized in that: The coefficients of the fractional delay filter are designed using the maximum flatness criterion approximation method.

9. A millimeter wave radar receiving method based on equivalent sampling, characterized in that: include: Performing mixing processing on the received target echo signal based on the frequency-doubled local oscillator signal to generate an analog intermediate frequency signal, wherein the frequency-doubled local oscillator signal is obtained by adjusting the relative delay of the local oscillator signal according to the delay voltage control signal; Perform analog-to-digital conversion on the analog intermediate frequency signal to generate a digital intermediate frequency signal; Generate a read / write address signal based on a single-frame synchronization signal and a multi-frame synchronization signal, wherein the single-frame synchronization signal and the multi-frame synchronization signal are generated according to a system frequency modulation frame length, a digital-to-analog conversion rate, and an equivalent sampling ratio; The digital intermediate frequency signal is read / written based on the read / write address signal to generate equivalent sampling data.

10. The millimeter wave radar receiving method based on equivalent sampling according to claim 9, characterized in that: The mixing process of the received target echo signal based on the frequency-multiplied local oscillator signal to generate an analog intermediate frequency signal includes: Performing low-noise amplification on the target echo signal to generate a low-noise amplified signal; Amplifying the power of the frequency-doubled local oscillator signal to generate a local oscillator amplified signal; Mixing the low noise amplifier signal and the local oscillator amplifier signal to generate a mixed signal; The mixed signal is band-pass filtered to generate the analog intermediate frequency signal.

11. The millimeter wave radar receiving method based on equivalent sampling according to claim 9, characterized in that: The method of generating a read / write address signal based on a single-frame synchronization signal and a multi-frame synchronization signal comprises: When the odd-numbered multi-frame synchronization signal arrives, the write address after the first single-frame synchronization signal arrives and the write address after the M-th single-frame synchronization signal arrives are corresponding addresses in the first address space; When an even-numbered multi-frame synchronization signal arrives, the write address after the first single-frame synchronization signal arrives and the write address after the Mth single-frame synchronization signal arrives are corresponding addresses in the second address space; After the odd-numbered multi-frame synchronization signal arrives, the read address is to take out one data from the first address space every AR number; After the even-numbered multi-frame synchronization signal arrives, the read address is to take out one data from the second address space every AR number; The addresses of the first address space and the second address space are [0 to (M*AR-1)] and [M*AR to (2*M*AR-1)] respectively, and AR is equal to the analog-to-digital conversion rate multiplied by the period of the single-frame synchronization signal.

12. The millimeter wave radar receiving method based on equivalent sampling according to claim 11, characterized in that: The method further comprises: When the odd-numbered multi-frame synchronization signal arrives, the write address after the first single-frame synchronization signal arrives is [0 to (1*AR-1)], and the write address after the Mth single-frame synchronization signal arrives is [(M-1)*AR to (M*AR-1)]; When the even-numbered multi-frame synchronization signal arrives, the write address after the first single-frame synchronization signal arrives is [M*AR~((M+1)*AR-1)], and the write address after the Mth single-frame synchronization signal arrives is [(2M-1)*AR~(2M*AR-1)].

13. The millimeter wave radar receiving method based on equivalent sampling according to claim 11, characterized in that: The reading / writing operation of the digital intermediate frequency signal based on the read / write address signal to generate equivalent sampling data includes: Writing the digital intermediate frequency signal into the first address space through the second address space based on the write address signal; Data in the first address space or the second address space is read out based on the read address signal to generate equivalent sample data.

14. A millimeter wave radar transmitting device based on equivalent sampling, characterized in that: include: A frequency modulation controller, used for generating a single-frame synchronization signal, a multi-frame synchronization signal and a long-frame selection signal according to a system frequency modulation period, a digital-to-analog conversion rate and an equivalent sampling ratio, and generating a baseband modulation signal and a delay line selection signal according to the single-frame synchronization signal and the multi-frame synchronization signal, wherein the period of the single-frame synchronization signal is equal to the period of the frequency modulation signal, the period of the multi-frame synchronization signal is a multiple of the single-frame synchronization signal, the sampling time is adjusted by a fractional delay filter when the long-frame selection signal is low, and the sampling time is adjusted by a step delay line when the long-frame selection signal is high; A voltage-controlled signal source, used for generating an analog voltage-controlled signal according to a baseband modulation signal; A stepping delay line, used to adjust the delay of the analog voltage-controlled signal using a delay line selection signal to generate a delayed voltage-controlled signal; The frequency modulation source is used to adjust the relative delay of each frame of the transmission signal and the local oscillator signal according to the delayed voltage control signal to generate the target transmission signal and the multiplied local oscillator signal.

15. The millimeter wave radar transmitting device based on equivalent sampling as claimed in claim 14, characterized in that: The single-frame synchronization signal and the multi-frame synchronization signal are both periodic repetitive pulses, and the period of the multi-frame synchronization signal is equal to the period of the single-frame synchronization signal multiplied by the equivalent sampling ratio.

16. The millimeter wave radar transmitting device based on equivalent sampling as claimed in claim 14, characterized in that: The frequency modulation controller comprises: A synchronization frame generator, used to generate a single-frame synchronization signal, a multi-frame synchronization signal and a long frame selection signal according to a system frequency modulation period, a digital-to-analog conversion rate and an equivalent sampling ratio; A waveform counter, used for counting the rising edges of a single-frame synchronization signal to generate a linear counting sequence; A frame counter, used to count the pulses of a single frame synchronization signal using a multi-frame synchronization signal as an initial clear signal, and generate a frame cycle count; A fractional delay filter, used for performing fractional delay filtering on a linear count sequence based on a fractional delay value to generate a baseband modulated signal, wherein the fractional delay value is zero when the long frame selection signal is high, and the fractional delay value is the frame cycle count when the long frame selection signal is low; A data switch is used to generate a delay line selection signal based on a frame cycle count, wherein the delay line selection signal is equal to the frame cycle count when the long frame selection signal is high, and is equal to zero when the long frame selection signal is low.

17. The millimeter wave radar transmitting device based on equivalent sampling as claimed in claim 14, characterized in that: In T s ≥T dac *2 Bdac When T s <T dac *2 Bdac When , the long frame selection signal is low; Among them, T s is the system frequency modulation period, T dac is the digital-to-analog conversion period, B dac This is the digital-to-analog conversion accuracy.

18. The millimeter wave radar transmitting device based on equivalent sampling as claimed in claim 14, characterized in that: The voltage-controlled signal source comprises: A digital-to-analog converter, used for performing digital-to-analog conversion on the baseband modulation signal to generate an analog voltage signal; An operational amplifier, used for amplifying the analog voltage signal to generate an analog amplified signal; The low-pass filter is used to perform low-pass filtering on the analog amplified signal to generate an analog voltage-controlled signal.

19. The millimeter wave radar transmitting device based on equivalent sampling as claimed in claim 14, characterized in that: The frequency modulation source comprises: A voltage controlled oscillator, used to modulate the voltage controlled oscillator using a delayed voltage control signal to generate a frequency modulated signal; The frequency multiplier is used to perform frequency multiplication on the frequency modulated signal, generate a frequency multiplied local oscillator signal and send it to the RF front end; The power amplifier is used to amplify the power of the frequency-multiplied local oscillator signal, generate a transmit signal and send it to the transmit antenna.

20. A millimeter wave radar receiving device based on equivalent sampling, characterized in that: include: The RF front end is used to perform mixing processing on the received target echo signal based on the frequency-doubled local oscillator signal to generate an analog intermediate frequency signal, wherein the frequency-doubled local oscillator signal is obtained by adjusting the relative delay of the local oscillator signal according to the delay voltage control signal; An analog-to-digital converter, used for performing analog-to-digital conversion on an analog intermediate frequency signal to generate a digital intermediate frequency signal; A frame processor is used to generate a read / write address signal based on a single-frame synchronization signal and a multi-frame synchronization signal, and perform read / write operations on a digital intermediate frequency signal based on the read / write address signal to generate equivalent sampling data and output it to a signal processor, wherein the single-frame synchronization signal and the multi-frame synchronization signal are generated according to the system frequency modulation frame length, the digital-to-analog conversion rate, and the equivalent sampling ratio.

21. The millimeter wave radar receiving device based on equivalent sampling as claimed in claim 20, characterized in that: The radio frequency front end comprises: A low noise amplifier, used for performing low noise amplification on the target echo signal to generate a low noise amplifier signal; A local oscillator amplifier, used to amplify the power of the frequency-doubled local oscillator signal to generate a local oscillator amplified signal; A mixer amplifier, used for mixing the low noise amplifier signal and the local oscillator amplified signal to generate a mixed signal; The anti-aliasing filter is used to perform band-pass filtering on the mixed signal to generate the analog intermediate frequency signal.

22. The millimeter wave radar receiving device based on equivalent sampling as claimed in claim 20, characterized in that: The frame processor comprises: A write controller, used for generating a write address signal based on a single-frame synchronization signal and a multi-frame synchronization signal and outputting the write address signal to a data buffer; A read controller, used for generating a read address signal based on a single-frame synchronization signal and a multi-frame synchronization signal and outputting the signal to a data buffer; The data buffer is used to perform a write or read operation on the digital intermediate frequency signal output by the analog-to-digital converter based on a write address signal and a read address signal to generate equivalent sampling data.

23. The millimeter wave radar receiving device based on equivalent sampling as claimed in claim 22, characterized in that: The data buffer is provided with a first address space and a second address space, the addresses of which are [0 to (M*AR-1)] and [M*AR to (2*M*AR-1)] respectively, where AR is equal to the analog-to-digital conversion rate multiplied by the period of the single-frame synchronization signal; The write controller is used for, when an odd-numbered multi-frame synchronization signal arrives, the write address after the first single-frame synchronization signal arrives and the write address after the M-th single-frame synchronization signal arrives are corresponding addresses in the first address space; When an even-numbered multi-frame synchronization signal arrives, the write address after the first single-frame synchronization signal arrives and the write address after the Mth single-frame synchronization signal arrives are corresponding addresses in the second address space; The read controller is used to fetch one data from the first address space every AR number of read addresses after the arrival of the odd-numbered multi-frame synchronization signal; and to fetch one data from the second address space every AR number of read addresses after the arrival of the even-numbered multi-frame synchronization signal.

24. The millimeter wave radar receiving device based on equivalent sampling as claimed in claim 23, characterized in that: When the odd-numbered multi-frame synchronization signal arrives, the write address after the first single-frame synchronization signal arrives is [0 to (1*AR-1)], and the write address after the Mth single-frame synchronization signal arrives is [(M-1)*AR to (M*AR-1)]; When the even-numbered multi-frame synchronization signal arrives, the write address after the first single-frame synchronization signal arrives is [M*AR~((M+1)*AR-1)], and the write address after the Mth single-frame synchronization signal arrives is [(2M-1)*AR~(2M*AR-1)].

25. A millimeter wave radar transceiver system based on equivalent sampling, characterized in that: It includes a transmitting device, a transmitting antenna, a receiving device and a receiving antenna; The transmitting device is used to execute the millimeter wave radar transmitting method based on equivalent sampling as described in any one of claims 1 to 8 to generate a target transmitting signal to a transmitting antenna; The receiving device is used to execute the millimeter wave radar receiving method based on equivalent sampling as described in any one of claims 9 to 13 to process the target echo signal generated by the receiving antenna to generate equivalent sampling data.

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