Digital signal processing chip

Abstract

The invention provides a digital signal processing chip which can be applied to the technical field of information processing. The signal processing chip comprises an orthogonal mixer used for converting an input signal into a baseband signal; the finite impulse response filter is used for filtering noise; the parameter generator is used for generating extraction algorithm parameters according to the input previous frame target information; the point extractor is used for compressing signal points in a time domain according to the parameters generated by the parameter generator; and the on-chip memory is used for storing the operation process data and the parameter data. The processor can extract needed fragments from input signals through existing target information, a one-dimensional digital signal processing flow is completed, and compared with a traditional digital signal processor, the processor has the advantages that invalid calculation is avoided, the parallel efficiency is high, and the configurability is high.

Description

Technical Field

[0001] The present invention relates to the field of information processing technology, and in particular to a digital signal processing chip. Background Art

[0002] As the cornerstone of information technology, one-dimensional digital signal processing is widely used in many industries such as communications, audio processing, image processing, and biomedicine. Its core lies in various transformations, filtering, detection, and analysis of discrete-time signals to achieve information extraction, enhancement, and compression. In this process, digital signal processors (DSPs) play a vital role. With their powerful computing power and flexible programmability, they have become the preferred tool for processing complex signal algorithms. However, with the advent of the big data era and the increasing diversification of signal processing needs, the limitations of traditional DSPs have gradually become apparent.

[0003] Traditional DSP designs often focus on versatility and the ability to handle a wide range of signal processing tasks. Although this design approach ensures the wide applicability of the processor, it also brings significant hardware complexity and power consumption issues. More importantly, since signal processing subtasks are mostly executed serially within and between subtasks, processing efficiency is severely restricted. In application scenarios with extremely high real-time requirements, such as high-speed communications and real-time audio monitoring, this serial processing mode often cannot meet the requirements of low latency.

[0004] In addition, traditional DSPs lack the ability to adjust adaptively based on target information, which is the so-called "intelligent" or "adaptive" processing. In practical applications, signal characteristics may change over time, environment, or task requirements. Fixed processing procedures often cannot optimally cope with these changes, resulting in limited processing effects and even the introduction of unnecessary errors. This static processing strategy not only limits the flexibility of the system, but also increases the difficulty and cost of tuning for different tasks.

[0005] In order to solve the above problems, academia and industry have begun to actively explore highly parallel, pipelined, dedicated one-dimensional digital signal processors. This type of new processor uses a highly parallelized architecture design to achieve parallel execution of multiple signal processing subtasks, greatly improving the processing speed. Pipeline technology further refines the processing flow, breaking down complex tasks into a series of simple steps, each of which is executed in parallel in an independent processing unit, thereby reducing the waiting time between tasks and improving overall processing efficiency.

[0006] More importantly, the new processor incorporates an adaptive processing mechanism that can dynamically adjust the processing strategy based on the characteristics of the input signal and the processing objectives, thereby optimizing the processing effect and improving the robustness and adaptability of the system. Summary of the invention

[0007] 1. Technical issues to be resolved

[0008] In order to solve the above problems existing in the conventional one-dimensional digital signal processor in the prior art, an embodiment of the present invention provides a digital signal processing chip, which integrates an orthogonal mixer, a finite impulse response filter and a point decimator. By parallelizing the internal processing of signal processing subtasks and streamlining the processing between subtasks to reduce the calculation delay, the flexibility is improved through configurable submodule calculation parameters and decimation rates, and more digital signal processing application scenarios are supported.

[0009] (II) Technical solution

[0010] In view of the above problems, an embodiment of the present invention provides a digital signal processing chip.

[0011] According to a first aspect of the present invention, there is provided a digital signal processing chip, characterized in that it comprises: an orthogonal mixer for mixing an input intermediate frequency signal through two orthogonal intermediate frequency reference signals to convert it into a baseband signal; a finite impulse response filter for filtering out the frequency-doubled signal and noise after mixing through low-pass filtering; a parameter generator for generating extraction algorithm parameters according to a configurable strategy based on input previous frame target information; a point number extractor for compressing the signal points in the time domain at a specified extraction rate according to the extraction algorithm parameters generated by the parameter generator to obtain a compressed echo signal; and an on-chip memory for storing operation process data and parameter data of the orthogonal mixer and the finite impulse response filter.

[0012] In some exemplary embodiments, the on-chip memory includes input signal storage, orthogonal mixer parameter storage, finite impulse response filter parameter storage, filtering result storage and parameter storage, wherein the input signal storage is used to cache the input signal and read it into the orthogonal mixer for processing; the orthogonal mixer parameter storage is used to store the parameters of the orthogonal mixer and can be reloaded during operation; the finite impulse response filter parameter storage is used to store the parameters of the finite impulse response filter and can be reloaded during operation; the filtering result storage is used to cache the results of the finite impulse response filtering and read it into the point extractor for processing; and the parameter storage is used to store the parameters of the parameter generator and can be reloaded during operation.

[0013] In some exemplary embodiments, the orthogonal mixer includes an I mixer and a Q mixer, wherein the I mixer is used to mix the intermediate frequency signal with a reference cosine signal; and the Q mixer is used to mix the intermediate frequency signal with a reference sine signal.

[0014] In some exemplary embodiments, the I mixer includes M multipliers; and the Q mixer includes M multipliers, where M is a positive integer.

[0015] In some exemplary embodiments, the finite impulse response filter includes a data storage to be filtered, which is used to store the data to be filtered formed by combining the first P data input this time and the last NP data input last time, and the P value of each group of storage units is different; a multiplier, which is used to multiply the data in the data storage to be filtered with the parameters in the finite impulse response filter parameter storage; a cache register, which is used to cache the results of the multiplier and the adder between pipeline stages; and an adder, which is used to accumulate the filtered sequence signal to obtain a filtering result, wherein N and P are positive integers.

[0016] In some exemplary embodiments, the parameter generator includes a target data mapping unit, an extraction center point calculation unit, an extraction rate adjustment unit, a head and tail coordinate calculation unit, and a bias calculation unit, wherein the target data mapping unit is used to convert the input target information into a data format that can be used for coordinate calculation; the center point calculation unit is used to obtain new extraction center point coordinates according to set parameters, the input old extraction center point coordinates and the mapped target information; the extraction rate adjustment unit is used to obtain a new extraction rate according to the old extraction rate and the extraction rate adjustment strategy specified in the set parameters; the head and tail coordinate calculation unit is used to calculate new extraction first coordinates and new extraction tail coordinates according to the new extraction rate and the extraction center point coordinates; and the bias calculation unit is used to calculate the address offset output by the point extractor according to the new extraction first coordinates.

[0017] In some exemplary embodiments, the point extractor includes a head and tail determination unit, an extraction point calculation unit, and W extraction execution units, wherein the head and tail determination unit is used to determine whether the points currently being processed are within the valid extraction interval, and if not, the extraction process is skipped to reduce resource usage; the extraction point calculation unit is used to calculate the coordinates of the valid extraction points in the points currently being processed; and the extraction execution unit is used to use the valid points calculated by the extraction point calculation unit as valid signals, and output them in sequence to the specified address outside the chip according to the address offset generated by the parameter generator, wherein W is a positive integer.

[0018] In some exemplary embodiments, operating parameters and operating modes are configurable.

[0019] In some exemplary embodiments, the data range to be processed can be adaptively selected according to input target information to avoid invalid calculations.

[0020] In some exemplary embodiments, the decimation rate can be adjusted dynamically at runtime.

[0021] (III) Beneficial effects

[0022] It can be seen from the above technical solutions that a digital signal processing chip provided by an embodiment of the present invention has at least one of the following beneficial effects:

[0023] (1) It can adaptively select the data range to be processed based on the input target information to avoid invalid calculations.

[0024] (2) Use parallel and pipelined sub-module data flows to improve data processing capabilities while reducing processor power consumption.

[0025] (3) The extraction rate can be adjusted dynamically at runtime to support extraction ranges of different lengths and expand the applicable scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above contents and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0027] Figure 1 A schematic diagram of the structure of a digital signal processing chip according to an embodiment of the present invention is shown;

[0028] Figure 2 The internal structure and data flow diagram of the finite impulse response filter according to the embodiment of the present invention are schematically shown;

[0029] Figure 3 A schematic diagram schematically showing the internal structure and data flow of a point extractor according to an embodiment of the present invention; and

[0030] Figure 4 The diagram schematically shows the internal structure and data flow of a parameter generator according to an embodiment of the present invention. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical scheme and advantages of the present invention more clearly understood, the present invention is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] Figure 1 The structure diagram of a digital signal processing chip according to an embodiment of the present invention is schematically shown.

[0033] like Figure 1As shown, a digital signal processing chip according to an embodiment of the present invention includes: an orthogonal mixer 10, used to mix an input intermediate frequency signal through two orthogonal intermediate frequency reference signals to convert it into a baseband signal; a finite impulse response filter 20, used to filter out the mixed frequency multiplier signal and noise through low-pass filtering; a parameter generator 40, used to generate extraction algorithm parameters according to a configurable strategy based on the input previous frame target information; a point number extractor 30, used to compress the signal points in the time domain at a specified extraction rate according to the extraction algorithm parameters generated by the parameter generator 40 to obtain a compressed echo signal; and an on-chip memory 50, used to store operation process data and parameter data of the orthogonal mixer 10 and the finite impulse response filter 20.

[0034] In the embodiment of the present invention, the digital signal processing chip is a configurable device, wherein the on-chip memory 50 includes: an input signal storage 510, an orthogonal mixer parameter storage 520, a finite impulse response filter parameter storage 530, a filtering result storage 540 and a parameter storage 550, wherein the input signal storage 510 is used to cache the input signal and read it into the orthogonal mixer 10 for processing; the orthogonal mixer parameter storage 520 is used to store the parameters of the orthogonal mixer 10 and can be reloaded during operation; the finite impulse response filter parameter storage 530 is used to store the parameters of the finite impulse response filter 20 and can be reloaded during operation; the filtering result storage 540 is used to cache the result of the finite impulse response filtering and read it into the point extractor 30 for processing; and the parameter storage 550 is used to store the parameters of the parameter generator 40 and can be reloaded during operation.

[0035] This highly configurable digital signal processing chip design not only improves the accuracy and efficiency of signal processing, but also significantly enhances the flexibility and maintainability of the system. By dynamically reloading parameters, the system can quickly adapt to different signal processing requirements, reducing the cost and complexity of hardware reconfiguration. At the same time, the modular memory design makes the signal processing process clearer and easier to manage.

[0036] In some exemplary embodiments, the orthogonal mixer 10 includes an I-channel mixer and a Q-channel mixer, wherein the I-channel mixer is used to mix the intermediate frequency signal with the reference cosine signal; and the Q-channel mixer is used to mix the intermediate frequency signal with the reference sine signal. The I-channel mixer includes M multipliers, each of which processes the sampling values ​​of different parts or different time periods of the intermediate frequency signal in parallel to improve the processing efficiency and accuracy; and the Q-channel mixer includes M multipliers, wherein M is a positive integer. Its working principle is based on signal mixing and baseband signal extraction. Among them, the I-channel mixer is specifically used to mix the intermediate frequency signal with the reference cosine signal, and the amplitude information of the intermediate frequency signal is combined with the phase information of the reference cosine signal through multiplication operation to generate an I-channel output signal; while the Q-channel mixer is responsible for mixing the intermediate frequency signal with the reference sine signal, and using the phase characteristics of the sine signal (90 degrees relative to the phase offset of the cosine signal) to generate a Q-channel output signal. These two signals together constitute the orthogonal component, providing the necessary phase and amplitude information for subsequent signal processing.

[0037] The design of the orthogonal mixer 10 not only improves the accuracy and efficiency of signal processing, but also enhances the anti-interference ability and stability of the system. Through the parallel processing of the I-way and Q-way mixers, the system can more accurately extract the phase and amplitude information of the intermediate frequency signal. In addition, the use of multiple multipliers 220 working in parallel also helps to improve the processing speed and throughput of the entire system, meeting the application requirements in high-speed signal processing scenarios.

[0038] Figure 2 The internal structure and data flow diagram of the finite impulse response filter 20 according to the embodiment of the present invention are schematically shown.

[0039] like Figure 2 As shown, the finite impulse response filter 20 according to the embodiment of the present invention includes: a data storage 210 to be filtered, which is used to store the data to be filtered formed by combining the first P data input this time and the last NP data input last time, and the P value of each group of storage units is different; a multiplier 220, which is used to multiply the data in the data storage 210 to be filtered with the parameters in the finite impulse response filter parameter storage 530; a cache register 230, which is used to cache the results of the multiplier 220 and the adder 240 between pipeline stages; and an adder 240, which is used to accumulate the filtered sequence signal to obtain a filtering result, wherein N and P are positive integers.

[0040] The finite impulse response filter 20 of the embodiment of the present invention not only improves the processing speed and accuracy of the filter through flexible sliding window design and efficient linear convolution operation, but also enhances its ability to adapt to different filtering requirements and data flow characteristics. At the same time, the introduction of the cache register 230 further improves the continuity and efficiency of data processing, so that the filter performs well in real-time signal processing applications.

[0041] Figure 3 The diagram schematically shows the internal structure and data flow of the point extractor 30 according to an embodiment of the present invention.

[0042] like Figure 3 As shown, the point extractor 30 according to the embodiment of the present invention includes a head and tail distinguishing unit 310, an extraction point calculating unit 320, and W extraction execution units 330, wherein the head and tail distinguishing unit 310 is used to determine whether the points currently being processed are within the valid extraction interval, and if not, the extraction process is skipped to reduce resource occupation; the extraction point calculating unit 320 is used to calculate the valid extraction point coordinates existing in the points currently being processed; and the extraction execution unit 330 is used to use the valid points calculated by the extraction point calculating unit 320 as valid signals, and output them to the specified address outside the chip in sequence according to the address offset generated by the parameter generator 40. The data range to be processed can be adaptively selected through the input target information to avoid invalid calculations. The extraction rate can be dynamically adjusted at runtime.

[0043] The point extractor 30 of the embodiment of the present invention has a working principle based on efficient data screening and accurate address mapping. Specifically, the extractor first pre-processes the input data stream through the head and tail distinguishing unit 310 to determine whether the points currently processed are within the preset extraction effective interval. This step effectively excludes the points that are not within the effective interval through intelligent screening, thereby avoiding unnecessary computing overhead, reducing the occupation of system resources, and improving overall processing efficiency. It can dynamically adjust the extraction rate at runtime, so that the system can be flexibly configured according to different application scenarios or requirements, further enhancing the flexibility and adaptability of the system. In addition, by avoiding invalid calculations, the extractor also achieves effective resource conservation and reduces the overall power consumption and cost of the system.

[0044] Figure 4 The diagram schematically shows the internal structure and data flow of the parameter generator 40 according to an embodiment of the present invention.

[0045] like Figure 4As shown, the parameter generator 40 according to the embodiment of the present invention includes: a target data mapping unit 410, an extraction center point calculation unit 420, an extraction rate adjustment unit 430, a head and tail coordinate calculation unit 440 and a bias calculation unit 450, wherein the target data mapping unit 410 is used to convert the input target information into a data format that can be used for coordinate calculation; the center point calculation unit is used to obtain new extraction center point coordinates according to set parameters, input old extraction center point coordinates and mapped target information; the extraction rate adjustment unit 430 is used to obtain a new extraction rate according to the old extraction rate and the extraction rate adjustment strategy specified in the set parameters; the head and tail coordinate calculation unit 440 is used to calculate new extraction first coordinates and new extraction tail coordinates according to the new extraction rate and the extraction center point coordinates; and the bias calculation unit 450 is used to calculate the address offset output by the point number extractor 30 according to the new extraction first coordinates.

[0046] The embodiments of the present invention are described above. However, these embodiments are only for the purpose of illustration, and are not intended to limit the scope of the present invention. Although each embodiment is described above, it does not mean that the measures in each embodiment cannot be used in combination advantageously. Without departing from the scope of the present invention, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A digital signal processing chip, characterized in that: include: The orthogonal mixer is used to mix the input intermediate frequency signal through two orthogonal intermediate frequency reference signals to convert it into a baseband signal; Finite impulse response filter, used to filter out the frequency-doubled signal and noise after mixing through low-pass filtering; A parameter generator, used to generate extraction algorithm parameters according to the input previous frame target information and a configurable strategy; A point decimator is used to compress the signal points at a specified decimation rate in the time domain according to the decimation algorithm parameters generated by the parameter generator to obtain a compressed echo signal; as well as On-chip memory is used to store operation process data and parameter data of orthogonal mixer and finite impulse response filter.

2. The digital signal processing chip according to claim 1, characterized in that: The on-chip memory includes input signal storage, orthogonal mixer parameter storage, finite impulse response filter parameter storage, filtering result storage and parameter storage. Wherein, the input signal storage is used to cache the input signal and read it into the orthogonal mixer for processing; The quadrature mixer parameter storage is used to store the parameters of the quadrature mixer and can be reloaded during operation; FIR filter parameter storage, used to store FIR filter parameters and can be reloaded during operation; The filtering result storage is used to cache the result of the finite impulse response filtering and read it into the point extractor for processing; and The parameter storage is used to store the parameters of the parameter generator and can be reloaded during operation.

3. The digital signal processing chip according to claim 2, characterized in that: The orthogonal mixer includes an I mixer and a Q mixer. Wherein, the I-channel mixer is used to mix the intermediate frequency signal and the reference cosine signal; The Q-channel mixer is used to mix the intermediate frequency signal with the reference sinusoidal signal.

4. The digital signal processing chip according to claim 3, characterized in that: The I-channel mixer includes M multipliers; and The Q-channel mixer includes M multipliers. Wherein, M is a positive integer.

5. The digital signal processing chip according to claim 2, characterized in that: The finite impulse response filter comprises, The data storage to be filtered is used to store the data to be filtered formed by combining the first P data input this time and the last NP data input last time, and the P value of each group of storage units is different; A multiplier, used for multiplying the data in the to-be-filtered data storage with the parameters in the finite impulse response filter parameter storage; Cache registers, used to cache the results of multipliers and adders between pipeline stages; The adder is used to accumulate the filtered sequence signal to obtain the filtering result. Wherein, N and P are positive integers.

6. The digital signal processing chip according to claim 1, characterized in that: The parameter generator includes a target data mapping unit, an extraction center point calculation unit, an extraction rate adjustment unit, a head and tail coordinate calculation unit and a bias calculation unit. Wherein, the target data mapping unit is used to convert the input target information into a data format that can be used for coordinate calculation; The center point calculation unit is used to obtain new extraction center point coordinates according to the set parameters, the input old extraction center point coordinates and the mapped target information; The decimation rate adjustment unit is used to obtain a new decimation rate according to the old decimation rate and the decimation rate adjustment strategy specified in the setting parameters; The head and tail coordinate calculation unit is used to calculate the new extraction head coordinate and the new extraction tail coordinate according to the new extraction rate and the extraction center point coordinate; and The offset calculation unit is used to calculate the address offset output by the point extractor according to the new extraction first coordinate.

7. The digital signal processing chip according to claim 1, characterized in that: The point number extractor includes a head and tail discrimination unit, an extraction point calculation unit, and W extraction execution units. The head and tail distinguishing unit is used to determine whether the points currently being processed are within the valid extraction interval. If not, the extraction process is skipped to reduce resource usage. The extraction point calculation unit is used to calculate the coordinates of valid extraction points existing in the points currently being processed; and The extraction execution unit is used to use the effective points calculated by the extraction point calculation unit as effective signals, and output them to the designated addresses outside the chip in sequence according to the address offset generated by the parameter generator. Wherein, W is a positive integer.

8. The digital signal processing chip according to claim 1, characterized in that: Operation parameters and operation modes can be configured.

9. The digital signal processing chip according to claim 1, characterized in that: It can adaptively select the data range to be processed based on the input target information to avoid invalid calculations.

10. The digital signal processing chip according to claim 1, characterized in that: The decimation rate can be adjusted dynamically at runtime.

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