High-voltage-resistant bootstrap switch

Abstract

Apparatuses and methods for a high voltage resistant bootstrap switch are disclosed. In some embodiments, an integrated circuit (IC) includes an input node that receives an input voltage, an output node, and a switch connected between the input node and the output node. The switch includes a first field effect transistor (FET) and a second FET electrically connected in series between an input node and an output node. The switch is configurable between an off state in which a gate of the first FET is controlled with a first voltage and a gate of the second FET is controlled with a second voltage and an on state; the gates of the first and second FETs are controlled with a voltage that tracks the input voltage in the on-state.

Description

Technical Field

[0001] Embodiments of the present invention relate to electronic systems, and more particularly to switches. Background Art

[0002] Switches, such as field effect transistor (FET) switches, can be used to provide or restrict electrical paths between nodes of an electronic system. For example, a single FET can be used to generate a low impedance or a high impedance between the source and drain of the FET in response to a control signal applied at the gate. However, the control signal applied to the FET may cause the FET to leak current under certain signal conditions. In addition, certain operating scenarios may result in high voltage levels that may damage the FET, such as causing junction damage and / or gate oxide damage. Summary of the invention

[0003] Apparatus and methods for high voltage resistant bootstrap switches are disclosed. In certain embodiments, an integrated circuit (IC) includes an input node receiving an input voltage, an output node, and a switch connected between the input node and the output node. The switch includes a first field effect transistor (FET) and a second FET electrically connected in series between the input node and the output node. The switch can be configured between an off state and an on state, in which the gate of the first FET is controlled by a first voltage and the gate of the second FET is controlled by a second voltage; in which the gates of the first FET and the second FET are controlled by a voltage that tracks the input voltage. By implementing the switch in this manner, the switch can achieve high voltage tolerance in the off state and high linearity in the on state. For example, in the off state, the switch can withstand large voltage fluctuations at the input node without the FET of the switch suffering from junction damage and / or gate oxide damage.

[0004] In one aspect, an IC includes a first node configured to receive an input voltage; a second node including a switch of a first FET and a second FET electrically connected in series between the first node and the second node; and a switch control circuit configured to set the switch to an off state based on controlling a gate of the first FET with a first voltage and a gate of the second FET with a second voltage, and to set the switch to an on state based on controlling the gate of the first FET and the gate of the second FET to track the input voltage.

[0005] In another aspect, a method of switching in an IC includes receiving an input voltage at a first node. The method also includes opening a switch using a switch control circuit, the switch including a first FET and a second FET electrically connected in series between the first node and the second node, wherein opening the switch includes setting the switch to an off state based on controlling a gate of the first FET with a first voltage and controlling a gate of the second FET with a second voltage. The method also includes turning on the switch using the switch control circuit, wherein turning on the switch includes setting the switch to an on state based on controlling a gate of the first FET and a gate of the second FET to track the input voltage.

[0006] On the other hand, a data conversion system includes an input node configured to receive an input voltage, an analog-to-digital converter (ADC) having an input, a switch including a first FET and a second FET electrically connected in series between the input node and the input of the ADC, and a switch control circuit, the switch control circuit being configured to set the switch to an off state based on controlling a gate of the first FET with a first voltage and a gate of the second FET with a second voltage, and to set the switch to an on state based on controlling the gate of the first FET and the gate of the second FET to track the input voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic diagram of an embodiment of a high voltage tolerant bootstrap switch.

[0008] Figure 2A yes Figure 1 Schematic diagram of an example of a high voltage bootstrap switch operating in the off state.

[0009] Figure 2B yes Figure 1 Schematic diagram of an example of a high voltage tolerant bootstrap switch operating in the on-state.

[0010] Figure 3A This is a schematic diagram of an example of transient simulation of the opening state of a high-voltage bootstrap switch.

[0011] Figure 3B yes Figure 3A An example of a graph of input voltage and input current versus time for an off-state transient simulation.

[0012] Figure 4 is a schematic diagram of one embodiment of an integrated circuit (IC) having a high voltage tolerant bootstrap switch coupled to a multi-function pin.

[0013] Figure 5 is a schematic diagram of an embodiment of a data conversion system.

[0014] Figure 6is a schematic diagram of another embodiment of a high voltage resistant bootstrap switch.

[0015] Figure 7 is a schematic diagram of another embodiment of a high voltage resistant bootstrap switch.

[0016] Figure 8 is a schematic diagram of another embodiment of a high voltage resistant bootstrap switch.

[0017] Fig. 9 is a schematic diagram of another embodiment of a high voltage resistant bootstrap switch. DETAILED DESCRIPTION

[0018] The detailed description of the following embodiments presents various descriptions of specific embodiments of the present invention. However, the present invention can be implemented in many different ways. In this specification, reference is made to the accompanying drawings. It should be understood that the elements shown in the drawings are not necessarily drawn to scale. In addition, it will be understood that some embodiments may include more elements than shown in the drawings and / or a subset of the elements illustrated in the drawings. In addition, some embodiments may combine any appropriate combination of features from two or more drawings.

[0019] An apparatus and method for a high voltage resistant bootstrap switch are disclosed. In some embodiments, an integrated circuit (IC) includes an input node receiving an input voltage, an output node, and a switch connected between the input node and the output node. The switch includes a first field effect transistor (FET) and a second FET connected in series between the input node and the output node. The switch can be configured between an off state and an on state, in which the gate of the first FET is controlled by a first voltage and the gate of the second FET is controlled by a second voltage; in which the gates of the first FET and the second FET are controlled by a voltage that tracks the input voltage. For example, in the on state, the gates of the first FET and the second FET can be controlled by a voltage corresponding to the sum of the first voltage and the input voltage.

[0020] By implementing the switch in this manner, the switch can achieve high voltage tolerance in the off state and high linearity in the on state. For example, in the off state, the switch can withstand large voltage swings at the input node without the switch's FET suffering from junction damage and / or gate oxide damage.

[0021] In some embodiments, the first voltage corresponds to the power supply voltage (V DD ), the second voltage corresponds to the ground voltage of the IC (V GND ). In addition, when in the off state, the switch can withstand high voltage conditions present at the input node, such as the ground voltage V GND and exceeds V DD The signal swings between the second supply voltage.

[0022] In some embodiments, the input node may correspond to a pin or pad of an IC. An IC is also referred to herein as a semiconductor die. When the switch is turned on and off, the input pad may be exposed to high voltage conditions. In one example, the input pad is a multi-function pin for two or more IC functions. In such an application, the switch may be turned on in a first mode and used for a desired function (e.g., sampling), and may be turned off and exposed to a high voltage in a second mode.

[0023] To further enhance the tolerance in the off state, one or more additional FETs may be included between the first FET and the second FET. For example, a third FET may be included between the first FET and the second FET, wherein the gate of the third FET is controlled in the off state by a third voltage between the first voltage and the second voltage. Furthermore, in the on state, the gates of the first FET, the second FET, and the third FET may be controlled with a voltage corresponding to the sum of the first voltage and the input voltage.

[0024] The switch can be used in a variety of applications, including high-precision sampling applications where the switch is specified to operate with a low resistance in the on state. For example, in high-linearity data conversion applications, the switch can be used to provide a sampled voltage to the input of an analog-to-digital converter (ADC).

[0025] In certain embodiments, the gate voltage for the FET in the on state is generated by a switched capacitor circuit, such as by the top plate of a bootstrap capacitor.

[0026] FETs can be implemented in a variety of ways, including using metal oxide semiconductor (MOS) transistors. In some embodiments, the FET is n-type. However, other implementations are possible. As used herein and as will be understood by one of ordinary skill in the art, a MOS transistor can have a gate made of a non-metallic material (e.g., polysilicon) and can have a dielectric region implemented not only with silicon oxide, but also with other dielectrics (e.g., high-k dielectrics).

[0027] Figure 1 2 is a schematic diagram of an embodiment of a high voltage resistant bootstrap switch 20. The high voltage resistant bootstrap switch 20 includes a switch 1 and a switch control circuit 2.

[0028] like Figure 1 As shown, switch 1 is connected to receive input voltage V IN The input node and provides the output voltage V OUTIn the illustrated embodiment, the switch 1 includes a first n-type field effect transistor (NFET) 11 and a second NFET 12 electrically connected in series between the input node and the output node. For example, the drain of the first NFET 11 is electrically connected to the input node, the source of the first NFET 11 is electrically connected to the drain of the second NFET 12, and the source of the second NFET 12 is electrically connected to the output node.

[0029] The switch control circuit 2 controls the gate voltages of the first NFET 11 and the second NFET 12 to set the switch 1 in an off state or an on state as required. In some embodiments, the switch control circuit 2 receives a switch enable signal for setting the state of the switch 1.

[0030] In the embodiment shown, the switch control circuit 2 sets the switch 1 to an off state by controlling the gate of the first NFET 11 with a first voltage and the gate of the second NFET 12 with a second voltage, and by tracking the input voltage V IN The voltage of the first NFET 11 and the second NFET 12 controls the gates of the first NFET 11 and the second NFET 12 to set the switch 1 to the on state. For example, in some embodiments, the gates of the first NFET 11 and the second NFET 12 can be connected with the voltage corresponding to the first voltage and the input voltage V IN The sum of the voltage controls the on state.

[0031] By implementing the bootstrap switch 20 in this manner, the bootstrap switch 20 can achieve high voltage tolerance in the off state and high linearity in the on state. For example, in the off state, the bootstrap switch 20 can withstand a large voltage swing at the input node without the first NFET 11 and the second NFET 12 suffering from junction damage and / or gate oxide damage.

[0032] In some embodiments, the first voltage corresponds to a supply voltage of the IC and the second voltage corresponds to a ground voltage of the IC. Additionally, when in the off state, the bootstrap switch 20 can withstand high voltage conditions present at the input node.

[0033] One or more instances of the high voltage tolerant bootstrap switch 20 may be fabricated on an IC as desired. Any of the high voltage tolerant bootstrap switches described herein may be implemented on an IC.

[0034] Figure 2A It is operated in disconnected state 21 Figure 1 Schematic diagram of an example of a high voltage tolerant bootstrap switch 20 . Figure 2B yes Figure 1 Schematic diagram of an example of a high voltage tolerant bootstrap switch 20 operating in an on state 22 .

[0035] In the illustrated embodiment, in the off state 21, the gate of the first NFET switch 11 is set by the switch control circuit to a first voltage, which in this example corresponds to the first supply voltage V DD1 Furthermore, in the off state 21, the gate of the second NFET switch 12 is set by the switch control circuit to a second voltage, which in this example corresponds to the ground voltage V GND .

[0036] By implementing the bootstrap switch in this manner, a high voltage tolerance can be achieved in the off state 21. For example, the bootstrap switch can withstand large voltage swings at the input node (e.g., input voltage V IN At ground voltage V GND and the second power supply voltage V DD2 swings between DD2 >V DD1 For example, in the off state 21, the bootstrap switch can withstand large voltage swings at the input node (including voltages exceeding the first supply voltage V DD1 The voltage swing of the first NFET 11 and the second NFET 12 is reduced without suffering junction damage and / or gate oxide damage.

[0037] In the illustrated embodiment, in the on state 22, the gates of the first NFET switch 11 and the second NFET switch 12 are set by the switch control circuit to be approximately equal to the first supply voltage V DD1 and input voltage V IN The sum of the voltages.

[0038] By implementing the bootstrap switch in this way, high linearity in the on-state 22 is achieved. For example, as the input voltage V IN The gate voltage of the first NFET switch 11 and the second NFET switch 12 changes with respect to the input voltage V IN Dynamically changes in voltage to keep the transistor turned on with low resistance, thus achieving high linearity.

[0039] Figure 3A is a schematic diagram of an example of an off-state transient simulation of the high voltage tolerant bootstrap switch 30. In this example, the high voltage tolerant bootstrap switch 30 is connected between the input node swinging from 0V to 5V and the sampling capacitor C Samp and leakage resistor R Leak In addition, the gate of the first NFET 11 is controlled to 3.3 V and the gate of the second NFET 12 is controlled to 0 V. In this simulation, the node between the first NFET 11 and the second NFET 12 swings from 0 V to 2.6 V, while the output node maintains a voltage of approximately 0 V.

[0040] Figure 3B yes Figure 3A An example of an input voltage and input current versus time plot for an off-state transient simulation. The plot shows that the input current maintains an acceptable input current leakage level when the input voltage changes from 0V to 5V. Figure 3B In the example shown, the transistor is rated for 3.3 V and the graph shows that throughout the transient simulation, the drain-source voltage (VDS), gate-source (VGS), and gate-drain voltage (VGD) are all less than 3.3 V. Therefore, the transistor reliability of the switch is maintained.

[0041] Figure 4 6 is a schematic diagram of one embodiment of an IC 60 having a high voltage tolerant bootstrap switch coupled to a multi-function pin 61. Figure 4 As shown, IC60 includes a switch 1, a switch control circuit 2, a first functional circuit 63, a second functional circuit 64 and a multi-function pin 61. Although for the sake of clarity of the figure, Figure 4 Although not shown in the figure, IC 60 generally includes additional pins and circuits. In this example, the first functional circuit 63 uses the first power supply voltage V DD1 and ground voltage V GND The second functional circuit 64 uses the second power supply voltage V DD2 and ground voltage V GND Operation, where V DD2 >V DD1 .

[0042] like Figure 4 As shown, switch 1 is connected between multi-function pin 61 and an output node coupled to first functional circuit 63. In addition, switch control circuit 2 sets switch 1 to an on state when first functional circuit 63 is used, and sets switch 1 to an off state when second functional circuit 64 is used.

[0043] Since the second functional circuit 64 operates at a higher supply voltage, the input node of switch 1 can experience a high steady-state voltage level when switch 1 is in the off state. By implementing a bootstrap switch according to the teachings herein, the bootstrap switch can withstand high voltage conditions present at the multi-function pin 61 or other input nodes.

[0044] Figure 5 is a schematic diagram of an embodiment of a data conversion system 70. The data conversion system 70 includes a switch 1, a switch control circuit 2, a sampling capacitor C Samp and ADC 61.

[0045] In the embodiment shown, switch 1 is connected to receive input voltage V IN The input node and provides the output voltage V OUTThe sampling capacitor C Samp Maintain output voltage V OUT The input of ADC 61 is connected to the output node of switch 1 and is used to generate an output voltage V OUT digital representation.

[0046] The bootstrap switch herein can be used in a variety of applications, including data conversion applications. For example, Figure 5 In the embodiment, the switch 1 can be turned on or off as needed to supply the sampling capacitor C Samp and ADC 61 provides input voltage V IN When on, switch 1 provides high linearity. When off, switch 1 provides high voltage tolerance, including a steady-state high voltage condition at the input node.

[0047] Figure 6 is a schematic diagram of another embodiment of a high voltage resistant bootstrap switch 80. The high voltage resistant bootstrap switch 80 includes a switch 71 and a switch control circuit 72. The switch 71 includes a first NFET 11, a second NFET 12, and a third NFET 13, which are connected in series between an input node and an output node, wherein the third NFET 13 is located between the first NFET 11 and the second NFET 12. The gates of the first NFET 11, the second NFET 12, and the third NFET 13 are controlled by the switch control circuit 72 to turn on or off the switch 71.

[0048] Figure 6 The high voltage bootstrap switch 80 is similar to Figure 1 The high voltage bootstrap switch 20 in FIG. Figure 6 The switch 71 further includes a third NFET 13 located between the first NFET 11 and the second NFET 12 .

[0049] To further enhance the voltage tolerance in the off state, one or more additional FETs may be included between the first NFET 11 and the second NFET 12. For example, the embodiment includes a third NFET 13 located between the first NFET 11 and the second NFET 12, wherein the gate of the third NFET 13 is controlled in the off state by a third gate voltage located between the first gate voltage of the first NFET 11 and the second gate voltage of the second NFET 12. In addition, in the on state, the gates of the NFETs 11-13 may be controlled to track the input voltage V IN , for example, corresponding to the first voltage and the input voltage V IN The sum of the voltages.

[0050] Figure 7FIG. 1 is a schematic diagram of another embodiment of a high voltage resistant bootstrap switch 90. The high voltage resistant bootstrap switch 90 includes a circuit connected to receive a non-inverting input voltage V IN+ The first input node and provides a non-inverting output voltage V OUT+ The first switch 1a is connected between the first output node and the inverting input voltage V IN- The second input node provides an inverting output voltage V OUT- A second switch 1b is connected between the second output nodes of the transistor and the control circuit.

[0051] Continue to refer Figure 7 , the first switch 1a includes a first NFET 11a and a second NFET 12a electrically connected in series between a first input node and a first output node, and the second switch 1b includes a first NFET 11b and a second NFET 12b electrically connected in series between a second input node and a second output node. The switch control circuit 2 generates a first switch control signal for controlling the gate of the first NFET 11a of the first switch 1a and the gate of the first NFET 11b of the second switch 1b, and a second switch control signal for controlling the gate of the second NFET 12a of the first switch 1a and the gate of the second NFET 12b of the second switch 1b. The switch control circuit 2 sets the switches 1a-1b in an on state or an off state using the switch control signals as needed.

[0052] Figure 7 The high voltage bootstrap switch 90 is similar to Figure 1 The high voltage bootstrap switch 20 in FIG. Figure 7 The medium-to-high voltage bootstrap switch 90 is implemented differentially.

[0053] Any of the high voltage tolerant bootstrap switches in this article can be implemented in either single-ended or differential configurations.

[0054] Figure 8 FIG. 1 is a schematic diagram of another embodiment of a high voltage bootstrap switch 120. The high voltage bootstrap switch 120 includes a switch 1, which includes a switch connected in series to receive an input voltage V IN The input node and provides the output voltage V OUT The first NFET 11 and the second NFET 12 are connected between the output nodes of the first NFET 11 and the second NFET 12. The gate voltages of the first NFET 11 and the second NFET 12 are controlled by a positive charge pump 102, which includes a bootstrap capacitor 110, a first control switch 111, a second control switch 112, a third control switch 113, a fourth control switch 114, and a fifth control switch 115.

[0055] like Figure 8 As shown, the first control switch 111 is electrically connected to the ground voltage V GNDand the bottom plate (cbot) of the bootstrap capacitor 110, and is controlled by the inverted clock signal CLKB. In addition, the second control switch 112 is electrically connected between the bottom plate of the bootstrap capacitor 110 and the input node, and is controlled by the non-inverted clock signal CLK. In addition, the third control switch 113 is electrically connected to the ground voltage V GND and the gate of the second NFET 12, and is controlled by the inverted clock signal CLKB. In addition, the fourth control switch 114 is electrically connected between the gate of the second NFET 12 and the top plate (ctop) of the bootstrap capacitor 110, and is controlled by the non-inverted clock signal CLK. In addition, the fifth control switch 115 is electrically connected between the power supply voltage V DD1 The gate of the first NFET 11 is electrically connected to the top plate of the bootstrap capacitor 110 and is controlled by the inverted clock signal CLKB.

[0056] In the illustrated embodiment, the positive charge pump 102 operates in the first phase (the non-inverted clock signal CLK is inactive and the inverted clock signal CLKB is active), wherein the first control switch 111, the third control switch 113, and the fifth control switch 115 are turned on and the remaining control switches are turned off to control the bottom plate of the bootstrap capacitor 110 to V GND , the top plate of the bootstrap device 110 is controlled to V DD1 , the gate of the first NFET 11 is controlled to V DD1 , and the gate of the second NFET 12 is controlled to V GND In addition, the positive charge pump 102 operates in the second phase (the non-inverted clock signal CLK is valid and the inverted clock signal CLKB is invalid), wherein the second control switch 112 and the fourth control switch 114 are turned on and the remaining control switches are turned off to control the bottom plate of the bootstrap capacitor 110 to V IN , the top plate of the bootstrap capacitor 110 is controlled to V DD1 +V IN , and the gates of the first NFET 11 and the second NFET 12 are controlled to be V DD1 +V IN .

[0057] although Figure 8 An example implementation of a circuit for controlling the gate of a FET of a switch is described, but the bootstrap switch here may be controlled in other ways. Therefore, other implementations are also possible.

[0058] Fig. 9 FIG. 2 is a schematic diagram of another embodiment of a high voltage bootstrap switch 200. The high voltage bootstrap switch 200 includes a switch 201 and a switch control circuit 202. The switch 202 is connected to receive an input voltage V IN The input node and provides the output voltage VOUT between the output nodes.

[0059] Fig. 9 The high voltage bootstrap switch 200 and Figure 1 The high voltage bootstrap switch 20 is similar to the Fig. 9 The medium-tolerance high-voltage bootstrap switch 200 depicts an implementation using p-type transistors.

[0060] For example, Fig. 9 As shown, the switch 201 includes a first p-type field effect transistor (PFET) 211 and a second PFET 212 electrically connected in series between an input node and an output node. For example, a source of the first PFET 211 is electrically connected to the input node, a drain of the first PFET 211 is electrically connected to a source of the second PFET 212, and a drain of the second PFET 212 is electrically connected to the output node.

[0061] The switch control circuit 202 controls the gate voltages of the first PFET 211 and the second PFET 212 to set the switch 201 in an off state or an on state as required. For example, the switch control circuit 202 can set the switch 201 in an off state by controlling the gate of the first PFET 211 with a first voltage and the gate of the second PFET 212 with a second voltage, and can also set the switch 201 in an off state by tracking the input voltage V IN The voltage of the first PFET 211 and the second PFET 212 controls the gate of the first PFET 211 and the second PFET 212 to set the switch 201 to the on state. For example, in some embodiments, the gates of the first PFET 211 and the second PFET 212 can be connected with the first voltage and the input voltage V IN The sum of the voltage controls the on state.

[0062] in conclusion

[0063] The above description may refer to elements or features as being "connected" or "coupled" together. As used herein, unless otherwise expressly stated, "connected" means that one element / feature is directly or indirectly connected to another element / feature, and is not necessarily mechanically connected. Similarly, unless otherwise expressly stated, "coupled" means that one element / feature is directly or indirectly coupled to another element / feature, and is not necessarily mechanically coupled. Therefore, although the various schematic diagrams shown in the figures depict exemplary arrangements of elements and components, in actual embodiments there may be additional intervening elements, devices, features, or components (assuming that the functionality of the depicted circuits is not adversely affected).

[0064] Although certain embodiments have been described, these embodiments are presented only by way of example and are not intended to limit the scope of the present disclosure. In fact, the novel devices, methods, and systems described herein may be embodied in various other forms; in addition, various omissions, substitutions, and changes may be made to the forms of the methods and systems described herein without departing from the spirit of the present disclosure. For example, although the disclosed embodiments are presented in a given arrangement, alternative embodiments may utilize different components and / or circuit topologies to perform similar functions, and may delete, move, add, subdivide, combine, and / or modify some elements. Each of these elements may be implemented in a variety of different ways. Any appropriate combination of the elements and actions of the various embodiments described above may be combined to provide further embodiments.

Claims

1. An integrated circuit (IC), comprising: A first node configured to receive an input voltage; Second node; a switch including a first field effect transistor (FET) and a second FET electrically connected in series between the first node and the second node; and The switch control circuit is configured to set the switch to an off state based on controlling the gate of the first FET with a first voltage and controlling the gate of the second FET with a second voltage, and to set the switch to an on state based on controlling the gate of the first FET and the gate of the second FET to track an input voltage. 2 . The IC of claim 1 , wherein the first voltage is a power supply voltage of the IC. 3 . The IC of claim 1 , wherein the second voltage is a ground voltage of the IC. The IC of claim 1 , wherein the first node is an input pad of the IC.

5. The IC of claim 4, wherein the input pad is multifunctional, the input voltage exceeding a supply voltage of the IC in an off state of the switch. 6 . The IC of claim 1 , wherein the control circuit is further configured to control the gate of the first FET and the gate of the second FET in an on state using a control voltage based on a sum of the first voltage and the input voltage.

7. The IC of claim 1, wherein the IC further comprises a switched capacitor circuit including a bootstrap capacitor, wherein a first plate of the bootstrap capacitor is configured to control the gates of the first FET and the second FET in a conductive state.

8. The IC of claim 7, wherein the bootstrap capacitor is connected between the first voltage and the second voltage in a first state of a clock signal, and is connected between the input voltage and gates of the first FET and the second FET in a second state of the clock signal.

9. The IC of claim 1, wherein the switch further comprises a third FET electrically connected between the first FET and the second FET.

10. The IC of claim 9, wherein the switch control circuit is further configured to set the switch to an on state based on controlling a gate of the third FET to track the input voltage.

11. The IC of claim 9, wherein the switch control circuit is further configured to set the switch to an off state based on controlling a gate of the third FET with a third voltage between the first voltage and the second voltage.

12. The IC of claim 1, wherein the first FET and the second FET are metal oxide semiconductor (MOS) transistors.

13. The IC of claim 1, wherein the first FET and the second FET are n-type transistors.

14. The IC of claim 1 further comprising a sampling capacitor connected to the second node.

15. The IC of claim 1, wherein the switch is implemented using differential signaling.

16. The IC of claim 1 further comprising an analog-to-digital converter (ADC) having an input electrically connected to the second node.

17. A method of switching in an integrated circuit (IC), the method comprising: receiving an input voltage at a first node; opening the switch using a switch control circuit, the switch comprising a first field effect transistor (FET) and a second FET electrically connected in series between the first node and the second node, wherein opening the switch comprises setting the switch to an off state based on controlling a gate of the first FET with a first voltage and controlling a gate of the second FET with a second voltage; and The switch is turned on using the switch control circuit, wherein turning on the switch includes setting the switch to an on state based on controlling a gate of the first FET and a gate of the second FET to track the input voltage. 18 . The method of claim 17 , wherein turning on the switch further comprises controlling a gate of the first FET and a gate of the second FET with a control voltage based on a sum of the first voltage and the input voltage.

19. A data conversion system, comprising: an input node configured to receive an input voltage; an analog-to-digital converter (ADC) having an input; a switch including a first field effect transistor (FET) and a second FET electrically connected in series between the input node and the input of the ADC; and The switch control circuit is configured to set the switch to an off state based on controlling the gate of the first FET with a first voltage and controlling the gate of the second FET with a second voltage, and to set the switch to an on state to track the input voltage based on controlling the gates of the first FET and the second FET. 20 . The data conversion system of claim 19 , wherein the control circuit is further configured to control the gate of the first FET and the gate of the second FET in an on state using a control voltage based on a sum of the first voltage and the input voltage.

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