A low-power SAR ADC switch control circuit based on common-mode level

Abstract

The application discloses a low-power SAR ADC switch control circuit based on a common-mode level, comprising a first flip-flop module, a second flip-flop module, a third flip-flop module, a digital logic gate module and a backplane control switch module, the first flip-flop module is used for generating a comparator latch signal and a first output signal, the second flip-flop module is used for storing a comparison result and generating a second output signal, the third flip-flop module is used for indicating a current conversion position according to the first output signal and generating a third output signal, the digital logic gate module is used for generating a switch control signal, and the backplane control switch module is used for connecting a capacitor backplane to a corresponding reference level according to the switch control signal. The application multiplexes the output signal of the first flip-flop module as the input of the third flip-flop module, dynamically indicates the current conversion position, can optimize the area and power consumption of the switch control circuit in the SAR ADC, and can be widely applied to the field of mixed signal circuit design.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of mixed signal circuit design, and in particular to a low-power SAR ADC switch control circuit based on common-mode level. BACKGROUND

[0002] In the design of low-power SAR ADC (Successive Approximation Register ADC), the switch timing design of CDAC is particularly critical. The traditional implementation method of moving guess one logic is simple, the switch on resistance is low, and the reference voltage is established quickly, but each comparison needs to be preset, and the continuous change of the capacitor bottom plate potential from the negative reference voltage VREFN to the positive reference voltage VREFP and then to the negative reference voltage VREFN in the establishment process makes the power consumption of the capacitor switch higher, and also puts higher requirements on the design of the reference voltage buffer.

[0003] The prior art proposes a switch switching strategy based on common-mode level. In the sampling stage, the upper plate of the capacitor is connected to the input signal, and all the lower plates of the capacitors are connected to the common-mode level. In the conversion stage, the upper plate of the capacitor is disconnected from the input signal, and after the completion of the comparison by the comparator, according to the comparison result, the lower plate of the capacitor on one side of the MSB (the most significant bit in the SAR ADC conversion process) is connected to the positive reference voltage VREFP, and the other side is connected to the negative reference voltage VREFN. After the DAC is established again and the comparator is compared again, according to the comparison result, the lower plate of the capacitor on the MSB-1 side is connected to the positive reference voltage VREFP, and the other side is connected to the negative reference voltage VREFN. The above process is repeated until the last bit comparison result is obtained. The switch switching strategy based on common-mode level does not have continuous changes of positive and negative reference voltages, does not need to be preset, and is more power-saving. However, since the corresponding switch control circuits need to be designed for top plate sampling and bottom plate sampling, and due to different precision and sampling rate requirements, the switch control circuits based on the common-mode level switching strategy are different, and in actual circuit design, a full custom design method is often used to realize it. SUMMARY

[0004] To solve the above technical problems, the purpose of the present application is to provide a low-power SAR ADC switch control circuit based on common-mode level, which can reduce the power consumption of the circuit and simplify the circuit design.

[0005] To achieve the above object, one aspect of the embodiment of the present application proposes a low-power SARADC switch control circuit based on common-mode level, comprising a first flip-flop module, a second flip-flop module, a third flip-flop module, a digital logic gate module and a backplane control switch module, the input ends of the second flip-flop module and the third flip-flop module are connected with the output end of the first flip-flop module, the output ends of the second flip-flop module and the third flip-flop module are connected with the input end of the digital logic gate module, the output end of the digital logic gate module is connected with the input end of the backplane control switch module, the first flip-flop module is used to generate a comparator latch signal and a first output signal, the second flip-flop module is used to store a comparison result according to the comparator latch signal and generate a second output signal, the third flip-flop module is used to indicate a current conversion position according to the first output signal and generate a third output signal, the digital logic gate module is used to obtain a switch control signal according to the second output signal and the third output signal, and the backplane control switch module is used to connect a capacitor backplane to a corresponding reference level according to the switch control signal.

[0006] In some embodiments, the first flip-flop module comprises a first flip-flop, a first end of the first flip-flop is used to access a sample-and-hold signal, a second end of the first flip-flop is grounded, a third end of the first flip-flop is used to access an external clock signal, a fourth end of the first flip-flop is used to access a system signal, a fifth end of the first flip-flop is connected with the input end of the second flip-flop module, and the fifth end of the first flip-flop is used to generate the comparator latch signal.

[0007] In some embodiments, the first flip-flop module further comprises a plurality of second flip-flops, a first end of each of the second flip-flops is used to access the system signal, a second end of each of the second flip-flops is connected with a sixth end of a previous second flip-flop or the first flip-flop, a third end of each of the second flip-flops is used to access the external clock signal, a fourth end of each of the second flip-flops is used to access the sample-and-hold signal, a fifth end of each of the second flip-flops is connected with the input end of the second flip-flop module, a sixth end of each of the second flip-flops is further connected with the input end of the third flip-flop module, the fifth end of each of the second flip-flops is used to generate the comparator latch signal, and the sixth end of each of the second flip-flops is used to generate the first output signal.

[0008] In some embodiments, the second output signal comprises a first interface output signal and a second interface output signal.

[0009] In some embodiments, the comparison result comprises a first comparison result, the second flip-flop module comprises a third flip-flop and a plurality of fourth flip-flops, the first end of the third flip-flop and each of the fourth flip-flops is connected to the output end of the first flip-flop module, the second end of the third flip-flop is connected to the third end of the third flip-flop, the second end of each of the fourth flip-flops is used to access the first comparison result, the third end of each of the fourth flip-flops is connected to the previous fourth flip-flop or the sixth end of the third flip-flop, the fourth end of the third flip-flop and each of the fourth flip-flops is used to access a sample-and-hold signal, the sixth end of each of the fourth flip-flops is also connected to the input end of the digital logic gate module, the second end of each of the fourth flip-flops is used to store the first comparison result according to the comparator latch signal, and the sixth end of each of the fourth flip-flops is used to generate the first interface output signal.

[0010] In some embodiments, the second flip-flop module further comprises a fifth flip-flop, the first end of the fifth flip-flop is connected to the output end of the first flip-flop module, the second end of the fifth flip-flop is used to access the first comparison result, the third end of the fifth flip-flop is connected to the sixth end of the fourth flip-flop, the fourth end of the fifth flip-flop is used to access a system signal, the sixth end of the fifth flip-flop is connected to the input end of the digital logic gate module, the second end of the fifth flip-flop is used to store the first comparison result according to the comparator latch signal, and the sixth end of the fifth flip-flop is used to generate the first interface output signal.

[0011] In some embodiments, the comparison result comprises a second comparison result, the second flip-flop module comprises a sixth flip-flop and a plurality of seventh flip-flops, the first end of the sixth flip-flop and each of the seventh flip-flops is connected to the output end of the first flip-flop module, the second end of the sixth flip-flop is connected to the third end of the sixth flip-flop, the second end of each of the seventh flip-flops is used to access the second comparison result, the third end of each of the seventh flip-flops is connected to the previous seventh flip-flop or the sixth end of the sixth flip-flop, the fourth end of the sixth flip-flop and each of the seventh flip-flops is used to access a sample-and-hold signal, the sixth end of each of the seventh flip-flops is also connected to the input end of the digital logic gate module, the second end of each of the seventh flip-flops is used to store the second comparison result according to the comparator latch signal, and the sixth end of each of the seventh flip-flops is used to generate the second interface output signal.

[0012] In some embodiments, the second flip-flop module further comprises an eighth flip-flop, a first end of the eighth flip-flop is connected with an output end of the first flip-flop module, a second end of the eighth flip-flop is used for accessing the second comparison result, a third end of the eighth flip-flop is connected with a sixth end of the seventh flip-flop, a fourth end of the eighth flip-flop is used for accessing a system signal, a sixth end of the eighth flip-flop is connected with an input end of the digital logic gate module, the second end of the eighth flip-flop is used for storing the second comparison result according to the comparator latch signal, and the sixth end of the eighth flip-flop is used for generating the second interface output signal.

[0013] In some embodiments, the third flip-flop module comprises a plurality of ninth flip-flops, a first end of each of the ninth flip-flops is used for accessing a system signal, a second end of each of the ninth flip-flops is used for accessing a power supply, a third end of each of the ninth flip-flops is connected with an output end of each of the first flip-flop modules, a fourth end of each of the ninth flip-flops is used for accessing a sample-and-hold signal, a sixth end of each of the ninth flip-flops is connected with an input end of the digital logic gate module, the third end of each of the ninth flip-flops is used for indicating a current conversion position according to the first output signal, and the sixth end of each of the ninth flip-flops is used for generating the third output signal.

[0014] In some embodiments, the digital logic gate module comprises a plurality of first NAND gates, second NAND gates, first AND gates, second AND gates and first NOT gates, an output end of the second flip-flop module and an output end of the third flip-flop module are connected with input ends of each of the first NAND gates, an output end of the second flip-flop module and an output end of the third flip-flop module are connected with input ends of each of the second NAND gates, an output end of the second flip-flop module and an output end of the third flip-flop module are connected with input ends of each of the first AND gates, an output end of the second flip-flop module and an output end of the third flip-flop module are connected with input ends of each of the second AND gates, an output end of the third flip-flop module is connected with input ends of each of the first NOT gates, output ends of each of the first NAND gates, each of the second NAND gates, each of the first AND gates, each of the second AND gates and each of the first NOT gates are connected with input ends of the backplane control switch module, each of the first NAND gates and each of the second AND gates are used for obtaining the switch control signal according to the third output signal and the first interface output signal, each of the second NAND gates and each of the first AND gates are used for obtaining the switch control signal according to the third output signal and the second interface output signal, and each of the first NOT gates are used for obtaining the switch control signal according to the third output signal.

[0015] The beneficial effects of the present application are: the low-power SAR ADC switch control circuit based on common-mode level, the first flip-flop module, the second flip-flop module, the third flip-flop module, the digital logic gate module and the bottom plate control switch module, the comparator latch signal and the first output signal are generated through the first flip-flop module, the comparison result is stored through the second flip-flop module according to the comparator latch signal, and the second output signal is generated, the current conversion position is indicated through the third flip-flop module according to the first output signal, and the third output signal is generated, the switch control signal is obtained through the digital logic gate module according to the second output signal and the third output signal, and the capacitor bottom plate is connected to the corresponding reference level through the bottom plate control switch module according to the switch control signal. The first output signal in the first flip-flop module is innovatively reused as the input signal of the third flip-flop module, the current conversion position is dynamically indicated, the area and power consumption of the switch control circuit in the traditional SAR ADC can be greatly optimized, and the circuit design is simplified without sacrificing the circuit performance. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following introduces the drawings needed to be used in the embodiments of the present application as follows. It should be understood that the drawings introduced in the following are only for facilitating the clear description of part of the embodiments in the technical solutions of the present application, and other drawings can be obtained by those skilled in the art without paying creative labor on the premise of the drawings.

[0017] Figure 1 A structural block diagram of the low-power SAR ADC switch control circuit based on common-mode level provided by the embodiments of the present application is provided.

[0018] Figure 2 A circuit structure schematic diagram of the low-power SAR ADC switch control circuit based on common-mode level provided by the embodiments of the present application is provided.

[0019] Figure 3 The digital logic part current simulation results of two SAR ADCs in a certain sampling-conversion cycle provided by the embodiments of the present application are provided.

[0020] Figure 4 The circuit total current simulation results of two SAR ADCs in a certain sampling-conversion cycle provided by the embodiments of the present application are provided. DETAILED DESCRIPTION

[0021] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not intended to limit the present application. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with embodiments of the present application. They are only examples of apparatuses and methods consistent with some aspects of the embodiments of the present application as detailed in the appended claims.

[0022] It can be understood that the terms "first", "second" and the like used in the present application can be used herein to describe various concepts, but unless specifically stated, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of the present application, the first information can also be referred to as the second information, and similarly, the second information can also be referred to as the first information. Depending on the context, the word "if" as used herein can be interpreted as "when" or "when" or "in response to determining".

[0023] The terms "at least one", "multiple", "each", "any" and the like used in the present application include one, two or more than two, multiple includes two or more than two, each refers to each of the corresponding multiple, and any refers to any one of the multiple.

[0024] Before the embodiments of the present application are described in detail, first, some nouns and terms involved in the embodiments of the present application are described, and the nouns and terms involved in the embodiments of the present application are applicable to the following explanations.

[0025] SAR ADC (Successive Approximation Register ADC), which is a good compromise between speed, resolution and power, has the characteristics of low power consumption, small size, moderate resolution and speed, short sampling delay, etc.

[0026] In recent years, analog front-end signal acquisition and processing circuit technology as a wearable biomedical chip key, has been the attention and research of many institutions and scholars, and is in a rapid development stage. In order to meet the requirements of portable brain-computer interface device use time, the ADC in the brain-computer interface chip needs to be designed with ultra-low power consumption to prolong the service life of the device under limited power supply.

[0027] SAR ADC was first realized by Gray team in 1975. It has become a research hotspot in recent years due to its simple structure and low power consumption. SAR ADC is based on binary search algorithm, which generates quantization results by successive approximation method in multiple clock cycles. SAR ADC does not need to use accurate amplification operational amplifier, so its structure is simple and power consumption is low. It is widely used in wearable biomedical chip design.

[0028] In the design of low-power SAR ADC, the switch timing design of CDAC is particularly important. The traditional implementation method of moving guess one logic is simple, the switch on resistance is low, and the reference voltage establishment speed is fast. However, each comparison needs to be preset, and the continuous change of the bottom plate potential of the capacitor from the negative reference voltage VREFN to the positive reference voltage VREFP and then to the negative reference voltage VREFN during the establishment process makes the power consumption of the capacitor switch high, and also puts higher requirements on the design of the reference voltage buffer.

[0029] The prior art proposes a switch switching strategy based on common mode level. In the sampling stage, the top plate of the capacitor is connected to the input signal, and all the bottom plates of the capacitors are connected to the common mode level. In the conversion stage, the top plate of the capacitor is disconnected from the input signal, and after the comparator comparison is completed, according to the comparison result, the bottom plate of the capacitor on one side of MSB (the most significant bit in the SAR ADC conversion process) is connected to the positive reference voltage VREFP, and the other side is connected to the negative reference voltage VREFN. After the DAC is established again and the comparator is compared again, according to the comparison result, the bottom plate of the capacitor on one side of MSB-1 is connected to the positive reference voltage VREFP, and the other side is connected to the negative reference voltage VREFN. Repeat the above process until the last bit comparison result is obtained. The switch switching strategy based on common mode level does not have the continuous change of positive and negative reference voltages, does not need to be preset, and is more power-saving. However, since the top plate sampling and bottom plate sampling need to be designed with corresponding switch control circuits, and due to different precision and sampling rate requirements, the switch control circuits based on common mode level switching strategy are different, and in actual circuit design, a full custom design method is often used to realize it.

[0030] To this end, the embodiment of the present application provides a low-power SAR ADC switch control circuit based on a common-mode level, a first flip-flop module, a second flip-flop module, a third flip-flop module, a digital logic gate module and a bottom plate control switch module, the comparator latch signal and the first output signal are generated through the first flip-flop module, the comparison result is stored according to the comparator latch signal through the second flip-flop module, and the second output signal is generated, the current conversion position is indicated according to the first output signal through the third flip-flop module, and the third output signal is generated, the switch control signal is obtained according to the second output signal and the third output signal through the digital logic gate module, and the capacitor bottom plate is connected to the corresponding reference level according to the switch control signal through the bottom plate control switch module. The first output signal in the first flip-flop module is innovatively reused as the input signal of the third flip-flop module, the current conversion position is dynamically indicated, the area and power consumption of the switch control circuit in the traditional SAR ADC can be greatly optimized, and the circuit design is simplified without sacrificing the circuit performance.

[0031] Reference Figure 1 , Figure 1 A structural block diagram of a low-power SAR ADC switch control circuit based on a common-mode level is provided for the embodiment of the present application, the embodiment of the present application provides a low-power SAR ADC switch control circuit based on a common-mode level, comprising a first flip-flop module, a second flip-flop module, a third flip-flop module, a digital logic gate module and a bottom plate control switch module, the input ends of the second flip-flop and the third flip-flop module are connected with the output end of the first flip-flop module, the output ends of the second flip-flop module and the third flip-flop module are connected with the input ends of the digital logic gate module, the output end of the digital logic gate module is connected with the input end of the bottom plate control switch module, the first flip-flop module is used for generating a comparator latch signal and a first output signal, the second flip-flop module is used for storing a comparison result according to the comparator latch signal and generating a second output signal, the third flip-flop module is used for indicating a current conversion position according to the first output signal and generating a third output signal, the digital logic gate module is used for obtaining a switch control signal according to the second output signal and the third output signal, and the bottom plate control switch module is used for connecting a capacitor bottom plate to a corresponding reference level according to the switch control signal.

[0032] Specifically, the first flip-flop module is used for, in a conversion stage, each D flip-flop in the first flip-flop module moving a high level output from a sixth end (Q end) to the right through an external clock signal CLK, and moving a low level output from a fifth end (QN end) to the right, to generate comparator latch signals SC<9>-SC<0> for the second flip-flop module;

[0033] The second flip-flop module is used for accepting the QN end signal (i.e. the comparator latch signal) of each D flip-flop in the first flip-flop module in the conversion stage, and making the first end (SN end) of the front part D flip-flop in the second flip-flop module selected in sequence, so as to set the Q end output (the second output signal) of the front part D flip-flop to high level in sequence. The rising edge of the Q end output (the second output signal) from low level to high level of a certain D flip-flop in the front part will trigger the previous D flip-flop, so as to store the first comparison result DCOMP_QN in the previous D flip-flop, and the second comparison result DCOMP_Q is stored in the D flip-flop in the rear part in the same way;

[0034] The third flip-flop module is used for making the third output signal CC<8>-CC<0> output by each D flip-flop in the third flip-flop module receive the first output signal C<8>-C<0> output by the first flip-flop module in sequence in the conversion stage, so as to indicate the current conversion position;

[0035] The digital logic gate module is used for making each logic gate in the digital logic gate module adjusted constantly according to the second output signal and the third output signal output by the second flip-flop module and the third flip-flop module in the conversion stage, so as to correctly generate the switch control signal.

[0036] The bottom plate control switch module is used for connecting the capacitor bottom plate to the corresponding reference level according to the switch control signal output by the digital logic gate module in the conversion stage, so as to ensure the correct establishment of the DAC again.

[0037] Referring to Figure 2 , Figure 2 The circuit structure schematic diagram of the low-power SAR ADC switch control circuit based on the common mode level provided by the embodiment of the application, further as an optional implementation manner, the first flip-flop module includes a first flip-flop, the first end of the first flip-flop is used for connecting the sample and hold signal, the second end of the first flip-flop is grounded, the third end of the first flip-flop is used for connecting the external clock signal, the fourth end of the first flip-flop is used for connecting the system signal, the fifth end of the first flip-flop is connected with the input end of the second flip-flop module, and the fifth end of the first flip-flop is used for generating the comparator latch signal.

[0038] Referring to Figure 2, further as an optional implementation, the first flip-flop module further comprises a plurality of second flip-flops, the first end of each second flip-flop is used for accessing the system signal, the second end of each second flip-flop is connected with the sixth end of the previous second flip-flop or the first flip-flop, the third end of each second flip-flop is used for accessing the external clock signal, the fourth end of each second flip-flop is used for accessing the sample and hold signal, the fifth end of each second flip-flop is connected with the input end of the second flip-flop module, the sixth end of each second flip-flop is further connected with the input end of the third flip-flop module, the fifth end of each second flip-flop is used for generating the comparator latch signal, and the sixth end of each second flip-flop is used for generating the first output signal.

[0039] In some optional embodiments, as shown in Figure 2 a 10-bit SAR ADC is used for illustration, the first flip-flop is a D flip-flop DFF10, and the second flip-flop comprises D flip-flops DFF1, DFF2, DFF3, DFF4, DFF5, DFF6, DFF7, DFF8 and DFF9.

[0040] Specifically, the external clock signal CLK is connected with the third end (CK end) of the D flip-flops DFF10-DFF1, the sample and hold signal CK_SH is connected with the first end (SN end) of the D flip-flop DFF10 and the fourth end (RN end) of the D flip-flops DFF9-DFF1, and the system signal SYS is connected with the fourth end (RN end) of the D flip-flop DFF10 and the first end (SN end) of the D flip-flops DFF9-DFF1. The second end (D end) of the D flip-flop DFF10 is grounded, the sixth end (Q end) of the D flip-flop DFF10 is connected with the second end (D end) of the D flip-flop DFF9, the sixth end (Q end) of the D flip-flops DFF9-DFF2 is respectively connected with the second end (D end) of the previous D flip-flop DFF8-DFF1, and the sixth end (Q end) of the D flip-flops DFF9-DFF1 is further connected with the input end of the third flip-flop module, and the wiring name is C<8>-C<0>, that is, the first output signal is output to the third flip-flop module. The fifth end (QN end) of the D flip-flops DFF10-DFF1 is connected with the input end of the second flip-flop module, and the wiring name is SC<9>-SC<0>, that is, the comparator latch signal is output to the second flip-flop module.

[0041] Further as an optional implementation, the second output signal comprises a first interface output signal and a second interface output signal.

[0042] Referring to Figure 2, further as an optional implementation, the comparison result includes a first comparison result, the second flip-flop module includes a third flip-flop and a plurality of fourth flip-flops, the first end of the third flip-flop and each fourth flip-flop is connected with the output end of the first flip-flop module, the second end of the third flip-flop is connected with the third end of the third flip-flop, the second end of each fourth flip-flop is used for accessing the first comparison result, the third end of each fourth flip-flop is connected with the sixth end of the previous fourth flip-flop or the third flip-flop, the fourth end of the third flip-flop and each fourth flip-flop is used for accessing the sample-and-hold signal, the sixth end of each fourth flip-flop is also connected with the input end of the digital logic gate module, the second end of each fourth flip-flop is used for storing the first comparison result according to the comparator latch signal, and the sixth end of each fourth flip-flop is used for generating the first interface output signal.

[0043] With reference to Figure 2 , further as an optional implementation, the second flip-flop module further includes a fifth flip-flop, the first end of the fifth flip-flop is connected with the output end of the first flip-flop module, the second end of the fifth flip-flop is used for accessing the first comparison result, the third end of the fifth flip-flop is connected with the sixth end of the fourth flip-flop, the fourth end of the fifth flip-flop is used for accessing the system signal, the sixth end of the fifth flip-flop is connected with the input end of the digital logic gate module, the second end of the fifth flip-flop is used for storing the first comparison result according to the comparator latch signal, and the sixth end of the fifth flip-flop is used for generating the first interface output signal.

[0044] In some optional embodiments, as shown in Figure 2 , the third flip-flop is a D flip-flop DFF11, the fourth flip-flop includes a D flip-flop DFF12, a D flip-flop DFF13, a D flip-flop DFF14, a D flip-flop DFF15, a D flip-flop DFF16, a D flip-flop DFF17, a D flip-flop DFF18, and a D flip-flop DFF19, and the fifth flip-flop is a D flip-flop DFF20.

[0045] Specifically, the fourth end (RN end) of the sample-and-hold signal CK_SH and the D flip-flop DFF19-DFF11 are connected, and the fourth end (RN end) of the system signal SYS and the D flip-flop DFF20 are connected. The first end (SN end) of the D flip-flop DFF20-DFF11 is connected with the fifth end (QN end) of the D flip-flop DFF10-DFF1 in the first flip-flop module respectively, and the wiring name is SC<9>-SC<0>, that is, the comparator latch signal output by the first flip-flop module is input. The first comparison result DCOMP_QN is connected with the second end (D end) of the D flip-flop DFF20-DFF12 at the same time. The sixth end (Q end) of the D flip-flop DFF20-DFF12 is connected with the input end of the digital logic gate module, and the wiring name is A<8>-A<0>, that is, the first interface output signal is output to the digital logic gate module. The sixth end (Q end) of the D flip-flop DFF11 is connected with the third end (CK end) of the D flip-flop DFF12, and the second end (D end) of the D flip-flop DFF11 is connected with the third end (CK end) of the D flip-flop DFF11.

[0046] With reference to Figure 2 , further as an optional implementation, the comparison result includes a second comparison result, the second flip-flop module includes a sixth flip-flop and a plurality of seventh flip-flops, the first end of the sixth flip-flop and each seventh flip-flop is connected with the output end of the first flip-flop module, the second end of the sixth flip-flop is connected with the third end of the sixth flip-flop, the second end of each seventh flip-flop is used for accessing the second comparison result, the third end of each seventh flip-flop is connected with the sixth end of the previous seventh flip-flop or the sixth flip-flop, the fourth end of the sixth flip-flop and each seventh flip-flop is used for accessing the sample-and-hold signal, and the sixth end of each seventh flip-flop is also connected with the input end of the digital logic gate module, the second end of each seventh flip-flop is used for storing the second comparison result according to the comparator latch signal, and the sixth end of each seventh flip-flop is used for generating the second interface output signal.

[0047] With reference to Figure 2 , further as an optional implementation, the second flip-flop module further includes an eighth flip-flop, the first end of the eighth flip-flop is connected with the output end of the first flip-flop module, the second end of the eighth flip-flop is used for accessing the second comparison result, the third end of the eighth flip-flop is connected with the sixth end of the seventh flip-flop, the fourth end of the eighth flip-flop is used for accessing the system signal, the sixth end of the eighth flip-flop is connected with the input end of the digital logic gate module, the second end of the eighth flip-flop is used for storing the second comparison result according to the comparator latch signal, and the sixth end of the eighth flip-flop is used for generating the second interface output signal.

[0048] In some optional embodiments, as Figure 2As shown, the sixth flip-flop is a D flip-flop DFF21, the seventh flip-flop includes D flip-flops DFF22, DFF23, DFF24, DFF25, DFF26, DFF27, DFF28, and DFF29, and the eighth flip-flop is a D flip-flop DFF30.

[0049] Specifically, the sample-and-hold signal CK_SH is connected to the fourth end (RN end) of the D flip-flops DFF29-DFF21, and the system signal SYS is connected to the fourth end (RN end) of the D flip-flop DFF30. The first ends (SN ends) of the D flip-flops DFF30-DFF21 are respectively connected to the fifth ends (QN ends) of the D flip-flops DFF10-DFF1 in the first flip-flop module, and the connection lines are named SC<9>-SC<0>, i.e., the comparator latch signals output by the first flip-flop module are received. The second comparison result DCOMP_Q is simultaneously connected to the second ends (D ends) of the D flip-flops DFF30-DFF22. The sixth ends (Q ends) of the D flip-flops DFF30-DFF22 are connected to the input ends of the digital logic gate module, and the connection lines are named B<8>-B<0>, i.e., the second interface output signals are output to the digital logic gate module. The sixth end (Q end) of the D flip-flop DFF21 is connected to the third end (CK end) of the D flip-flop DFF22, and the second end (D end) of the D flip-flop DFF21 is connected to the third end (CK end) of the D flip-flop DFF21.

[0050] Reference Figure 2 As a further optional implementation, the third flip-flop module includes a plurality of ninth flip-flops, the first end of each ninth flip-flop is used to access the system signal, the second end of each ninth flip-flop is used to access the power supply, the third end of each ninth flip-flop is connected to the output end of each first flip-flop module, the fourth end of each ninth flip-flop is used to access the sample-and-hold signal, the sixth end of each ninth flip-flop is connected to the input end of the digital logic gate module, the third end of the ninth flip-flop is used to indicate the current conversion position according to the first output signal, and the sixth end of the ninth flip-flop is used to generate a third output signal.

[0051] In some optional embodiments, as shown in Figure 2 The ninth flip-flop includes D flip-flops DFF31, DFF32, DFF33, DFF34, DFF35, DFF36, DFF37, DFF38, and DFF39.

[0052] Specifically, the power supply VDD is connected to the second end (D end) of the D flip-flop DFF39-DFF31, the sampling and holding signal CK_SH is connected to the fourth end (RN end) of the D flip-flop DFF39-DFF31, and the system signal SYS is connected to the first end (SN end) of the D flip-flop DFF39-DFF31. The sixth end (Q end) of the D flip-flop DFF39-DFF31 is connected to the input end of the digital logic gate module, and the wiring name is CC<8>-CC<0>, that is, the third output signal is output to the digital logic gate module. The third end (CK end) of the D flip-flop DFF39-DFF31 is connected to the sixth end (Q end) of the D flip-flop DFF9-DFF1 in the first flip-flop module, and the wiring name is C<8>-C<0>, that is, the first output signal output by the first flip-flop module is input.

[0053] With reference to Figure 2 As a further optional embodiment, the digital logic gate module includes a plurality of first NAND gates, second NAND gates, first AND gates, second AND gates, and first NOT gates. The output ends of the second flip-flop module and the third flip-flop module are connected to the input ends of the first NAND gates, the output ends of the second flip-flop module and the third flip-flop module are connected to the input ends of the second NAND gates, the output ends of the second flip-flop module and the third flip-flop module are connected to the input ends of the first AND gates, the output ends of the second flip-flop module and the third flip-flop module are connected to the input ends of the second AND gates, the output ends of the third flip-flop module are connected to the input ends of the first NOT gates, the output ends of the first NAND gates, the second NAND gates, the first AND gates, the second AND gates, and the first NOT gates are connected to the input ends of the backplane control switch module, the first NAND gates and the second AND gates are used to obtain switch control signals according to the third output signal and the first interface output signal, the second NAND gates and the first AND gates are used to obtain switch control signals according to the third output signal and the second interface output signal, and the first NOT gates are used to obtain switch control signals according to the third output signal.

[0054] In some optional embodiments, as Figure 2As shown, the first NAND gate includes NAND gate NAND1, NAND gate NAND2, NAND gate NAND3, NAND gate NAND4, NAND gate NAND5, NAND gate NAND6, NAND gate NAND7, NAND gate NAND8, and NAND gate NAND9; the second NAND gate includes NAND gate NAND10, NAND gate NAND11, NAND gate NAND12, NAND gate NAND13, NAND gate NAND14, NAND gate NAND15, NAND gate NAND16, NAND gate NAND17, and NAND gate NAND18; the first AND gate includes AND gate AND1, AND gate AND2, AND gate AND3, AND gate AND4, AND gate AND5, AND gate AND6, AND gate AND7, AND gate AND8, and AND gate AND9; the second AND gate includes AND gate AND10, AND gate AND11, AND gate AND12, AND gate AND13, AND gate AND14, AND gate AND15, AND gate AND16, AND gate AND17, and AND gate AND18; and the first NOT gate includes NOT gate INV1, NOT gate INV2, NOT gate INV3, NOT gate INV4, NOT gate INV5, NOT gate INV6, NOT gate INV7, NOT gate INV8, and NOT gate INV9.

[0055] Specifically, the first input terminals of the NAND gates NAND1-NAND9 and the NAND gates NAND10-NAND18 are respectively connected to the sixth terminals (Q terminals) of the D flip-flops DFF39-DFF31, and are wired CC<8>-CC<0>, i.e., inputting the third output signals output by the third flip-flop module; the second input terminals of the NAND gates NAND1-NAND9 are respectively connected to the sixth terminals (Q terminals) of the D flip-flops DFF20-DFF12, and are wired A<8>-A<0>, i.e., inputting the first interface output signals output by the second flip-flop module; the second input terminals of the NAND gates NAND10-NAND18 are respectively connected to the sixth terminals (Q terminals) of the D flip-flops DFF30-DFF22, and are wired B<8>-B<0>, i.e., inputting the second interface output signals output by the second flip-flop module; the output terminals of the NAND gates NAND1-NAND9 are connected to the input terminals of the backplane control switch module, and are wired PSWP<8>-PSWP<0>; and the output terminals of the NAND gates NAND10-NAND18 are connected to the input terminals of the backplane control switch module, and are wired NSWP<8>-NSWP<0>.

[0056] The first input terminals of AND gates AND1-AND9 and AND gates AND10-AND18 are connected to the sixth terminal (Q terminal) of D flip-flops DFF39-DFF31, respectively, with the wiring name CC. <8> -CC <0> That is, the third output signal of the input third flip-flop module; the second input terminals of AND gates AND1-AND9 are respectively connected to the sixth terminal (Q terminal) of D flip-flops DFF30-DFF22, and the wiring name is B. <8> -B <0> That is, the second interface output signal of the input second flip-flop module; the second input terminals of AND gates AND10-AND18 are respectively connected to the sixth terminal (Q terminal) of D flip-flops DFF20-DFF12, and the wiring name is A. <8> -A <0> That is, the first interface output signal of the input second trigger module; the output terminals of AND gates AND1-AND9 are connected to the input terminals of the base plate control switch module, and the wiring name is PSWN. <8> -PSWN <0> The output terminals of AND gates AND10-AND18 are connected to the input terminals of the base plate control switch module, with the wiring name NSWN. <8> -NSWN <0> .

[0057] The input terminals of NOT gates INV1-INV9 are connected to the sixth terminal (Q terminal) of D flip-flops DFF39-DFF31, with the wiring name CC. <8> -CC <0> This refers to the third output signal from the input third trigger module; the output terminals of NOT gates INV1-INV9 are connected to the input terminals of the baseboard control switch module, with the wiring name SWCM. <8> -SWCM <0> .

[0058] Furthermore, such as Figure 2 As shown, the baseboard control switch module includes MOSFETs M1-M54. Figure 2The structure shown in the figure is described, the positive reference voltage VREFP is connected to the drain of MOS transistor M1, MOS transistor M25, MOS transistor M28 and MOS transistor M52 at the same time; the negative reference voltage VREFN is connected to the source of MOS transistor M2, MOS transistor M26, MOS transistor M29 and MOS transistor M53 at the same time; the common mode voltage VCM is connected to the source of MOS transistor M3, MOS transistor M27, MOS transistor M30 and MOS transistor M54 at the same time. The source of MOS transistor M1 is connected to the drain of MOS transistor M2 and MOS transistor M3 at the same time, and an output point is arranged on the wire, which is used to output CSP<8>; the source of MOS transistor M25 is connected to the drain of MOS transistor M26 and MOS transistor M27 at the same time, and an output point is arranged on the wire, which is used to output CSP<0>; the source of MOS transistor M28 is connected to the drain of MOS transistor M29 and MOS transistor M30 at the same time, and an output point is arranged on the wire, which is used to output CSN<8>; the source of MOS transistor M52 is connected to the drain of MOS transistor M53 and MOS transistor M54 at the same time, and an output point is arranged on the wire, which is used to output CSN<0>. The gate of each MOS transistor is connected to the output end of the digital logic gate, which is used to input the switch control signal output by the digital logic gate module (including PSWP<8>-PSWP<0> output by NAND1-NAND9, NSWP<8>-NSWP<0> output by NAND10-NAND18, PSWN<8>-PSWN<0> output by AND1-AND9, NSWN<8>-NSWN<0> output by AND10-AND18, SWCM<8>-SWCM<0> output by INV1-INV9), and the specific connection mode is as shown in the figure, which will not be repeated here. Figure 2

[0059] The structure of the low-power SAR ADC switch control circuit based on the common mode voltage of the embodiment of the application is described above, and the working principle thereof is described below.

[0060] When the SAR ADC circuit does not work, the system signal SYS is set to 0, and after the SAR ADC circuit starts to work, the system signal SYS is set to 1.

[0061] ​During the sampling phase, the sample-and-hold signal CK_SH is low, the output of the sixth terminal (Q terminal) of D flip-flop DFF10 is set high, and the fifth terminal (QN terminal) is set low. The outputs of the sixth terminals (Q terminals) of D flip-flops DFF9 to DFF1 are set low, and the fifth terminals (QN terminals) are set high. The first interface output signal A is output from the sixth terminal (Q terminal) of D flip-flops DFF19 to DFF12. <7> To A <0> It is also set to low level. The third output signal CC from D flip-flops DFF39 to DFF31 in the third flip-flop module. <8> -CC <0> It is set to low level. At this time, the outputs PSWP of NAND gates NAND1 to NAND gate 9 in the digital logic gate module are... <8> -PSWP <0> The output NSWP of NAND gates NAND10 to NAND18 is set to high. <8> -NSWP <0> The output PSWN of AND gates AND1 to AND9 is set to high level. <8> -PSWN <0> The output NSWN of AND gates AND10 to AND18 is set to low. <8> -NSWN <0> The outputs SWCM of NOT gates INV1 to INV9 are set to low level. <8> -SWCM <0> It is set to high level.

[0062] In the base plate control switch module, CSP <8> -CSP <0> Both are connected to the common-mode level VCM, CSN <8> -CSN <0> All are connected to the common-mode level VCM.

[0063] During the conversion phase, the sample-and-hold signal CK_SH changes from low to high. D flip-flops DFF10 to DFF1, via the external clock signal CLK, shift the high level of their sixth terminal (Q terminal) output to the right, and also shift the low level of their fifth terminal (QN terminal) to the right. This sequentially selects the first terminal (SN terminal) of D flip-flops DFF20 to DFF11, thus setting the sixth terminal (Q terminal) output of D flip-flops DFF20 to DFF11 to a high level sequentially. Starting with D flip-flop DFF19, the rising edge of the sixth terminal (Q terminal) output transitioning from low to high triggers the preceding D flip-flop, storing the first comparison result DCOMP_QN in the preceding flip-flop. Each comparison result serves as the input to the digital logic gate module, and the output of the digital logic gate module serves as the input to the baseboard control switch module, thereby connecting the capacitor baseboard to the corresponding reference level and controlling the establishment of the DAC. The detailed process is as follows:

[0064] The first output signals C<8>-C<0> outputted by the D flip-flops DFF9-DFF1 in the first flip-flop module rise from low to high in turn, the third output signals CC<8>-CC<0> outputted by the D flip-flops DFF39-DFF31 in the third flip-flop module also rise from low to high in turn, and just indicate the current conversion position.

[0065] When not converted to the nth bit, C <n>is set to low, CC <n>is set to low. At this time, the PSWP <n>is set to high, NSWP <n>is set to high, PSWN <n>is set to low, NSWN <n>SWCM is set to low <n>is set to high level. In the backplane control switch module, CSP <n>Connected to VCM, CSN <n>connected to the VCM.

[0066] When converting to the nth bit, C <n>is set to high, CC <n>Subsequently, C <n>is set to high level. At this time, the comparison result of the nth bit is delivered to the second flip-flop module. If the second comparison result DCOMP_Q = 1 and the first comparison result DCOMP_QN = 0, then A <n>B is set to low, B <n>PSWP in the digital logic gate module is set to high level <n>is set to high, NSWP <n>is set to low, PSWN <n>is set to high, NSWN <n>SWCM is set to low <n>is set to low level. In the backplane control switch module, CSP <n>connected to a negative reference voltage VREFN, CSN <n>is connected to the positive reference voltage VREFP. If the second comparison result DCOMP_Q = 0 and the first comparison result DCOMP_QN = 1, then A <n>is set to high, B <n>PSWP in the digital logic gate module is set to low level <n>is set to low, NSWP <n>is set to high, PSWN <n>is set to low, NSWN <n>SWCM is set to high <n>is set to low level. In the backplane control switch module, CSP <n>Connected to VREFP, CSN <n>is connected to VREFN.

[0067] It should be noted that the above operation ensures the correct re-establishment of the DAC, and the first output signal of the D flip-flop in the first flip-flop module is innovatively reused as the input signal of the third flip-flop module, which dynamically indicates the current conversion position, can greatly optimize the area and power consumption of the switch control circuit in the traditional SAR ADC, and simplifies the circuit design without sacrificing the circuit performance.

[0068] Further, for the differential structure, the first flip-flop module generating the comparator latch signal can be reused, and the digital logic gate module generating the switch control signal needs to be controlled by the second flip-flop module storing the comparator comparison result, Figure 3 The second comparison result DCOMP_Q and the first comparison result DCOMP_QN in the second comparator correspond to the output of the SAR ADC dynamic comparator, so the D flip-flop DFF20 to the D flip-flop DFF11 in the second flip-flop module store the first comparison result DCOMP_QN, and the D flip-flop DFF30 to the D flip-flop DFF21 store the second comparison result DCOMP_Q, and the results of the two are just opposite. The final conversion result only needs to output the second interface output signal B<8> to B<0> and the last bit of the second comparison result DCOMP_Q stored by the 10 D flip-flops controlled by the same clock from the D flip-flop DFF30 to the D flip-flop DFF22 in parallel, that is, a complete conversion process can be completed.

[0069] The structure and working principle of the low-power SAR ADC switch control circuit based on the common-mode level of the embodiment of the application are described above. It can be recognized that, compared with the traditional switch switching strategy, the first output signal in the first flip-flop module is innovatively reused as the input signal of the third flip-flop module, which dynamically indicates the current conversion position, can greatly optimize the area and power consumption of the switch control circuit in the traditional SAR ADC, and simplifies the circuit design without sacrificing the circuit performance.

[0070] To further verify the low-power characteristics of the switch control circuit proposed in the embodiment of the application, the effects of the embodiment of the application are further described in combination with experiments.

[0071] The embodiment of the application uses Cadence virtuoso software to realize two low-power SAR ADCs with a precision of 10 bits and a sampling rate of 16KS / s under a 0.18μm CMOS process using the traditional moving guess one logic and the switch control circuit proposed in the embodiment of the application, respectively, and the power supply voltage is 1.8V.

[0072] Experiment 1: Digital logic part current simulation experiment. As Figure 4 The simulation result of the current of the digital logic part of the low-power SAR ADC with 10-bit precision and 16KS / s sampling rate realized by using the switch control circuit proposed in the embodiment of the present application and the traditional moving guess one logic in a sampling-conversion cycle is shown. The green is the simulation result of the current of the digital logic part of the SAR ADC realized by using the traditional moving guess one logic in a sampling-conversion cycle, and the average current is 421.3nA and the average power consumption is 758.34nW. The blue is the simulation result of the current of the digital logic part of the SAR ADC realized by using the switch control circuit proposed in the embodiment of the present application in a sampling-conversion cycle, and the average current is 248.5nA and the average power consumption is 447.3nW. It can be seen that the power consumption of the digital logic part of the SAR ADC realized by using the switch control circuit proposed in the embodiment of the present application is greatly reduced compared with that of the SAR ADC realized by using the traditional moving guess one logic.

[0073] Experiment 2: total current simulation experiment. As shown in ​ The simulation result of the total current of the low-power SAR ADC with 10-bit precision and 16KS / s sampling rate realized by using the switch control circuit proposed in the embodiment of the present application and the traditional moving guess one logic in a sampling-conversion cycle is shown. The orange is the simulation result of the total current of the SAR ADC realized by using the traditional moving guess one logic in a sampling-conversion cycle, and the average current is 1.1μA and the average power consumption is 1.98μW. The red is the simulation result of the total current of the SAR ADC realized by using the switch control circuit proposed in the embodiment of the present application in a sampling-conversion cycle, and the average current is 484.1nA and the average power consumption is 871.38nW. It can be seen that the total power consumption of the SAR ADC realized by using the switch control circuit proposed in the embodiment of the present application is greatly reduced compared with that of the SAR ADC realized by using the traditional moving guess one logic.

[0074] Experiment 3: dynamic parameter test. The output of the two circuits is tested for dynamic parameters, and the test result shows that the SFDR of the SAR ADC realized by using the traditional moving guess one logic is 72.24dBc, and the effective number of bits can reach 9.81bits; the SFDR of the SAR ADC realized by using the switch control circuit proposed in the embodiment of the present application is 72.47dBc, and the effective number of bits can reach 9.82bits, which all meet the design requirements.

[0075] From the above experiments, it can be seen that the switch control circuit proposed in the embodiment of the present application can greatly optimize the area and power consumption of the switch control circuit in the traditional SAR ADC without sacrificing the performance of the circuit, simplify the design of the circuit, and can be widely applied to the field of low-power SAR ADC design technology.

[0076] In the above description of the present specification, the description referring to the terms "one embodiment", "another embodiment", or "certain embodiments" or the like means that the specific features, structures, materials or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present application. In the present specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Also, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in an appropriate manner.

[0077] Although the embodiments of the present application have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions, and alterations can be made hereto without departing from the principles and spirit of the application, and the scope of the present application is defined by the claims and their equivalents.

[0078] The above is a specific description of the preferred embodiments of the present application, but the present application is not limited to the embodiments, and those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present application, and these equivalent modifications or substitutions are included in the scope defined by the claims of the present application.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A low-power SAR ADC switching control circuit based on common-mode level, characterized in that, The system includes a first trigger module, a second trigger module, a third trigger module, a digital logic gate module, and a baseboard control switch module. The inputs of the second and third trigger modules are connected to the output of the first trigger module, and the outputs of the second and third trigger modules are connected to the input of the digital logic gate module. The output of the digital logic gate module is connected to the input of the baseboard control switch module. The first trigger module generates a comparator latch signal and a first output signal. The second trigger module stores the comparison result based on the comparator latch signal and generates a second output signal. The third trigger module indicates the current switching position based on the first output signal and generates a third output signal. The digital logic gate module obtains a switch control signal based on the second and third output signals. The baseboard control switch module connects the capacitor baseboard to the corresponding reference level based on the switch control signal.

2. The low-power SAR ADC switching control circuit based on common-mode level according to claim 1, characterized in that, The first flip-flop module includes a first flip-flop, a first terminal of which is used to connect to a sample-and-hold signal, a second terminal of which is grounded, a third terminal of which is used to connect to an external clock signal, a fourth terminal of which is used to connect to a system signal, and a fifth terminal of which is connected to the input terminal of the second flip-flop module. The fifth terminal of the first flip-flop is used to generate the comparator latch signal.

3. The low-power SAR ADC switching control circuit based on common-mode level according to claim 2, characterized in that, The first flip-flop module further includes a plurality of second flip-flops. The first terminal of each second flip-flop is used to connect to the system signal. The second terminal of each second flip-flop is connected to the sixth terminal of the preceding second flip-flop or the first flip-flop. The third terminal of each second flip-flop is used to connect to the external clock signal. The fourth terminal of each second flip-flop is used to connect to the sample-and-hold signal. The fifth terminal of each second flip-flop is connected to the input terminal of the second flip-flop module. The sixth terminal of each second flip-flop is also connected to the input terminal of the third flip-flop module. The fifth terminal of each second flip-flop is used to generate the comparator latch signal. The sixth terminal of each second flip-flop is used to generate the first output signal.

4. The low-power SAR ADC switching control circuit based on common-mode level according to claim 1, characterized in that, The second output signal includes the first interface output signal and the second interface output signal.

5. The low-power SAR ADC switching control circuit based on common-mode level according to claim 4, characterized in that, The comparison result includes a first comparison result. The second trigger module includes a third trigger and multiple fourth triggers. The first terminals of the third trigger and each of the fourth triggers are connected to the output terminal of the first trigger module. The second terminal of the third trigger is connected to the third terminal of the third trigger. The second terminal of each of the fourth triggers is used to receive the first comparison result. The third terminal of each of the fourth triggers is connected to the sixth terminal of the preceding fourth trigger or the third trigger. The fourth terminals of the third trigger and each of the fourth triggers are used to receive a sample-and-hold signal. The sixth terminal of each of the fourth triggers is also connected to the input terminal of the digital logic gate module. The second terminal of each of the fourth triggers is used to store the first comparison result according to the comparator latch signal. The sixth terminal of each of the fourth triggers is used to generate the first interface output signal.

6. The low-power SAR ADC switching control circuit based on common-mode level according to claim 5, characterized in that, The second trigger module further includes a fifth trigger. The first terminal of the fifth trigger is connected to the output terminal of the first trigger module. The second terminal of the fifth trigger is used to receive the first comparison result. The third terminal of the fifth trigger is connected to the sixth terminal of the fourth trigger. The fourth terminal of the fifth trigger is used to receive system signals. The sixth terminal of the fifth trigger is connected to the input terminal of the digital logic gate module. The second terminal of the fifth trigger is used to store the first comparison result according to the comparator latch signal. The sixth terminal of the fifth trigger is used to generate the first interface output signal.

7. The low-power SAR ADC switching control circuit based on common-mode level according to claim 4, characterized in that, The comparison result includes a second comparison result. The second trigger module includes a sixth trigger and multiple seventh triggers. The first terminals of the sixth trigger and each of the seventh triggers are connected to the output terminal of the first trigger module. The second terminal of the sixth trigger is connected to the third terminal of the sixth trigger. The second terminal of each of the seventh triggers is used to receive the second comparison result. The third terminal of each of the seventh triggers is connected to the sixth terminal of the previous seventh trigger or the sixth trigger. The fourth terminals of the sixth trigger and each of the seventh triggers are used to receive a sample-and-hold signal. The sixth terminal of each of the seventh triggers is also connected to the input terminal of the digital logic gate module. The second terminal of each of the seventh triggers is used to store the second comparison result according to the comparator latch signal. The sixth terminal of each of the seventh triggers is used to generate the second interface output signal.

8. The low-power SAR ADC switching control circuit based on common-mode level according to claim 7, characterized in that, The second trigger module further includes an eighth trigger. The first terminal of the eighth trigger is connected to the output terminal of the first trigger module. The second terminal of the eighth trigger is used to receive the second comparison result. The third terminal of the eighth trigger is connected to the sixth terminal of the seventh trigger. The fourth terminal of the eighth trigger is used to receive system signals. The sixth terminal of the eighth trigger is connected to the input terminal of the digital logic gate module. The second terminal of the eighth trigger is used to store the second comparison result according to the comparator latch signal. The sixth terminal of the eighth trigger is used to generate the second interface output signal.

9. The low-power SAR ADC switching control circuit based on common-mode level according to claim 1, characterized in that, The third flip-flop module includes multiple ninth flip-flops. The first terminal of each ninth flip-flop is used to connect to a system signal, the second terminal of each ninth flip-flop is used to connect to a power supply, the third terminal of each ninth flip-flop is connected to the output terminal of each first flip-flop module, the fourth terminal of each ninth flip-flop is used to connect to a sample-and-hold signal, and the sixth terminal of each ninth flip-flop is connected to the input terminal of the digital logic gate module. The third terminal of the ninth flip-flop is used to indicate the current switching position according to the first output signal, and the sixth terminal of the ninth flip-flop is used to generate the third output signal.

10. A low-power SAR ADC switching control circuit based on common-mode level according to claim 4, characterized in that, The digital logic gate module includes multiple first NAND gates, second NAND gates, first AND gates, second AND gates, and first NOT gates. The outputs of the second flip-flop module and the third flip-flop module are connected to the inputs of each first NAND gate, the second flip-flop module and the third flip-flop module are connected to the inputs of each second NAND gate, the second flip-flop module and the third flip-flop module are connected to the inputs of each first AND gate, the third flip-flop module and the third flip-flop module are connected to the inputs of each second AND gate, and the third flip-flop module is connected to the inputs of each first NOT gate. The outputs of each first NAND gate, each second NAND gate, each first AND gate, each second AND gate, and each first NOT gate are all connected to the input of the baseboard control switch module. Each first NAND gate and each second AND gate is used to obtain the switch control signal based on the third output signal and the first interface output signal. Each second NAND gate and each first AND gate is used to obtain the switch control signal based on the third output signal and the second interface output signal. Each first NOT gate is used to obtain the switch control signal based on the third output signal.

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