Level shifter

Abstract

The embodiment of the invention provides a level shifter. An input circuit receives an input signal operated in a first level. A second level supplied by a second level line coupled to a pull-up circuit is higher than the first level, and a first coupling point of the pull-up circuit and the input circuit is used as an output end of the level shifter. An acceleration circuit is coupled to the first coupling point to accelerate the low-to-high transition of the output terminal. An acceleration controller coupled to the acceleration circuit includes a plurality of pulse generating transistors having first sides connected in series. Particularly, in the pulse generation transistors connected in series at the first side, different transistors respectively receive driving signals with time differences so as to be instantly conducted, so that the acceleration circuit is enabled in a pulse mode, and the driving signals received by the different transistors are from the input signals.

Description

Technical Field

[0001] The present invention relates to the field of level conversion, and in particular to a level converter (levelshifter) for high-speed level conversion. Background Art

[0002] A level shifter generally has an input circuit and a pull-up circuit superimposed on the input circuit. The input circuit is used to receive an input signal operating within a first level. The pull-up circuit is further connected to a second level higher than the first level to pull up the level of the input signal to form an output signal.

[0003] The input circuit is also responsible for the high-to-low transition ('1'→'0') of the output signal. In order to make the high-to-low transition ('1'→'0') of the output signal smooth, the driving capability of the pull-up circuit cannot be too strong. However, this also results in the low-to-high transition ('0'→'1') not being immediate enough.

[0004] How to provide a high-speed level converter is an important issue in the art. Summary of the invention

[0005] The present invention provides a high-speed level shifter.

[0006] A level converter implemented according to an embodiment of the present invention includes an input circuit, a pull-up circuit, an acceleration circuit, and an acceleration controller. The input circuit receives an input signal operating within a first voltage level. The pull-up circuit is coupled between a second voltage line and the input circuit; wherein a second voltage level supplied by the second voltage line is higher than the first voltage level, and a first coupling point between the pull-up circuit and the input circuit is used as an output terminal of the level converter. The acceleration circuit is coupled to the first coupling point to accelerate the low-to-high transition of the output terminal. The acceleration controller is coupled to the acceleration circuit and includes a plurality of pulse generating transistors connected in series on a first side. Among the pulse generating transistors connected in series on the first side, different transistors receive driving signals with time differences respectively to be turned on instantly, so that the acceleration circuit is pulse-enabled. The level converter provides a driving signal to the pulse generating transistors connected in series on the first side according to the input signal.

[0007] With such a design, the pulsed enabling of the acceleration circuit does not involve complicated logic operations and the operation is quite instant. The present invention does not use any NAND, NOR, AND, OR logic gates in the acceleration controller.

[0008] In one embodiment, the acceleration circuit includes a first current mirror, which provides a first acceleration current to the first coupling point in a pulsed manner under the control of the acceleration controller. The first current mirror may include a first current mirror transistor of a P-type channel and a second current mirror transistor. A gate of the first current mirror transistor is coupled to a drain of the first current mirror transistor and a gate of the second current mirror transistor. A source of the first current mirror transistor is coupled to the second level line. The first current mirror transistor is coupled to the pulse generating transistor connected in series on the first side with its own drain. A source of the second current mirror transistor is coupled to the second level line. The second current mirror transistor provides the first acceleration current to the first coupling point via a drain.

[0009] In one embodiment, the acceleration controller further includes a first delay circuit for receiving an inverted input signal that is the inverse of the input signal to generate a delayed inverted input signal. The pulse generating transistor connected in series on the first side includes a first pulse generating transistor of an N-type channel and a second pulse generating transistor. The first pulse generating transistor has a source connected to ground and a gate for receiving the inverted input signal. The second pulse generating transistor has a source coupled to a drain of the first pulse generating transistor, a gate for receiving the delayed inverted input signal from the first delay circuit, and a drain coupled to the drain of the first current mirror transistor. In particular, the acceleration controller does not include any NAND, NOR, AND, or OR logic gates.

[0010] In one embodiment, the level converter includes a leakage protection circuit. When the acceleration circuit is disabled, the leakage protection circuit couples the gate of the first current mirror transistor and the gate of the second current mirror transistor to the second level line. In this way, the first current mirror is actually turned off, effectively avoiding leakage.

[0011] In one embodiment, the gate of the first current mirror transistor is coupled to the gate of the second current mirror transistor and the drain of the first current mirror transistor via a first resistance element. This design enables the first current mirror to respond more quickly and provide the first acceleration current.

[0012] The same design can be implemented on the inverting output of the level converter. In this way, the low-to-high transition of the inverting output can also be effectively accelerated and save power. The output of the level converter can immediately and power-savingly present a high-to-low transition.

[0013] The following is a detailed description of the present invention with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 FIG. 1 is a block diagram of a level shifter 100 implemented according to an embodiment of the present invention.

[0015] Figure 2 FIG. 2 is a diagram illustrating a detailed circuit of a level converter 200 according to an embodiment of the present invention.

[0016] [Explanation of symbols]

[0017] 100, 200: Level converter

[0018] 102: Input circuit

[0019] 104: Pull-up circuit

[0020] 106: Acceleration Circuit

[0021] 108: Acceleration controller

[0022] DU1, DU2: Delay circuit

[0023] IN: Input signal

[0024] INB: Inverting input signal

[0025] INB_D: Delayed inverting input signal

[0026] Inv1, Inv2: Inverters

[0027] N1, N2: N-type channel transistors

[0028] NAUX1, NAUX2: Pulse generating transistors

[0029] NAUX3, NAUX4: Pulse generating transistors

[0030] OUT: output terminal / output signal

[0031] P1, P2: P-type channel transistors

[0032] PAUX1, PAUX2, PAUX3, PAUX4: Current mirror transistors

[0033] PHOLD1, PHOLD2: Leakage protection transistor

[0034] R1, R2: resistance components

[0035] t1, t2: first and second coupling points

[0036] VCCH: Second level

[0037] VCCL: First level DETAILED DESCRIPTION

[0038] The following description lists various embodiments of the present invention, but is not intended to limit the content of the present invention. The actual scope of the invention should be defined in accordance with the claims of the present invention.

[0039] Figure 1 1 is a block diagram illustrating a level shifter 100 implemented according to an embodiment of the present invention, for converting an input signal IN operated at a first level (hereinafter labeled VCCL) into an output signal OUT operated at a higher second level (hereinafter labeled VCCH, greater than VCCL).

[0040] The level converter 100 includes an input circuit 102, a pull-up circuit 104, an acceleration circuit 106, and an acceleration controller 108. The input circuit 102 receives the input signal IN operating within the first level VCCL, and the first level variation range can be 0 to VCCL volts. The pull-up circuit 104 is coupled between a second level line (supplying the second level VCCH) and the input circuit 102. A first coupling point t1 between the pull-up circuit 104 and the input circuit 102 is used as an output terminal of the level converter (with the same number as the output signal OUT output). The input signal IN is activated by the pull-up circuit 104 through the input circuit 102 to pull up the output terminal OUT to a high state. The low state of the output signal OUT is formed by pulling down the input circuit 102. Under the conventional design, in order for the transistor of the input circuit 102 to smoothly pull down the level of the output terminal OUT, the pull-up capability of the transistor of the pull-up circuit 104 cannot be too strong. Therefore, the output terminal OUT of the conventional level converter has a slow transition speed from low to high.

[0041] The present invention couples the first coupling point t1 with an acceleration circuit 106 to accelerate the low-to-high transition of the output terminal OUT (e.g., 0V transition to VCCH). In particular, the acceleration controller 108 coupled to the acceleration circuit 106 includes a plurality of first pulse generating transistors (shown as NAUX1 and NAUX2) connected in series, wherein different transistors receive driving signals with time differences (e.g., NAUX1 is driven by the inverted input signal INB, and NAUX2 is driven by the delayed inverted input signal INB_D) to be turned on instantaneously, so that the acceleration circuit 106 is pulse-enabled (i.e., the acceleration circuit 106 is turned on instantaneously and then returns to an open circuit state). The transistors NAUX1 and NAUX2 can also be driven by other signals that vary with the corresponding input signal IN. Even more, the number of transistors connected in series can be greater than two. The driving signal of the acceleration controller 108 implemented by the serially connected transistors (such as NAUX1 and NAUX2) can be quite simple, and can be obtained without processing the input signal IN with complex logic operations. For example, in one embodiment, the acceleration controller 108 does not include any NAND, NOR, AND, OR logic gates. In this way, the pulsed enable of the acceleration circuit 106 does not involve complex logic operations, and the operation is quite instant. The output signal OUT can be instantly changed from 0V to VCCH in response to the low-to-high transition of the input signal IN.

[0042] The same design can be implemented on the inverting output terminal of the level converter 100 (hereinafter the same as the inverting output signal OUTB outputted therefrom). In this way, the low-to-high transition of the inverting output terminal OUTB can also be effectively accelerated. Taking the pull-up circuit implemented by the staggered transistors as an example, the output terminal OUT of the level converter 100 can instantly complete the high-to-low transition corresponding to the high-speed low-to-high transition of the inverting output terminal OUTB. The level converter of the present invention has an extremely fast transition speed.

[0043] Figure 2 A detailed circuit diagram of a level converter 200 is illustrated according to an embodiment of the present invention. N-channel transistors (such as NMOS) N1 and N2 form an input circuit, and receive the input signal IN of the first level VCCL operation and the inverted input signal INB at the gate respectively; the input signal IN and the inverted input signal INB can vary in the range of 0 to VCCL volts. P-channel transistors (such as PMOS) P1 and P2 are cross-connected to form a pull-up circuit, which is coupled to the input circuit at a first coupling point t1 and a second coupling point t2. The first coupling point t1 and the second coupling point t2 are used as the output terminal OUT and the inverted output terminal OUTB of the level converter 200, respectively, to generate the output signal OUT of the second level VCCH operation and the inverted output signal OUTB; the output signal OUT and the inverted output signal OUTB can vary in the range of 0 to VCCH volts.

[0044] Figure 2 A first current mirror is formed by a first current mirror transistor PAUX1 of a P-type channel and a second current mirror transistor PAUX2, a second current mirror is formed by a third current mirror transistor PAUX3 of a P-type channel and a fourth current mirror transistor PAUX4, and an acceleration circuit is implemented by the first current mirror and the second current mirror. The first current mirror (including PAUX1 and PAUX2) provides a first acceleration current to the first coupling point t1 to accelerate the low-to-high transition of the output terminal OUT. The second current mirror (including PAUX3 and PAUX4) provides a second acceleration current to the second coupling point t2 to accelerate the low-to-high transition of the inverting output terminal OUTB. The present invention enables the first current mirror (PAUX1 and PAUX2) by pulse-conducting a plurality of pulse generating transistors (NAUX1 and NAUX2) connected in series, and enables the second current mirror (PAUX3 and PAUX4) by pulse-conducting a plurality of pulse generating transistors (NAUX3 and NAUX4) connected in series. The circuit that provides pulse control does not include any NAND, NOR, AND, or OR logic gates at all, and the operation is quite instantaneous.

[0045] Figure 2In the embodiment, the design of the corresponding first current mirror (PAUX1 and PAUX2) of the acceleration controller includes not only the first pulse generating transistor NAUX1 of the N-type channel and the second pulse generating transistor NAUX2, but also a first delay circuit DU1. First, the circuit details of the first current mirror (PAUX1 and PAUX2) are described. A gate of the first current mirror transistor PAUX1 is coupled to a drain of the first current mirror transistor PAUX1 and a gate of the second current mirror transistor PAUX2. A source of the first current mirror transistor PAUX1 is coupled to the second level line VCCH. The first current mirror transistor PAUX1 is coupled to the pulse generating transistors NAUX1 and NAUX2 connected in series with the drain. A source of the second current mirror transistor PAUX2 is coupled to the second level line VCCH. The second current mirror transistor PAUX2 provides the first acceleration current to the first coupling point t1 through a drain. Next, the corresponding acceleration control circuit is described. The first delay circuit DU1 receives an inverted input signal INB which is the inverted input signal IN to generate a delayed inverted input signal INB_D. The first pulse generating transistor NAUX1 has a source connected to the ground and a gate receiving the inverted input signal INB. The second pulse generating transistor NAUX2 has a source coupled to a drain of the first pulse generating transistor NAUX1, a gate receiving the delayed inverted input signal INB_D from the first delay circuit DU1, and a drain coupled to the drain of the first current mirror transistor PAUX1.

[0046] In particular, the gate of the first current mirror transistor PAUX1 is coupled to the gate of the second current mirror transistor PAUX2 and the drain of the first current mirror transistor PAUX1 via a first resistance element R1. The first resistance element R1 can also be replaced by other high resistance elements, so that its low-pass effect effectively suppresses the diode current of the first current mirror transistor PAUX1, so that the first current mirror (PAUX1 and PAUX2) can provide the first acceleration current to the first coupling point t1 more immediately, accelerating the low-to-high transition of the output terminal OUT.

[0047] Figure 2A leakage protection circuit is further provided for the acceleration circuit. In the figure, a first leakage protection transistor PHOLD1 of a P-type channel and a first inverter Inv1 are used to implement leakage protection of the first current mirror (PAUX1 and PAUX2). The first leakage protection transistor PHOLD1 has a source coupled to the second level line VCCH, and a drain coupled to the gate of the first current mirror transistor PAUX1. The first inverter Inv1 has an input terminal coupled to the drain of the first current mirror transistor PAUX1, and an output terminal coupled to a gate of the first leakage protection transistor PHOLD1. When the first current mirror (PAUX1 and PAUX2) is disabled, the serially connected pulse generating transistors NAUX1 and NAUX2 are disconnected, the drain of the first current mirror transistor PAUX1 is pulled up, and the inverter Inv1 generates a low state signal to turn on the first leakage protection transistor PHOLD1 to couple the gate of the first current mirror transistor PAUX1 and the gate of the second current mirror transistor PAUX2 to the second level line VCCH. In this way, the first current mirror (PAUX1 and PAUX2) is truly turned off, effectively suppressing leakage.

[0048] The inverting output terminal OUTB can have the same low-to-high state transition acceleration design. The following describes the relevant circuit details for the inverting output terminal OUTB.

[0049] Figure 2In the design of the corresponding second current mirror (PAUX3 and PAUX4) of the acceleration controller, in addition to including the third pulse generating transistor NAUX3 and the fourth pulse generating transistor NAUX4 of the N-type channel, also includes a second delay circuit DU2. First, the circuit details of the second current mirror (PAUX3 and PAUX4) are described. A gate of the third current mirror transistor PAUX3 is coupled to a drain of the third current mirror transistor PAUX3 and a gate of the fourth current mirror transistor PAUX4. A source of the third current mirror transistor PAUX3 is coupled to the second level line VCCH. The third current mirror transistor PAUX3 is coupled to the pulse generating transistors NAUX3 and NAUX4 connected in series with the drain. A source of the fourth current mirror transistor PAUX4 is coupled to the second level line VCCH. The fourth current mirror transistor PAUX4 provides the second acceleration current to the second coupling point t2 through a drain. Then, the corresponding acceleration control circuit is described. The second delay circuit DU2 receives the input signal IN to generate a delayed input signal IN_D. The third pulse generating transistor NAUX3 has a source connected to the ground and a gate receiving the input signal IN. The fourth pulse generating transistor NAUX4 has a source coupled to a drain of the third pulse generating transistor NAUX3, a gate receiving the delayed input signal IN_D from the second delay circuit DU2, and a drain coupled to the drain of the third current mirror transistor PAUX3.

[0050] In particular, the gate of the third current mirror transistor PAUX3 is coupled to the gate of the fourth current mirror transistor PAUX4 and the drain of the third current mirror transistor PAUX3 via a second resistance element R2. The second resistance element R2 can also be replaced by other high resistance elements, so that its low-pass effect effectively suppresses the diode current of the third current mirror transistor PAUX3, so that the second current mirror (PAUX3 and PAUX4) can provide the second acceleration current to the second coupling point t2 more immediately, accelerating the low-to-high transition of the inverting output terminal OUTB.

[0051] Figure 2A second leakage protection transistor PHOLD2 of a P-type channel and a second inverter Inv2 are used to implement leakage protection of the second current mirror (PAUX3 and PAUX4). The second leakage protection transistor PHOLD2 has a source coupled to the second level line VCCH, and a drain coupled to the gate of the third current mirror transistor PAUX3. The second inverter Inv2 has an input terminal coupled to the drain of the third current mirror transistor PAUX3, and an output terminal coupled to a gate of the second leakage protection transistor PHOLD2. When the second current mirror (PAUX3 and PAUX4) is disabled, the serially connected pulse generating transistors NAUX3 and NAUX4 are disconnected, the drain of the third current mirror transistor PAUX3 is pulled up, and the second inverter Inv2 generates a low state signal to turn on the second leakage protection transistor PHOLD2 to couple the gate of the third current mirror transistor PAUX3 and the gate of the fourth current mirror transistor PAUX4 to the second level line VCCH. In this way, the second current mirror (PAUX3 and PAUX4) is truly turned off, effectively suppressing leakage.

[0052] For the convenience of explanation, the string pulse generating transistors NAUX1 and NAUX2 used in the above output terminal OUT transition acceleration control can be understood as the first side pulse generating transistors, and the string pulse generating transistors NAUX3 and NAUX4 used in the inverting output terminal OUTB transition acceleration control can be understood as the second side pulse generating transistors.

[0053] The above circuit may have many variations. For example, the input circuit and pull-up circuit may have many improvements. The acceleration circuit and leakage protection circuit may have many variations. The acceleration controller may also be fine-tuned.

[0054] However, any pulsed enable of a transition acceleration circuit of a level converter using serially connected transistors belongs to the technical field of the present invention. In particular, in one embodiment, the acceleration controller configured for the transition acceleration does not use any NAND, NOR, AND, OR logic gates.

[0055] Although the present invention has been disclosed as above in terms of preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the claims of the present invention.

Claims

1. A level converter, characterized in that: include: An input circuit receives an input signal operating within a first level; a pull-up circuit coupled between a second level line and the input circuit, wherein a second level supplied by the second level line is higher than the first level, and a first coupling point between the pull-up circuit and the input circuit is used as an output terminal of the level converter; an acceleration circuit coupled to the first coupling point to accelerate the low-to-high transition of the output terminal; and An acceleration controller coupled to the acceleration circuit includes a plurality of pulse generating transistors connected in series on a first side, wherein different transistors among the pulse generating transistors connected in series on the first side respectively receive first driving signals with a time difference, so that the acceleration circuit is pulse-enabled, and the first driving signals received by different transistors are derived from the input signal.

2. The level converter according to claim 1, wherein: The acceleration circuit includes a first current mirror, the first current mirror is controlled by the acceleration controller to provide a first acceleration current to the first coupling point in a pulsed manner, and the first current mirror includes a first current mirror transistor of a P-type channel and a second current mirror transistor; A gate of the first current mirror transistor is coupled to a drain of the first current mirror transistor and a gate of the second current mirror transistor; A source of the first current mirror transistor is coupled to the second level line; The first current mirror transistor is coupled to the pulse generating transistor connected in series on the first side through its drain; A source of the second current mirror transistor is coupled to the second level line; and The first acceleration current is provided to the first coupling point through a drain of the second current mirror transistor.

3. The level converter according to claim 2, wherein: The acceleration controller further includes a first delay circuit, receiving an inverted input signal which is an inverted version of the input signal, to generate a delayed inverted input signal; The pulse generating transistors connected in series on the first side include a first pulse generating transistor with an N-type channel and a second pulse generating transistor; The first pulse generating transistor has a source connected to the ground and a gate receiving the inverted input signal; and The second pulse generating transistor has a source coupled to a drain of the first pulse generating transistor, a gate receiving the delayed inverted input signal from the first delay circuit, and a drain coupled to the drain of the first current mirror transistor.

4. The level converter according to claim 2, wherein: Also includes: A leakage protection circuit couples the gate of the first current mirror transistor and the gate of the second current mirror transistor to the second level line when the acceleration circuit is disabled.

5. The level converter according to claim 4, characterized in that: The leakage protection circuit comprises: a first leakage protection transistor of a P-type channel, having a source coupled to the second level line, and a drain coupled to the gate of the first current mirror transistor; and A first inverter has an input terminal coupled to the drain of the first current mirror transistor and an output terminal coupled to a gate of the first leakage protection transistor.

6. The level converter according to claim 2, wherein: The gate of the first current mirror transistor is coupled to the gate of the second current mirror transistor and the drain of the first current mirror transistor via a first resistance element.

7. The level converter according to claim 2, wherein: A second coupling point between the pull-up circuit and the input circuit is used as an inverting output terminal of the level converter; The acceleration circuit further includes a second current mirror, which is controlled by the acceleration controller to provide a second acceleration current to the second coupling point in a pulsed manner to accelerate the low-to-high transition of the inverting output terminal; and The acceleration controller further includes a plurality of pulse generating transistors connected in series on a second side, wherein different transistors of the pulse generating transistors connected in series on the second side receive second driving signals with time differences, so that the second current mirror is pulse-enabled; The level converter provides the second driving signal to the pulse generating transistor connected in series on the second side according to the input signal; The second current mirror includes a third current mirror transistor of a P-type channel and a fourth current mirror transistor; A gate of the third current mirror transistor is coupled to a drain of the third current mirror transistor and a gate of the fourth current mirror transistor; A source of the third current mirror transistor is coupled to the second level line; The third current mirror transistor is coupled to the pulse generating transistor connected in series on the second side through its drain; A source of the fourth current mirror transistor is coupled to the second level line; and The second acceleration current is provided to the second coupling point through a drain of the fourth current mirror transistor.

8. The level converter according to claim 7, wherein: The acceleration controller further includes a second delay circuit, receiving the input signal to generate a delayed input signal; The pulse generating transistors connected in series on the second side include a third pulse generating transistor of an N-type channel and a fourth pulse generating transistor; The third pulse generating transistor has a source connected to the ground and a gate receiving the input signal; and The fourth pulse generating transistor has a source coupled to a drain of the third pulse generating transistor, a gate receiving the delayed input signal from the second delay circuit, and a drain coupled to the drain of the third current mirror transistor.

9. The level converter according to claim 7, characterized in that: Also includes: a leakage protection circuit, coupling the gate of the third current mirror transistor and the gate of the fourth current mirror transistor to the second level line when the acceleration circuit is disabled; Wherein, the leakage protection circuit comprises: a second leakage protection transistor of a P-type channel, having a source coupled to the second level line, and a drain coupled to the gate of the third current mirror transistor; and A second inverter has an input terminal coupled to the drain of the third current mirror transistor and an output terminal coupled to a gate of the second leakage protection transistor.

10. The level converter according to claim 7, wherein: The gate of the third current mirror transistor is coupled to the gate of the fourth current mirror transistor and the drain of the third current mirror transistor via a second resistance element.

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