System and method for generating signal for analog-to-digital converter (ADC) calibration

Abstract

The disclosure relates to a system and method for generating a signal for analog-to-digital converter (ADC) calibration. An apparatus may include an oscillator and a driver. The oscillator may be coupled to circuitry that provides calibration of the oscillator. The oscillator may receive a first signal from the circuitry that causes the oscillator to generate a second signal having a first frequency to be used for calibration of an analog-to-digital converter (ADC). The driver may be coupled to the oscillator and the ADC. The driver may receive the second signal from the oscillator. The driver may receive a third signal indicative of a magnitude to be applied to the second signal. The driver may provide an output signal having the first frequency and amplitude to the ADC based at least on the second signal and the third signal.

Description

Technical Field

[0001] The present disclosure relates generally to systems and methods for controlling an analog-to-digital converter (ADC), and more particularly to efficiently generating signals for ADC calibration. Background Art

[0002] In data communication systems (e.g., narrowband communication systems such as 5G wireless systems), high-performance and high-resolution ADCs can be used to capture radio frequency (RF) signals and convert them into digital signals. With the expansion of complementary metal oxide semiconductor (CMOS) technology, time interleaving of multiple unit ADCs (e.g., successive approximation (SAR) ADCs) can achieve low power and compact area. Time-interleaved ADCs can also achieve a wide range of data sampling frequencies, such as tens of GHz. Time-interleaved ADCs can have a wide variety of applications in modern high-performance data communication and processing systems, including but not limited to wireless systems, base stations, network switches, serializer / deserializer (SERDES) PHYs, optical receivers, data acquisition systems, sensors, etc. For example, compared with receivers based on analog mixers, RF direct sampling receivers implemented with time-interleaved ADCs can make low-power and high-performance data communication systems (e.g., wireless systems, 5G wireless base stations, or electrical and optical links) easier to implement. Time-interleaved ADCs may be subject to inherent interleaving errors, such as direct current (DC) offsets and / or gain and skew errors between unit ADCs. These errors can be calibrated using input signals before using the ADCs to process real-time data. However, it would be difficult to efficiently generate such input signals that would ensure sufficiently fast error detection and calibration convergence. Summary of the invention

[0003] In one aspect, the present disclosure provides a device comprising: an oscillator coupled to a circuit system that provides calibration of the oscillator, the oscillator being configured to receive a first signal from the circuit system, the first signal causing the oscillator to generate a second signal having a first frequency to be used for calibration of an analog-to-digital converter (ADC); and a driver coupled to the oscillator and the ADC, the driver being configured to: receive the second signal from the oscillator; receive a third signal indicating an amplitude to be applied to the second signal; and provide an output signal having the first frequency and the amplitude to the ADC based at least on the second signal and the third signal.

[0004] On the other hand, the present disclosure provides a circuit system comprising: a first circuit coupled to an oscillator and configured to: receive a signal indicating a first frequency to be used for calibration of an analog-to-digital converter (ADC), calibrate the frequency of the oscillator, and generate one or more first signals based at least on the signal and the frequency of the oscillator; and a second circuit coupled to the oscillator and configured to: receive the one or more first signals from the first circuit, and control the oscillator to generate a second signal having the first frequency based at least on the one or more first signals.

[0005] On the other hand, the present disclosure provides a method, comprising: receiving, by a first circuit coupled to an oscillator, a signal indicating a first frequency to be used for calibration of an analog-to-digital converter (ADC); calibrating, by the first circuit, the frequency of the oscillator; generating, by the first circuit, one or more first signals based at least on the signal and the frequency of the oscillator; receiving, by a second circuit coupled to the oscillator, the one or more first signals from the first circuit; and controlling, by the second circuit, the oscillator to generate a second signal having the first frequency based at least on the one or more first signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various objects, aspects, features and advantages of the present disclosure will become more apparent and better understood by reference to the detailed description in conjunction with the accompanying drawings, wherein the same reference symbols identify corresponding elements throughout. In the drawings, the same reference symbols generally indicate the same, functionally similar and / or structurally similar elements.

[0007] Figure 1 is a schematic block diagram of an example system for generating a signal for ADC calibration.

[0008] Figure 2 is a schematic block diagram of an example system for using an oscillator to generate a signal for ADC calibration according to an embodiment.

[0009] Figure 3 is a schematic block diagram of an example system for generating a signal for ADC calibration using a ring oscillator according to an embodiment.

[0010] Figure 4 is a graph showing simulation results of residual interleaving gain error with various calibration signal frequencies according to an embodiment.

[0011] Figure 5 is a schematic block diagram of an exemplary system for providing a signal to an ADC for ADC calibration according to an embodiment.

[0012] Figure 6 is a schematic block diagram of an example system for controlling a ring oscillator to adjust frequency for ADC calibration according to an embodiment.

[0013] Figure 7 is a schematic block diagram of an example system for calibrating the frequency of a ring oscillator for ADC calibration according to an embodiment.

[0014] Figure 8 is a flow chart showing a process of using an oscillator to generate a signal for ADC calibration according to an embodiment.

[0015] The details of various embodiments of the method and system are set forth in the accompanying drawings and the description below. DETAILED DESCRIPTION

[0016] The following disclosure provides many different embodiments or examples for implementing the different features of the provided inventive themes. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be restrictive. For example, in the following description, a first feature formed above or on a second feature may include an embodiment in which the first and second features are formed as direct contacts and may also include an embodiment in which an additional feature may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0017] Various embodiments disclosed herein relate to a device including an oscillator and a driver. In some embodiments, the oscillator may be a ring oscillator, which is any circuit or hardware that includes multiple amplifiers in a ring to produce an output that oscillates between two voltage levels. Each of the multiple amplifiers may be one of a buffer, an inverter, a NOT gate, a non-inverting amplifier. In some embodiments, the device may be implemented in an integrated circuit or chip. The oscillator may be coupled to a circuit system that provides calibration of the oscillator. The oscillator may be configured to receive a first signal from the circuit system, which causes the oscillator to generate a second signal having a first frequency to be used for calibration of an analog-to-digital converter (ADC). In some embodiments, the circuit system may include (1) hardware, one or more processors (e.g., a microprocessor), or a combination of hardware and / or one or more processors and software and / or firmware; or (2) a single component or a combination of multiple components. The ADC may be a time-interleaved ADC that can perform analog-to-digital conversion, a successive approximation (SAR) ADC, a delta-sigma ADC, a dual slope ADC, a pipelined ADC, a flash ADC, or any circuit, hardware, or any combination thereof. The driver may be coupled to the oscillator and the ADC. The driver may be configured to receive a second signal from the oscillator. The driver may be configured to receive a third signal indicating an amplitude to be applied to the second signal. The driver may be configured to provide an output signal having a first frequency and amplitude to the ADC based at least on the second signal and the third signal.

[0018] In some embodiments, the second signal may be a pair of complementary signals. In some embodiments, the complementary signal pair may have two signals that are 180 degrees out of phase with each other. In some embodiments, the driver may be configured to receive a fourth signal indicating the rise time and fall time to be applied to the second signal. The driver may be configured to provide an output signal having a first frequency, amplitude, rise time, and fall time to the ADC based at least in part on the second signal, the third signal, and the fourth signal. In some embodiments, the rise time of a signal (such as a voltage signal or a current signal) may be the time it takes for the signal to change from a specified low value to a specified high value. These values ​​may be expressed as a ratio or equivalently as a percentage relative to a given reference value, for example, 10% and 90% (or equivalently 0.1 and 0.9) of the amplitude of the signal or the height of the step function of the signal. In some embodiments, the fall time of a signal (such as a voltage signal or a current signal) may be the time it takes for the signal to change from a specified high value to a specified low value. These values ​​may be expressed as ratios or equivalently as percentages relative to a given reference value, for example 90% and 10% (or equivalently 0.9 and 0.1) of the amplitude of a signal or the height of a step function of a signal.

[0019] In some embodiments, the driver may include one or more amplifiers coupled to the oscillator and configured to amplify the second signal based on at least the third signal to generate an output signal. The driver may include one or more capacitors coupled to the output of the one or more amplifiers. The driver may be configured to provide the output signal to the ADC through the one or more capacitors. The driver may include one or more switches coupled to the output of the one or more amplifiers. The driver may be further configured to receive a fifth signal indicating enabling or disabling the driver, so that the driver is enabled during calibration of the ADC and disabled in response to the ADC being calibrated. The driver may be configured to turn on or off one or more switches according to the fifth signal.

[0020] In some embodiments, the ADC may receive one or more input signals through a first amplifier. The driver may be configured to turn off the first amplifier during calibration of the ADC and turn on the first amplifier in response to the ADC being calibrated. The driver may be configured to provide a sixth signal indicating enabling or disabling the first amplifier to the first amplifier, so that the first amplifier is disabled during calibration of the ADC and enabled in response to the ADC being calibrated. The driver may be configured to turn on or off the first amplifier according to the sixth signal. The ADC may further receive one or more input signals through a second amplifier having an impedance smaller than the impedance of the first amplifier. The driver may be configured to provide an output signal to the ADC through the second amplifier during calibration of the ADC. In other words, during calibration of the ADC, the driver may be configured to provide an output signal to a second amplifier having an impedance smaller than the impedance of the first amplifier, and the ADC may receive one or more input signals from the second amplifier.

[0021] Various embodiments disclosed herein relate to a circuit system including a first circuit coupled to an oscillator and a second circuit coupled to the oscillator. The first circuit may be configured to receive a signal indicating a first frequency to be used for calibration of an analog / digital converter (ADC). The first circuit may be configured to calibrate the frequency of the oscillator. The first circuit may be configured to generate one or more first signals based at least on the signal and the frequency of the oscillator. The second circuit may be configured to receive the one or more first signals from the first circuit. The second circuit may be configured to control the oscillator to generate a second signal having a first frequency based at least on the one or more first signals.

[0022] In some embodiments, the first circuit may include a controller, a first counter, and a second counter. The controller may be any circuit, hardware (e.g., a microprocessor), software, firmware, or any combination thereof that can use one or more control signals to control the first counter, the second counter, and the oscillator. The first counter may be configured to receive a first clock signal output from the oscillator. The second counter may be configured to receive a second clock signal. The controller may be a circuit that implements a finite state machine (FSM).

[0023] In some embodiments, the controller may be configured to receive a signal indicating a first number corresponding to a first frequency. The controller may be configured to receive a third signal indicating the start of calibration of the oscillator. In response to the third signal, the controller may be configured to reset the first counter and the second counter, control each of the first counter and the second counter to start counting, and determine whether the counter number indicated by the output of the second counter is equal to the second number. In response to determining that the counter number of the second counter is equal to the second number, the controller may be configured to control the first counter to stop counting and determine whether the counter number indicated by the output of the first counter is equal to the first number. In response to determining that the counter number of the first counter is not equal to the first number, the controller may be configured to generate one or more first signals. In response to determining that the counter number of the first counter is equal to the first number, the controller may be configured to disable the first counter and the second counter.

[0024] In some embodiments, the controller may be configured to receive a fifth signal indicative of enabling or disabling the first circuit, such that the first circuit is enabled during calibration of the ADC and is disabled in response to the ADC being calibrated.

[0025] In some embodiments, the oscillator may be a ring oscillator including a plurality of amplifiers. The one or more first signals may include a first control signal and a second control signal. The second circuit may be configured to determine a first number of amplifiers in the plurality of amplifiers according to the first control signal. The second circuit may be configured to enable the first number of amplifiers in the plurality of amplifiers. The second circuit may be configured to determine a second number of capacitors according to the second control signal. The second circuit may be configured to connect the second number of capacitors to corresponding amplifiers in the plurality of amplifiers.

[0026] In some embodiments, the second circuit may be configured to receive a sixth signal indicating enabling or disabling the oscillator, so that the oscillator is enabled during calibration of the ADC and disabled in response to the ADC being calibrated. The second circuit may be configured to enable or disable the oscillator according to the sixth signal.

[0027] Various embodiments disclosed herein are directed to a method. The method includes receiving, by a first circuit coupled to an oscillator, a signal indicating a first frequency to be used for calibration of an analog-to-digital converter (ADC). The method may include calibrating, by the first circuit, the frequency of the oscillator. The method may include generating, by the first circuit, one or more first signals based at least on the signal and the frequency of the oscillator. The method may include receiving, by a second circuit coupled to the oscillator, the one or more first signals from the first circuit. The method may include controlling, by the second circuit, the oscillator to generate a second signal having a first frequency based at least on the one or more first signals.

[0028] In some embodiments, the second circuit may receive another signal indicating enabling or disabling the oscillator, such that the oscillator is enabled during calibration of the ADC and disabled in response to the ADC being calibrated. The second circuit may enable or disable the oscillator according to the another signal.

[0029] In one aspect, in a data communication system (e.g., a narrowband communication system such as a 5G wireless system). A high-performance and high-resolution ADC can be used to capture RF signals and convert them into digital signals. With the expansion of CMOS technology, time interleaving of multiple unit ADCs (e.g., SAR ADCs) can achieve low power and compact area. Time-interleaved ADCs can also achieve a wide range of data sampling frequencies, such as tens of GHz. Time-interleaved ADCs can have a wide variety of applications in modern high-performance data communication and processing systems, including but not limited to wireless systems, base stations, network switches, SERDES PHYs, optical receivers, data acquisition systems, sensors, etc. For example, compared to analog mixer-based receivers, RF direct sampling receivers implemented with time-interleaved ADCs can make low-power and high-performance data communication systems (e.g., wireless systems, 5G wireless base stations, or electrical and optical links) easier to implement.

[0030] Time-interleaved ADCs may be subject to inherent interleaving errors, such as direct current (DC) offsets and / or gain and skew errors between unit ADCs. Before using the ADC to process real-time data, these errors can be calibrated using input signals (e.g., training signals). However, it will be difficult to efficiently generate such input signals that can guarantee sufficiently fast error detection and calibration convergence. For example, although interleaved DC offset errors can be detected by zeroing the ADC input, calibration of interleaved gain and skew errors may require certain input signals to be within a certain frequency range and within a certain amplitude range to ensure sufficiently fast error detection and calibration convergence. In addition, calibration may require that the signal received by each individual unit ADC should not have any data-related inherent DC offset and / or gain and skew errors. Otherwise, the errors from the unit ADC cannot be correctly calibrated.

[0031] Such input / training signals used for calibration may be provided and / or generated from an external system or circuit. Figure 1 Examples of such external systems or circuits are shown in . Figure 11 is a schematic block diagram of an exemplary system 1000 (e.g., an on-chip signal generator) that generates a signal for ADC calibration. The system 1000 may include an ADC 110, a phase interpolator 120, a phase locked loop (PLL) 130 configured to output a clock signal based on a reference clock signal 131, a transmitter (TX) 140, a digital pattern generator 150, a phase interpolator (PI) controller 160, and / or a calibration circuit 170. The digital pattern generator 150 may generate a signal (Dtx) 151 having a specific data pattern, such as a 1-modulated continuous wave (CW) signal or a random wideband pseudo-random binary sequence (PRBS) signal. The signal may be sent to the transmitter 140, which provides the signal 151 to the ADC 110 (as an ADC calibration signal 141). The ADC may convert the calibration signal 141 into an analog signal (Dout) 111 that is provided to the calibration circuit 170.

[0032] refer to Figure 1 , transmitter 140 may provide a clock signal (e.g., TX clock signal 132) from PLL 130. In one case, a single PLL (not shown) may provide a clock signal (not shown) to transmitter 140 and ADC 110, respectively. In another case, the TX PLL (not shown) and the ADC PLL (not shown) may be separate and share the same reference clock source. In both cases, the phase of the TX signal may be well aligned with the phase of the ADC sampling clock signal, which may potentially produce inherent gain and skew errors. To remove this data dependency (between the TX signal and the ADC sampling clock signal), a phase interpolator (e.g., PI 120) may be used. For example, PI controller 160 may provide PI code 161 to PI 120, which is constantly adjusted to produce a small frequency shift from the ADC sampling clock signal (e.g., clock signal 122). In this way, ADC sampling clock signal 122 may be suitable for time-interleaved ADC calibration. However, in systems in the art, such signals may not always be found or easily obtained during system power-up and ADC calibration. Even if such a signal can be generated and sent to the ADC, the generation of such a signal may incur more infrastructure resource overhead (such as power dividers, multiplexers, routers, buffers, etc.) and preparation time. Figure 1 , system 1000 may include PI 120 and PI controller 160 to generate a signal suitable for ADC calibration. Generally speaking, there may be strict system / time requirements (eg, chip boot time) to generate such a signal suitable for ADC calibration.

[0033] To address this problem, according to certain aspects, embodiments in the present disclosure relate to a technique for generating calibration signals for ADC calibration (e.g., calibration of ADC errors such as DC offset, gain, and skew errors) at various frequencies and amplitudes. In some embodiments, an oscillator can be used to generate the calibration signal for ADC calibration. The oscillator can be an RC oscillator, an oscillator based on an LC resonator, a harmonic oscillator, a relaxation oscillator, a ring oscillator, a voltage-controlled oscillator, or any electronic circuit that can generate a periodic oscillation or alternating signal. In some embodiments, an oscillator (e.g., an on-chip ring oscillator) can be used to generate the calibration signal for ADC calibration. The oscillator can be implemented with a delay-based oscillator or a delay line oscillator, which is very compact and power efficient compared to other types of oscillators (e.g., linear electronic oscillator circuits such as phase-shift oscillators).

[0034] In some embodiments, the system may include an ADC, a first buffer, a second buffer, a driver (e.g., a driver circuit), an oscillator, an oscillator calibrator (e.g., an oscillator calibrator circuit), and / or an ADC calibrator. The ADC calibrator may be any circuit, hardware (e.g., a microprocessor), software, firmware, or any combination thereof that can perform calibration of the ADC. Each of the first buffer and the second buffer may be an amplifier (e.g., an operational amplifier) ​​with a differential input. The oscillator may be coupled to the driver and the oscillator calibrator. The oscillator calibrator may receive a reference clock (from an external device or clock source) and a clock signal from the oscillator. The oscillator calibrator may calibrate the frequency of the oscillator. The oscillator calibrator may be any circuit, hardware (e.g., a microprocessor), software, firmware, or any combination thereof that implements oscillator calibration logic that can perform calibration of the frequency of the oscillator. Based on the result of the frequency calibration, the oscillator calibrator may send a control signal to the oscillator to set the frequency of the oscillator to a specific frequency or within a frequency range (e.g., a target frequency range). After the oscillator frequency is calibrated to be within the target frequency range, the oscillator may send an output signal (e.g., an oscillator output signal) to the driver. The output signal may be a single-ended signal or a complementary signal (or a differential signal). The complementary signal may include a pair of complementary signals (eg, a positive output signal and a negative output signal).

[0035] In some embodiments, the oscillator calibrator can adjust or control the frequency of the oscillator to meet the signal frequency requirement for ADC calibration. In some embodiments, not all 1-tone signals (e.g., monotone signals with one frequency) can be used for calibration of the time-interleaved ADC. Assume that the frequency Fin of the input signal (which is a 1-tone signal) is expressed as follows:

[0036] Fin=Fs*M / (N*K) (Equation 1)

[0037] Fsar=Fs / N (Equation 2)

[0038] Wherein Fs is the sampling clock frequency of the time-interleaved ADC, N is the number of unit ADCs in the time-interleaved ADC, M and K are integers, and Fsar is the sampling clock frequency of the unit ADC.

[0039] If the input signal frequency satisfies Equation 1, there may be a potential risk that the modulation signal Fin may introduce a data-dependent gain error and cannot be used as a calibration signal. For example, if K=1, then Fin=M*Fs / N=M*Fsar, which indicates that the sampled data on each unit ADC may have only one fixed value, thereby causing a data-dependent gain error. This significant data-dependent gain error in the unit ADC may cause a huge gain calibration error.

[0040] The simulation results show the simulated residual interleaving gain error calibrated with a 1-tone signal at various calibration signal frequencies (e.g., normalized calibration signal frequencies). It is shown that there are certain frequencies that are not suitable for ADC calibration due to high interleaving gain error, such as 7Fsar, 7.25Fsar, 7.5Fsar, 7.75Fsar, 8Fsar, 8.25Fsar, 8.5Fsar, etc. It is also shown that there is a frequency range (e.g., a target frequency range) that is suitable for ADC calibration.

[0041] Based on this simulation result, the system (e.g., an oscillator calibrator or an ADC calibrator) can calculate or select a target frequency range for the 1-tone calibration signal. In some embodiments, the system can use Equation 1 to calculate the target frequency range for the 1-tone calibration signal. In some embodiments, the system can use Equation 1 to calculate a frequency or frequency range that is not suitable for the 1-tone calibration signal. As long as the signal frequency (e.g., the input signal frequency) falls within the target frequency range, the ADC calibration system can achieve good calibration results for the interleaved gain. In some embodiments, after the target frequency range is calculated (e.g., by an oscillator calibrator or an ADC calibrator), the oscillator calibrator can send a control signal to the oscillator to set the frequency of the oscillator within the calculated target frequency range. After the oscillator frequency is calibrated to be within the target frequency range, the oscillator can send an output signal (e.g., an oscillator output signal) to the driver.

[0042] In some embodiments, the driver may receive an output signal from an oscillator as an input signal and adjust the amplitude and / or bandwidth of the input signal according to an amplitude control signal (or attenuation control signal) and / or a bandwidth control signal, respectively. In some embodiments, the ADC calibrator may generate an amplitude control signal and / or a bandwidth control signal. The bandwidth control signal may adjust the rise time and / or fall time of the input signal. Based on the result of the adjustment, the driver may generate an output signal to be injected or provided to the main data path toward the ADC. The output signal may be a pair of signals 180 degrees out of phase with each other. In some embodiments, the output signal may be provided to the output of the first buffer and the input of the second buffer. The first buffer may have an impedance higher than the impedance of the second buffer. In the calibration mode, the driver may be enabled according to the enable control signal, the second buffer may be enabled according to the enable control signal, and the first buffer may be disabled according to the enable control signal. For example, the first buffer (e.g., an amplifier) ​​may be powered off according to the enable control signal during calibration to isolate the input signal of the ADC and maximize the swing of the calibration signal (e.g., the output signal of the driver). In response to the calibration mode, the signal injected from the driver may be sent or provided to the second buffer so that the output signal of the second buffer may be provided to the ADC for calibration. In a normal mode (e.g., ADC mode), the driver may be disabled according to an enable control signal, the second buffer may be disabled according to an enable control signal, and the first buffer may be enabled according to an enable control signal. In response to the normal mode, an analog signal may be sent or provided to the first buffer so that an output signal of the first buffer may be provided to the ADC for analog / digital conversion. In some embodiments, the ADC calibrator may determine a calibration mode or a normal mode, and generate corresponding enable control signals for the driver, the first buffer, and the second buffer based on the result of the determination.

[0043] In some embodiments, the driver may adjust the amplitude and / or bandwidth of the input signal to meet one or more requirements (e.g., requirements for the amplitude of the calibration signal). In addition to frequency, the amplitude of the calibration signal may also affect the calibration of the interleaving gain and / or skew. In some embodiments, the amplitude of the calibration signal may be set or adjusted to be less than the full scale of the ADC to avoid clipping. In some embodiments, the amplitude of the calibration signal may be set or adjusted to be large enough to have a sufficiently short calibration time. For example, the target amplitude range of the calibration signal may be from -10 dBFS (i.e., decibels relative to full scale) to -2 dBFS. In some embodiments, the driver may adjust the amplitude of the input signal to be within the target amplitude range of the calibration signal (e.g., -10 dBFS to -2 dBFS) to generate an output signal to be provided to the ADC for calibration.

[0044] In some embodiments, the driver or driver circuit may include a pair of amplifiers (or buffers) with controls, a pair of capacitors respectively coupled to the amplifier pair, and / or a pair of switches (e.g., a pair of transistors) respectively coupled to the capacitor pair. The capacitor may be an AC coupling capacitor for ensuring reliability and adapting to different power domains. The switch may be a high-speed switching transistor (e.g., a bipolar junction transistor (BJT) or a metal oxide semiconductor field effect transistor (MOSFET)). The amplifier pair may receive a pair of complementary clock signals (e.g., a pair of clock signals 180 degrees out of phase with each other) from an oscillator as input signals, adjust the amplitude or signal strength of the corresponding input signals according to the corresponding attenuation control signal, and generate an output signal (e.g., a calibration signal) with the adjusted amplitude or signal strength. The switch may be turned on according to the corresponding enable control signal (e.g., an indication value of 1) during calibration of the ADC. In some embodiments, the ADC calibrator may determine a calibration mode or a normal mode, and generate a corresponding enable control signal of the switch based on the result of the determination. In this way, during calibration, the complementary clock signal from the oscillator may be connected, provided, or injected to the output of the first buffer (e.g., an amplifier) ​​through the high-speed switch.

[0045] In some embodiments, a system or circuit (e.g., an oscillator circuit) may control or adjust the frequency of an oscillator according to one or more control signals. The one or more control signals may include a first control signal indicating a coarse control (adjustment) of the frequency and / or a second control signal indicating a fine control (adjustment) of the frequency. For example, using the first control signal and the second control signal, the oscillator circuit may perform both coarse and fine frequency adjustments of the frequency of the oscillator. The oscillator may be a ring oscillator (e.g., a ring oscillator circuit or a ring oscillator loop) including a plurality of inverters (e.g., an odd number of inverters). The ring oscillator circuit may include a plurality of multiplexers (e.g., m multiplexers, where m is less than or equal to n), a plurality of switches (e.g., m switches), a plurality of capacitors (e.g., m capacitors), and / or a converter.

[0046] In some embodiments, the ring oscillator circuit may perform a coarse adjustment of the frequency of the ring oscillator by a first control signal (which controls the number of inverters in the ring oscillator loop). The first control signal may include m control signals, each indicating an enable signal or a disable signal. Each of the plurality of multiplexers may select between (1) an input signal of the corresponding inverter or (2) an output signal of the corresponding inverter according to the corresponding control signal. For example, the ring oscillator circuit may provide a first control signal including k enable signals to m multiplexers so that the selected k inverters are enabled or turned on (k≤m). The ring oscillator circuit may perform a coarse frequency adjustment to ensure that a target frequency can be achieved under various PVT (process, voltage, temperature) conditions.

[0047] In some embodiments, the ring oscillator circuit can perform fine adjustment of the frequency of the ring oscillator through a second control signal (which controls the number of capacitors loaded into the ring oscillator loop). The second control signal may include m control signals, each indicating a closed signal or an open signal. Each of the plurality of switches can selectively connect between (1) the output of the corresponding inverter (or the corresponding multiplexer) and (2) the corresponding capacitor according to the corresponding control signal. For example, the ring oscillator circuit can provide a second control signal including k closed signals to the m switches, so that the k capacitors are connected to the output of the corresponding inverter by selecting the k switches (k≤m). The ring oscillator circuit can perform fine frequency adjustment to perform a small frequency calibration of the ring oscillator and ensure that the frequency of the ring oscillator is accurate enough to avoid inappropriate frequencies as shown in simulation results or as calculated using Equation 1.

[0048] In some embodiments, to change the frequency of a ring oscillator, a system or circuit (e.g., a ring oscillator calibrator or ADC calibrator) may use three methods (other methods exist). First, the system or circuit may change the number of inverters and / or buffers in the ring oscillator chain, thereby producing a higher or lower frequency of the ring oscillator. Second, the system or circuit may change the supply voltage of the ring oscillator, thereby increasing or decreasing the propagation delay through the chain of stages and changing the frequency of the ring oscillator. Third, the system or circuit may change the number of capacitors loaded into the ring oscillator loop, thereby changing the propagation delay through the chain of stages and changing the frequency of the ring oscillator.

[0049] In some embodiments, the converter may be configured to convert a single-ended output signal of the ring oscillator into a pair of complementary output signals (e.g., a pair of output signals that are 180 degrees out of phase with each other). The single-ended output signal may be a signal referenced to a shield (e.g., ground on an output connector). The complementary output signal pair may have both (1) a first signal on a channel and (2) an inverted version of the first signal (e.g., 180 degrees out of phase with the first signal). The ring oscillator may be enabled only during ADC calibration according to an enable control signal. During ADC calibration, the ring oscillator may provide an output signal (e.g., a single-ended output signal) to a ring oscillator calibrator circuit. After calibration is completed, the ring oscillator may be disabled, for example, according to an enable control signal indicating 0.

[0050] In some embodiments, the system may perform a frequency calibration of the ring oscillator. The system may include a ring oscillator and a circuit (e.g., a ring oscillator calibrator circuit) configured to perform a frequency calibration of the ring oscillator. The ring oscillator may be enabled or disabled according to an enable control signal. The ring oscillator may be enabled during ADC calibration to provide an output signal (e.g., a single-ended output signal) to the ring oscillator calibrator circuit, and perform an adjustment or calibration of the frequency of the ring oscillator (e.g., by the ring oscillator circuit) according to one or more control signals received from the ring oscillator calibrator circuit. After completing the frequency adjustment or calibration, the ring oscillator may generate an output signal (e.g., a pair of complementary output signals) for ADC calibration. In some embodiments, the ADC calibrator may determine a calibration mode or a normal mode, and generate an enable control signal for the ring oscillator based on the result of the determination.

[0051] In some embodiments, the ring oscillator calibration circuit may include a first counter, a second counter, and a controller. The controller may be any circuit, hardware (e.g., a microprocessor), software, firmware, or any combination thereof that can use one or more control signals to control the first counter, the second counter, and the ring oscillator. In some embodiments, the controller may implement a finite state machine (FSM). In some embodiments, the FSM may be any model of a finite state automaton, a finite automaton, a state machine, or a computational model that can be in one of a finite number of states at any given time and can change from one state to another in response to some input or input signal. The controller may receive a calibration start signal, a signal indicating a target frequency word, a power-off signal, and / or a reference clock signal. In some embodiments, the ADC calibrator may generate a calibration start signal, a signal indicating a target frequency word, and / or a power-off signal. The reference clock signal may be a system clock signal. The controller may receive a counter output signal (from the first counter). The controller may (1) output a counter reset signal to the first counter and the second counter, (2) output a counter enable signal to the first counter and the second counter, and / or (3) output one or more control signals including a first control signal for coarse frequency adjustment and a second control signal for fine frequency adjustment to the ring oscillator. The counter reset signal may be a pulse signal. The first counter may perform counting when clocked by a clock signal from the ring oscillator, and output a counter output signal indicating a counter value of the first counter. The second counter may receive a number control signal indicating a target counter value, perform counting when clocked by a reference clock signal, and determine whether the counter value of the second counter reaches the target counter value. In response to determining that the counter value of the second counter reaches the target counter value, the second counter may output a counter stop signal to the first counter, thereby controlling the first counter to stop counting.

[0052] In response to receiving the calibration start signal, the controller may generate a counter reset signal to reset the first counter and the second counter. In response to receiving the counter reset signal, the controller may reset the first counter and control the first counter to start counting when clocked by the clock signal from the ring oscillator. In response to receiving the counter reset signal, the controller may reset the second counter and control the second counter to start counting when clocked by the reference clock signal. In response to determining that the counter value of the second counter reaches the target counter value specified by the number control signal, the second counter may issue a counter stop signal to stop the first counter from counting. In response to the first counter being stopped, the controller may read a counter output signal indicating the current counter value of the first counter and compare the current counter value with the target frequency word. In response to determining that the current counter value (of the first counter) is greater than the target frequency word, the controller may generate a first control signal and / or a second control signal based on the difference between the current counter value and the target frequency word to adjust (e.g., reduce or decrease) the frequency of the ring oscillator. Similarly, in response to determining that the current counter value (of the first counter) is less than the target frequency word, the controller may generate a first control signal and / or a second control signal based on the difference between the current counter value and the target frequency word to adjust (e.g., increase) the frequency of the ring oscillator. In some embodiments, a coarse frequency adjustment may be performed first (by the ring oscillator circuit) and then a fine frequency adjustment may be performed (by the ring oscillator circuit). In response to determining that the current counter value (of the first counter) is equal to or sufficiently close to (e.g., within a predetermined range) the target frequency word, the controller may determine that the frequency calibration is complete and, for example, disable both the first counter and the second counter by setting the counter enable signal to 0. In response to determining that the frequency calibration is complete, the ring oscillator may be used for ADC calibration. In response to the ADC calibration being complete, the ring oscillator calibration circuit may be powered off according to a power-off signal set to 1 (e.g., by the ADC calibrator).

[0053] Embodiments of the present disclosure have at least the following advantages and benefits. First, embodiments of the present disclosure may provide useful techniques for generating signals for ADC calibration in a flexible, robust, and compact manner. For example, a ring oscillator (e.g., an on-chip ring oscillator) according to some embodiments may introduce flexible calibration signals at various frequencies and amplitudes for ADC calibration. A ring oscillator according to some embodiments may perform robust ADC calibration without relying on external signals (e.g., signals generated by external devices such as PLLs, phase interpolator (PI) controllers, and / or PIs). A ring oscillator according to some embodiments may be compact without relying on external devices such as PLLs, PI controllers, and / or PIs.

[0054] Secondly, the embodiments in the present disclosure can provide useful techniques for providing an independent integrated solution for ADC calibration without relying on external systems and circuits. Without interacting with external circuits and systems, the embodiments in the present disclosure can achieve short chip startup and calibration time and reduce overall ADC power.

[0055] Third, embodiments of the present disclosure may provide useful techniques for providing on-chip signals for ADC calibration for various products using time-interleaved ADCs (e.g., 5G wireless base station products, 5G wireless base station receivers based on direct sampling of ADCs, and efficient high-speed data receivers). Embodiments of the present disclosure may improve the performance of such products by enabling ADC calibration without the need for external calibration signals.

[0056] Figure 22 is a schematic block diagram of an exemplary system 2000 that uses an oscillator 260 to generate a signal for ADC calibration according to an embodiment. The oscillator 260 may be an RC oscillator, an oscillator based on an LC resonator, a harmonic oscillator, a relaxation oscillator, a ring oscillator, a voltage controlled oscillator, or any electronic circuit that can generate a periodic oscillation or alternating signal. The system 2000 may include an ADC 210, a first buffer 220, a second buffer 240, a driver (e.g., a driver circuit) 250, an oscillator 260, an oscillator calibrator (e.g., an oscillator calibrator circuit) 270, and / or an ADC calibrator 290. The ADC calibrator 290 may be any circuit, hardware (e.g., a microprocessor), software, firmware, or any combination thereof that can perform calibration of the ADC. Each of the first buffer 220 and the second buffer 240 may be an amplifier (e.g., an operational amplifier) ​​with a differential input. The oscillator 260 may be coupled to the driver 250 and the oscillator calibrator 270. The oscillator calibrator 270 may receive a reference clock (Clk_cal) 271 (from an external device or clock source) and a clock signal (Clk_osc) 262 from the oscillator 260. The oscillator calibrator 270 may calibrate the frequency of the oscillator 260. The oscillator calibrator 270 may be any circuit, hardware (e.g., a microprocessor), software, firmware, or any combination thereof that implements oscillator calibration logic that may perform calibration of the frequency of the oscillator 260. Based on the result of the frequency calibration, the oscillator calibrator 270 may send a control signal (Osc_freq_ctrl) 272 to the oscillator 260 to set the frequency of the oscillator to a specific frequency or within a frequency range (e.g., a target frequency range). After the oscillator frequency is calibrated to be within the target frequency range, the oscillator 260 may send an output signal (e.g., an oscillator output signal (Sig_osc) 261) to the driver 250. The output signal 261 may be a single-ended signal or a complementary signal (or a differential signal). The complementary signal may include a pair of complementary signals (eg, a positive output signal and a negative output signal or a pair of signals that are 180 degrees out of phase with each other).

[0057] In some embodiments, the oscillator calibrator 270 may adjust or control the frequency of the oscillator 260 to meet the signal frequency requirements of the ADC calibration. In some embodiments, not all 1-tone signals (e.g., monotone signals with one frequency) can be used for calibration of the time-interleaved ADC. The system (e.g., the oscillator calibrator 270 or the ADC calibrator 290) may calculate or select a target frequency range for the 1-tone calibration signal experimentally or based on simulation results. In some embodiments, the system may use Equation 1 to calculate the target frequency range for the 1-tone calibration signal. In some embodiments, the system may use Equation 1 to calculate the frequency or frequency range that is not suitable for the 1-tone calibration signal. As long as the signal frequency (e.g., the input signal frequency) falls within the target frequency range, the ADC calibrator 290 can achieve a good calibration result for the interleaved gain. After the target frequency range is calculated (e.g., by the oscillator calibrator 270 or the ADC calibrator 290), the oscillator calibrator 270 may send a control signal (e.g., control signal 272) to the oscillator 260 to set the frequency of the oscillator 260 within the calculated target frequency range. After calibrating the oscillator frequency to be within a target frequency range, oscillator 260 may send an output signal (eg, oscillator output signal 261 ) to driver 250 .

[0058] refer to Figure 2, the driver 250 may receive the output signal 261 from the oscillator 260 as an input signal and adjust the amplitude and / or bandwidth of the input signal according to the amplitude control signal (Atten_ctrl) 252 and / or the bandwidth control signal (BW_ctrl) 253, respectively. The ADC calibrator 290 may generate the amplitude control signal 252 and / or the bandwidth control signal 253. The bandwidth control signal 253 may adjust the rise time and / or the fall time of the input signal 261. Based on the result of the adjustment, the driver 250 may generate an output signal 254 to be injected or provided to the main data path toward the ADC 210. The output signal 254 may be a pair of complementary signals (e.g., a pair of signals that are 180 degrees out of phase with each other). The output signal 254 may be provided to the output of the first buffer 220 and the input of the second buffer 240. The first buffer 220 may have an impedance higher than the impedance of the second buffer 240. In the calibration mode, the driver 250 may be enabled according to the enable control signal (En_drv) 251, the second buffer 240 may be enabled, and the first buffer 220 may be disabled according to the enable control signal (En_buf) 223. For example, the first buffer (e.g., amplifier) ​​220 may be powered down during calibration according to the enable control signal 223 to isolate the input signal (e.g., input voltage signal Vip 221, Vin 222) of the ADC and maximize the swing of the calibration signal (e.g., output signal 254 of the driver 250). In response to the calibration mode, the signal 254 injected from the driver 250 (as a calibration signal) may be sent or provided to the second buffer 240, so that the output signal (e.g., output voltage signal Vop 241, Von 242) of the second buffer may be provided to the ADC 210 for calibration. In a normal mode (e.g., ADC mode), the driver 250 may be disabled according to an enable control signal (e.g., enable control signal 251), the second buffer 240 may be disabled, and the first buffer 220 may be enabled according to an enable control signal (e.g., enable control signal 223). In response to the normal mode, an analog signal (e.g., analog input voltage signal Vip 221, Vin 222) may be sent or provided to the first buffer 220, so that the output signal of the first buffer may be provided to the ADC 210 for analog / digital conversion. The ADC calibrator 290 may determine the calibration mode or the normal mode, and generate corresponding enable control signals 251, 223 of the driver 250, the first buffer 220, and the second buffer 240 based on the result of the determination.

[0059] refer to Figure 2, the driver 250 can adjust the amplitude and / or bandwidth of the input signal 261 to meet one or more requirements (e.g., the requirements for the amplitude of the calibration signal 254). In addition to frequency, the amplitude of the calibration signal 254 can also affect the calibration of the interleaving gain and / or skew. The amplitude of the calibration signal 254 can be set or adjusted to be less than the full scale of the ADC to avoid clipping. The amplitude of the calibration signal 254 can be set or adjusted to be large enough to have a sufficiently short calibration time. The driver 250 can adjust the amplitude of the input signal 261 to be within the target amplitude range of the calibration signal to generate an output signal (e.g., calibration signal) 254 to be provided to the ADC 210 for calibration.

[0060] Figure 3 3 is a schematic block diagram of an exemplary system 3000 for generating a signal for ADC calibration using a ring oscillator according to an embodiment. The system 3000 includes an ADC 310, a first buffer 320, a second buffer 340, a driver (e.g., a driver circuit) 350, a ring oscillator 360, a ring oscillator calibrator (e.g., a ring oscillator calibrator circuit) 370, and / or an ADC calibrator 390. The ADC calibrator 390 may be any circuit, hardware (e.g., a microprocessor), software, firmware, or any combination thereof that can perform calibration of an ADC. Each of the first buffer 320 and the second buffer 340 may be an amplifier (e.g., an operational amplifier) ​​with a differential input. The ring oscillator 360 may be coupled to the driver 350 and the ring oscillator calibrator 370. The ring oscillator calibrator 370 may receive a reference clock (Clk_cal) 371 (from an external device or clock source) and a clock signal (Clk_rosc) 362 from the ring oscillator 360. The ring oscillator calibrator 370 may calibrate the frequency of the ring oscillator 360. The ring oscillator calibrator 370 may be any circuit, hardware (e.g., a microprocessor), software, firmware, or any combination thereof that implements a ring oscillator calibration logic that may perform calibration of the frequency of the ring oscillator 360. Based on the result of the frequency calibration, the ring oscillator calibrator 370 may send a control signal (Rosc_freq_ctrl) 372 to the ring oscillator 360 to set the frequency of the ring oscillator to a specific frequency or within a frequency range (e.g., a target frequency range). After the ring oscillator frequency is calibrated to be within the target frequency range, the ring oscillator 360 may send an output signal (e.g., a ring oscillator output signal (Sig_rosc) 361) to the driver 350. The output signal 361 may be a single-ended signal or a complementary signal (or a differential signal). The complementary signal may include a pair of complementary signals (e.g., a positive output signal and a negative output signal or a pair of signals that are 180 degrees out of phase with each other).

[0061] In some embodiments, ring oscillator calibrator 370 may adjust or control the frequency of ring oscillator 360 to meet the signal frequency requirement for ADC calibration. In some embodiments, not all monotonic signals (eg, monotonic signals with one frequency) may be used for calibration of the time-interleaved ADC. Figure 3 is a graph 3000 showing simulation results of residual interleaving gain error with various calibration signal frequencies, according to an embodiment. Figure 4 The simulated residual interleaving gain error 402 calibrated with a 1-tone signal at various calibration signal frequencies (e.g., normalized calibration signal frequency 402) is shown. It is shown that there are certain frequencies that are not suitable for ADC calibration due to high interleaving gain error, such as 7Fsar (411), 7.25Fsar (412), 7.5Fsar (413), 7.75Fsar (414), 8Fsar (415), 8.25Fsar (416), 8.5Fsar (417), etc. It is also shown that there are frequency ranges that are suitable for ADC calibration (e.g., target frequency range 420).

[0062] Based on this simulation result (e.g. Figure 4 420). In some embodiments, the system may use Equation 1 to calculate the target frequency range for the 1-tone calibration signal. In some embodiments, the system may use Equation 1 to calculate the frequency or frequency range that is not suitable for the 1-tone calibration signal. As long as the signal frequency (e.g., the input signal frequency) falls within the target frequency range (e.g., range 420), the ADC calibrator 390 may achieve good calibration results for the interleaved gain. After calculating the target frequency range (e.g., by the ring oscillator calibrator 370 or the ADC calibrator 390), the ring oscillator calibrator 370 may send a control signal (e.g., control signal 372) to the ring oscillator 360 to set the frequency of the ring oscillator 360 within the calculated target frequency range. After calibrating the ring oscillator frequency to be within the target frequency range, the ring oscillator 360 may send an output signal (e.g., ring oscillator output signal 361) to the driver 350.

[0063] refer to Figure 3, the driver 350 may receive the output signal 361 from the ring oscillator 360 as an input signal and adjust the amplitude and / or bandwidth of the input signal according to the amplitude control signal (Atten_ctrl) 352 and / or the bandwidth control signal (BW_ctrl) 353, respectively. The ADC calibrator 390 may generate the amplitude control signal 352 and / or the bandwidth control signal 353. The bandwidth control signal 353 may adjust the rise time and / or the fall time of the input signal 361. Based on the result of the adjustment, the driver 350 may generate an output signal 354 to be injected or provided to the main data path toward the ADC 310. The output signal 354 may be a pair of complementary signals (e.g., a pair of signals that are 180 degrees out of phase with each other). The output signal 354 may be provided to the output of the first buffer 320 and the input of the second buffer 340. The first buffer 320 may have an impedance higher than the impedance of the second buffer 340. In the calibration mode, the driver 350 may be enabled according to an enable control signal (En_drv) 351, the second buffer 340 may be enabled, and the first buffer 320 may be disabled according to an enable control signal (En_buf) 323. For example, the first buffer (e.g., amplifier) ​​320 may be powered down during calibration according to the enable control signal 323 to isolate the input signal (e.g., input voltage signal Vip 321, Vin 322) of the ADC and maximize the swing of the calibration signal (e.g., output signal 354 of the driver 350). In response to the calibration mode, the signal 354 injected from the driver 350 (as a calibration signal) may be sent or provided to the second buffer 340, so that the output signal (e.g., output voltage signal Vop 341, Von 342) of the second buffer may be provided to the ADC 310 for calibration. In a normal mode (e.g., ADC mode), the driver 350 may be disabled according to an enable control signal (e.g., enable control signal 351), the second buffer 340 may be disabled, and the first buffer 320 may be enabled according to an enable control signal (e.g., enable control signal 323). In response to the normal mode, an analog signal (e.g., analog input voltage signal Vip 321, Vin 322) may be sent or provided to the first buffer 320, so that the output signal of the first buffer may be provided to the ADC 310 for analog / digital conversion. The ADC calibrator 390 may determine the calibration mode or the normal mode, and generate corresponding enable control signals 351, 323 of the driver 350, the first buffer 320, and the second buffer 340 based on the result of the determination.

[0064] refer to Figure 3, the driver 350 can adjust the amplitude and / or bandwidth of the input signal 361 to meet one or more requirements (e.g., the requirements of the amplitude of the calibration signal 354). In addition to frequency, the amplitude of the calibration signal 354 can also affect the calibration of the interleaving gain and / or skew. The amplitude of the calibration signal 354 can be set or adjusted to be less than the full scale of the ADC to avoid clipping. The amplitude of the calibration signal 354 can be set or adjusted to be large enough to have a sufficiently short calibration time. For example, the target amplitude range of the calibration signal can be from -10dBFS (i.e., decibels relative to full scale) to -2dBFS. The driver 350 can adjust the amplitude of the input signal 361 to be within the target amplitude range of the calibration signal (e.g., -10dBFS to -2dBFS) to generate an output signal (e.g., calibration signal) 354 to be provided to the ADC 310 for calibration.

[0065] Figure 5 5 is a schematic block diagram of an exemplary system 5000 for providing a signal for ADC calibration to an ADC according to an embodiment. The system 5000 may include an ADC 510, a first buffer 520, a second buffer 540, and / or a driver (e.g., a driver circuit) 550. The ADC 510, the first buffer 520, and the second buffer 540 may have respective Figure 3 540 . The ADC 310, the first buffer 320, and the second buffer 340 in FIG. 540 are configured similarly. For example, the first buffer (e.g., amplifier) ​​520 may be powered off according to the enable control signal 523 during ADC calibration to isolate the input signal (e.g., input voltage signal Vip 521, Vin 522) of the ADC 510 and maximize the swing of the calibration signal (e.g., output signal 562 of the driver 550). In response to the calibration mode, the signal 562 injected from the driver 550 (as the calibration signal) may be sent or provided to the second buffer 540, so that the output signal (e.g., output voltage signal Vop 541, Von 542) of the second buffer may be provided to the ADC 510 for calibration. In the normal mode (e.g., ADC mode), the driver 550 may be disabled according to the enable control signal (e.g., enable control signal 557, 558), the second buffer 540 may be disabled, and the first buffer 520 may be enabled according to the enable control signal (e.g., enable control signal 523). In response to the normal mode, an analog signal (eg, analog input voltage signal Vip 521 , Vin 522 ) may be sent or provided to the first buffer 520 , so that an output signal of the first buffer may be provided to the ADC 510 for analog / digital conversion.

[0066] refer to Figure 5, the driver or driver circuit 550 may include a pair of amplifiers (or buffers) 553, 554 with control, a pair of capacitors 555, 556 coupled to the amplifier pair 553, 554, respectively, and / or a pair of switches (e.g., a pair of transistors) 559, 560 coupled to the capacitor pair 555, 556, respectively. The capacitors 555, 556 may be AC ​​coupling capacitors for ensuring reliability and adapting to different power domains. The switches 559, 560 may be high-speed switching transistors (e.g., bipolar junction transistors (BJT) or metal oxide semiconductor field effect transistors (MOSFET)). The amplifier pair 553, 554 may receive a pair of complementary clock signals as input signals 561 from a ring oscillator (e.g., ring oscillator 360), respectively, adjust the amplitude or signal strength of the corresponding input signal 561 according to the corresponding attenuation control signal (Attn_ctrl) 551, 552, and generate an output signal (Drv_out) 562 with the adjusted amplitude or signal strength as a calibration signal. The switches 559, 560 may be turned on according to the respective enable control signals 557, 558 (e.g., indicating a value of 1) during calibration of the ADC 510. An ADC calibrator (e.g., ADC calibrator 390) may determine a calibration mode or a normal mode, and based on the result of the determination, generate respective enable control signals 557, 558 for the switches 559, 560. In this manner, during calibration, the complementary clock signal 561 from the ring oscillator may be connected, provided, or injected to the output of the first buffer (e.g., amplifier) ​​520 through the high-speed switches 559, 560.

[0067] Figure 66000 is a schematic block diagram of an exemplary system 6000 for controlling a ring oscillator 660 to adjust a frequency for ADC calibration according to an embodiment. The system 6000 may be a ring oscillator circuit that controls the frequency of the ring oscillator 660 according to one or more control signals 671, 672. The one or more control signals may include a first control signal (rosc_freq_ctrl_coarse) 671 indicating a coarse control (adjustment) of the frequency and / or a second control signal (rosc_freq_ctrl_fine) 672 indicating a fine control (adjustment) of the frequency. For example, using the first control signal 671 and the second control signal 672, the ring oscillator circuit 6000 may perform both coarse and fine frequency adjustments of the frequency of the ring oscillator 660. The ring oscillator (e.g., a ring oscillator loop) 660 may include a plurality of inverters (e.g., an odd number (n) of inverters 662-1, 662-2, 662-3, ..., 662-n). The ring oscillator circuit 6000 may include multiple multiplexers (e.g., m multiplexers 650-1, 650-2, 650-3, ..., 650-m, where m is less than or equal to n), multiple switches (e.g., m switches 670-1, 670-2, 670-3, ..., 670-m), multiple capacitors (e.g., m capacitors 675-1, 675-2, 675-3, ..., 675-m) and / or a converter 680.

[0068] refer to Figure 6 , the ring oscillator circuit 6000 can perform a coarse adjustment of the frequency of the ring oscillator 660 through a first control signal 671 (which controls the number of inverters in the ring oscillator loop 660). The first control signal 671 may include m control signals, each indicating an enable signal or a disable signal. Each of the multiple multiplexers (e.g., multiplexer 650-1) can select between (1) an input signal of a corresponding inverter (e.g., inverter 662-2) or (2) an output signal of a corresponding inverter (e.g., inverter 662-2) according to the corresponding control signal. For example, the ring oscillator circuit 6000 can provide a first control signal 671 including k enable signals to m multiplexers, so that the selected k inverters are enabled or turned on (k≤m). The ring oscillator circuit 6000 can perform a coarse frequency adjustment to ensure that the target frequency can be achieved under various PVT (process, voltage, temperature) conditions.

[0069] refer to Figure 6, the ring oscillator circuit 6000 can perform fine adjustment of the frequency of the ring oscillator 660 through the second control signal 672 (which controls the number of capacitors loaded into the ring oscillator loop 660). The second control signal 672 may include m control signals, each indicating a closed signal or an open signal. Each of the plurality of switches (e.g., switch 670-1) can selectively connect between (1) the output of the corresponding inverter (e.g., inverter 662-2) or the output of the corresponding multiplexer (e.g., multiplexer 650-1) and (2) the corresponding capacitor (e.g., capacitor 675-1) according to the corresponding control signal. For example, the ring oscillator circuit 6000 can provide the second control signal 672 including k closed signals to the m switches, so that the k capacitors are connected to the output of the corresponding inverter (or the corresponding multiplexer) by selecting the k switches (k≤m). Ring oscillator circuit 6000 can perform fine frequency adjustment to perform a small frequency calibration of ring oscillator 660 and ensure that the frequency of ring oscillator 660 is accurate enough to avoid the simulation results (see Figure 4 ) or as calculated using Equation 1.

[0070] refer to Figure 6 To change the frequency of ring oscillator 660, a system or circuit (e.g. Figure 3 Three methods (other methods exist) may be used to modify the ring oscillator calibrator 370 or ADC calibrator 390 in the ring oscillator calibrator 370 (other methods exist). First, the system or circuit may change the number of inverters (e.g., inverter 662) and / or buffers in the ring oscillator chain to produce a higher or lower frequency of the ring oscillator 660. Second, the system or circuit may change the supply voltage of the ring oscillator 660, thereby increasing or decreasing the propagation delay through the chain of stages and changing the frequency of the ring oscillator 660. Third, the system or circuit may change the number of capacitors (e.g., capacitor 675) loaded into the ring oscillator loop, thereby changing the propagation delay through the chain of stages and changing the frequency of the ring oscillator 660.

[0071] refer to Figure 6, the converter 680 can be configured to convert a single-ended output signal of the ring oscillator (e.g., output signal (rosc_int) 665) into a pair of complementary output signals (e.g., output signals (rosc_outp, rosc_outn) 667, 668). The single-ended output signal can be a signal referenced to a shield (e.g., ground on an output connector). The complementary output signal pair can have both (1) a first signal on a channel and (2) an inverted version of the first signal (e.g., 180 degrees out of phase with the first signal). According to the enable control signal (en_rosc) 661, the ring oscillator 660 can be enabled only during ADC calibration. During ADC calibration, the ring oscillator 660 can provide an output signal (e.g., a single-ended output signal) 665 to a ring oscillator calibrator circuit (e.g., ring oscillator calibrator 370). After calibration is completed, for example, the ring oscillator 660 can be disabled according to the enable control signal 661 indicating 0.

[0072] Figure 7 7000 is a schematic block diagram of an exemplary system for calibrating the frequency of a ring oscillator for ADC calibration according to an embodiment. The system 7000 may include a ring oscillator 760 and a circuit (e.g., a ring oscillator calibrator circuit 770) configured to perform frequency calibration of the ring oscillator 760. The ring oscillator 760 may be enabled or disabled according to an enable control signal (en_rosc) 761. The ring oscillator 760 may be enabled during ADC calibration to provide an output signal (e.g., a single-ended output signal (rosc_int) 765) to the ring oscillator calibrator circuit 770, and to perform adjustment or calibration of the frequency of the ring oscillator (e.g., by the ring oscillator circuit 6000) according to one or more control signals (rosc_freq_ctrl_coarse, rosc_freq_ctrl_fine) 771, 772 received from the ring oscillator calibrator circuit 770. After completing the frequency adjustment or calibration, the ring oscillator 760 can generate an output signal (e.g., a pair of complementary output signals (rosc_outp, rosc_outn) 767, 768) for ADC calibration. Figure 3 The ADC calibrator 390 in the embodiment may determine the calibration mode or the normal mode, and generate an enable control signal 761 of the ring oscillator 760 based on the determined result.

[0073] refer to Figure 7, the ring oscillator calibration circuit 770 may include a first counter 776, a second counter 778, and a controller 773. The controller 773 may be any circuit, hardware (e.g., a microprocessor), software, firmware, or any combination thereof that can use one or more control signals (e.g., signals 771, 772, 774, 775) to control the first counter 776, the second counter 778, and the ring oscillator 760. The controller 773 may implement a finite state machine (FSM). The controller 773 may receive a calibration start signal (rosc_cal_start) 782, a signal 783 indicating a target frequency word (freq_target_wd), a power-off signal (pd_rosc) 781, and / or a reference clock signal (clk_cal) 784. In some embodiments, an ADC calibrator (e.g., an ADC calibrator 390) may generate a calibration start signal 782, a signal 783 indicating a target frequency word, and / or a power-off signal 781. The reference clock signal 784 may be a system clock signal. The controller 773 may receive a counter output signal (cnt1_out) 777 from the first counter 776. The controller 773 may (1) output a counter reset signal (cnt_rst) 774 to the first counter 776 and the second counter 778, (2) output a counter enable signal (cnt_en) 775 to the first counter 776 and the second counter 778, and / or (3) output one or more control signals including a first control signal 771 for coarse frequency adjustment and a second control signal 772 for fine frequency adjustment to the ring oscillator 760. The counter reset signal 774 may be a pulse signal. The first counter 776 may perform counting when clocked by a clock signal (rosc_int) 765 from the ring oscillator 760, and output a counter output signal 777 indicating a counter value of the first counter 776. The second counter 778 may receive a number control signal (num_cnt_ctrl) 785 indicating a target counter value, and perform counting when clocked by the reference clock signal 784 to determine whether the counter value of the second counter reaches the target counter value. In response to determining that the counter value of the second counter reaches the target counter value, the second counter 778 may output a counter stop signal (cnt_stop) 779 to the first counter 776, thereby controlling the first counter 776 to stop counting.

[0074] refer to Figure 7In response to receiving the calibration start signal 782, the controller 773 may generate a counter reset signal 774 to reset the first counter 776 and the second counter 778. In response to receiving the counter reset signal 774, the controller may reset the first counter 776 (e.g., set the first counter to zero) and control the first counter 776 to start counting when clocked by the clock signal 765 from the ring oscillator 760. In response to receiving the counter reset signal 774, the controller may reset the second counter 778 (e.g., set the second counter to zero) and control the second counter 778 to start counting when clocked by the reference clock signal 784. In response to determining that the counter value of the second counter 778 reaches the target counter value specified by the number control signal 785, the second counter 778 may issue a counter stop signal 779 to stop the first counter 776 from counting. In response to the first counter 776 being stopped, the controller 773 may read the counter output signal 777 indicating the current counter value of the first counter 776, and compare the current counter value with the target frequency word indicated by the signal 783. In response to determining that the current counter value (of the first counter 776) is greater than the target frequency word, the controller 773 may generate a first control signal 771 and / or a second control signal 772 based on the difference between the current counter value and the target frequency word to adjust (e.g., lower or decrease) the frequency of the ring oscillator 760. Similarly, in response to determining that the current counter value (of the first counter 776) is less than the target frequency word, the controller 773 may generate a first control signal 771 and / or a second control signal 772 based on the difference between the current counter value and the target frequency word to adjust (e.g., increase) the frequency of the ring oscillator 760. In some embodiments, a coarse frequency adjustment may be performed first (by the ring oscillator circuit 6000), and then a fine frequency adjustment may be performed (by the ring oscillator circuit 6000). In response to determining that the current counter value (of the first counter 776) is equal to or sufficiently close to (e.g., within a predetermined range) the target frequency word (indicated by the signal 783), the controller 773 may determine that the frequency calibration is complete, and disable both the first counter 776 and the second counter 778, for example, by setting the counter enable signal 775 to 0. In response to determining that the frequency calibration is complete, the ring oscillator 760 may be used for ADC calibration. In response to determining that the ADC calibration is complete, the ring oscillator calibration circuit 770 may be powered off according to the power-off signal 781 set to 1. In some embodiments, in response to determining that the ADC calibration is complete, the ADC calibrator (e.g., the ADC calibrator 390) may set the power-off signal 781 to 1.

[0075] Figure 88000 is a flow chart showing a process 8000 of using a ring oscillator (e.g., ring oscillator 360, 660, 760) to generate a signal for ADC calibration according to an embodiment. In some embodiments, process 8000 is performed by a first circuit (e.g., oscillator calibrator circuit 270, ring oscillator calibrator circuit 370, 770) and / or a second circuit (e.g., oscillator 260, ring oscillator 360, ring oscillator circuit 6000). The first circuit may be coupled to an oscillator (e.g., oscillator 260, ring oscillator 360, 660, 760). The second circuit may be coupled to an oscillator. In some embodiments, the first circuit and the second circuit may be implemented in the same circuit or the same integrated circuit or chip. In other embodiments, process 8000 is performed by other entities. In some embodiments, process 8000 includes comparing Figure 8 More, fewer, or different steps may be shown.

[0076] In step 802, the first circuit may receive a signal (e.g., signal 783) indicating a first frequency (e.g., target frequency word) to be used for calibration of an ADC (e.g., ADC 210, 310, 510). In some embodiments, the first circuit may include a controller (e.g., controller 773), a first counter (e.g., first counter 776), and a second counter (e.g., second counter 778). The first counter may be configured to receive a first clock signal (e.g., first clock signal 765) output from an oscillator (e.g., ring oscillator 760). The second counter may be configured to receive a second clock signal (e.g., second clock signal 784). The controller may be a circuit that implements a finite state machine (FSM).

[0077] In step 804, the first circuit may calibrate the frequency of the oscillator. The controller may be configured to receive a signal (e.g., signal 783) indicating a first quantity (e.g., target frequency word) corresponding to the first frequency. The controller may be configured to receive a third signal (e.g., signal 782) indicating that calibration of the oscillator is to begin.

[0078] In step 806, the first circuit may generate one or more first signals (e.g., signals 771, 772) based at least on a signal (e.g., signal 783 indicating a target frequency word) and a frequency of the oscillator (e.g., a current frequency of the oscillator). In response to a third signal (e.g., third signal 782), the controller may be configured to reset the first counter and the second counter, control each of the first counter and the second counter to start counting, and determine whether the counter number indicated by the output of the second counter (e.g., output signal 777) is equal to a second number (e.g., a target counter value indicated by signal 785). In response to determining that the counter number of the second counter is equal to the second number, the controller may be configured to control the first counter to stop counting and determine whether the counter number indicated by the output of the first counter is equal to the first number (e.g., the target frequency word). In response to determining that the counter number of the first counter (e.g., the counter number indicated by signal 777) is not equal to the first number (e.g., the target frequency word), the controller may be configured to generate one or more first signals (e.g., signals 771, 772). In response to determining that the counter number of the first counter is equal to the first quantity, the controller 773 may be configured to disable the first counter 776 and the second counter 778 (e.g., by setting the signal 775 to 0). In some embodiments, the controller may be configured to receive a fifth signal (e.g., signal 781) indicating enabling (e.g., when the signal 781 indicates 0) or disabling (e.g., when the signal 781 indicates 1) the first circuit 770, so that the first circuit 770 is enabled during calibration of the ADC and disabled in response to the ADC being calibrated.

[0079] In step 808, the second circuit (e.g., oscillator 260, ring oscillator 360, ring oscillator circuit 6000) may receive one or more first signals (e.g., control signals 771, 772 or control signals 671, 672) from the first circuit. The oscillator may be a ring oscillator (e.g., ring oscillator 660) including a plurality of amplifiers (e.g., inverters 662-1, ..., 662-n). The one or more first signals may include a first control signal (e.g., first control signal 671) and a second control signal (e.g., second control signal 672). The second circuit may be configured to determine a first number of amplifiers (e.g., k inverters) among the plurality of amplifiers (e.g., among n inverters) according to the first control signal. The second circuit may be configured to enable a first number of amplifiers (e.g., k inverters) among the plurality of amplifiers (e.g., among n inverters). The second circuit may be configured to determine a second number of capacitors (e.g., k capacitors among capacitors 675-1, ..., 675-m) according to the second control signal. The second circuit may be configured to connect a second number of capacitors (eg, k capacitors) to corresponding amplifiers (eg, k inverters) of the plurality of amplifiers (eg, n inverters).

[0080] In step 810, the second circuit may control the oscillator to generate a second signal having a first frequency (e.g., output signal 665 of ring oscillator 660 when frequency calibration is completed) based at least on one or more first signals (e.g., signals 671, 672). In some embodiments, the second circuit may be configured to receive a sixth signal (e.g., signal 661) indicating enabling or disabling the oscillator, such that the oscillator is enabled during calibration of the ADC and disabled in response to the ADC being calibrated (e.g., ADC calibration is completed). The second circuit may be configured to enable or disable the oscillator according to the sixth signal.

[0081] The term "circuitry" and its variations include (1) hardware, one or more processors (such as microprocessors), or a combination of hardware and / or one or more processors with software and / or firmware; or (2) a single component or a combination of multiple components. The term "controller" and its variations include any circuit, hardware, processor (such as microprocessors), or a combination of hardware and / or one or more processors with software and / or firmware.

[0082] The systems and methods described herein may be embodied in other specific forms without departing from their characteristics. Unless otherwise expressly indicated, references to "approximately," "about," "substantially," or other terms of degree include variations of + / -10% from a given measurement, unit, or range. Unless otherwise expressly indicated, references to specific quantities or values ​​also include variations of + / -10% from a given measurement, unit, or range, allowing for engineering tolerances, deviations, noise, settling time, etc. For example, "an output signal having a first frequency and / or a first amplitude" need not exactly match the first frequency and / or the first amplitude, but only be close enough from an engineering perspective.

[0083] The term "coupling" and its variations include causing two components to be directly or indirectly coupled to each other. The term "electrically coupled" and its variations include causing two components to be directly or indirectly coupled to each other through a conductive material (e.g., metal or copper traces). This coupling (for both terms "coupling" and "electrically coupled") may be fixed (e.g., permanent or fixed) or movable (e.g., removable or releasable). This coupling (for both terms "coupling" and "electrically coupled") may be achieved with two components that are directly coupled to or coupled to each other, with two components that are coupled to each other using a separate intermediary component, or with any additional intermediate components that are coupled to each other, or with two components that are coupled to each other using an intermediary component that is integrally formed as a single entity with one of the two components. If "coupling" or its variations are modified by additional terms (e.g., direct coupling), the general definition of "coupling" provided above is modified by the ordinary language meaning of the additional terms (e.g., "direct coupling" means combining two components without any separate intermediary component), thereby producing a narrower definition than the general definition of "coupling" provided above. Such coupling may be mechanical, electrical, or fluid.

[0084] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

[0085] It should be noted that certain paragraphs of the present disclosure may refer to terms related to transmit spatial streams, sounding frames, responses, and subsets of devices, such as "first" and "second", for identification or distinction from each other or from other objects. These terms are not intended to relate entities (such as first devices and second devices) only in time or according to sequence, but in some cases, these entities may include such a relationship. These terms also do not limit the number of possible entities that can operate within a system or environment. It should be understood that the system described above may provide multiple of any or each of those components and that these components may be provided on a stand-alone machine or, in some embodiments, on multiple machines in a distributed system. In addition, the systems and methods described above may be provided as one or more computer-readable programs or executable instructions embodied on or in one or more articles of manufacture (such as floppy disks, hard disks, CD-ROMs, flash memory cards, PROMs, RAMs, ROMs, or tapes). The program may be implemented in any programming language (such as LISP, PERL, C, C++, C#, or any bytecode language (such as JAVA)). The software program or executable instructions may be stored as object code on or in one or more articles of manufacture. In some embodiments, the ADC is used as an integrated circuit in a transmitter for wireless communication. The ADC is disposed on an integrated circuit including a calibration engine. In some embodiments, the ADC and the calibration engine are disposed in a single chip or a multi-chip integrated package.

[0086] Although the foregoing written description of the methods and systems enables one of ordinary skill to make and use embodiments thereof, one of ordinary skill will understand and appreciate the existence of variations, combinations, and equivalents of the specific embodiments, methods, and examples herein. Therefore, the methods and systems should not be limited to the above-described embodiments, methods, and examples, but should be limited to all embodiments and methods within the scope and spirit of the present disclosure.

Claims

1. A device comprising: an oscillator coupled to circuitry providing calibration of the oscillator, the oscillator being configured to receive a first signal from the circuitry, the first signal causing the oscillator to generate a second signal having a first frequency to be used for calibration of an analog-to-digital converter ADC; and a driver coupled to the oscillator and the ADC, the driver being configured to: receiving the second signal from the oscillator; receiving a third signal indicative of an amplitude to be applied to the second signal; and An output signal having the first frequency and the amplitude is provided to the ADC based at least on the second signal and the third signal. 2 . The apparatus of claim 1 , wherein the second signal is a pair of signals that are 180 degrees out of phase with each other.

3. The device of claim 1, wherein the driver is configured to: receiving a fourth signal indicating a rise time and a fall time to be applied to the second signal; and An output signal having the first frequency, the amplitude, the rise time, and the fall time is provided to the ADC based at least on the second signal, the third signal, and the fourth signal.

4. The apparatus according to claim 1, wherein the driver comprises: One or more amplifiers coupled to the oscillator and configured to amplify the second signal based at least on the third signal to produce the output signal.

5. The apparatus of claim 4, wherein the driver comprises: one or more capacitors coupled to the outputs of the one or more amplifiers, Wherein the driver is configured to provide the output signal to the ADC through the one or more capacitors.

6. The apparatus of claim 4, wherein the driver comprises: one or more switches coupled to the outputs of the one or more amplifiers, The driver is further configured to: receiving a fifth signal indicative of enabling or disabling the driver, such that the driver is enabled during the calibration of the ADC and disabled in response to the ADC being calibrated, and The one or more switches are turned on or off according to the fifth signal.

7. The device according to claim 1, wherein The ADC receives one or more input signals through a first amplifier, and The driver is configured to turn off the first amplifier during the calibration of the ADC and turn on the first amplifier in response to the ADC being calibrated.

8. The device of claim 7, wherein the driver is configured to: providing a sixth signal indicating enabling or disabling of the first amplifier to the first amplifier, so that the first amplifier is disabled during the calibration of the ADC and is enabled in response to the ADC being calibrated, and The first amplifier is turned on or off according to the sixth signal.

9. The apparatus of claim 7, wherein during the calibration of the ADC, The driver is configured to provide the output signal to a second amplifier having an impedance less than an impedance of the first amplifier, and The ADC receives the one or more input signals from the second amplifier.

10. A circuit system comprising: A first circuit is coupled to the oscillator and is configured to: receiving a signal indicative of a first frequency to be used for calibration of an analog-to-digital converter ADC, calibrating the frequency of the oscillator, and generating one or more first signals based at least on the signal and a frequency of the oscillator; and a second circuit coupled to the oscillator and configured to: receiving the one or more first signals from the first circuit, and The oscillator is controlled based at least on the one or more first signals to generate a second signal having the first frequency.

11. The circuit system of claim 10, wherein the first circuit comprises: Controller; a first counter configured to receive a first clock signal output from the oscillator; and The second counter is configured to receive a second clock signal.

12. The circuit system of claim 11, wherein the controller is a circuit implementing a finite state machine (FSM).

13. The circuit system of claim 11 , wherein the controller is configured to: receiving a signal indicating a first quantity corresponding to the first frequency; receiving a third signal indicating the start of calibration of the oscillator; in response to the third signal, resetting the first counter and the second counter, controlling each of the first counter and the second counter to start counting, and determining whether a counter number indicated by an output of the second counter is equal to a second number; in response to determining that the counter number of the second counter is equal to the second number, controlling the first counter to stop counting and determining whether the counter number indicated by the output of the first counter is equal to the first number; and In response to determining that the counter number of the first counter is not equal to the first quantity, the one or more first signals are generated.

14. The circuit system of claim 13, wherein the controller is configured to: In response to determining that the counter number of the first counter is equal to the first quantity, the first counter and the second counter are disabled.

15. The circuit system of claim 11, wherein the controller is configured to: A fifth signal indicative of enabling or disabling the first circuit is received, such that the first circuit is enabled during the calibration of the ADC and is disabled in response to the ADC being calibrated.

16. The circuit system of claim 10, wherein The oscillator is a ring oscillator, The ring oscillator includes a plurality of amplifiers, The one or more first signals include a first control signal and a second control signal, and The second circuit is configured to: determining a first number of amplifiers among the plurality of amplifiers according to the first control signal; and The first number of amplifiers of the plurality of amplifiers are enabled.

17. The circuit system of claim 16, wherein the second circuit is configured to: determining a second number of capacitors according to the second control signal, and The second number of capacitors is connected to corresponding amplifiers of the plurality of amplifiers.

18. The circuit system of claim 10, wherein the second circuit is configured to: receiving a sixth signal indicative of enabling or disabling the oscillator, such that the oscillator is enabled during the calibration of the ADC and is disabled in response to the ADC being calibrated; and The oscillator is enabled or disabled according to the sixth signal.

19. A method comprising: receiving, by a first circuit coupled to the oscillator, a signal indicative of a first frequency to be used for calibration of the analog-to-digital converter ADC; calibrating the frequency of the oscillator by the first circuit; generating, by the first circuit, one or more first signals based at least on the signal and the frequency of the oscillator; receiving, by a second circuit coupled to the oscillator, the one or more first signals from the first circuit; and The oscillator is controlled by the second circuit based at least on the one or more first signals to generate a second signal having the first frequency.

20. The method of claim 19, further comprising: receiving, by the second circuit, another signal indicative of enabling or disabling the oscillator, such that the oscillator is enabled during the calibration of the ADC and disabled in response to the ADC being calibrated; and The oscillator is enabled or disabled by the second circuit according to the other signal.

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