Low parasitic capacitance architecture for successive approximation register analog-to-digital converter

Abstract

The invention relates to a low parasitic capacitance architecture for successive approximation register analog-to-digital converters. A unit capacitor for a switched capacitor digital-to-analog converter is provided. An apparatus includes a first plate formed of an electrically conductive material, where the first plate includes one or more first fingers, where each respective first finger of the one or more first fingers has an elongated structure extending longitudinally in a first direction. The apparatus further includes a second plate formed of the conductive material, where the second plate includes two or more second fingers, where each respective second finger of the two or more second fingers has an elongated structure extending in a second direction. Each first finger of the one or more first fingers is disposed between two adjacent second fingers of the two or more second fingers.

Description

[0001] Copyright Notice

[0002] A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document and the patent disclosure as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever. Technical Field

[0003] The present disclosure generally relates to methods, systems, and apparatus for reducing parasitic capacitance in a successive approximation register analog-to-digital converter. Background Art

[0004] A typical modern successive approximation register (SAR) analog-to-digital converter (ADC) utilizes a top-plate sampling architecture with a switched capacitor (SC) (also known as a "switched capacitor") digital-to-analog converter (DAC). The unit capacitor is the smallest individual capacitor in the SC DAC capacitor array. Low unit capacitor mismatch allows high resolution, while low unit capacitor capacitance allows high speed. The large full-scale voltage range in the SAR ADC allows improved linearity and signal-to-noise ratio (SNR) performance.

[0005] Conventional metal oxide metal (MOM) capacitors (also referred to as metal finger capacitors) are used to implement capacitors in deep submicron and advanced complementary metal oxide semiconductor (CMOS) technologies. When the feature size of the metal layer of the MOM capacitor continues to shrink, the parasitic capacitance on the metal connection node becomes more significant compared to the capacitance of the MOM capacitor.

[0006] Thus, a low parasitic capacitance architecture for a SAR ADC is provided. Summary of the invention

[0007] On the one hand, the present disclosure relates to a device, comprising: a first capacitor, wherein the first capacitor comprises: a first plate, which is formed of a conductive material, wherein the first plate comprises one or more first fingers, wherein each corresponding first finger of the one or more first fingers has an elongated structure extending longitudinally in a first direction; and a second plate, which is formed of the conductive material, wherein the second plate comprises two or more second fingers, wherein each corresponding second finger of the two or more second fingers has an elongated structure extending in a second direction, wherein each first finger of the one or more first fingers is disposed between two adjacent second fingers of the two or more second fingers.

[0008] On the other hand, the present disclosure relates to a capacitor array, comprising: a plurality of unit capacitors, wherein each corresponding unit capacitor further comprises: a first capacitor, wherein the first capacitor comprises: a first plate formed of a conductive material, wherein the first plate comprises one or more first fingers, wherein each corresponding first finger of the one or more first fingers has an elongated structure extending longitudinally in a first direction; and a second plate formed of the conductive material, wherein the second plate comprises two or more second fingers, wherein each corresponding second finger of the two or more second fingers has an elongated structure extending in a second direction, wherein each first finger of the one or more first fingers is disposed between two adjacent second fingers of the two or more second fingers; and a second capacitor coupled to the first capacitor, wherein the second capacitor includes at least a portion of one of the first plate or the second plate.

[0009] On the other hand, the present disclosure relates to a system, comprising: a circuit configured to sample and generate an input signal; a digital / analog converter configured to receive the input signal from the circuit and generate an output signal based at least in part on the input signal, wherein the digital / analog converter further comprises: a capacitor array, wherein the capacitor array comprises a plurality of unit capacitors, wherein each respective unit capacitor further comprises: a first capacitor, wherein the first capacitor comprises: a first plate formed of a conductive material, wherein the first plate comprises one or more first fingers, wherein each respective first finger of the one or more first fingers has an elongated structure extending longitudinally in a first direction; and A second plate formed from the conductive material, wherein the second plate includes two or more second fingers, wherein each corresponding second finger of the two or more second fingers has an elongated structure extending in a second direction, wherein each first finger of the one or more first fingers is disposed between two adjacent second fingers of the two or more second fingers; and a second capacitor coupled to the first capacitor, wherein the second capacitor includes at least a portion of one of the first plate or the second plate; a comparator configured to compare the output signal with a reference voltage; and logic configured to generate a digital code based at least in part on an output of the comparator. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] A further understanding of the nature and advantages of particular embodiments may be achieved by reference to the remainder of the specification and drawings, wherein like reference numerals are used to refer to like components. In some instances, a sub-label is associated with a reference numeral to denote one of multiple similar components. When reference is made to a reference numeral without specifying an existing sub-label, it is intended to refer to all such multiple similar components.

[0011] Figure 1 is a schematic block diagram of a SAR ADC according to various embodiments;

[0012] Figure 2A is a schematic top view of a unit capacitor of an SC DAC according to various embodiments;

[0013] Figure 2B is a schematic diagram of a cross-section of a first configuration of a unit capacitor of an SC DAC according to various embodiments;

[0014] Figure 2C is a schematic diagram of a cross-section of a second configuration of a unit capacitor of an SC DAC according to various embodiments;

[0015] Figure 2D is a schematic diagram of a cross-section of a third configuration of a unit capacitor of an SC DAC according to various embodiments;

[0016] Figure 3A is a schematic top view of a first alternative arrangement of unit capacitors of an SC DAC according to various embodiments;

[0017] Figure 3B is a schematic diagram of a cross-section of a first alternative arrangement of unit capacitors of an SC DAC according to various embodiments;

[0018] Figure 4A is a schematic top view of a second alternative arrangement of unit capacitors for an SC DAC according to various embodiments; and

[0019] Figure 4B is a schematic diagram of a cross-section of a third alternative arrangement of unit capacitors for an SC DAC according to various embodiments. DETAILED DESCRIPTION

[0020] Various embodiments describe various configurations of capacitors and SC DACs in a low parasitic capacitance SAR ADC.

[0021] In some embodiments, an apparatus for a low parasitic capacitance unit capacitor is provided. The apparatus includes a first plate formed of a conductive material, wherein the first plate includes one or more first fingers, wherein each respective first finger of the one or more first fingers has an elongated structure extending longitudinally in a first direction. The apparatus further includes a second plate formed of the conductive material, wherein the second plate includes two or more second fingers, wherein each respective second finger of the two or more second fingers has an elongated structure extending in a second direction. Each first finger of the one or more first fingers is disposed between two adjacent second fingers of the two or more second fingers.

[0022] In another embodiment, a capacitor array for a switched capacitor DAC architecture is provided. The capacitor array includes a first capacitor and a second capacitor. The first capacitor includes a first plate formed of a conductive material, wherein the first plate includes one or more first fingers, wherein each corresponding first finger of the one or more first fingers has an elongated structure extending longitudinally in a first direction. The first capacitor further includes a second plate formed of the conductive material, wherein the second plate includes two or more second fingers, wherein each corresponding second finger of the two or more second fingers has an elongated structure extending in a second direction. Each first finger of the one or more first fingers is disposed between two adjacent second fingers of the two or more second fingers. The capacitor array may further include a second capacitor coupled to the first capacitor, wherein the second capacitor includes at least a portion of one of the first plate or the second plate.

[0023] In another embodiment, a system for a SAR ADC with a low parasitic capacitance architecture is provided. The system includes a circuit configured to sample and generate an input signal, and a digital / analog converter configured to receive the input signal from the circuit and generate an output signal based at least in part on the input signal. The digital / analog converter includes a capacitor array, wherein the capacitor array includes a plurality of unit capacitors. Each corresponding unit capacitor further includes a first capacitor. The first capacitor includes a first plate formed of a conductive material, wherein the first plate includes one or more first fingers, wherein each corresponding first finger of the one or more first fingers has an elongated structure extending longitudinally in a first direction. The first capacitor further includes a second plate formed of the conductive material, wherein the second plate includes two or more second fingers, wherein each corresponding second finger of the two or more second fingers has an elongated structure extending in a second direction. Each first finger of the one or more first fingers is disposed between two adjacent second fingers of the two or more second fingers. Each respective unit capacitor may further include a second capacitor coupled to the first capacitor, wherein the second capacitor includes at least a portion of one of the first plate or the second plate. The system further includes a comparator configured to compare the output signal to a reference voltage, and logic configured to generate a digital code based at least in part on an output of the comparator.

[0024] In the following description, for the purpose of explanation, numerous details are set forth to provide a thorough understanding of the described embodiments. However, it will be apparent to one skilled in the art that other embodiments may be practiced without some of these details. Several embodiments are described herein, and although various features are attributed to different embodiments, it should be understood that features described with respect to one embodiment may also be combined with other embodiments. However, for the same reasons, it should not be considered that a single or multiple features of any described embodiment are essential to every embodiment of the present invention, as other embodiments of the present invention may omit such features.

[0025] When an element is referred to herein as being "connected" or "coupled" to another element, it is understood that the element may be directly connected to the other element, or that there may be an intervening element between the elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, it is understood that there may be no intervening elements in the "direct" connection between the elements. However, the presence of a direct connection does not exclude other connections where there may be intervening elements.

[0026] When an element is referred to herein as being "disposed" in some manner relative to another element (e.g., disposed on, disposed between, disposed below, disposed adjacent to, or disposed in some other relative manner), it is understood that the element may be disposed directly relative to the other element (e.g., disposed directly on the other element) or that there may be intervening elements between the elements. In contrast, when an element is referred to as being "directly disposed" relative to another element, it is understood that there are no intervening elements in the "direct" instance. However, the presence of a direct placement does not exclude other instances in which there may be intervening elements.

[0027] Likewise, when an element is referred to herein as a "layer," it is understood that the layer may be a single layer or may include multiple layers. For example, a conductive layer may include a plurality of different conductive materials or multiple layers of different conductive materials, and a dielectric layer may include a plurality of dielectric materials or multiple layers of dielectric materials. When a layer is described as being coupled or connected to another layer, it is understood that the coupled or connected layer may include intervening elements present between the coupled or connected layers. In contrast, when a layer is referred to as being "directly" connected or coupled to another layer, it is understood that there are no intervening elements between the layers. However, the presence of a directly coupled or connected layer does not exclude other connections in which intervening elements may be present.

[0028] In addition, the terms left, right, front, back, top, bottom, forward, reverse, clockwise, and counterclockwise are used for explanation purposes only and are not limited to any fixed direction or orientation. Instead, they are only used to indicate the relative position and / or direction between the various parts of an object and / or component.

[0029] In addition, for ease of description, the methods and processes described herein may be described in a particular order. However, it should be understood that unless the context indicates otherwise, intervening processes may occur before and / or after any portion of the described process, and various other procedures may be reordered, added, and / or omitted according to various embodiments.

[0030] Unless otherwise indicated, all numbers used herein to express quantities, dimensions, and the like are to be understood as being modified in all instances by the term "about". In this application, the use of the singular includes the plural unless otherwise specifically indicated, and the use of the terms "and" and "or" means "and / or" unless otherwise indicated. In addition, the use of the terms "including" and "having" and other forms such as "includes", "included", "has", "have" and "had" should be considered non-exclusive. In addition, terms such as "element" or "component" encompass elements and components comprising one unit and elements and components comprising more than one unit, unless otherwise specifically indicated.

[0031] As used herein, the phrase "at least one of..." following a series of items using the terms "and" or "or" to separate any of the items modifies the list as a whole, rather than each member of the list (i.e., each item). The phrase "at least one of..." does not require selection of at least one of each item listed; in contrast, the phrase allows for a meaning that includes at least one of any of the items and / or at least one of any combination of items. By way of example, the phrase "at least one of A, B, and C" or "at least one of A, B, or C" each refers to only A, only B, or only C; and / or any combination of A, B, and C. Where selection of "at least one of each of A, B, C" or alternatively "at least one of A, at least one of B, and at least one of C" is desired, it is so explicitly described.

[0032] In conventional SC SAR ADCs utilizing a top-plate sampling architecture, a larger full-scale voltage range allows for improved performance. However, the full-scale voltage range of a top-plate sampling SAR ADC architecture is inversely related to the total parasitic capacitance on the top-plate node of the SC DAC at a given reference voltage. Therefore, minimizing the parasitic capacitance on the top-plate node of the SD DAC is very important to achieve a large full-scale voltage range in a SAR ADC.

[0033] The proposed SAR ADC architecture describes a unit capacitor that mitigates undesirable parasitic capacitance on the top plate node of the SC DAC in a top plate sampling SAR ADC. By utilizing a MOM capacitor in which the top plate is shielded by the structure of the bottom plate, the parasitic capacitance can be mitigated while maintaining low unit capacitor mismatch. As used herein, a unit capacitor may refer to an individual capacitor within the SC DAC capacitor array.

[0034] Figure 1 1 is a schematic block diagram of a SAR ADC 100 according to various embodiments. The ADC 100 includes a sample and hold circuit 105, a DAC 110, a comparator 115, and a SAR logic 120. It should be noted that in Figure 1 Various portions and components of ADC 100 are schematically shown in FIG. 1 , and the various components and other arrangements of ADC 100 may be modified according to various embodiments.

[0035] In various examples, ADC 100 may be a differential ADC. Thus, as depicted, SAR ADC 100 may utilize both a positive input voltage (Vip) and a negative input voltage (Vin), collectively referred to as an input signal (Vi). In various embodiments, a sample and hold (S / H) circuit 105 may be configured to sample the input signal (V i ) and in this example forward the signal to a circuit of DAC110. In various embodiments, DAC 110 may be an SC DAC utilizing a top plate sampling architecture. DAC 110 may include a plurality of unit capacitors, referred to as a "unit capacitor array". Each of the unit capacitors may include a top plate and a bottom plate. In some embodiments, each individual unit capacitor in the plurality of unit capacitors may include one or more metal-to-metal (MOM) capacitors, also referred to as "finger-shaped" or "interdigitated" capacitors. For example, an individual unit capacitor of the unit capacitor array may be divided into two individual MOM capacitors. As depicted, DAC 110 itself may be a differential DAC, including a corresponding capacitor array for each of the input signals Vip and Vin. It should be understood that in other embodiments, different architectures of the ADC may be utilized, such as a single-ended architecture or a pseudo-differential arrangement utilizing only a single input signal (Vi), and the embodiments are not limited to the depicted full differential arrangement.

[0036] As follows about Figures 2A to 4B It will be described that each individual MOM capacitor is configured so that the bottom plate shields the top plate of the unit capacitor on at least three sides. For example, in some embodiments, the parasitic capacitance on the top plate can reduce the full-scale voltage range of ADC 100, thereby causing performance degradation. In contrast, the full-scale voltage range may be insensitive to the parasitic capacitance on the bottom plate. Therefore, by using the structure of the bottom plate to provide shielding of the top plate, the parasitic capacitance on the top plate can be reduced.

[0037] In some embodiments, the shielding provided by the bottom plate has the effect of converting undesirable parasitic capacitances between the top plate metal structure and the silicon substrate and between the top plate metal structure and adjacent metal wiring into effective capacitances between the top and bottom plates of a unit capacitor.

[0038] As used herein, a substrate may refer to a semiconductor substrate, such as but not limited to bulk silicon, glass, ceramic or other suitable substrate materials. In various examples, the structure of a capacitor and / or capacitor array (including the top plate and bottom plate of the corresponding capacitor) may be deposited or otherwise disposed on a substrate. As used herein, a top plate refers to the top plate of a capacitor, and a bottom plate may refer to the bottom plate of a capacitor. A capacitor may include two plates separated by a dielectric material (e.g., a conductive structure formed by metal, conductive polysilicon or other conductive material), and a charge may be applied thereto to form a capacitance. In some examples, a top plate may refer to a conductive structure of a capacitor on which a charge (Q) is applied. In contrast, a bottom plate may refer to a conductive structure of a capacitor on which a second charge (-Q) is applied, where Q may be a positive charge or a negative charge. The top plate and bottom plate may include but are not limited to conductive plates or other planar structures, fingers, and other structures formed by metal or other conductive materials and separated by dielectric materials. Suitable materials may further include but are not limited to copper (Cu), gold (Au), silver (Ag), aluminum (Al), tantalum (Ta), conductive polysilicon.

[0039] Thus, in various examples, the top and bottom plates of one or more capacitors and / or capacitor arrays may be disposed on the top surface of the substrate (including any shielding structures, as will be described below with respect to Figures 2A to 4B described in more detail).

[0040] The top plate sampling architecture refers to an arrangement in which the S / H circuit 105 is coupled to the top plate of the capacitor array of the DAC 100. In various examples, the DAC 100 can generate an output signal based on a digital code. The output of the DAC 100 can be transmitted to the comparator 115, which can be configured to compare the output of the top plate of the DAC 100 with a reference voltage. The comparator then provides the output to the SAR logic 120, which then generates a new digital code. In various examples, the DAC 100 includes one or more capacitor arrays, each array having n unit capacitors (e.g., C0 to C1). n-1 ), where n is an integer. In such examples, SAR logic 120 may be configured to output an n-bit code based at least in part on the output of comparator 115. Although a binary-weighted SC DAC array is described in this and other examples for purposes of explanation, it should be understood that in other embodiments, DAC 100 may include a non-binary-weighted SC DAC array, and DAC 100 is not limited to any one implementation of an SC DAC array.

[0041] The following is about Figures 2A to 4B Various details of the arrangement of the unit capacitors are set forth. Figures 2A to 2D An alternative arrangement of a unit capacitor in a split configuration is shown, where the unit capacitor is split into two individual MOM capacitors, where the top plate is shielded by the bottom plate. Specifically, Figure 2A 2 is a schematic top view of a unit capacitor 200A of an SC DAC according to various embodiments. The unit capacitor 200A may include a top plate 205, a top plate via 215, a first top plate finger 210a and a second top plate finger 210b, a first bottom plate 220, a first bottom plate finger 225a and a second bottom plate finger 225b, a first bottom plate via 230, a bottom plate shielding structure 235, a second bottom plate 240 (with a third bottom plate finger 245a and a fourth bottom plate finger 245b), and a second bottom plate via 250. It should be noted that in Figure 2A Various parts and structures of the unit capacitor 200A are schematically shown in FIG. 1 , and various components and other arrangements of the capacitor 200A may be modified according to various embodiments.

[0042] In various examples, each individual MOM capacitor of the unit capacitor 200A may include one or more interdigitated fingers. As used herein, a finger refers to an elongated conductive structure of the corresponding top plate 205 and / or bottom plate 220, 240. In various examples, the corresponding finger may be described as having a length extending in a "longitudinal direction" and a width extending in a "lateral direction".

[0043] As previously described, the unit capacitor can be divided into a pair of MOM capacitors. Thus, the unit capacitor 200A can include two sets of interdigitated fingers (e.g., the fingers of the respective bottom plates 220, 240 can interdigitate with the respective fingers of the top plate 205). In another example, the unit capacitor 200A can include more than two sets of interdigitated fingers. For example, the top plate 205 can include multiple fingers in the lateral direction, and the bottom plates 220, 240 similarly include multiple sets of fingers surrounding each of the respective fingers of the top plate 205. An example of this arrangement is optionally depicted in dashed lines.

[0044] For example, in various embodiments, the top plate 205 includes two sets of fingers: first top plate fingers 210a and second fingers 210b. The first top plate fingers 210a can interdigitate with the fingers of the first bottom plate 220 (e.g., first bottom plate fingers 225a and second bottom plate fingers 225b). Thus, in some examples, the first top plate fingers 210a are surrounded on at least three sides by the first bottom plate, and on at least two sides by the first bottom plate fingers 225a and second bottom plate fingers 225b. In some further embodiments, the first top plate finger 210a may be surrounded on at least four sides by the first bottom plate 220 (e.g., by the first bottom plate finger 225a and the second bottom plate finger 225b) and by a shielding structure (e.g., bottom plate shielding structure 235) that extends along the bottom of the unit capacitor between the first bottom plate 220 and the second bottom plate 240 and under the top plate 205 (e.g., at Figures 2B to 2D ) and / or above the top plate 205 (as shown in Figure 2C ) extension.

[0045] Similarly, in various embodiments, the second top plate finger 210b may be surrounded on at least three sides by the second bottom plate 240, including corresponding fingers of the second bottom plate 240 (e.g., third bottom plate finger 245a and fourth bottom plate finger 245b). In another example, the second top plate finger 210b may be further shielded on the top and / or bottom by the second bottom plate. In this way, the top plate 205 and its corresponding fingers 210a, 210b may be shielded by the structure of the first and second bottom plates 220, including the corresponding fingers 225a, 225b of the first bottom plate 220, and the corresponding fingers 245a, 245b of the second bottom plate 240, as well as the bottom plate shielding structure 235.

[0046] The top plate 205 may further include a top plate through-hole 215. In various examples, the through-hole may refer to a through-hole (e.g., a plated through-hole (PTH) through-hole, a through-silicon via (TSV), etc.). The top plate through-hole 215 may be configured to interconnect (e.g., electrically couple and / or physically couple) one or more layers of the top plate 205, as will be described in more detail below. Similarly, the first bottom plate through-hole 230 may be configured to interconnect one or more layers of the first bottom plate 220, and the second bottom plate through-hole 250 may be configured to interconnect one or more layers of the second bottom plate 240.

[0047] Figures 2B to 2D Various cross-sectional views taken across line xx are shown. Figure 2B is a schematic diagram of a cross-section of a first configuration of a unit capacitor 200B of an SC DAC according to various embodiments. Figure 2C is a schematic diagram of a cross-section of a second configuration of a unit capacitor 200C of an SC DAC according to various embodiments. Figure 2D is a schematic diagram of a cross-section of a third configuration 200D of unit capacitors of an SC DAC according to various embodiments. Figures 2B to 2D Various portions and structures of the unit capacitors 200B to 200D are schematically illustrated in FIG. 1 , and various structures and other arrangements of the unit capacitors 200B to 200D may be modified according to various embodiments.

[0048] about Figures 2B to 2D , the unit capacitors 200B to 200D may include m layers, where m is an integer. For example, the unit capacitors 200B to 200D may include m layers M1 to M2. m In a first configuration, the first layer M1 of the unit capacitor 200B may be a continuous bottom plate shielding structure 235, and the first bottom plate 220 and the second bottom plate 240 are coupled together, for example, by respective vias 230, 250 coupled to the bottom plate shielding structure 235. In various examples, the bottom plate shielding structure 235 is formed of a conductive material, such as copper. In this way, the bottom side of the top plate 205 may be at least partially shielded by the bottom plates 220, 240 and specifically the bottom plate shielding structure 235, which thereby forms part of the respective bottom plates 220, 240. Thus, in various examples, the bottom plate shielding structure 235 may be disposed under at least a portion of the top plate 205, and specifically under at least a portion of the top plate fingers 210a, 210b.

[0049] Figure 2C A second configuration of the unit capacitor 200C is shown, in which the second bottom plate shield structure 255 is disposed on (e.g., above) at least a portion of the top plate 205 together with the bottom plate shield structure 235 disposed under at least a portion of the top plate 205. In some embodiments, similar to the bottom plate shield structure 235, the second bottom plate shield structure 255 can be coupled to both bottom plates 220, 240.

[0050] Figure 2D A third configuration of the unit capacitor 200D is shown in which the bottom plate shielding structure 235 is split to create two half-unit capacitors. Specifically, the bottom plate shielding structure 235 does not couple the first bottom plate 220 to the second bottom plate 240. Therefore, the first bottom plate 220 is labeled "B1" and the second bottom plate 240 is labeled "B2". Therefore, although the bottom plate shielding structure 235 may be separated, each of the first bottom plate 220 and the second bottom plate 240 has a corresponding portion of the bottom plate shielding structure 235. Using two half-unit capacitors provides an additional bit of resolution for the SAR ADC 100 while maintaining unit capacitor matching accuracy.

[0051] In each of configurations 2B-2D, the capacitance between the top plate 205 and the bottom plates 220, 240 is generally beneficial to the operation of the SCDAC and effectively increases the effective capacitance between the top plate 205 and the bottom plates 220, 240. The parasitic capacitance (C par ) is reduced by shielding through the conductive structures of the bottom plates 220 , 240 (including the corresponding fingers 225 a , 225 b , 245 a , 245 b ) and the bottom plate shielding structure 235 and the second bottom plate shielding structure 255 .

[0052] Figure 3A is a schematic top view of a first alternative arrangement of a unit capacitor 300A for an SC DAC according to various embodiments. The unit capacitor 300A may include a bottom plate 305, a first top plate 320, and a second top plate 335. The bottom plate 305 may include a first set of bottom plate fingers 310a and a second set of bottom plate fingers 310b. The first top plate 320 may include a first top plate finger 325, and the second top plate 335 may include a second top plate finger 340. The bottom plate 305 further includes a bottom plate through hole 315, while the first top plate 320 includes a first top plate through hole 330, and the second top plate 335 includes a second top plate through hole 345. The bottom plate 305 further includes a bottom plate shielding structure 350. It should be noted that in Figure 3A Various portions and structures of the unit capacitor 300A are schematically shown in FIG. 1 , and various components and other arrangements of the capacitor 300A may be modified according to various embodiments.

[0053] and Figure 2A Compared to the arrangement of the unit capacitor 200A of FIG. 1 , the unit capacitor 300A utilizes a bottom plate 305 positioned between two top plates 320, 335, and wherein the bottom plate 305 includes two sets of bottom plate fingers 310a, 310b extending on opposite sides of the bottom plate 305. In this arrangement, two top plates 320, 335 are utilized instead of Figure 2A The bottom plate 305 further shields the respective top plates 320, 335 on either side opposite to the respective top plate fingers 325, 340. For example, the first top plate fingers 325 may extend from the first side toward the bottom plate 305 and specifically the bottom plate through hole 315 centrally disposed between the first top plate 320 and the second top plate 335. Thus, the bottom plate 305 may further shield the first top plate 320 on a second side opposite to the first side. Similarly, the second top plate fingers 340 may extend from the second side toward the centrally disposed portion of the bottom plate 305. The bottom plate 305 may be further configured to shield the second top plate 335 on a first side opposite to the second side. In some examples, such portions of the bottom plate 305 that shield respective sides of the top plates 320, 335 may be referred to as lateral portions of the bottom plate 305.

[0054] As previously mentioned Figure 2A As depicted, unit capacitor 300A may include one or more sets of interdigitated fingers (e.g., where top plate fingers 325, 340 interdigitate with bottom plate fingers 310a, 310b, respectively). In further examples, unit capacitor 300A may include more than two sets of interdigitated fingers. For example, bottom plate 305 and top plates 320, 335 may include multiple fingers along a lateral direction, as optionally depicted in dashed lines.

[0055] The first top plate finger 325 may be surrounded on at least three sides by the bottom plate 305 and the first set of bottom plate fingers 310a. Similarly, the second top plate 335 also includes a second top plate finger 340, which is surrounded on at least three sides by the bottom plate 305 and the second set of bottom plate fingers 310b. Thus, the first top plate 320 and the second top plate 335 are surrounded on at least four sides by the structural bottom plate 305 including the bottom plate shielding structure 350.

[0056] In various examples, each individual MOM capacitor of the unit capacitor 300A includes one or more interdigitated fingers. As previously described, the unit capacitor can be split into a pair of MOM capacitors. Thus, the unit capacitor 300A can include two sets of interdigitated fingers (e.g., the fingers of the respective top plates 320, 335 can interdigitate with the respective fingers of the bottom plate 305).

[0057] As previously described, the first top plate vias 330 and the second top plate vias 345 can be configured to interconnect (e.g., electrically and / or physically couple) one or more layers of the respective top plate 320, 335 structures. For example, the first top plate vias 330 can be configured to interconnect one or more layers of the first top plate 320, and the second top plate vias 345 can be configured to interconnect one or more layers of the second top plate 335. Similarly, the bottom plate vias 315 can be configured to interconnect one or more layers of the bottom plate 305. In some further embodiments, the lateral portions of the bottom plate 305 can also include vias, respectively.

[0058] Figure 3B is a schematic diagram of a cross-section of a first alternative arrangement of a unit capacitor 300B according to various embodiments. Specifically, Figure 3B Depicts a cross section taken along line yy across unit capacitor 300A. Figure 3B , the unit capacitor 300B includes i layers, where i is an integer. For example, the unit capacitor 300B includes i layers M1 to M iIn a first configuration, the first layer M1 of the unit capacitor 300B may be a bottom plate shielding structure 350. Compared to the previous arrangements of the unit capacitors 200A to 200D, the first top plate 320 and the second top plate 335 of the unit capacitor 300A are not coupled together, where the first top plate 320 is labeled as T1 and the second top plate 335 is labeled as T2. In this way, the bottom sides of the first top plate 320 and the second top plate 335 may be shielded by the bottom plate shielding structure 350.

[0059] Figure 4A 4 is a schematic top view of a second alternative arrangement of unit capacitors for an SC DAC according to various embodiments. Unit capacitor 400A may include a top plate 405 including a first top plate portion 440 and a second top plate portion 445, respective top plate fingers 410, and respective top plate vias 415. Unit capacitor 400A further includes a bottom plate 420 having respective sets of bottom plate fingers 425 and respective bottom plate vias 430. Bottom plate 420 may further include one or more bottom plate shielding structures 435. It should be noted that in Figure 4A Various portions and structures of a unit capacitor 400A are schematically shown in FIG. 4 , and various components and other arrangements of the capacitor 400A may be modified according to various embodiments.

[0060] In various embodiments, the top plate 405 may include two top plate fingers 410. The bottom plate 420 may include two sets of bottom plate fingers 425, each set of bottom plate fingers 425 interdigitating with a corresponding top plate finger 410. As will be noted, each top plate finger may be surrounded by a corresponding set of two bottom plate fingers 425. Thus, each top plate finger 410 may be shielded by two corresponding bottom plate fingers 425. Furthermore, each top plate finger 410 may be shielded by a corresponding bottom plate shielding structure 435.

[0061] and Figure 2A and 3A Compared to the arrangement of the unit capacitors 200A, 300A of FIG. 4 , the unit capacitor 400A utilizes a top plate 405 having two top plate fingers 410 extending in the same direction (on a first side of the top plate 405). The top plate 405 is further shielded on a second side opposite the first side by a lateral portion of the bottom plate 420. In addition, a single bottom plate 420 is used, with each top plate finger 410 having a corresponding set of bottom plate fingers 425. In this arrangement, one top plate 405 and one bottom plate 420 may be utilized.

[0062] As previously described, unit capacitor 400A may include one or more sets of interdigitated fingers (e.g., where top plate fingers 410 are each interdigitated with a corresponding set of bottom plate fingers 425). Thus, top plate fingers 410 may each be surrounded on at least three sides by the structure of bottom plate 420.

[0063] In various examples, each individual MOM capacitor of unit capacitor 400A includes one or more interdigitated fingers. As previously described, unit capacitor 400A can be divided into a pair of MOM capacitors. Thus, unit capacitor 400A can include two sets of interdigitated fingers (e.g., each top plate finger 410 can interdigitate with a corresponding set of bottom plate fingers 425).

[0064] As described, in some embodiments, the top plate 405 can be shielded on at least three sides by the bottom plate 420. In some further embodiments, the top plate 405 can be shielded on at least four sides by the bottom plate 420 (e.g., on the bottom side, between the top plate and the substrate, via the bottom plate shielding structure 435).

[0065] Figure 4B 4 is a schematic diagram of a cross-section of a second alternative arrangement of unit capacitors 400B of an SC DAC according to various embodiments. Specifically, Figure 4B Depicts a cross section taken along line zz across unit capacitor 400A. Figure 4B , the unit capacitor 400B includes j layers, where j is an integer. For example, the unit capacitor 400B includes j layers M1 to M j In the first configuration, the first layer M1 of the unit capacitor 400B may be the bottom plate shield structure 435. In some further alternative embodiments, the unit capacitor 400B may utilize different layers of unit capacitors (e.g., M1 and M2) compared to the previous arrangements of the unit capacitors 200A-200D, 300A-300B, 400A. j-1 , where j=4) to form corresponding individual MOM capacitors. In other words, M j-1 M1 may form a first individual MOM capacitor of the unit capacitor 400B, and M1 may form a second individual MOM capacitor of the unit capacitor 400B.

[0066] Although some features and aspects have been described with respect to embodiments, those skilled in the art will recognize that numerous modifications are possible. For example, although for ease of description, the various methods and processes described herein may be described with respect to specific structural and / or functional components, the methods provided by the various embodiments are not limited to any specific structural and / or functional architecture, but may be implemented in any suitable hardware configuration. Similarly, although some functionality is attributed to one or more system components, unless the context indicates otherwise, according to several embodiments, this functionality may be distributed among various other system components.

[0067] In addition, although the procedures of the methods and processes described herein are described in a particular order for ease of description, various procedures may be reordered, added, and / or omitted according to various embodiments unless the context indicates otherwise. In addition, the procedures described with respect to a method or process may be incorporated into other described methods or processes; similarly, system components described according to a particular structural architecture and / or with respect to one system may be organized in an alternative structural architecture and / or incorporated into other described systems. Therefore, although the embodiments are described with or without some features for ease of description and explanation of aspects of various embodiments, various components and / or features described herein with respect to specific embodiments may be replaced, added, and / or subtracted from other described embodiments unless the context indicates otherwise. Therefore, although several embodiments are described above, it will be understood that the present invention is intended to cover all modifications and equivalents within the scope of the appended claims.

Claims

1. A device comprising: a first capacitor, wherein the first capacitor comprises: a first plate formed of a conductive material, wherein the first plate includes one or more first fingers, wherein each respective first finger of the one or more first fingers has an elongated structure extending longitudinally in a first direction; and a second plate formed of the conductive material, wherein the second plate includes two or more second fingers, wherein each respective second finger of the two or more second fingers has an elongated structure extending in a second direction, Wherein each first finger of the one or more first fingers is disposed between two adjacent second fingers of the two or more second fingers.

2. The apparatus of claim 1, wherein the second plate comprises a shielding structure that is elongated and has a length extending in the second direction, wherein the shielding structure is at least partially disposed above or below at least a portion of the first plate.

3. The apparatus of claim 1 , further comprising a second capacitor, wherein the second capacitor comprises: at least a portion of the first plate, the first plate further comprising one or more third fingers, wherein each respective third finger of the one or more third fingers has an elongated structure extending longitudinally in one of the first or second directions; and a third plate formed of the conductive material, wherein the third plate includes two or more fourth fingers, wherein each respective fourth finger of the two or more fourth fingers has an elongated structure extending in a direction opposite to the one or more third fingers, Wherein each of the one or more third fingers is disposed between two adjacent fourth fingers of the two or more fourth fingers. 4 . The apparatus of claim 3 , wherein the second board further comprises a shielding structure extending in the second direction, wherein the third board is coupled to the shielding structure.

5. The apparatus of claim 4, wherein the shielding structure is disposed at least partially beneath at least a portion of the first plate.

6. The apparatus of claim 2, wherein the third plate comprises a second shielding structure separate from the first shielding structure, wherein the second shielding structure is disposed under at least a portion of a corresponding third finger of the one or more third fingers of the first plate.

7. The apparatus of claim 1, further comprising a second capacitor, wherein the second capacitor comprises: at least a portion of the second plate, the second plate further comprising two or more third fingers, wherein each respective third finger of the two or more third fingers has an elongated structure extending longitudinally in the first direction; and a third plate formed of the conductive material, wherein the third plate includes one or more fourth fingers, wherein each respective fourth finger of the one or more fourth fingers has an elongated structure extending in the second direction, Wherein each of the one or more fourth fingers is disposed between two adjacent third fingers of the two or more third fingers.

8. The apparatus of claim 7, wherein the shielding structure is disposed under at least a portion of the first plate and at least a portion of the third plate.

9. The apparatus of claim 1, further comprising a second capacitor, wherein the second capacitor comprises: at least a portion of the second plate, wherein the second plate further comprises two or more fourth fingers, wherein the second plate comprises a first layer and a second layer, wherein the two or more second fingers form at least a portion of the first layer, and wherein the two or more fourth fingers form at least a portion of the second layer; and a third plate disposed below the first plate, wherein the third plate is coupled to the first plate, and wherein the third plate further comprises one or more third fingers, wherein the one or more first fingers form at least part of a first layer, and wherein the one or more third fingers form at least part of the second layer, Wherein each of the one or more third fingers is disposed between two adjacent fourth fingers of the two or more fourth fingers.

10. The apparatus of claim 1, wherein the first plate comprises at least two first fingers and the second plate comprises at least three second fingers, wherein each respective first finger of the at least two first fingers is disposed between two adjacent second fingers.

11. A capacitor array, comprising: a plurality of unit capacitors, wherein each respective unit capacitor further comprises: a first capacitor, wherein the first capacitor comprises: a first plate formed of a conductive material, wherein the first plate includes one or more first fingers, wherein each respective first finger of the one or more first fingers has an elongated structure extending longitudinally in a first direction; and a second plate formed of the conductive material, wherein the second plate includes two or more second fingers, wherein each respective second finger of the two or more second fingers has an elongated structure extending in a second direction, wherein each of the one or more first fingers is disposed between two adjacent second fingers of the two or more second fingers; and A second capacitor is coupled to the first capacitor, wherein the second capacitor includes at least a portion of one of the first plate or the second plate.

12. The capacitor array of claim 11, wherein the second plate comprises a shielding structure that is elongated and has a length extending in the second direction, wherein the shielding structure is at least partially disposed above or below at least a portion of the first plate.

13. The capacitor array of claim 11 , wherein the second capacitor comprises: at least a portion of the first plate, the first plate further comprising one or more third fingers, wherein each respective third finger of the one or more third fingers has an elongated structure extending longitudinally in one of the first or second directions; and a third plate formed of the conductive material, wherein the third plate includes two or more fourth fingers, wherein each respective fourth finger of the two or more fourth fingers has an elongated structure extending in a direction opposite to the one or more third fingers, Wherein each of the one or more third fingers is disposed between two adjacent fourth fingers of the two or more fourth fingers.

14. The capacitor array of claim 13, wherein the second plate comprises a shielding structure that is elongated and has a length extending in the second direction, wherein the shielding structure is at least partially disposed above or below at least a portion of the first plate, and wherein the third plate is coupled to the shielding structure.

15. The capacitor array of claim 14, wherein the shielding structure is at least partially disposed under at least a portion of the first plate.

16. A system comprising: A circuit configured to sample and generate an input signal; a digital-to-analog converter configured to receive the input signal from the circuit and to generate an output signal based at least in part on the input signal, wherein the digital-to-analog converter further comprises: A capacitor array, wherein the capacitor array comprises a plurality of unit capacitors, wherein each respective unit capacitor further comprises: a first capacitor, wherein the first capacitor comprises: a first plate formed of a conductive material, wherein the first plate includes one or more first fingers, wherein each respective first finger of the one or more first fingers has an elongated structure extending longitudinally in a first direction; and a second plate formed of the conductive material, wherein the second plate includes two or more second fingers, wherein each respective second finger of the two or more second fingers has an elongated structure extending in a second direction, wherein each of the one or more first fingers is disposed between two adjacent second fingers of the two or more second fingers; and a second capacitor coupled to the first capacitor, wherein the second capacitor includes at least a portion of one of the first plate or the second plate; a comparator configured to compare the output signal with a reference voltage; and Logic is configured to generate a digital code based at least in part on the output of the comparator.

17. The system of claim 16, wherein the second plate includes a shielding structure that is elongated and has a length extending in the second direction, wherein the shielding structure is at least partially disposed above or below at least a portion of the first plate.

18. The system of claim 16, wherein the second capacitor comprises: at least a portion of the first plate, the first plate further comprising one or more third fingers, wherein each respective third finger of the one or more third fingers has an elongated structure extending longitudinally in one of the first or second directions; and a third plate formed of the conductive material, wherein the third plate includes two or more fourth fingers, wherein each respective fourth finger of the two or more fourth fingers has an elongated structure extending in a direction opposite to the one or more third fingers, Wherein each of the one or more third fingers is disposed between two adjacent fourth fingers of the two or more fourth fingers.

19. The system of claim 16, wherein the second capacitor comprises: at least a portion of the second plate, the second plate further comprising two or more third fingers, wherein each respective third finger of the two or more third fingers has an elongated structure extending longitudinally in the first direction; and a third plate formed of the conductive material, wherein the third plate includes one or more fourth fingers, wherein each respective fourth finger of the one or more fourth fingers has an elongated structure extending in the second direction, Wherein each of the one or more fourth fingers is disposed between two adjacent third fingers of the two or more third fingers.

20. The system of claim 16, wherein the second capacitor comprises: at least a portion of the second plate, wherein the second plate further comprises two or more fourth fingers, wherein the second plate comprises a first layer and a second layer, wherein the two or more second fingers form at least a portion of the first layer, and wherein the two or more fourth fingers form at least a portion of the second layer; and a third plate disposed below the first plate, wherein the third plate is coupled to the first plate, and wherein the third plate further comprises one or more third fingers, wherein the one or more first fingers form at least part of a first layer, and wherein the one or more third fingers form at least part of the second layer, Wherein each of the one or more third fingers is disposed between two adjacent fourth fingers of the two or more fourth fingers.

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