Dac circuit with isi dynamic error detection and compensation

Abstract

A kind of DAC circuit with dynamic ISI error detection and compensation, comprising: a plurality of subunit arrays of DAC subunit, ISI detection module, comparator and serial peripheral interface (SPI) module, wherein: DAC subunit array receives digital signal and clock signal output analog signal, ISI detection module generates detection voltage according to analog signal and outputs to comparator, comparator exports instruction according to comparison result to SPI module to control the compensation control of subunit array.This application is realized using passive device independent of Sigma-Delta analog-digital converter, can realize fast DAC static error detection and compensation, real-time DAC dynamic inter-symbol interference error detection and compensation;By integrating dynamic inter-symbol interference error detection and compensation circuit in DAC circuit, the on-chip dynamic inter-symbol interference error detection and compensation function of DAC is realized.

Description

Technical Field

[0001] This invention relates to a technology in the field of digital-to-analog conversion, specifically a DAC circuit with dynamic inter-symbol interference (ISI) error detection and compensation. Background Technology

[0002] In wireless communication and radar detection, analog-to-digital converters (ADCs) are typically implemented using a continuous-time Sigma-Delta architecture. To achieve higher energy efficiency with this architecture, lower oversampling rates, multi-bit subquantizers, and multi-bit feedback ADCs are commonly used in the design. However, the dynamic performance of multi-bit feedback ADCs is limited by inter-symbol interference (ISI), thus restricting their overall performance. Summary of the Invention

[0003] This invention addresses the shortcomings of existing technologies in achieving real-time background ISI detection and calibration, as well as on-chip automatic ISI detection and calibration. It proposes a DAC circuit with dynamic ISI error detection and compensation, implemented using passive components independent of the Sigma-Delta analog-to-digital converter. This enables rapid DAC static error detection and compensation, and real-time DAC dynamic inter-symbol interference (ISI) error detection and compensation. By integrating the dynamic ISI error detection and compensation circuit into the DAC circuit, on-chip dynamic ISI error detection and compensation functions are achieved.

[0004] This invention is achieved through the following technical solution:

[0005] This invention relates to a DAC circuit with dynamic ISI error detection and compensation, comprising: a sub-unit array composed of several DAC sub-units, an ISI detection module, a comparator, and a serial peripheral interface (SPI) module, wherein: the DAC sub-unit array receives digital signals and clock signals and outputs analog signals; the ISI detection module generates a detection voltage based on the analog signals and outputs it to the comparator; the comparator outputs a command to the SPI module based on the comparison result to control the compensation control of the sub-unit array.

[0006] This invention relates to a dynamic ISI error detection and compensation method based on the above-mentioned circuit. The method involves sequentially resetting the DAC subunit for ISI error detection and detecting inter-symbol interference (ISI) error. During the reset phase, the output multiplexer of the DAC subunit being tested connects its output node to the ISI detection module to detect its static output error. The N-type current source of the subunit is connected to a common auxiliary N-type current source to calibrate the static error. During the ISI error detection phase, a passive integrator in the ISI detection module stores the dynamic ISI error generated during switch switching in the DAC subunit. The output voltage of the passive integrator controls the ISI calibration module to calibrate the error caused by ISI interference in the digital-to-analog converter.

[0007] Technical effect

[0008] This invention utilizes a passive integrator in the DAC circuit for ISI error detection and calibration, employing only passive circuitry and operating independently of the analog-to-digital converter (ADC). Compared to existing technologies, it has minimal impact on the loop delay in the Sigma-Delta ADC, low hardware overhead, and enables real-time dynamic ISI error detection and compensation. A 6-bit non-return-to-zero (NRZ) DAC prototype capable of real-time dynamic ISI error detection and compensation is presented. Compared to other architectures, the advantage of this invention lies in the independence of dynamic ISI error detection and compensation from other modules; therefore, the DAC can perform dynamic ISI error detection and compensation regardless of its application scenario. It has minimal impact on the loop delay in the Sigma-Delta ADC, low hardware overhead, and enables real-time dynamic ISI error detection and compensation. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of the structure of the present invention;

[0010] Figure 2 This is a schematic diagram of the circuit related to ISI detection.

[0011] Figure 3 This is a schematic diagram of the ISI calibration module;

[0012] Figure 4 This is a diagram showing the signal relationship during the ISI detection phase.

[0013] Figure 5 The spectrum diagram shows the test results for an example. Detailed Implementation

[0014] like Figure 1As shown, this embodiment relates to a DAC circuit with dynamic ISI error detection and compensation, including: a sub-unit array consisting of 64 DAC sub-units, an ISI detection module, a comparator, and a Serial Peripheral Interface (SPI) module, wherein: the sub-unit array receives digital signals and clock signals and outputs analog signals; the ISI detection module generates a detection voltage based on the analog signals and outputs it to the comparator; the comparator outputs instructions to the SPI module based on the comparison results to perform compensation control on the sub-unit array.

[0015] The digital signal mentioned herein may be, but is not limited to, a 64-bit thermometer code digital signal D. in <63:0>, each DAC subunit receives one bit of thermometer code digital signal.

[0016] The DAC subunit includes: a D flip-flop, an ISI calibration module, a switch driver, a current source module with a switch, and a multiplexer (MUX) connected in sequence. The clock-controlled D flip-flop receives a single digital signal and outputs instruction S1 to the ISI calibration module to generate instruction S2 to control the switch driver. The switch driver then generates a switch drive signal S3 to control the switch of the current source module. The analog signal S4 generated by the current source module is determined by the MUX to be output as an analog signal or output to the ISI detection module.

[0017] like Figure 2 As shown, the current source module includes: five transistors M1-M5, a P-type current source I1, and an N-type current source I2. The output of the P-type current source I1 is connected to transistors M1 and M2; the output of the N-type current source I2 is connected to the third and fourth transistors M3 and M4; and the first and third transistors M1 and M3 are connected to the first input terminal (DAC) of the multiplexer. outp The second and fourth transistors M2 and M4 are connected to the second input terminal DAC of the multiplexer. outn .

[0018] The first to fourth transistors M1-M4 control the output current flow of the P-type current source I1 and the N-type current source I2 to the DAC. outp Or DAC outn The ideal output current of the P-type current source I1 is slightly larger than that of the N-type current source I2. For example, I1 ideally outputs a quiescent current of 28.5uA, while I2 ideally outputs a quiescent current of 27.5uA. The fifth transistor M5 operates according to the digital enable signal en_cali. The output of the auxiliary N-type current source is connected to the N-type current source of the i-th DAC subunit so that the output current of the N-type current source is equal to the output current of the P-type current source.

[0019] like Figure 2 As shown, the multiplexer includes two selection outputs, wherein the inputs of the multiplexer are DACs. outp With DAC outn The two output ports of the multiplexer are respectively connected to the output ports of the DAC. out With ISI detection module.

[0020] like Figure 2 As shown, the ISI detection module includes: a sixth transistor M6 and a seventh transistor M7 serving as auxiliary N-type current sources, and two capacitors C serving as passive integrators. D With C ref Where: storage capacitor C D and reference capacitor C ref Connected via the seventh transistor M7, the storage capacitor C D Store the detection voltage V CD Reference capacitor C ref The reference voltage V stored above ref Detecting voltage V CD With reference voltage V ref The magnitude will be compared by a comparator, with reference voltage V. ref The output current of the sixth transistor M6, which serves as an auxiliary N-type current source, is controlled.

[0021] like Figure 3 As shown, the ISI calibration module consists of four transistors, M8-M. 11 The programmable output edge adjustment circuit calibrates the ISI error by changing the rising and falling edge delays of its output signal S2, wherein the ninth and tenth transistors M9 and M... 10 The effective aspect ratio remains constant, and the eighth and eleventh transistors M8 and M... 11 The effective aspect ratio is controlled by the binary code control word CTRL. p <2:0> and CTRL n <2:0> controls. For example, it controls the CTRL key. p The larger the code value of <2:0>, the larger the effective aspect ratio of the eighth transistor M8. Binary code control word CTRL p <2:0> and CTRL n <2:0> is controlled by the SPI module.

[0022] The eighth and eleventh transistors M8 and M 11 The effective aspect ratio of the eleventh transistor M8 determines the rise and fall edge delays of the output signal S2. The larger the effective aspect ratio of the eighth transistor M8, the smaller the rise edge delay of the output signal S2. 11 The smaller the effective aspect ratio, the greater the rising edge delay of the output signal S2.

[0023] like Figure 4 As shown, this embodiment relates to a dynamic ISI error detection and compensation method based on the above circuit, which sequentially performs dynamic ISI error detection reset and inter-symbol interference error detection on the DAC subunit.

[0024] The reset mentioned above refers to: when the i-th DAC sub-unit enters the reset phase of dynamic ISI error detection, the enable signal en_cali is activated. Switching to a high level connects the auxiliary N-type current source (M6) to the DAC sub-unit, and controls the MUX to connect the output of this DAC sub-unit to the ISI detection module. Switching the enable signal en_detect to a high level turns on transistor M7, connecting capacitor C. D With C ref At the same time, the switch control signal D swp+ / - Switch to low level, switch control signal D swn+ / - Switching to high level connects the P-type current source I1 and the N-type current source I2. Due to component errors in the actual circuit, the output currents of current sources I1 and I2 will deviate from the ideal design values. The ideal output current value of I1 is slightly greater than that of I2, ensuring that the actual current I1 is still greater than I2. Since I1 is greater than I2, the current output of this DAC sub-unit will supply capacitor C. D And C ref Charging, voltage V CD and V ref It will continue to rise. With voltage V ref As the voltage increases, the output current of the auxiliary N-type current source (M6) will gradually increase, gradually compensating for the difference in current output between current sources I1 and I2. When the sum of the current outputs of current source I2 and the auxiliary N-type current source equals the output current of current source I1, the circuit reaches a balanced state, and voltage C... D And C ref The voltage remains constant.

[0025] The aforementioned dynamic inter-symbol interference (ISI) error detection refers to the detection phase when the i-th DAC sub-unit enters the dynamic ISI error detection stage, during which the switching control signal D... swp+ / - With D swn+ / - The digital signal D is input from the digital-to-analog converter. in Control (e.g., when D) in If it is high, then D swp+ D is a high level. swp- D is low level. swn+ D is a high level. swn- (Low level). The enable signal en_detect switches to low level, controlling transistor M7 to not conduct, and capacitor C... D With C ref They are not connected. Current sources I1 and I2 are respectively connected to capacitor C. D Charging and discharging are performed. Since the static error between current sources I1 and I2 has been compensated by the auxiliary N-type current source, when the input signal D... in When constant, voltage V CD It remains unchanged. When the input signal D... in During switching, the dynamic output error of the digital-to-analog converter subunit will cause voltage V to... CD Changes occur, related to voltage V ref A difference is generated between them. When the input signal D... in The number of switching times increases, and the voltage V CD With voltage V ref The difference between them will gradually increase. Then, the voltage V can be compared using a comparator. CD With voltage V ref The relative relationship between the two can be obtained through voltage V. CD With voltage V ref The relative relationship between them can be used to calibrate the dynamic error generated by the digital-to-analog converter subunit through the ISI calibration module.

[0026] like Figure 5 The image shows the test spectrum of this device, obtained using a 2048-point Fast Fourier Transform (FFT) algorithm. The test results are derived by averaging the results of 10 tests. The test results show that after enabling dynamic ISI calibration, the second harmonic distortion decreases by approximately 6.3 dB, the fourth harmonic distortion decreases by approximately 16 dB, and the signal-to-noise ratio (SNDR) improves by approximately 5.2 dB. This invention significantly improves the performance of the Sigma-Delta analog-to-digital converter prototype.

[0027] The above-described specific implementations can be partially adjusted by those skilled in the art in different ways without departing from the principles and purpose of the present invention. The scope of protection of the present invention is defined by the claims and is not limited to the above-described specific implementations. All implementation schemes within the scope of the claims are bound by the present invention.

Claims

1. A DAC circuit with dynamic ISI error detection and compensation, characterized in that, include: The system comprises a sub-unit array consisting of several DAC sub-units, an ISI detection module, a comparator, and a serial peripheral interface (SPI) module. The DAC sub-unit array receives digital enable signals and clock signals and outputs analog signals. The ISI detection module generates a detection voltage based on the analog signals and outputs it to the comparator. The comparator outputs instructions to the SPI module based on the comparison results to control the compensation control of the sub-unit array. The DAC subunit includes: a D flip-flop, an ISI calibration module, a switch driver, a current source module with a switch, and a multiplexer (MUX) connected in sequence. The clock-controlled D flip-flop receives a digital signal and outputs a command to the ISI calibration module to generate a command to control the switch driver. The switch driver then generates a switch drive signal to control the switch of the current source module. The analog signal generated by the current source module is determined by the MUX to be output as an analog signal or output to the ISI detection module. The ISI calibration module is a programmable output edge adjustment circuit that calibrates ISI error by changing the rising and falling edge delays of its output signal. The current source module includes: first to fifth transistors, a P-type current source, and an N-type current source, wherein: the output terminal of the P-type current source is connected to the first and second transistors respectively, the output terminal of the N-type current source is connected to the third and fourth transistors respectively, the first and third transistors are connected to the first input terminal of the multiplexer switch respectively, and the second and fourth transistors are connected to the second input terminal of the multiplexer switch respectively; the gate of the fifth transistor receives a digital enable signal, the source is connected to the auxiliary N-type current source of the ISI detection module to control the output of the auxiliary N-type current source to be connected to the N-type current source of the i-th DAC sub-unit, and the drain is connected to the output terminal of the N-type current source; The ISI detection module includes: a sixth transistor and a seventh transistor as auxiliary N-type current sources, and two storage capacitors and a reference capacitor as passive integrators. The storage capacitor and the reference capacitor are connected through the seventh transistor. The storage capacitor stores the detection voltage, and the reference capacitor stores the reference voltage. The magnitudes of the detection voltage and the reference voltage are compared by a comparator. The reference voltage controls the output current of the sixth transistor as an auxiliary N-type current source. The ISI calibration module is a programmable output edge adjustment circuit composed of the eighth to eleventh transistors. It calibrates the ISI error by changing the rising and falling edge delays of the output signal. The gates and drains of the ninth and tenth transistors are connected and serve as the input and output terminals of the ISI calibration module, respectively. The drain of the eighth transistor is connected to the source of the ninth transistor, and the drain of the eleventh transistor is connected to the source of the tenth transistor. The gates of the eighth and eleventh transistors receive positive and negative binary code control words, respectively. These binary code control words are controlled by the SPI module.

2. A method for dynamic ISI error detection and compensation based on the circuit described in claim 1, characterized in that, The DAC subunit undergoes ISI error detection reset and inter-symbol interference (ISI) error detection sequentially: During the reset phase, the multiplexer at the output of the DAC subunit under test connects the subunit's output node to the ISI detection module to detect its static output error, and connects the subunit's N-type current source to a common auxiliary N-type current source to calibrate the static error; During the ISI error detection phase, the passive integrator in the ISI detection module stores the dynamic ISI error generated during the switching of the DAC subunit, and the ISI calibration module is controlled according to the output voltage of the passive integrator to calibrate the error caused by the ISI error of the digital-to-analog converter.

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